Single-stage synchronous general regulator

Abstract

A voltage-controlled bridge is coupled to the line voltage and the transformer primary harmonic voltage, while a current-controlled bridge is coupled to the line current and the transformer secondary harmonic voltage. A synchronous average harmonic current compensator synchronously integrates the error between the measured bridge current and the command current every half-switch cycle and samples the compensator output to control the line current and linearize the harmonic coupling between the isolation bridges. A synchronous pulse-width modulation process tracks the commanded line voltage. One or more of the primary and secondary harmonic command circuits regulate the harmonic coupling voltages of the voltage-controlled and current-controlled bridges, respectively. The line voltage, line current, and primary and secondary harmonic commands provide generalized line and isolation voltage bus regulation freedom within a single stage.

Description

Technical Field

[0001] This disclosure generally relates to bidirectional isolated buck-boost power conversion systems, and more specifically, to line-connected single-stage isolated buck-boost power converters with synchronous average harmonic current control and their control methods. Background Technology

[0002] Single-stage power conversion systems are used to perform voltage conversion between isolated voltages with minimal components and high efficiency. Existing single-stage systems include... Figure 1 The diagram illustrates a single-stage Cuk converter and a single-stage semi-resonant power converter. The semi-resonant architecture uses a current-feed arrangement where a voltage source (V1) is filtered to provide an average current through an inductor (L0), which is switched relative to ground potential (using SW0). The load current (ILOAD) draws DC current from the isolation voltage (V2), where the average DC current flows from the switching diode D1, and the unsteady current is balanced between the switching diode and the capacitor (CS2). Unsteady currents cause the switching diodes (D1 and D2) to commutate, generating a pulse-width modulated voltage applied to the DC blocking capacitor and the secondary transformer winding (LT2). The coupling transformer windings (LT1 and LT2) generate a switching voltage across the resonant network (LR and CR) that harmonic-filters the coupling current. The inductance associated with the resonant network can be explicit or formed partly or entirely from the leakage inductance of the transformer. Figure 1 The design shown is highly efficient and can be implemented with low electromagnetic interference and efficient semi-resonant switches, has current limiting when operating at switching frequencies far from the resonance, and low impedance when aligned with the inherent frequency of the resonant network. The component efficiency of prior art resonant converters can lead to poor power efficiency at high power levels with a wide range of duty cycles, partly due to passive diode commutation. The duty cycle of the diodes and active switches is related, which can result in low harmonic voltages and high harmonic currents across the resonant network to maintain power output. Prior art designs can be implemented with bidirectional switches to allow arbitrary AC or DC bus voltages, and with additional series stages to achieve low ripple regulated output. Improvements to single-stage power converters are desired to allow arbitrary harmonic buck and boost voltages with improved current conduction losses, and to include regulated line and DC voltage bus connections within a single stage. Summary of the Invention

[0003] In one aspect, the object of the present invention is to realize a highly efficient single-stage power converter having regulated voltage and current line connections, and an isolated DC voltage bus with independent harmonic regulation. This object is achieved in the present invention by using synchronous average harmonic current control of a power converter having a command harmonic coupling signal. Embodiment 2 illustrates the use of a synchronous average harmonic current (SAHC) compensator (210) resonantly coupled (205) through a transformer (209) to a voltage control bridge (202) of a current control bridge (201). The SAHC compensator uses the measured current (206) across the switching nodes (VC and VD) of the current control bridge (202) to generate a superimposed feedback signal, which is passed to a pulse width modulation (PWM) process (208) controlled by the SAHC. The superimposed feedback signal encodes an unmodulated duty cycle command to control the current through the line connection (VAC2) to track the command current (ICMD), and a modulated phase command to control the current coupled through the transformer winding (LT1). A voltage-controlled pulse width modulation (PWM) process (207) controls the voltage control bridge line voltage (VAC1) to proportionally track the command voltage (VCMD). A synchronous average harmonic current compensator couples the harmonic current between the primary harmonic voltage (of the voltage-controlled bridge) and the secondary harmonic voltage (of the current-controlled bridge) to transmit harmonic power through the isolation transformer. The primary harmonic voltage is controlled by the voltage-controlled PWM process (207) as a function of the command voltage and the primary command harmonic signal (B1). The secondary harmonic voltage is controlled by a synchronous average harmonic current-controlled PWM process (208) as a function of the command current and the secondary command harmonic signal (B2). The primary and secondary command harmonic signals are generated by primary (211) and secondary (212) differential harmonic controllers (DHC), which command the corresponding pulse width modulation processes (207 and 208). Figure 2 The single-stage embodiment shown can be magnetically integrated by combining line filter elements with transformer coils (e.g.) Figure 3 (As shown). In Figure 4 A simplified embodiment of a single-stage synchronous generalized regulator (SGR) is shown, illustrating a similarity to that in... Figure 2The diagram shows several external interfaces of the power converter. The power converter applies current (ICD) according to a current command (ICMD), applies voltage (VAB) according to a voltage command (VAB), and uses harmonic commands B1 and B2 to regulate the harmonic current flowing between the second bus voltage (V2) and the first bus voltage (V1). Figure 5 The figure shows a detailed embodiment of a synchronous generalized regulator, which illustrates a combination of duty cycle (d1, d2), phase (p2), and harmonic command (B1, B2) signals to regulate isolated line voltages and line currents as well as isolated bus voltages in a single stage. Figure 6 The illustrated embodiment describes a method for estimating harmonic current flow between isolated voltage buses of a single-stage synchronous generalized regulator using harmonic command signals. Figure 7 The illustrated embodiment demonstrates a method for regulating the isolated output line (VAC1), wherein the isolated input line is reduced to zero volts (VAC2) by commanding the input line current to zero and regulating the output relative to the stored DC bus energy using a harmonic command signal. Figure 8 Another embodiment is shown, illustrating a method for soft-starting and regulating the current entering the energy storage capacitor and regulating the output line voltage and bus voltage in a single stage. Using the converter of the present invention, multiple additional embodiments are possible, providing adjustment degrees of freedom to independently control isolated voltage and current-controlled line connections and isolated bus voltages in a single stage.

[0004] These and additional objects and advantages provided by the embodiments described herein will be more fully understood in light of the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0005] Figure 1 A prior art single-stage half-resonant power converter is shown.

[0006] Figure 2 A single-stage synchronous generalized regulator according to one or more embodiments shown and described herein is illustrated.

[0007] Figure 3 A single-stage synchronous generalized regulator with an integrated magnet is shown according to one or more embodiments illustrated and described herein.

[0008] Figure 4 A simplified interface for a single-stage synchronous generalized regulator according to one or more embodiments shown and described herein is illustrated.

[0009] Figure 5 Detailed dynamics of a single-stage synchronous generalized regulator according to one or more embodiments shown and described herein are illustrated.

[0010] Figure 6Detailed dynamics of a single-stage synchronous generalized regulator with feedback-regulated harmonic current transfer according to one or more embodiments shown and described herein are illustrated.

[0011] Figure 7 A feedforward regulation circuit is shown that uses stored energy to regulate the output voltage according to one or more embodiments shown and described herein.

[0012] Figure 8 An energy regulation circuit according to one or more embodiments shown and described herein is illustrated, the energy regulation circuit also being coupled to an isolation voltage bus and a line voltage. Detailed Implementation

[0013] The embodiments described herein generally relate to a bidirectional single-stage power converter with independently regulated isolated line and bus voltage connections, and a method for using synchronous average harmonic current control and harmonic command signal formation. As shown and described herein, a new embodiment of a single-stage synchronous generalized regulator (SGR) power system is provided. The power converter uses synchronous average harmonic current control to superimpose multiple functions to regulate a current control bridge and couple a regulating voltage control bridge, with primary and secondary harmonic command signals used to provide independent degrees of regulation freedom. The single-stage power system allows regulation of the isolated line current and isolated line voltage by independently controlling their respective DC bus voltages. Detailed schematic diagrams are provided (…). Figure 2 The diagram illustrates and describes a first embodiment of a single-stage synchronous generalized regulator, with the schematic shown at the interface ( Figure 4 The internal dynamics are shown in detail at [location](link). Figure 5 The detailed internal dynamics are further discussed using mathematical equations, which provide control relationships and extend the characterization of one or more embodiments. Figure 3 An embodiment of effectively integrating transformer and line filter magnets is shown. Figure 6 An example of using feedback to regulate harmonic current transfer between isolated voltage buses is shown. Figure 7 An exemplary embodiment of an SGR converter used in a system is shown, which provides power relative to internal energy storage as an option in the case of a line voltage drop. Figure 8 One embodiment is shown in which a current-controlled bridge is used to control the energy exchanged with a storage capacitor and also to couple to isolated line and bus voltages. The techniques and methods described in one or more embodiments can serve as building blocks for a variety of types of power systems due to their components, power efficiency, and flexibility in regulating line and bus voltage connections. Bus voltage connections may include energy storage elements such as capacitors or batteries, thereby allowing the transfer of stored energy and line power.

[0014] Examples of single-stage synchronous generalized regulators in Figure 2The synchronous generalized regulator also includes a current-controlled bridge (202) driving the line current (via VAC2) and a voltage-controlled bridge driving the line voltage (via VAC1). Each bridge is coupled by a transformer (209) via an admittance network (205). The transformer provides isolation between a first voltage bus V1 relative to a first reference (203) and a second voltage bus V2 relative to a second reference (204). An isolation current sensor (206) senses the bridge current flowing from node VC to VD, representing the sum of the low-frequency line current and the high-frequency transformer current. A voltage proportional to the bridge current (VICD) is fed back to a synchronous average harmonic current (SAHC) compensator (210). The SAHC compensator weights and sums the bridge current signal with a command current (ICMD) to form an error current signal, and synchronously compensates and integrates the error current signal on every half-switching cycle of the synchronous square wave (SQ). The command current may contain line and transformer current information. The SAHC compensator features linear-time-periodic dynamics, effectively representing two independent feedback degrees of freedom using a single hardware path. The sampled outputs of the SAHC compensator encode the duty cycle command and phase command using superimposed unmodulated and modulated feedback signals (d2p2), respectively. The SAHC-compensated pulse-width modulation (PWM) process (208) generates fully differential pulse-width modulated gate signals (gC, gCN, gD, and gDN). The differential harmonic controller (DHC2) uses the command harmonic input (B2) to superimpose the differential harmonic command onto a common modulation waveform (TRI) modulated with a synchronous square wave (SQ) of the harmonic command. The SAHC-compensated PWM process is sensitive to the superimposed feedback signals and the differential harmonic command waveforms (TRI+H and TRI-H). The signal set of the PWM process, given by the superimposed feedback signals and the differential harmonic command, results in a differential gate output with the common and differential duty cycles of the command and the common and differential phases of the command (related to the harmonic content). Figure 5 The mathematical description of differential gate signal control with harmonic signal content is further discussed. The coupling admittance between the secondary harmonic voltage of the linearized current-controlled bridge and the primary harmonic voltage of the voltage-controlled bridge in the SAHC compensator causes linearized harmonic current to flow between the bridges. The voltage-controlled bridge is controlled using a voltage-controlled pulse width modulation process (207) to generate a line voltage (across VAC1) proportional to the command voltage (VCMD). The primary differential harmonic command is generated by the primary differential harmonic controller (DHC1) with a common modulation waveform (TRI) to control the primary harmonic voltage. The system's command degrees of freedom, including the current command (ICMD), voltage command (VCMD), primary harmonic command (B1), and secondary harmonic command (B2), support independent adjustment of the isolated line and voltage bus in a single stage. The low part number single-stage architecture offers the opportunity for good efficiency and part number-based reliability.

[0015] Figure 2 The illustrated current-controlled bridge also includes complementary groups of switching elements (SC and SCN) and (SD and SDN). According to existing technology, the complementary groups of switches are driven with corresponding complementary drive signals (gC and gCN) and (gD and gDN), where appropriate dead times are used to reduce cross-conduction. The switching elements are implemented according to existing technology based on application-specific engineering standards such as switching and conduction losses, examples of which include SiCFETs, GaNFETs, MOSFETs, and IGBTs and their appropriate gate drivers. The switching elements can be implemented using switches containing integral or explicit diodes. The current-controlled bridge switches the second bus voltage (V2) relative to a second voltage potential (204) connected in parallel with the energy storage capacitor (CS2). Switching nodes VC and VD are inductively coupled (using L5 and L6) to the line current (via VAC2) and coupled to the transformer coil (LT2) via a capacitor (C0). The current-controlled bridge transformer coil (LT1) is coupled to the voltage-controlled bridge transformer coil (LT1) of the transformer (209). A current sensor (206) senses a current signal proportional to the current across the bridge nodes (VC and VD), which in the illustrated embodiment includes both line current and transformer current. Alternatively, the current sensor may sense only the transformer current to free the line current. A buffer (BUF1) isolates the current signal (VICD) to drive a synchronous average harmonic current compensator. Isolated current sensors are implemented according to existing technology with bandwidths higher than the bridge switching frequency. Resistive shunts can be used for wide-bandwidth current sensing, where the signal element is located in a switching reference frame, or have suitable amplifiers to suppress common-mode voltages relative to a non-switching reference frame (such as long-tailed pairs or IC isolation amplifiers). Another approach to current sensing is to implement an air-gap transformer with derivative (frequency-proportional) current sensitivity, which can be added to and filtered with a proportional current signal to form a wide-bandwidth current sensor. Additional examples known in the art include Hall sensors and current-sensing transformers.

[0016] Synchronous average harmonic current (SAHC) compensator (210) in Figure 2The illustrated embodiment uses an inverting switched-capacitor filter to compensate for and sample the error current signal to generate a superimposed feedback signal (d2p2). The switched-capacitor filter also includes resistors R12 and R11, which sum the current signal (VICD) to the command current (ICMD) to form the error current entering the inverting node of the operational amplifier (OP1). Switched capacitors C1 and C2 are alternately switched at the operational amplifier output and the inverting node (using SC1 and SC2), and are sampled synchronously with a square wave (SQ) and its complement (using N1) to integrate and compensate for the error current. The sampled switched capacitors encode the superimposed feedback signal (d2p2), where the duty cycle command is represented as a superimposed unmodulated signal and the phase command is represented as a superimposed modulated signal. The operational amplifier used for the switched-capacitor filter is selected relative to the switching bandwidth and signal slew rate. Analog switches SC1 and SC2 can be implemented according to existing techniques, such as using integrated circuits like CMOS or JFET circuits to simulate switches.

[0017] In variant embodiments, alternative methods can be used to achieve synchronous average harmonic current compensation and the superposition of feedback signals. An analog multiplicative phase detector can be implemented as an alternative method for compensating for synchronous average harmonic current errors on each half-switching cycle, where the current signal drives the synchronous average multiplication process and an integral error amplifier. The error current signal feedback is modulated by the multiplication process and averaged by the error amplifier to drive a voltage-controlled oscillator (VCO). This alternative method is less preferred because the VCO introduces an integrator, which can make stable compensation more difficult, and the VCO method is synchronized relative to the resonance of the admittance network rather than the synchronous clock signal. Alternative analog multipliers and VCO methods for synchronous average harmonic current compensation also require additional components to superimpose feedback from multiple (e.g., lines) current control signals using multiple independent hardware paths. Other alternative methods, such as phase-locked loops based on logic zero-crossing detection, are not discussed here because they typically do not reduce the synchronous average current. Another alternative method is possible for encoding phase and duty cycle commands into a feedback signal superimposed on a hardware path in a modulated and unmodulated reference frame. Sawtooth signals can be used to compare with unmodulated commands to result in modified edge phase shifts, and with modulated commands to result in modified edge duty cycles. The alternating sawtooth method of encoding superimposed phase and duty cycle commands is less suitable for resonant power converters because the dynamic range of the duty cycle command may be relatively larger than that of the phase command. Figure 2 The embodiment (210) shown for the SAHC compensator is preferably used to encode superimposed unmodulated and modulated feedback for resonant applications, wherein the phase shift associated with current transport is small, resulting in a small superimposed modulated signal.

[0018] An embodiment (212) of a differential harmonic controller (DHC) is shown in Figure 2 The differential harmonic controller shown also includes a fully differential operational amplifier (OP2) with output resistors R22 and R24 switched using complementary analog switches SDM1 and SDM2, and input resistors R21 and R23. The DHC input includes a command harmonic (B2) relative to a reference, and a square wave (SQ) for multiplying the command harmonic to encode it onto the modulated differential output signal. The differential harmonic command waveforms (TRI+H and TRI-H) consist of a triangular wave superimposed as a common signal and a superimposed modulated differential harmonic command. The fully differential operational amplifier (OP2) generating the command can be implemented according to existing technology, for example, using a differential driver circuit with sufficient bandwidth to represent the modulated waveform. Figure 5 Further mathematical discussion describes how differential harmonic commands drive the pulse width modulation process to change harmonic voltage coupling. Figure 2 The illustrated embodiment (212) applies a differential phase input to the pulse width modulation process to command harmonic variations, and alternative methods can be used to drive differential harmonic commands to change harmonic coupling. Alternative methods, such as driving the duty cycle (which is fixed or omits switches SMD1 and SDM2), can be used to change the differential harmonic content due to the (complementary) differential pulse width modulation process.

[0019] Figure 2 The illustrated SAHC compensated pulse width modulation (PWM) process (208) embodiment also includes comparators CMP3 and CMP4. The comparators take differential harmonic commands TRI+H and TRI-H, along with a superimposed feedback command d2p2, as inputs to generate gate differential signals (gC and gCN) and (gD and gDN). The differential harmonic commands encode the modulated positive and negative differential phase shift command signals onto a common triangular modulated waveform to alter harmonic coupling. The superimposed feedback command encodes the unmodulated duty cycle feedback signal and the modulated phase feedback signal. The inputs of the respective comparators are complementary, such that the superimposed feedback command differential duty cycle and common phase shift, and the differential harmonic command input results in differential phase shift and a common triangular waveform. Alternative embodiments can configure the differential pulse width modulation process, for example, by complementary (or swapped) inputs and inverted command signals, to exchange command codes between the differential and common command signals, with equivalent results. The superimposed unmodulated and modulated feedback, as well as the command harmonic input path to the pulse width modulation process, result in control of the line current relative to the command current (ICMD), and harmonic coupling between the current-controlled bridge and the voltage-controlled bridge.

[0020] An embodiment of a voltage-controlled bridge is shown in Figure 2The voltage-controlled bridge is commanded by a voltage-controlled pulse width modulation process (207) to control the line voltage (VAC1) according to the duty cycle of the command voltage (VCMD) and the bus voltage (VAC1) relative to the isolation voltage reference (203). The voltage-controlled bridge also includes complementary sets of switching elements (SA and SAN) and (SB and SBN), which are controlled by corresponding gate signals (gA and gAN) and (gB and gBN). Switches are implemented according to the prior art and appropriate gate drive circuitry to reduce switching losses, conduction losses, and cross-conduction. Switches may include integral or explicit diodes that limit reverse voltage bias. The switching nodes VA and VB of the voltage-controlled bridge are inductively coupled (using L1 and L2) to the line voltage (VAC1) and coupled to the primary winding of the transformer (LT1) through admittance networks (LR and CR). The admittance network may include reactive elements that reflect back to either of the transformer windings with similar results. A storage capacitor (CS1) is located at both ends of the voltage bus to locally recirculate the high-frequency switching current. The voltage-controlled pulse width modulation (PWM) process also includes comparators CMP1 and CMP2 and is sensitive to both voltage commands and differential harmonic commands. The differential harmonic command to the voltage-controlled PWM process is generated by the primary differential harmonic controller (DHC1), whose components have a similar description to DHC2. The primary differential harmonic controller generates a differential harmonic command proportional to the harmonic command input (B1) and superimposes a triangular waveform as a common-mode signal. Alternative PWM processes that produce similar outputs are possible, for example, in... Figure 5 The related mathematical discussion describes this. Other methods include digitally controlled pulse width modulation; however, analog control methods offer superior phase resolution relative to the switching cycle of a resonant power converter.

[0021] It is possible to develop a system relative to the primary or secondary differential harmonic controller by omitting one or more of the primary or secondary differential harmonic controllers. Figure 2 The illustrated embodiment is a simplified version. This simplified version benefits from reduced component complexity and makes the harmonic coupling voltage dependent on the line command. Similar simplified embodiments can be developed where the line command is set to zero and the line conditions are set according to the harmonic coupling command. Figure 2 The advantage of the complete embodiment shown is that the harmonic voltage coupling can be changed relative to the harmonic conditions controlled by line commands.

[0022] Figure 3 An embodiment of a synchronous generalized regulator with an integrated magnet is shown. Individual magnetic elements connected to a voltage control bridge (201) and a current control bridge (202) are respectively superimposed on the integrated magnet. Figure 2 The inductor line filters (L5 and L6) and transformer secondary (LT2) of the current-controlled bridge shown in the figure are in Figure 3It is integrated into differential line filters and coupling transformer elements (LT2A and LT2B). Figure 2 The inductor line filters (L1 and L2) and transformer secondary (LT1) of the voltage-controlled bridge shown are in Figure 3 These are integrated into the differential line filter and coupling transformer elements (LT1A and LT1B). They are respectively connected to... Figure 2 The inductors and capacitors associated with the primary and secondary windings of the transformer are similarly superimposed. Figure 3 The shared filter and transformer networks (305, LR, CR, and C0, respectively) are used. When the isolated line connection currents are approximately balanced, the integrated magnets are approximately flux balanced for the AC and DC flux terms. Figure 3 The remaining blocks (303, 304, 305, 306, 307, 308, 309, 310, 311, 312) are descriptively similar to Figure 2 The ones described in the text (203, 204, 205, 206, 207, 208, 209, 210, 211, 212). Additional common-mode filters can be connected to the line connection of the synchronous generalized regulator, where, due to the approximately balanced magnetic flux, the common-mode filter has the advantage of small component size.

[0023] A simplified embodiment of a synchronous generalized regulator is in Figure 4 As shown in the figure, the internal dynamics are in Figure 5 The detailed dynamic embodiment shown in the figure illustrates this. Figure 4 The SGR block shown includes a current-controlled bridge power interface along the left edge, a voltage-controlled bridge power interface along the right edge, and a signal interface along the bottom edge. The current-controlled bridge interface includes a bus voltage V2 relative to the return reference RTN2, and a current ICD across the bridge's switching nodes VC and VD. The current is controlled to track the command current (ICMD) via a differential gate signal (gCD) generated by a synchronous average harmonic current (SAHC) controller with a differential harmonic command input (B2). Signals SQ and TRI represent synchronous square and triangular waveforms used for timing the power converter, and d2p2 represents the superimposed duty cycle and phase command output. The voltage-controlled bridge interface includes a bus voltage V1 relative to the return reference RTN1, and a voltage VAB across the bridge's switching nodes VA and VB. The voltage is controlled to track the command voltage (VCMD) via a differential gate signal (gAB), generated by a voltage-controlled pulse width modulation controller with a differential harmonic command input (B1). The voltage-controlled PWM stage is synchronized with the current-controlled PWM stage. The SGR block ( Figure 4The interface shown can be used to implement flexible power systems, where voltage and current interfaces connect to external systems and the associated bus voltages are regulated relative to each other based on harmonic (buck-boost) commands. The external interface shown has modest bandwidth requirements (relative to internal feedback dynamics and switching frequency), which allows for direct integration into a wider range of analog or digitally controlled power systems using readily available components.

[0024] exist Figure 5 The SGR (Details) box illustrates a detailed dynamic embodiment of the synchronous generalized regulator. The current-controlled bridge power interface is shown along the left edge of the block, including the bus voltage V2 relative to the return RTN2, and the bridge current ICD through the switching bridge nodes VC and VD. The current-controlled bridge is controlled by a differential gate signal gCD generated by a pulse-width modulation (PWM) process controlled by the synchronous average harmonic current (SAHC). The signal level interface of the SAHC PWM process includes: the current command (ICMD), the resulting superimposed duty cycle and phase signals (d2p2), triangular and square waveforms (TRI and SQ), and the secondary harmonic of the command (B2). The current-controlled bridge drive current (ICD) is a function of the current command (ICMD), which is approximately related by power to a linear bus current (120) proportional to the duty cycle (2d2-1). The secondary harmonic command is superimposed on the modulation process signal using a differential harmonic controller (DHC2) that affects the secondary harmonic voltage. The voltage-controlled bridge power interface is shown along the right edge of the SGR (in detail), including the bus voltage V1 relative to the return RTN1, and the bridge voltage VAB across the switching bridge nodes VA and VB. The voltage-controlled bridge is controlled by the differential gate signal gAB generated by the voltage-controlled pulse width modulation process. The signal level interface to the voltage-controlled PWM process includes: voltage command (VCMD), and primary harmonic voltage command to the differential harmonic control process (DHC1). The current flowing through the voltage-controlled bridge is approximately related to the power of the linear bus current (I10) through the duty cycle (2d1-1). The synchronous average harmonic current control attenuates the reactive harmonic current (synchronized with the square wave), generating linearized harmonic coupling through the equivalent harmonic admittance (LEQ) between the bridges. The linearized coupling between the harmonic voltages of each bridge is given by the proportionality constants VMULT2 and VMULT1, which result in the harmonic current (ILEQ) flowing through the LEQ. This can be achieved by using the bridge current proportional signal (i.e., VICD, ...). Figure 2The transmitted harmonic current is estimated by multiplying it by an orthogonal square wave that lags 90 degrees relative to the synchronous square wave used by the SAHC controller. The harmonic power is approximately maintained by balancing the current flowing through each corresponding bus I2X and I1X using the proportionality constants given by IMULT2 and IMULT1. Sufficient degrees of freedom are available to independently control the line current, line voltage, and relative harmonic power flow between buses. The harmonic coupling coefficient of the current-controlled bridge is a function of the duty cycle (d2) and the secondary harmonic command (B2), while the harmonic coupling coefficient of the voltage-controlled bridge is a function of the duty cycle (d1) and the primary harmonic command (B1). Assuming d1 and d2 are functions of the command voltage and current, respectively, the primary and secondary harmonic commands B1 and B2 are the degrees of freedom for adjusting the harmonic power transfer generated between the harmonic coupling voltage and the isolation bridge. The resulting dynamic model approximates the harmonic equivalent of a buck-boost stage for isolated DC-DC power transfer.

[0025] Embodiments of synchronous generalized regulators can independently command line and harmonic coupling, as mathematically described for a representative example by extending the DC and harmonic content of the pulse width modulation process. In one embodiment, the logic gate signal g... A and g B It was generated as:

[0026]

[0027] PWM indicates a pulse width modulation process, and CPWM indicates a complementary pulse width modulation process, in which the input (or output) is transposed. A and g B The subscript indicates the corresponding switch voltage nodes VA and VB associated with switches SA and SB (e.g., Figure 2 As shown). Each pulse width modulation process has a first parameter given by the duty cycle command d1 (as shown). Figure 2 (as shown in the VCMD), and the parameters applied by the second differential generated by the differential harmonic controller. and The differentially applied independent variable represents the superposition of the common triangular waveform and the differential phase command (used in one or more embodiments to control differential harmonics). The steady-state superposition DC of the gate signal and the switching harmonic content are given as follows:

[0028]

[0029] Each term is a weighted DC term (1) and a weighted harmonic basis ( ). The DC weights are superimposed. The DC weights are given by pulse width modulation of the duty cycle signal and complementary pulse width modulation of the duty cycle signal, respectively. The harmonic weights of PWM and CPWM processes have similar amplitudes and are out of phase. For a rectangular function with a specified duty cycle, the harmonic weights are related to the Fourier series, and for time... and normalized differential phase shift The normalized phase over the switching period of the function gives the harmonic basis. For a half-bridge arrangement (which can use g alone) A or g B The harmonic amplitude is directly linked to the duty cycle input, and for a full-bridge configuration, the harmonic amplitude across the transformer coil is based on the difference in the gate signal. The harmonic amplitude can be controlled independently of the duty cycle of the differential modulation process, as follows:

[0030]

[0031] The differential gate signal g AB It is the gate signal g A and g B The difference between them, and the differential phase shift It is a function of harmonic command B1. The differential gate signal has a DC sensitivity (2d1-1) given by the duty cycle, and an AC sensitivity given by the duty cycle and harmonic command. Due to harmonic commands The sensitivity is due to the g of the embodiment A and g B Differential phase cancellation. EQ3A is used to represent harmonic command sensitivity, similar to duty cycle sensitivity, using a linear transformation where the harmonic command ranges between zero and one, with the midpoint at halfway. The range of the DHC circuit can be scaled relative to any setpoint using resistors. Harmonic command B1 allows the sensitivity of the harmonic term to be adjusted independently after considering the duty cycle sensitivity of the control DC term. A similar process can be used to generate the gate signal g. C and g D and their difference g CD The additional superimposed commands for the modulation phase and unmodulated duty cycle are applied by the feedback compensator.

[0032] The following equation illustrates an alternative embodiment where the duty cycle command d1 is close to half (causing the relevant sensitivity term to be close to 1):

[0033]

[0034] This simplifies the EQ4 to have AC sensitivity controlled by harmonic command input. For an alternative embodiment with a duty cycle close to half, the center voltage potential can be inductively coupled to either of the associated nodes (VA or VB). The described embodiment results in a bipolar regulated power supply with positive and negative voltages relative to the center potential and adds very few components. Different unipolar configurations can be developed where the common-mode gate duty cycle is used to modulate harmonics using inverting modulation. The common duty cycle represents a DHC block with the switch omitted, resulting in positive and negative duty cycle commands superimposed on a common triangular waveform, and the negative duty cycle is supplemented to result in a common gate DC potential with inverting harmonic content. Alternating duty cycle methods for commanding harmonic outputs are less preferred than phase command methods because the sensitivity may not be monotonic at some operating points. Additional variations, such as non-complementary PWM processes, are possible, resulting in equivalent gate signal control behavior.

[0035] The dynamic behavior of embodiments of the synchronous generalized regulator (SAHC) is mathematically described using superposition feedback of a synchronous average harmonic current compensator (SAHC). In one or more embodiments, the SAHC compensator utilizes a switched-capacitor filter driven by measurements of the bridge currents. The switched-capacitor filter exhibits linear time-varying characteristics, resulting in a signal path capable of representing two independent degrees of freedom in both modulated and unmodulated reference frames. The measured currents (across bridge switching nodes VC and VD) are given by:

[0036]

[0037] in, It is the conjugate symmetric current frequency response vector. It is the admittance (or current response due to voltage input) vector (e.g., representing) Figure 2 Network 205), and Due to The admittance vector is represented by the parallel combination of the network and the magnetizing inductance. The magnetizing inductance can represent the equivalent magnetizing inductance of the transformer, the inductance connected in series with the line current, or both. The input voltage used to calculate the current is calculated as follows: and This indicates the modulation of each corresponding gate signal and bus voltage using a convolution operator in the frequency domain. The Hadamard multiplication operator... "" indicates element-wise multiplication. The bridge current frequency vector represents the response in the frequency domain, including line current and switching transformer current. SAHC compensator non-modulation path direct feedback. The measured values ​​are used to control the online current, and the modulated path feedback reactive (square wave synchronous) current is used to linearize the coupling admittance between the isolation bridges.

[0038] Synchronous average harmonic current compensator unmodulated feedback control low-frequency bridge (and line) current response. This is achieved by finding the sensitivity of the bridge current to changes in the duty cycle command of the current-controlled bridge (its change...). The unmodulated current loop gain is calculated using [the following method / method]. The current response caused by voltage is determined by admittance. Given, it represents the parallel high-frequency current through the transformer and the low-frequency current through the magnetizing inductor. The unmodulated loop gain is:

[0039]

[0040] Where LG0[f] represents the unmodulated SAHC loop gain at a given frequency exponential, k[f] represents the compensator response, and Y Lm [f] represents the current response through the equivalent magnetizing inductance (connected to a transformer or line, or both), and This represents the pulse width modulation gain of the differential modulation process. The bridge is considered to be current-controlled over a bandwidth where the loop gain is greater than 1. The compensator response is handled by a switched-capacitor filter (e.g., Figure 2 The 210, SAHC) description uses twice the nominal switched capacitor values ​​(C1, C2) and nominal input resistance values ​​(R11, R12) to define the integration frequency. Additional lead-lag dynamics can be achieved by including a resistor-capacitor network connected in parallel with each switched capacitor. For Figure 2 In the embodiment shown, the compensator dynamic k[f] is similar for both unmodulated and modulated feedback loops.

[0041] The superimposed modulation feedback path of the synchronous average harmonic current compensator linearizes the harmonic coupling between the bridge bus voltages. The current flowing into each corresponding voltage bus is calculated by modulating the current at the bridge switching nodes using the bridge gate signal. A concise representation is described for calculating the output bus current, which is modulated relative to the bridge current in response to the modulated input bus voltage:

[0042]

[0043] Where I1[f] and I2[f] represent the bus current response at a given frequency exponential, and V1[f] and V2[f] represent the dynamic voltage disturbance at a given frequency. The expression ( and )and( and This represents the corresponding linearized admittance from the voltage bus input to the current flowing through each bus. The calculation of each linearized admittance term is illustrated by an example of a representative cross-admittance term:

[0044]

[0045] in This represents the second bus current caused by the first bus voltage at each output frequency, and... It is the current response caused by voltage at the selected frequency. EQ8A and EQ8B indicate the response to the gate signal g. CD, k1 Primary harmonics and input disturbance gate signal g AB, k1 The sum of the terms of the first harmonic modulation. The conjugate pairs of signals (one of which has an overbar) represent combinations of first harmonic frequency modulations projected onto the same linearized output frequency response, weighted by the frequency shift admittance vectors respectively. and Conjugate symmetry is used to calculate EQ8B using only positive frequencies, where EQ8B can be interpreted as a function of the switching frequency. conjugate image frequency The weighted sum of the responses at each location.

[0046] The system response is linearized by using modulated feedback to control the gate signal of the current control bridge to minimize the synchronous average harmonic current. The open-loop response (without feedback) given in EQ7A and EQ7B is highly variable, as it may behave like a current source or a voltage source depending on the interaction of the switching frequency and the admittance network. The open-loop characteristics are not ideal for power converters with potentially tolerant reactive admittance network components. The closed-loop response, superimposed with linearized system admittance, synchronously decays the reactive current with the square wave every half switching cycle as follows:

[0047]

[0048] Where I 1：V1 [f] and I 1：V2 [f] represents the first bus current response caused by the corresponding first bus voltage disturbance and second bus voltage disturbance, and I 2：V1 [f] and I 2：V2 [f] denotes the second bus current response resulting from the corresponding first and second bus voltage disturbances. Each response given in EQ9A, EQ9B, EQ9C, and EQ9D is a superposition of the open-loop linearized admittance response and the electronically modified admittance due to feedback control. These equations approximate the dynamic coupling behavior of the synchronous generalized regulator system under the condition that the superimposed modulation feedback loop gain is greater than 1:

[0049]

[0050] Wherein, the modulation feedback loop gain LG1[f] is the linearization constant g, the compensator gain k[f], and the linearization admittance. The product of the two. Loop gain is the gain from the phase command input to the compensated modulation bridge current. Linearized admittance. This represents the modulation current response generated due to the modulation phase command input, where g SQ It is approximately orthogonal to g AB and g CD The synchronous square wave. EQ10A is calculated using a method similar to EQ8B, where the terms reflecting the input and output modulation of the synchronous square wave are replaced. The linearization constant g reflects the amplitude sensitivity of the harmonic filter pulse width modulation process. Embodiments with a loop gain less than 1 can be used for power converters with high impedance between control buses, and embodiments with a loop gain greater than 1 approximate... Figure 5 The low-impedance coupling dynamics are shown.

[0051] The closed-loop response of the synchronous generalized regulator system (for modulation loop gain greater than 1) is described by combining the system equations given by EQ9A, EQ9B, EQ9C, and EQ9D, the linearized modulation described in EQ8B, and the harmonic expansion given in EQ3. The linearized cross-admittance term... and , and This represents the frequency response pair conjugate to the switching frequency, as shown in EQ8B. The cross-admittance term represents the minimum symmetry error when the frequency response is conjugate symmetric about the switching frequency, such as when the switching frequency is aligned with the natural frequency of the resonant admittance network. For loop gains greater than 1, the effect of control is to superimpose admittance terms that actively adjust the total electronic admittance to have a natural frequency aligned with the switching frequency. At this operating point, the sum of the active and passive admittances is conjugate symmetric about the switching frequency, resulting in linearized admittance exhibiting inductance (similar to the admittance of a resonant network sampled above the resonant frequency). Equivalent harmonic linearized admittance network (e.g., using LEQ, Figure 5 As shown below:

[0052]

[0053] Where Y LEQ R0 is the linearized harmonic admittance, R0 is the resistance of the switch and passive components, and L is the resistance of the passive components. R It is the inductance associated with the admittance network. The current flowing through the effective linearized harmonic admittance is determined by I. LEQ [f] gives, I LEQ[f] The harmonic admittance is calculated by taking the difference between the harmonic-weighted input voltages and projecting it onto the linearized harmonic admittance. The harmonic-transferred current is linearized by attenuating the reactive current using a synchronous average harmonic current control process that reduces the current synchronized with the square wave switching cycle. The harmonic-transferred current is not measured directly in the linearized reference frame, but is estimated by modulating the bridge current with an orthogonal square wave with a 90-degree delay relative to the synchronous square wave used by the SAHC compensator. The current calculated in EQ11B is related to the current-limiting process in the safe operating area, such as hysteresis or cycle-by-cycle current limiting. The current flowing through each bus is calculated using harmonic weights, which represent the output current due to input voltage disturbances as a function of the equivalent linearized harmonic current:

[0054]

[0055] Among them, the corresponding bus currents I1[f] and I2[f] are harmonic transfer currents I LEQ The weighted function of [f].

[0056] The behavior of the synchronous generalized regulator can be approximated using EQ12A and EQ12B for balanced current flow as follows:

[0057]

[0058] The steady-state ratio between the bus voltages is proportional to the sine of the corresponding duty cycle and harmonic command. The relationship shown in EQ13 is provided for transformers with a unity turns ratio, and the equations and dynamics can be scaled for arbitrary turns ratios while maintaining power. Terms B1 and B2 denote harmonic buck and boost commands, which can be used to regulate the relative bus voltage using a feedforward process or feedback relative to a reference with a voltage error amplifier.

[0059] Detailed dynamic implementation of harmonic current control of a synchronous generalized regulator is in Figure 6 As shown in the figure, Figure 5 The SGR (details) block is enhanced using quadrature current control to form Figure 6 The SGR (IQC) block. Figure 6 The dynamic embodiments are descriptively similar to Figure 5In the embodiment shown, the harmonic commands (B1 and B2) are controlled by an added quadrature current control block (IQC). The quadrature current control block uses a precision diode (PD) stage to adjust the harmonic commands to generate buck and boost harmonic signals, which reduces the tracking error between the estimated harmonic current (ILEQ) and the command current (IQCMD). The precision diode can be implemented using active operational amplifier circuitry according to the prior art, or using alternative complementary signal separation circuitry (such as those known in the field of solid-state power amplification). Figure 6 The estimated harmonic current shown is a linearized measurement, which can be obtained by converting the measured values ​​of the bridge current (e.g., ...) Figure 2 The harmonic current is calculated by multiplying the VICD (current transmitted in harmonics) by an orthogonal square wave (QSQ) synchronized with the harmonic current transmitted. The synchronous average harmonic current compensator attenuates the reactive current from the current sensor signal (synchronized with the square wave), resulting in the harmonic current signal primarily consisting of the transmitted current (synchronized with the orthogonal square wave). The transmitted harmonic current command (IQCMD) can be used to control isolated harmonic power sharing between one or more synchronous generalized regulators. The analog level command (IQCMD) can be driven to regulate one or more bus voltages, and the bandwidth requirement of the command signal is minimal, allowing for simple analog control of multiple modules or low-bandwidth commercial digital control.

[0060] Figure 7 An embodiment of a synchronous generalized regulator is shown, which is commanded to use stored power to regulate the output under low line voltage conditions. Figure 7 The interface terminals of the SGR block are descriptively similar to those of the SGR block. Figure 4 The interface terminals shown in the SGR block have command inputs for handling low line voltage conditions. Under low line voltage conditions (given by VAC2 equal to zero), detectable by existing audio power amplification techniques, the command current (ICMD) is set to zero to reflect the absence of line power. In this configuration, feedforward regulation (700) is achieved by driving a reference voltage (VREF) to the line voltage command (VCMD) and harmonic command (B2) configured as a buck input. This reference voltage can be a sine wave or other output waveform according to existing techniques. Under these conditions, DC buses V1 and V2 are approximately equal. The resulting configuration regulates the line output relative to an internal energy source (stored energy represented by capacitors CS1 and CS2) without requiring additional power components. Figure 7 The adjustment relationship shown is given by the following formula:

[0061]

[0062] The voltage command (VCMD) controlling d1 is set equal to the harmonic suppression command B2, causing V2 to track V1 using a feedforward harmonic relationship. With the current control line connection at zero volts, control is simplified by setting other adjustment degree-of-freedom constants (d2=0.5 and B1=0.5). The output line voltage (VAC1) tracks the voltage command (VCMD) proportionally to the tracking bus voltage.

[0063] and Figure 7 In contrast to the feedforward embodiment shown, an alternative feedback embodiment can be used to automatically adjust the converter output without needing to detect losses due to line voltage conditions. Figure 5 Harmonic voltage controlled synchronous generalized regulator or Figure 6 The harmonic current-controlled synchronous generalized regulator can be further integrated into the power system, which commands the harmonic power flow to regulate the isolated bus voltage using a voltage feedback error amplifier. In embodiments where the bus voltage is regulated, the corresponding current and voltage line commands (ICMD and VCMD) can be directly used to control the corresponding isolated line connections. In other embodiments, power factor correction can be performed using current shaping based on line current commands or harmonic current transfer commands.

[0064] Soft-start implementation of a single-stage synchronous generalized regulator in Figure 8 As shown in [the image]. According to [the image]... Figure 8 In one embodiment, the current-controlled bridge has multiple bus voltage connections that are separated between V2S and a voltage bus V2 associated with energy storage. Current can be transferred between the separated voltage buses using a current command (ICMD). In this configuration, the current-controlled bridge line voltages are closed, and the voltage-controlled bridge line voltages have open-circuit connections, thus the power converter acts as a DC / DC converter with a command soft-start current to the energy storage element (CS2). Figure 8 and Figure 2 The embodiments shown are different because Figure 8The voltage bus connection between the bus connection nodes of switches SC and SD (at the current control bridge 602) is separated. This separation of the bus connection allows command current flow between buses V2S and V2 via inductor L5 and isolated power transfer via transformer coil LT2. The embodiment is further simplified by setting L5 to be given by the magnetizing inductance associated with coil LT2, resulting in the same magnetic element serving both functions. The illustrated embodiment also shows that the synchronous generalized regulator can be configured as a DC / DC converter by closing the current control line and opening the voltage control line. Assuming the current is regulated by a current command, harmonic commands (B2 and B1) can be used to buck and boost the output to the isolated bus voltage V1. The remaining blocks (801, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812) are descriptively similar to... Figure 2 Those shown in (201, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212). Figure 8 The illustrated embodiment has a harmonic bus voltage regulation relationship:

[0065]

[0066] The relative duty cycle of the current-controlled bridge is controlled by the SAHC controller, and the remaining harmonic (B1 and B2) and duty cycle (d1) command degrees of freedom are free for voltage regulation. Figure 7 and Figure 8 The embodiments shown are intended to illustrate possible configurations, and further adaptations are possible using multiple regulation connections provided by the synchronous generalized regulator.

[0067] While specific embodiments have been shown and described herein, it should be understood that various other changes and modifications may be made without departing from the spirit and scope of the claimed subject matter. Furthermore, although various aspects of the claimed subject matter have been described herein, these aspects need not be used in combination. Therefore, the appended claims are intended to cover all such changes and modifications within the scope of the claimed subject matter. Claims (as amended under Article 19 of the Treaty) 1. A power converter, comprising: A voltage-controlled bridge includes a plurality of first switches, wherein one or more first switch nodes of the voltage-controlled bridge are coupled to: a first transformer winding of a transformer assembly and a line voltage; A current-controlled bridge includes multiple second switches, wherein one or more second switch nodes of the current-controlled bridge are coupled to: the second transformer winding of the transformer unit and the line current; At least one first voltage controller circuit is configured to use the plurality of first switching devices to control the line voltage relative to a command voltage and to change the primary harmonic voltage relative to a primary harmonic command. At least one second current controller circuit is configured to use the plurality of second switching devices to control the bridge current relative to the command current and to change the secondary harmonic voltage relative to the secondary harmonic command. Admittance network, including inductive admittance or capacitive admittance or resonant inductive admittance and capacitive admittance, wherein the admittance network is coupled to a first transformer winding or a second transformer winding; and The modulation loop gain, coupled phase command input, and synchronously modulated bridge current are used to linearize the coupling admittance between the primary harmonic voltage and the secondary harmonic voltage, which is linearized to approximate the effective induced harmonic admittance over the bandwidth where the modulation loop gain is greater than 1. 2. The power converter of claim 20, wherein the synchronous average harmonic current compensator further comprises a switched capacitor filter configured to synchronously integrate and compensate the current error signal on each half of the square wave switching cycle, and employing the switched capacitor output to generate superimposed modulated and unmodulated feedback signals. 3. The power converter according to claim 20, wherein the synchronous average harmonic current compensator further comprises an analog multiplication phase-locked loop, wherein the analog multiplication phase-locked loop further comprises an analog multiplication phase detector, the analog multiplication phase detector synchronously modulates the current error signal through a multiplication process in each half-switching cycle to drive an integral error amplifier, and wherein the integral error amplifier controls a voltage-controlled oscillator to provide feedback on the modulated waveform. 4. The power converter of claim 1, wherein the first voltage controller circuit or the second current controller circuit or the first voltage controller circuit and the second current controller circuit further comprises a harmonic command circuit, the harmonic command circuit being configured to command a pulse width modulation process to modify harmonic coupling relative to a harmonic command. 5. The power converter of claim 1, wherein the command voltage and the primary harmonic command are related, or the command voltage and the primary harmonic command are independent. 6. The power converter of claim 1, wherein the current feedback signal and the secondary harmonic command are related, or the current feedback signal and the secondary harmonic command are independent. 7. The power converter according to claim 1, wherein one or more of the following: a voltage command, a current command, a primary harmonic command, and a secondary harmonic command are generated according to a feedforward regulation circuit. 8. The power converter of claim 1, wherein a feedback mechanism is used to change the primary harmonic voltage or the secondary harmonic voltage or the primary harmonic voltage and the secondary harmonic voltage, wherein the feedback mechanism reduces the error between the estimated harmonic transmission current and the commanded harmonic current or reduces the error between the measured voltage and the reference voltage. 9. The power converter of claim 1, wherein the line voltage is coupled to an open circuit and the voltage command is set to an adjustment input. 10. The power converter of claim 1, wherein the line current is coupled to a closed circuit and the current command is set to an adjustment input, or the line current is freely controlled by an independent element and the current command is set to an adjustment input. 11. The power converter of claim 1, wherein the first transformer winding or the second transformer winding or both the first transformer winding and the second transformer winding further comprises one or more line filter elements. 12. The power converter of claim 1, wherein the transformer device has a distributed inductance, the distributed inductance participating in the admittance network, or one or more line filters, or the admittance network and the one or more line filters. 13. The power converter of claim 1, wherein the measurement of the current across the bridge switching node includes transformer current and line current, or includes transformer current, wherein the line current is controlled by a separate circuit or component. 14. The power converter of claim 1, wherein the first plurality of switches or the second plurality of switches or the first plurality of switches and the second plurality of switches are coupled to one or more energy storage elements. 15. The power converter of claim 1, wherein one or more of the following are generated by an analog controller as part of a power system: voltage commands, current commands, primary harmonic commands, and secondary harmonic commands. 16. The power converter of claim 1, wherein one or more of the following are included: voltage commands, current commands, primary harmonic commands, and secondary harmonic commands generated by a digital controller as part of a power system. 17. The power converter of claim 1, wherein the current control bridge is coupled to a discrete bridge circuit, the discrete bridge circuit further comprising a plurality of discrete switches coupled to a discrete voltage bus. 18. A method comprising: The line voltage and the primary harmonic coupling voltage of the voltage-controlled bridge are controlled by a voltage-controlled pulse width modulation process. The admittance network is linearized using the modulation loop gain between the phase command input and the compensated modulation bridge current to couple the primary harmonic coupling voltage and the secondary harmonic coupling voltage across the effective linearized inductor harmonic admittance over a bandwidth where the modulation loop gain is greater than 1. The bridge current and the secondary harmonic coupling voltage of the current-controlled bridge are controlled using a pulse width modulation process; and Harmonic gain is independently commanded using harmonic commands, wherein the harmonic commands include a primary harmonic command that changes the primary harmonic coupling voltage, or a secondary harmonic command that changes the secondary harmonic coupling voltage, or a primary harmonic command that changes the primary harmonic coupling voltage and a secondary harmonic command that changes the secondary harmonic coupling voltage. 19. The method of claim 18, further comprising: The current control bridge is used to transfer current between the voltage divider bus and the energy storage element. 20. The power converter of claim 1, further comprising a synchronous average harmonic current compensator, the synchronous average harmonic current compensator including a feedback circuit that reduces a synchronously averaged current error signal at each half of the switching cycle by changing the modulation waveform of at least one of the first controller circuit or the second controller, the current error signal including the error between the command current and the current measurement value of the bridge switching node.

Claims

1. A power converter, comprising: A voltage-controlled bridge includes a plurality of first switches, wherein one or more first switch nodes of the voltage-controlled bridge are coupled to: a first transformer winding of a transformer assembly and a line voltage; A current-controlled bridge includes a second plurality of switches, wherein one or more second switch nodes of the current-controlled bridge are coupled to: a second transformer winding of a transformer assembly and line current; At least one first voltage controller circuit is configured to use the first plurality of switching devices to control the line voltage relative to a command voltage and to change the primary harmonic voltage relative to a primary harmonic command. At least one second current controller circuit is configured to control the bridge current using the second plurality of switching devices and to change the secondary harmonic voltage relative to a secondary harmonic command; Admittance network, including inductive admittance or capacitive admittance or resonant inductive admittance and capacitive admittance, wherein the admittance network is coupled to a first transformer winding or a second transformer winding; and A synchronous average harmonic current compensator includes a feedback circuit that reduces a synchronously averaged current error signal over each half-switching cycle by altering the modulation waveform of at least one of a first controller circuit or a second controller circuit. The current error signal includes the error between the command current and the current measurement value across the bridge switching node. The synchronous average harmonic current compensator also couples the modulated loop gain between the phase command input and the synchronously modulated bridge current to linearize the coupling admittance between the primary harmonic voltage and the secondary harmonic voltage. The coupling admittance is linearized to approximate the equivalent induced harmonic admittance over a bandwidth where the modulated loop gain is greater than 1.

2. The power converter according to claim 1, wherein, The synchronous average harmonic current compensator further includes a switched capacitor filter configured to synchronously integrate and compensate the current error signal over each half-square wave switching cycle, and to sample the switched capacitor output to generate superimposed modulated and unmodulated feedback signals.

3. The power converter according to claim 1, wherein, The synchronous average harmonic current compensator further includes an analog multiplication phase-locked loop, wherein the analog multiplication phase-locked loop further includes an analog multiplication phase detector, wherein the analog multiplication phase detector synchronously modulates the current error signal through a multiplication process in every half switching cycle to drive an integral error amplifier, and wherein the integral error amplifier controls a voltage-controlled oscillator to provide feedback on the modulated waveform.

4. The power converter according to claim 1, wherein, The first voltage controller circuit or the second current controller circuit or the first voltage controller circuit and the second current controller circuit further include a harmonic command circuit, which is configured to command a pulse width modulation process to modify harmonic coupling relative to a harmonic command.

5. The power converter according to claim 1, wherein, The command voltage and the primary harmonic command are related, or the command voltage and the primary harmonic command are independent.

6. The power converter according to claim 1, wherein, The current feedback signal and the secondary harmonic command are related, or the current feedback signal and the secondary harmonic command are independent.

7. The power converter according to claim 1, wherein, The feedforward control circuit generates one or more of the following: voltage command, current command, primary harmonic command, and secondary harmonic command.

8. The power converter according to claim 1, wherein, The feedback mechanism is used to change the primary harmonic voltage or the secondary harmonic voltage or both the primary and secondary harmonic voltages, wherein the feedback mechanism reduces the error between the estimated harmonic transmission current and the commanded harmonic current or reduces the error between the measured voltage and the reference voltage.

9. The power converter according to claim 1, wherein, The line voltage is coupled to an open circuit and the voltage command is set to the regulation input.

10. The power converter according to claim 1, wherein, The line current is coupled to a closed circuit and the current command is set to the regulating input, or the line current is freely controlled by an independent element and the current command is set to the regulating input.

11. The power converter according to claim 1, wherein, The first transformer winding or the second transformer winding, or both the first transformer winding and the second transformer winding, further include one or more line filter elements.

12. The power converter according to claim 1, wherein, The transformer device has a distributed inductance, which participates in the admittance network, or one or more line filters, or the admittance network and the one or more line filters.

13. The power converter according to claim 1, wherein, The measured current at the bridge switching node includes both transformer current and line current, or includes transformer current, wherein the line current is controlled by a separate circuit or component.

14. The power converter according to claim 1, wherein, The first plurality of switches or the second plurality of switches or the first plurality of switches and the second plurality of switches are coupled to one or more energy storage elements.

15. The power converter according to claim 1, wherein, The analog controller, which is part of the power system, generates one or more of the following: voltage command, current command, primary harmonic command, and secondary harmonic command.

16. The power converter according to claim 1, wherein, The digital controller, which is part of the power system, generates one or more of the following: voltage command, current command, primary harmonic command, and secondary harmonic command.

17. The power converter according to claim 1, wherein, The current-controlled bridge is coupled to a discrete bridge circuit, which further includes discrete multiple switches coupled to a discrete voltage bus.

18. A method comprising: The line voltage and the primary harmonic coupling voltage of the voltage-controlled bridge are controlled by a voltage-controlled pulse width modulation process. The admittance network is linearized using the modulation loop gain between the phase command input and the compensated modulation bridge current, so as to couple the primary harmonic coupling voltage and the secondary harmonic coupling voltage across the equivalent linearized inductor harmonic admittance over a bandwidth where the modulation loop gain is greater than 1. The bridge current and the secondary harmonic coupling voltage of the current-controlled bridge are controlled using a pulse width modulation process; and Harmonic gain is independently commanded using harmonic commands, wherein the harmonic commands include a primary harmonic command that changes the primary harmonic coupling voltage, or a secondary harmonic command that changes the secondary harmonic coupling voltage, or a primary harmonic command that changes the primary harmonic coupling voltage and a secondary harmonic command that changes the secondary harmonic coupling voltage.

19. The method of claim 18, further comprising: The current control bridge is used to transfer current between the voltage divider bus and the energy storage element.

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