Radio frequency integrated circuit structure, heterojunction bipolar transistor and method of manufacturing the same

Abstract

The application discloses a radio frequency integrated circuit structure, a heterojunction bipolar transistor and a preparation method thereof. The radio frequency integrated circuit structure comprises a collector epitaxial layer, a base step, a surface passivation layer and a base metal. The collector epitaxial layer is provided with an active region and an isolation region. The base step is arranged on the collector epitaxial layer and located in the active region. The surface passivation layer covers the base step and the collector epitaxial layer. The surface passivation layer is provided with a first windowing position and a second windowing position. The first windowing position exposes the base step. The second windowing position exposes the collector epitaxial layer located in the isolation region. The base metal is arranged on the surface passivation layer and located on the surface and the sidewall of the base step and extends to the isolation region. The first end of the base metal forms an ohmic contact with the base step. The second end of the base metal is in contact with the collector epitaxial layer. The application can effectively improve the adhesion reliability of the base metal without significantly changing the existing device structure and standard process flow, so as to balance high performance, high reliability and process compatibility.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing technology, and in particular to a radio frequency integrated circuit structure, a heterojunction bipolar transistor, and a method for fabricating the same. Background Technology

[0002] Gallium arsenide heterojunction bipolar transistors (HBTs), especially indium gallium phosphide / gallium arsenide HBTs, often employ emitter edge mesa passivation structures to improve reliability, using base metal systems based on diffusing metals such as platinum, palladium, or nickel to achieve good ohmic contact with indium gallium phosphide and gallium arsenide. However, in high-frequency processes, to reduce the base-collector junction capacitance (Cbc), the base mesa needs to be reduced in size and a silicon nitride passivation layer needs to be introduced, extending the base metal overlay step into the isolation region. However, the adhesion between diffusing base metal systems such as platinum / palladium and the silicon nitride passivation layer is extremely poor, making them prone to warping or peeling under thermal or mechanical stress, severely damaging device performance, yield, and long-term reliability, and becoming a key bottleneck restricting the development of this technology. Summary of the Invention

[0003] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes a radio frequency integrated circuit structure, a heterojunction bipolar transistor, and a method for fabricating the same, which can effectively improve the adhesion reliability of the base metal without significantly changing the existing device structure and standard process flow, thus achieving a balance between high performance, high reliability, and process compatibility.

[0004] In a first aspect, embodiments of the present invention provide a radio frequency integrated circuit structure, comprising: The collector epitaxial layer is provided with an active region and an isolation region; A base step is disposed on the collector epitaxial layer and located in the active region; A surface passivation layer covers the base step and the collector epitaxial layer. The surface passivation layer is provided with a first window and a second window. The first window exposes the base step, and the second window exposes the collector epitaxial layer located in the isolation region. A base metal is disposed on the surface passivation layer and located on the surface and sidewall of the base step and extending to the isolation region. The first end of the base metal forms an ohmic contact with the base step through the first window position, and the second end of the base metal is connected to the collector epitaxial layer through the second window position.

[0005] According to some embodiments of the present invention, an emitter step is provided on the base step, and an emitter metal is provided on the emitter step.

[0006] According to some embodiments of the present invention, the surface passivation layer includes a first passivation layer covering the base step, the emitter step, and the emitter metal.

[0007] According to some embodiments of the present invention, the surface passivation layer further includes a second passivation layer, which covers the first passivation layer, the sidewall of the base step, and the collector epitaxial layer.

[0008] According to some embodiments of the present invention, the second end of the base metal is used as a capacitor plate or an upper metal connection point.

[0009] Secondly, embodiments of the present invention provide a heterojunction bipolar transistor, including the above-described radio frequency integrated circuit structure.

[0010] Thirdly, embodiments of the present invention provide a method for fabricating a heterojunction bipolar transistor, comprising: A first semi-finished product is provided, the first semi-finished product comprising a collector epitaxial layer, a base step and a surface passivation layer, wherein the collector epitaxial layer is provided with an active region and an isolation region, the base step is disposed on the collector epitaxial layer and located in the active region, and the surface passivation layer covers the base step and the collector epitaxial layer; A first window and a second window are etched on the surface passivation layer to obtain a second semi-finished product; the first window exposes the base step, and the second window exposes the collector epitaxial layer located in the isolation region; A base metal is deposited on the second semi-finished product to obtain a third semi-finished product; the base metal is deposited on the surface passivation layer and is located on the surface and sidewall of the base step and extends to the isolation region; the first end of the base metal forms an ohmic contact with the base step through the first window position; and the second end of the base metal is connected to the collector epitaxial layer through the second window position.

[0011] According to some embodiments of the present invention, the provision of the first semi-finished product includes: An initial semi-finished product is provided, the initial semi-finished product comprising an initial collector epitaxial layer and an initial base layer stacked sequentially; A first passivation layer is deposited in the predetermined patterned area of ​​the initial base layer to cover the patterned area and expose the remaining non-patterned area; The non-patterned areas of the initial substrate are etched to form the base step and expose the target area of ​​the initial collector epitaxial layer; An isolation region is formed in the target region of the initial collector epitaxial layer by ion implantation, so as to form a collector epitaxial layer with an active region and an isolation region.

[0012] According to some embodiments of the present invention, the step of forming an isolation region in a target region of the initial collector epitaxial layer by ion implantation to form a collector epitaxial layer having an active region and an isolation region further includes: A second passivation layer is deposited to form a surface passivation layer covering the base step and the collector epitaxial layer.

[0013] According to some embodiments of the present invention, the initial semi-finished product further includes an initial emission layer laminated on the initial base layer, and the provision of the initial semi-finished product further includes: Electrode metal is deposited on the initial emission layer; The emitter metal and the initial emitter layer are etched to form emitter steps.

[0014] The embodiments of the present invention have at least the following beneficial effects: The surface passivation layer covers the base step and collector epitaxial layer area, providing effective protection and a continuous wiring path for the base metal. This allows the base metal to extend from the base step through the sidewall to the isolation region of the collector epitaxial layer, helping to reduce the active area of ​​the device while maintaining the original electrical performance. A first and second window are provided on the surface passivation layer to expose the collector epitaxial layer surfaces of the base step and the isolation region, respectively. This allows the two ends of the base metal to be anchored at both ends through the first and second window. Even if there is localized poor adhesion in the middle area of ​​the base metal, it can still maintain overall stability under thermal or mechanical stress, effectively preventing warping or peeling. This reduces the risk of failures such as open circuits or performance degradation caused by base metal breakage or detachment, improving device reliability. Furthermore, it eliminates the need for new materials, additional photomasks, or complex process steps, ensuring good compatibility with existing standard processes, thus balancing high performance, high reliability, and process compatibility.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the schematic diagrams of an existing radio frequency integrated circuit structure; Figure 2 This is one of the schematic diagrams of the radio frequency integrated circuit structure according to an embodiment of the present invention; Figure 3 This is a flowchart illustrating the steps of a heterojunction bipolar transistor fabrication method according to an embodiment of the present invention. Figure 4This is one of the schematic diagrams of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 5 This is a second schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 6 This is a third schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 7 This is a fourth schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 8 This is the fifth schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 9 This is a schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention; Figure 10 This is the seventh schematic diagram of a heterojunction bipolar transistor according to an embodiment of the present invention.

[0017] Figure label: Collector epitaxial layer 100, active region 101, isolation region 102, initial collector epitaxial layer 110, base step 200, initial base layer 210, surface passivation layer 300, first window position 301, second window position 302, first passivation layer 310, second passivation layer 320, base metal 400, emitter step 500, emitter metal 600. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0020] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc. are understood to exclude the stated number, and "above," "below," "within," etc. are understood to include the stated number. If "first," "second," etc. are used in the description, they are only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features or the order of the indicated technical features.

[0021] In the description of this invention, unless otherwise explicitly defined, terms such as "set", "install", and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0022] Gallium arsenide heterojunction bipolar transistors (HBTs), especially indium gallium phosphide / gallium arsenide HBTs (InGaP / GaAs HBTs), have become key devices in wireless communication and other fields due to their high electron mobility, high cutoff frequency, and excellent RF performance. In these devices, the use of emitter edge mesa passivation structures is one of the core technologies for improving reliability. This structure effectively suppresses surface carrier recombination, thereby reducing non-ideal base current, significantly improving device reliability and extending its operating life. In this structure, to achieve high-performance base ohmic contacts, a diffusing metal (platinum, palladium, nickel, etc.) base system is typically used as the base metal. This reacts with indium gallium phosphide (InGaP) and gallium arsenide (GaAs) to form a stable and reliable ohmic contact. However, in the pursuit of higher frequency characteristics, to reduce the base-collector junction capacitance (Cbc), a dielectric such as silicon nitride is introduced as a passivation layer. The base metal can then cross the base step and extend over the isolation region of the collector epitaxial layer. Please refer to [reference needed]. Figure 1 The collector epitaxial layer 100 has an active region 101 and an isolation region 102. The base metal 400 is disposed on the passivation layer (as shown by label P4), and the first end of the base metal 400 (as shown by label P1) forms an ohmic contact with the base step 200 through the window of the passivation layer, while the second end of the base metal 400 (as shown by label P2) extends to the isolation region 102 of the collector epitaxial layer 100. However, the adhesion between the diffusive base metal system with a platinum / palladium substrate and the silicon nitride passivation layer is extremely poor. In subsequent processes or reliability tests, the poorly adhered metal layer is prone to lifting or peeling due to thermal and mechanical stress. This problem not only leads to device performance degradation and reduced manufacturing yield, but also seriously threatens the long-term reliability of the circuit, becoming a key bottleneck restricting technological development.

[0023] To address the issues of metal warpage, delamination, and even device failure caused by insufficient interfacial adhesion between the base metal and the silicon nitride passivation layer, the industry has conducted research and proposed several improvement schemes through multiple technical approaches. Typical technical concepts include the following three categories: (1) Introducing an interfacial adhesion layer: One or more transition metal materials (such as titanium, chromium, tantalum, tungsten or their alloys) are placed between the base metal and the silicon nitride passivation layer as an adhesion layer. This adhesion layer can improve the wettability of the silicon nitride surface and buffer the interfacial stress under thermal cycling or mechanical stress, thereby improving the bonding strength and long-term reliability of the overall structure.

[0024] (2) Surface modification treatment of passivation layer: The surface of silicon nitride passivation layer is pretreated by plasma activation (such as oxygen plasma, ammonia plasma), ultraviolet ozone treatment, chemical surface functionalization or other interface engineering methods to improve the surface energy of silicon nitride passivation layer or introduce functional groups that are conducive to metal nucleation, thereby enhancing the physical / chemical bonding ability between the subsequently deposited base metal and silicon nitride passivation layer.

[0025] (3) Material system innovation: On the one hand, explore the use of non-precious metals or composite metal stacks (such as nickel-germanium-titanium-platinum-gold multilayer structures) to replace the traditional base metal system based on platinum and palladium, while maintaining good ohmic contact performance and optimizing its interfacial compatibility with the passivation medium; on the other hand, try to partially or completely replace silicon nitride as the passivation layer with low-stress, high-adhesion alternative dielectric materials (such as alumina, silicon oxynitride or atomic layer deposited dielectric materials), so as to alleviate the problem of poor adhesion from the perspective of the intrinsic properties of the material.

[0026] However, the aforementioned technical concepts generally share a common challenge: implementation typically involves structural reconfiguration of critical areas of the device, addition of new process modules, or fundamental adjustments to the metal / dielectric material system. Such modifications can not only affect the core electrical performance of heterojunction bipolar transistors (such as base contact resistance and parasitic capacitance), but more importantly, they often struggle to achieve seamless compatibility with current mainstream heterojunction bipolar transistor standard manufacturing processes. This leads to a significant increase in process complexity and yield fluctuation risks, thereby limiting their practical application value in large-scale mass production environments.

[0027] Therefore, there is an urgent need for a technical solution that can effectively improve the adhesion reliability of the base metal without significantly changing the existing device structure and standard process flow, so as to take into account the three core requirements of high performance, high reliability and process compatibility.

[0028] Please refer to Figure 2The radio frequency integrated circuit structure disclosed in this embodiment includes a collector epitaxial layer 100, a base step 200, a surface passivation layer 300, and a base metal 400. The collector epitaxial layer 100 has an active region 101 and an isolation region 102. The base step 200 is disposed on the collector epitaxial layer 100 and located in the active region 101. The surface passivation layer 300 covers the base step 200 and the collector epitaxial layer 100. The surface passivation layer 300 has a first window position 301 and a second window position 302. The first window position 301 exposes the base step 200, and the second window position 302 exposes the collector metal located in the isolation region 102. The electrode epitaxial layer 100 has a base metal 400 disposed on the surface passivation layer 300 and located on the surface and sidewalls of the base step 200 (as shown by label P3) and extending to the isolation region 102. The first end of the base metal 400 (as shown by label P1) forms an ohmic contact with the base step 200 through the first window position 301, and the second end of the base metal 400 (as shown by label P2) is connected to the collector epitaxial layer 100 through the second window position 302.

[0029] The active region 101 forms the functional area of ​​the active device, while the isolation region 102 is used to achieve electrical isolation between adjacent active devices to prevent adverse effects such as current crosstalk, parasitic coupling, or leakage, ensuring that each active device can operate independently and stably. The base step 200, as a key component of the active device, is disposed in the active region 101 of the collector epitaxial layer 100, and is located in the vertical direction (i.e.,...). Figure 2 The base step 200 protrudes from the surface of the collector epitaxial layer 100 (as shown in the vertical direction), thus having a defined upper surface and sidewall structure. The surface passivation layer 300 covers the upper surface and sidewalls of the base step 200 and the remaining area of ​​the collector epitaxial layer 100, which includes the portion of the active region 101 not covered by the base step 200 and the entire isolation region 102.

[0030] In conventional integrated circuit manufacturing practices, the surface passivation layer 300 is typically composed of dielectric materials such as silicon nitride. Its main function is to provide physical protection and environmental isolation for the underlying semiconductor structure (such as the base step 200 and the collector epitaxial layer 100), preventing environmental moisture, ion contamination, and mechanical damage. Therefore, the industry generally follows the "minimum windowing" principle, which means that windows are only opened at locations where electrical interconnection is necessary (such as metal-metal pads and metal-epitaxy layer contacts). The remaining areas should maintain the integrity of the passivation layer as much as possible to avoid introducing potential leakage paths or weakening the isolation effect. This is especially true in the isolation region 102, because the isolation region 102 is designed to provide electrical isolation, i.e., an electrically "non-connected" region. Traditional processes not only do not set metal leads in the isolation region 102, but also do not perform windowing treatment on the passivation layer covering the isolation region 102.

[0031] Under the influence of the aforementioned inherent understanding, when faced with the technical problems of metal warping, peeling and even device failure caused by insufficient interfacial adhesion between the base metal 400 and the silicon nitride passivation layer, the mainstream solutions in the industry focus on introducing an interfacial adhesion layer, optimizing the surface properties of the passivation layer or developing new materials, without noticing that mechanical anchoring can enhance the adhesion of the base metal 400.

[0032] In addressing the aforementioned technical issues, this embodiment does not follow the mainstream technical concept in the industry. Instead, it provides a first window position 301 and a second window position 302 on the surface passivation layer 300. The first window position 301 is located on the upper surface of the base step 200 to expose a local portion of the upper surface of the base step 200. The second window position 302 is located in the isolation region 102 of the collector epitaxial layer 100 to expose a local portion of the surface of the collector epitaxial layer 100 located in the isolation region 102. The base metal 400 is formed on the surface passivation layer 300 and extends along the upper surface of the base step 200 through the sidewall of the base step 200 to the isolation region 102 covered by the surface passivation layer 300, ultimately covering the second window position 302. Thus, the first end of the base metal 400 forms an ohmic contact with the base step 200 through the first window position 301, realizing normal base electrical signal input; while the second end of the base metal 400 establishes a physical connection with the collector epitaxial layer 100 located in the isolation region 102 through the second window position 302, so that the second end of the base metal 400 is no longer entirely attached to the poorly adhesive silicon nitride passivation layer, but is partially or entirely anchored to the collector epitaxial layer 100 with better interface bonding performance. It should be noted that the connection of the second end of the base metal 400 is not used for conducting signals or current, but to realize a purely mechanical anchoring function. That is, there is no electrical path between the second end of the base metal 400 and the collector epitaxial layer 100 of the isolation region 102. The adhesion and stress resistance of the overall structure are enhanced only through physical contact, which can improve the adhesion performance of the base metal 400 without sacrificing the electrical isolation performance.

[0033] The radio frequency integrated circuit structure of this embodiment can be realized based on existing semiconductor manufacturing processes without introducing new materials or developing additional complex processes, and without adding additional photomasks. It can be optimized by specifically designing the existing layout, such as reasonably defining the position and size of the second window position 302 in the isolation region 102, to be compatible with existing standard processes and avoid problems such as yield fluctuations, equipment adaptation or cost increases caused by process changes.

[0034] Therefore, the surface passivation layer 300 covers the base step 200 and the collector epitaxial layer 100 region, providing effective protection and a continuous wiring path for the base metal 400. This allows the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102 of the collector epitaxial layer 100, helping to reduce the area of ​​the active region 101 of the device while maintaining the original electrical performance. A first window position 301 and a second window position 302 are provided on the surface passivation layer 300 to expose the base step 200 and the collector epitaxial layer 100 surface of the isolation region 102, respectively, allowing the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102. The two ends of the base metal 400 are anchored at both ends through the first window position 301 and the second window position 302. Even if there is local adhesion failure in the middle area of ​​the base metal 400, the base metal 400 can still maintain overall stability when subjected to thermal or mechanical stress, effectively avoiding lifting or peeling. This reduces the risk of failure such as open circuit or performance degradation caused by the breakage or detachment of the base metal 400, which is conducive to improving the reliability of the device. Moreover, there is no need to introduce new materials, add photomasks or complex process steps, and it is well compatible with existing standard processes, so as to balance high performance, high reliability and process compatibility.

[0035] In some application examples, please refer to Figure 10 An emitter step 500 is disposed on the base step 200, and an emitter metal 600 is disposed on the emitter step 500. Exemplarily, the emitter step 500, as one of the core components of the active device, together with the base step 200 and the collector epitaxial layer 100, constitutes the vertical structure of a heterojunction bipolar transistor. The emitter metal 600 disposed on the upper surface of the emitter step 500 enables low-resistance ohmic contact and serves as an external electrical connection port for the emitter. Specifically, the emitter step 500 is typically made of a wide-bandgap semiconductor material. By being disposed on the base step 200, a heterojunction with bandgap shift can be formed, effectively suppressing the injection of base carriers into the emitter, which is beneficial for improving current gain and high-frequency performance. The emitter metal 600 can be deposited and patterned on the exposed area of ​​the emitter step 500 using standard metallization processes, ensuring good electrical contact and signal extraction capabilities, and is compatible with existing standard heterojunction bipolar transistor processes without requiring additional masks or material changes.

[0036] Please continue to refer to Figure 10 The surface passivation layer 300 includes a first passivation layer 310, which covers the base step 200, the emitter step 500, and the emitter metal 600. The base step 200 is formed by selectively etching the initial substrate 210. Please refer to... Figure 6 and Figure 7During the manufacturing process, the initial semi-finished product includes an initial collector epitaxial layer 110 and an initial base layer 210 stacked sequentially. An emitter step 500 and emitter metal 600 located on the emitter step 500 are sequentially fabricated on the initial base layer 210. At this stage, the initial base layer 210 serves as the carrier of the entire device structure, supporting the construction of the emitter region. After the patterning of the emitter step 500 and emitter metal 600 is completed, a first passivation layer 310 is deposited and patterned. The first passivation layer 310 is used to cover the formed emitter metal 600, emitter step 500, and the non-etched areas of the initial base layer 210, while selectively exposing the areas in the initial base layer 210 intended for forming the base step 200. Next, anisotropic etching is performed on the exposed areas of the initial base layer 210 to form the base step 200 with a defined upper surface and sidewalls in the initial base layer 210, exposing the collector epitaxial layer 100 located beneath the initial base layer 210. Thus, the base region is defined, while the emitter structure remains intact during the formation of the base step 200 due to the protection of the first passivation layer 310. The entire fabrication process is compatible with existing standard process flows for heterojunction bipolar transistors, without introducing any new materials or requiring additional photomasks.

[0037] Please refer to Figure 10 The surface passivation layer 300 further includes a second passivation layer 320, which covers the first passivation layer 310, the sidewalls of the base step 200, and the collector epitaxial layer 100. For example, after the base step 200 is fabricated, the second passivation layer 320 is further deposited, thereby forming a complete surface passivation layer 300 together with the aforementioned first passivation layer 310. The second passivation layer 320 covers the first passivation layer 310, the sidewalls of the base step 200, and the exposed area of ​​the collector epitaxial layer 100 (including the active region 101 and the isolation region 102), forming a continuous and dense dielectric protective layer. Thus, by covering the sidewalls of the base step 200, the second passivation layer 320 can effectively reduce the risk of carrier recombination or leakage caused by surface states or environmental factors in high-frequency product applications. Furthermore, the second passivation layer 320 can provide additional encapsulation protection for the edge of the first passivation layer 310 and the collector epitaxial layer 100 below it, thereby comprehensively suppressing potential failure problems such as surface degradation, ion contamination, and mechanical damage. Therefore, the introduction of the second passivation layer 320 can effectively improve the performance of transistor devices. In terms of process implementation, the deposition and patterning of the second passivation layer 320 can be achieved using existing standard semiconductor passivation processes, such as plasma-enhanced chemical vapor deposition of silicon nitride or similar dielectric materials. The process flow matches existing production line conditions, eliminating the need to introduce new materials or develop dedicated processes or equipment, thus reducing the difficulty of technology implementation.

[0038] The second end of the base metal 400 serves as a capacitor plate or an upper metal connection point. For example, the second end of the base metal 400 not only acts as a mechanical anchor to enhance the overall adhesion stability of the base metal 400, but can also be functionally reused as a capacitor plate or an upper metal connection point, thereby further improving device integration and wiring flexibility. In some application examples, in RF integrated circuits, on-chip passive components, such as metal-insulator-metal (MIM) capacitors, metal-oxide-semiconductor (MOS) capacitors, or metal-dielectric-semiconductor structure capacitors, can be introduced to achieve matching, filtering, or decoupling functions. In this case, using the second end of the base metal 400 extending to the isolation region 102 as a plate of the capacitor structure allows for a compact and collaborative layout of active and passive devices without additional chip area. In other application examples, the second end of the base metal 400 can serve as an access node for upper-layer interconnects, connecting upper-layer metal traces formed in subsequent processes, such as through vias or contact windows to achieve vertical interconnects.

[0039] Please refer to Figure 2 or Figure 10 This embodiment provides a heterojunction bipolar transistor, including the aforementioned radio frequency integrated circuit structure, specifically including a collector epitaxial layer 100, a base step 200, an emitter step 500, an emitter metal 600, a surface passivation layer 300 (including a first passivation layer 310 and a second passivation layer 320), and a base metal 400, among other key components. The first end of the base metal 400 forms an ohmic contact with the base step 200 through a first window 301, and the second end of the base metal 400 is anchored to the collector epitaxial layer 100 of the isolation region 102 through a second window 302, and can further be used as a capacitor plate or an upper metal connection point, combining mechanical stability and functional integration advantages.

[0040] The surface passivation layer 300 covers the base step 200 and the collector epitaxial layer 100 region, providing effective protection and a continuous wiring path for the base metal 400. This allows the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102 of the collector epitaxial layer 100, helping to reduce the area of ​​the active region 101 of the device while maintaining its original electrical performance. A first window position 301 and a second window position 302 are provided on the surface passivation layer 300 to expose the base step 200 and the collector epitaxial layer 100 surface of the isolation region 102, respectively, allowing the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102. The two ends of the base metal 400 are anchored at both ends through the first window position 301 and the second window position 302. Even if there is local adhesion failure in the middle area of ​​the base metal 400, the base metal 400 can still maintain overall stability when subjected to thermal or mechanical stress, effectively avoiding lifting or peeling. This reduces the risk of failure such as open circuit or performance degradation caused by the breakage or detachment of the base metal 400, which is conducive to improving the reliability of the device. Moreover, there is no need to introduce new materials, add photomasks or complex process steps, and it is well compatible with existing standard processes, so as to balance high performance, high reliability and process compatibility.

[0041] Please refer to Figure 3 This embodiment provides a method for fabricating a heterojunction bipolar transistor, including steps S100 to S300. It should be noted that the numbering of the steps in this embodiment is only for ease of review and understanding, and not to limit the order of execution. The details of each step are described below: S100. Provide a first semi-finished product, which includes a collector epitaxial layer 100, a base step 200, and a surface passivation layer 300. The collector epitaxial layer 100 is provided with an active region 101 and an isolation region 102. The base step 200 is disposed on the collector epitaxial layer 100 and located in the active region 101. The surface passivation layer 300 covers the base step 200 and the collector epitaxial layer 100. For example, in the fabrication process of a heterojunction bipolar transistor (HBT), initial raw materials such as wafers need to undergo multiple standard processes in sequence, including epitaxial growth, photolithography, etching, doping, metallization, passivation, windowing, annealing, and interconnection, gradually transforming the original substrate into a finished device with complete electrical functions. During this process, the material structure continuously evolves with each process, forming a series of intermediate states with specific physical and electrical characteristics, i.e., "semi-finished products." Among these, before a certain key process (such as the base metal 400 deposition and patterning process) is executed, the structure of the semi-finished product has become relatively stable and can be defined as the first semi-finished product.

[0042] Please refer to Figure 4The first semi-finished product includes a collector epitaxial layer 100, a base step 200, and a surface passivation layer 300. The collector epitaxial layer 100 has been completed by epitaxy or ion implantation and is clearly divided into an active region 101 and an isolation region 102 on a plane. The active region 101 is used to construct the core functional area of ​​the transistor, and the isolation region 102 is used to achieve electrical isolation between adjacent devices. The base step 200 has been formed by selectively etching the initial base layer 210 and is disposed on the active region 101 of the collector epitaxial layer 100 to form the upper surface and sidewalls. The surface passivation layer 300 covers the upper surface and sidewalls of the base step 200, as well as the remaining areas of the collector epitaxial layer 100 (including the uncovered portion of the active region 101 and the entire isolation region 102), serving to protect the semiconductor surface, suppress surface states, and prevent contamination. It is worth noting that the first semi-finished product can be obtained through the standard process flow of existing heterojunction bipolar transistors without the need to introduce additional masks or complex unconventional process steps, demonstrating compatibility and feasibility in the manufacturing process.

[0043] S200, first window position 301 and second window position 302 are etched on surface passivation layer 300 to obtain second semi-finished product; first window position 301 exposes base step 200, and second window position 302 exposes collector epitaxial layer 100 located in isolation region 102. For example, please refer to Figure 4 and Figure 5 Based on the aforementioned first semi-finished product, the surface passivation layer 300 is selectively etched to form a corresponding window structure. Specifically, the window pattern is defined by photolithography, and anisotropic dry etching or selective wet etching is used to etch a first window position 301 and a second window position 302 on the surface passivation layer 300 to obtain the second semi-finished product. The first window position 301 is located on the upper surface of the base step 200 to fully expose a local area on the upper surface of the base step 200, providing the necessary conditions for the subsequent formation of an ohmic contact between the base metal 400 and the base step 200. The second window position 302 is located in the isolation region 102 to expose the surface of the underlying collector epitaxial layer 100. The windowing step can utilize existing contact holes or metal interconnect layer photolithography masks for layout optimization and adaptation, without requiring additional dedicated mask plates or changing the etching process parameter system, and is fully compatible with standard manufacturing processes. It should be noted that, as mentioned above, in conventional integrated circuit manufacturing practices, considering that the design purpose of the isolation region 102 is to provide electrical isolation rather than to set up metal leads, the surface passivation layer 300 usually does not need to be windowed at the corresponding position of the isolation region 102. However, this embodiment breaks through by windowing the surface passivation layer 300 located in the isolation region 102 in order to facilitate the subsequent mechanical anchoring of the base metal 400.

[0044] S300, deposit base metal 400 on the second semi-finished product to obtain the third semi-finished product; the base metal 400 is deposited on the surface passivation layer 300 and is located on the surface and sidewall of the base step 200 and extends to the isolation region 102. The first end of the base metal 400 forms an ohmic contact with the base step 200 through the first window position 301, and the second end of the base metal 400 is connected to the collector epitaxial layer 100 through the second window position 302.

[0045] For example, please refer to Figure 5 and Figure 2 After obtaining the second semi-finished product, the base metal 400 formation process is carried out: the base metal 400 layer is deposited on the entire surface of the second semi-finished product (including the surface passivation layer 300, the first window position 301 and the second window position 302 area) through standard metallization processes such as physical vapor deposition, electron beam evaporation or sputtering. Then, the patterning process (such as photolithography and stripping or etching) is carried out to form a predetermined wiring pattern, thereby obtaining the third semi-finished product.

[0046] In the third semi-finished product, base metal 400 covers the surface passivation layer 300 and extends along the upper surface of the base step 200 through the sidewall (e.g. Figure 2 As shown in the middle (P3), it extends to the isolation region 102 covered by the surface passivation layer 300, and finally reaches the location of the second window position 302. Specifically: The first end of the base metal 400 (e.g.) Figure 2 (As shown by the mark P1) The first opening position 301 contacts and covers the exposed upper surface of the base step 200. After subsequent heat treatment, it forms an ohmic contact with the base step 200, realizing the injection of the base electrical signal. The second end of the base metal 400 (as shown by the mark P1) Figure 2 (As shown in P2) a second window 302 establishes a physical connection with the surface of the collector epitaxial layer 100 located in the isolation region 102. This physical connection does not constitute a current path, but because the second end of the base metal 400 can directly adhere to the surface of the collector epitaxial layer 100 with better adhesion rather than the surface passivation layer 300 with poor adhesion, it is beneficial to enhance the interfacial bonding strength of the base metal 400 and effectively suppress warping, peeling or breakage under thermal cycling or mechanical stress.

[0047] It is worth noting that the base metal 400 wiring configuration (extending to the isolation region 102 and anchoring to the collector epitaxial layer 100 through the window position) is not a conventional practice in traditional heterojunction bipolar transistor processes. However, the process implementation can rely entirely on existing metal deposition and patterning process platforms without introducing new material systems (such as additional adhesion layers or new alloys), or adding dedicated photomasks or special post-processing steps. It can be achieved in the standard process flow simply by optimizing the layout, which fully ensures process compatibility and mass production feasibility.

[0048] Therefore, the surface passivation layer 300 covers the base step 200 and the collector epitaxial layer 100 region, providing effective protection and a continuous wiring path for the base metal 400. This allows the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102 of the collector epitaxial layer 100, helping to reduce the area of ​​the active region 101 of the device while maintaining the original electrical performance. A first window position 301 and a second window position 302 are provided on the surface passivation layer 300 to expose the base step 200 and the collector epitaxial layer 100 surface of the isolation region 102, respectively, allowing the base metal 400 to extend from the base step 200 through the sidewall to the isolation region 102. The two ends of the base metal 400 are anchored at both ends through the first window position 301 and the second window position 302. Even if there is local adhesion failure in the middle area of ​​the base metal 400, the base metal 400 can still maintain overall stability when subjected to thermal or mechanical stress, effectively avoiding lifting or peeling. This reduces the risk of failure such as open circuit or performance degradation caused by the breakage or detachment of the base metal 400, which is conducive to improving the reliability of the device. Moreover, there is no need to introduce new materials, add photomasks or complex process steps, and it is well compatible with existing standard processes, so as to balance high performance, high reliability and process compatibility.

[0049] Please refer to Figure 6 and Figure 7 In some application examples, step S100, providing a first semi-finished product, includes the following steps: S110. Provide an initial semi-finished product, which includes an initial collector epitaxial layer 110 and an initial base layer 210 stacked sequentially. For example, during the manufacturing process, the initial semi-finished product includes an initial collector epitaxial layer 110 and an initial base layer 210 stacked sequentially. The initial collector epitaxial layer 110 is usually formed by an epitaxial growth process and has a specific doping concentration and type to meet the functional requirements of the subsequent transistor. The initial base layer 210 serves as a carrier for the subsequent base step 200 and emitter region.

[0050] S120. A first passivation layer 310 is deposited in the preset pattern area of ​​the initial base layer 210 to cover the pattern area and expose the remaining non-pattern area. For example, the first passivation layer 310 is mainly used to cover the non-etched areas in the initial base layer 210, while selectively exposing the areas in the initial base layer 210 that are intended to form the base step 200, which can provide a precise mask for subsequent etching.

[0051] S130, Etch the non-patterned area of ​​the initial base layer 210 to form the base step 200 and expose the target area of ​​the initial collector epitaxial layer 110. For example, anisotropic etching is performed on the non-patterned regions of the initial substrate 210 to form a base step 200 with a defined upper surface and sidewalls in the initial substrate 210, exposing the collector epitaxial layer 100 located beneath the initial substrate 210. This process defines the location and morphology of the base region and ensures that the base step 200 can establish an effective electrical contact with the collector epitaxial layer 100.

[0052] S140. An isolation region 102 is formed in the target region of the initial collector epitaxial layer 110 by ion implantation, so as to form a collector epitaxial layer 100 having an active region 101 and an isolation region 102.

[0053] For example, high-resistivity impurities are introduced into the target region (i.e., isolation region 102) of the initial collector epitaxial layer 110 through ion implantation or other doping techniques to achieve electrical isolation between adjacent active devices. Thus, the collector epitaxial layer 100 is divided into an active region 101 and an isolation region 102. The active region 101 is used to construct the core functional region of the transistor, while the isolation region 102 is used to prevent current crosstalk and parasitic effects, ensuring that each device operates independently and stably.

[0054] The entire processing is based on the existing standard process flow for heterojunction bipolar transistors, without introducing any new materials or requiring additional photomasks. This enables efficient and reliable device manufacturing while maintaining high frequency performance and long-term reliability.

[0055] Please refer to Figure 8 Step S140 involves forming an isolation region 102 in the target region of the initial collector epitaxial layer 110 by ion implantation, thereby forming a collector epitaxial layer 100 having an active region 101 and an isolation region 102. The process further includes: A second passivation layer 320 is deposited to form a surface passivation layer 300 covering the base step 200 and the collector epitaxial layer 100.

[0056] For example, after the base step 200 is fabricated, a second passivation layer 320 is further deposited, thereby forming a complete surface passivation layer 300 together with the aforementioned first passivation layer 310. The second passivation layer 320 covers the first passivation layer 310, the sidewalls of the base step 200, and the exposed collector epitaxial layer 100 region (including the active region 101 and the isolation region 102), forming a continuous and dense dielectric protection layer. Thus, by covering the sidewalls of the base step 200, the second passivation layer 320 can effectively reduce the risk of carrier recombination or leakage caused by surface states or environmental factors in high-frequency product applications. Furthermore, the second passivation layer 320 can provide additional encapsulation protection for the edge of the first passivation layer 310 and the collector epitaxial layer 100 below it, thereby comprehensively suppressing potential failure problems such as surface degradation, ion contamination, and mechanical damage. Therefore, the introduction of the second passivation layer 320 can effectively improve the performance of transistor devices. In terms of process implementation, the deposition and patterning of the second passivation layer 320 can be achieved using existing standard semiconductor passivation processes, such as plasma-enhanced chemical vapor deposition of silicon nitride or similar dielectric materials. The process flow is compatible with existing production line conditions, requiring no introduction of new materials or development of dedicated processes or equipment, thus reducing the difficulty of implementation. Please refer to [reference needed]. Figure 8 , Figure 9 and Figure 10 After the second passivation layer 320 is processed, a first window position 301 and a second window position 302 are formed on the second passivation layer 320, and then the base metal 400 is deposited, so that the first end of the base metal 400 (e.g., Figure 10 (As shown by the mark P1) can form an ohmic contact with the base step 200 through the first window position 301, and the second end of the base metal 400 (as shown by the mark P1) can form an ohmic contact with the base step 200. Figure 10 As shown in the mark P2, it can establish a physical connection with the collector epitaxial layer 100 through the second window position 302, thereby achieving double-end anchoring.

[0057] Please refer to Figure 6 and Figure 7 In some application examples, the initial semi-finished product also includes an initial emission layer stacked on the initial base layer 210, providing the initial semi-finished product, and subsequently includes: Electrode metal 600 is deposited on the initial emission layer; The emitter metal 600 and the initial emitter layer are etched to form the emitter step 500.

[0058] For example, the emitter step 500, as one of the core components of the active device, together with the base step 200 and the collector epitaxial layer 100, constitutes the vertical structure of a heterojunction bipolar transistor. An emitter metal 600 is disposed on the upper surface of the emitter step 500, enabling low-resistance ohmic contact and serving as an external electrical connection port for the emitter. Specifically, the emitter step 500 is typically made of a wide-bandgap semiconductor material. By being disposed above the base step 200, a heterojunction with bandgap shift can be formed, effectively suppressing the injection of base carriers into the emitter, which is beneficial for improving current gain and high-frequency performance. The emitter metal 600 can be deposited and patterned on the exposed area of ​​the emitter step 500 using standard metallization processes, ensuring good electrical contact and signal extraction capabilities. This process is compatible with existing standard heterojunction bipolar transistor processes without requiring additional masks or material changes. It should be noted that after the first passivation layer 310 is prepared, the first passivation layer 310 simultaneously covers the already formed emitter metal 600, emitter step 500 and the non-etched area in the initial base layer 210.

[0059] Therefore, this embodiment has the following beneficial effects: Extremely strong anti-peeling capability: By setting anchoring structures at both ends of the base metal 400, such as the first end of the base metal 400 forming an ohmic contact with the base step 200 through the first window position 301, and the second end of the base metal 400 establishing a physical connection with the collector epitaxial layer 100 of the isolation region 102 through the second window position 302, a "double-end anchoring" structure is achieved. This structure is similar to a ship using double anchors. Even if the bridging section in the middle of the base metal 400 is covered by the surface passivation layer 300 and there is a problem of insufficient interface adhesion in some areas, the entire metal line of the base metal 400 can still maintain overall positional stability and structural continuity when subjected to thermal and mechanical stress. This fundamentally suppresses the risk of metal lifting or peeling caused by the weak interface bonding between the platinum / palladium and other precious metal systems and silicon nitride. It breaks through the process reliability bottleneck caused by continuously reducing the area of ​​the base step 200 in pursuit of high-frequency performance and solves the long-standing problem of metal adhesion failure in high-frequency heterojunction bipolar transistor devices.

[0060] Exceptional reliability: Because the base metal 400 is spatially and firmly fixed at both ends, its physical integrity and geometric position are maintained to a high degree throughout the device's lifespan. This significantly suppresses typical failure modes caused by metal stripping, loss, or wire breakage in traditional processes, such as open-circuit faults, contact resistance drift, and current gain degradation. Especially under high-temperature, high-humidity, temperature cycling, or high-power RF operating conditions, the device exhibits excellent long-term stability and durability, which helps improve device reliability and lifespan, meeting the stringent requirements of high-reliability applications.

[0061] Excellent process compatibility: By creating a first window 301 and a second window 302 on the surface passivation layer 300 to achieve dual-end anchoring of the base metal 400, this is entirely based on the existing standard manufacturing process for heterojunction bipolar transistors. No new materials or complex processes need to be introduced, and no additional photomasks are required. Implementation can be completed without changing the process sequence or equipment configuration simply by reasonably optimizing the existing layout, for example, by defining the second window 302 in the isolation region 102. Therefore, it boasts extremely low process modification costs, extremely high production line adaptability, and good yield controllability, making it a low-cost, highly efficient, and easily mass-producible solution.

[0062] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A radio frequency integrated circuit structure, characterized in that, include: The collector epitaxial layer (100) is provided with an active region (101) and an isolation region (102). A base step (200) is disposed on the collector epitaxial layer (100) and located in the active region (101). A surface passivation layer (300) covers the base step (200) and the collector epitaxial layer (100). The surface passivation layer (300) is provided with a first window position (301) and a second window position (302). The first window position (301) exposes the base step (200), and the second window position (302) exposes the collector epitaxial layer (100) located in the isolation region (102). A base metal (400) is disposed on the surface passivation layer (300) and located on the surface and sidewall of the base step (200) and extends to the isolation region (102). The first end of the base metal (400) forms an ohmic contact with the base step (200) through the first window position (301), and the second end of the base metal (400) is contacted and connected to the collector epitaxial layer (100) through the second window position (302).

2. The radio frequency integrated circuit structure according to claim 1, characterized in that, An emitter step (500) is provided on the base step (200), and an emitter metal (600) is provided on the emitter step (500).

3. The radio frequency integrated circuit structure according to claim 2, characterized in that, The surface passivation layer (300) includes a first passivation layer (310) covering the base step (200), the emitter step (500), and the emitter metal (600).

4. The radio frequency integrated circuit structure according to claim 3, characterized in that, The surface passivation layer (300) further includes a second passivation layer (320), which covers the first passivation layer (310), the sidewall of the base step (200), and the collector epitaxial layer (100).

5. The radio frequency integrated circuit structure according to any one of claims 1 to 4, characterized in that, The second end of the base metal (400) is used as a capacitor plate or an upper metal connection point.

6. A heterojunction bipolar transistor, characterized in that, Includes the radio frequency integrated circuit structure as described in any one of claims 1 to 5.

7. A method for fabricating a heterojunction bipolar transistor, characterized in that, include: A first semi-finished product is provided, the first semi-finished product comprising a collector epitaxial layer (100), a base step (200) and a surface passivation layer (300), wherein the collector epitaxial layer (100) is provided with an active region (101) and an isolation region (102), the base step (200) is disposed on the collector epitaxial layer (100) and located in the active region (101), and the surface passivation layer (300) covers the base step (200) and the collector epitaxial layer (100); A first window (301) and a second window (302) are etched on the surface passivation layer (300) to obtain a second semi-finished product; the first window (301) exposes the base step (200), and the second window (302) exposes the collector epitaxial layer (100) located in the isolation region (102). A base metal (400) is deposited on the second semi-finished product to obtain a third semi-finished product; the base metal (400) is deposited on the surface passivation layer (300) and located on the surface and sidewall of the base step (200) and extends to the isolation region (102); the first end of the base metal (400) forms an ohmic contact with the base step (200) through the first window position (301); and the second end of the base metal (400) is connected to the collector epitaxial layer (100) through the second window position (302).

8. The method for fabricating a heterojunction bipolar transistor according to claim 7, characterized in that, The provision of the first semi-finished product includes: An initial semi-finished product is provided, the initial semi-finished product comprising an initial collector epitaxial layer (110) and an initial base layer (210) stacked sequentially. A first passivation layer (310) is deposited in the preset patterned area of ​​the initial base layer (210) to cover the patterned area and expose the remaining non-patterned area; The non-patterned areas of the initial base layer (210) are etched to form the target area of ​​the base step (200) and expose the initial collector epitaxial layer (110); An isolation region (102) is formed by ion implantation in the target region of the initial collector epitaxial layer (110) to form a collector epitaxial layer (100) having an active region (101) and an isolation region (102).

9. The method for fabricating a heterojunction bipolar transistor according to claim 8, characterized in that, The process further includes forming an isolation region (102) in the target region of the initial collector epitaxial layer (110) by ion implantation to form a collector epitaxial layer (100) having an active region (101) and an isolation region (102), and then further includes: A second passivation layer (320) is deposited to form a surface passivation layer (300) covering the base step (200) and the collector epitaxial layer (100).

10. The method for fabricating a heterojunction bipolar transistor according to claim 8 or 9, characterized in that, The initial semi-finished product further includes an initial emission layer laminated on the initial base layer (210), and the provision of the initial semi-finished product further includes: An emitter metal (600) is deposited on the initial emitter layer. The emitter metal (600) and the initial emitter layer are etched to form emitter steps (500).

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