Display panel, preparation method of display panel and electronic device

Abstract

The embodiment of the application provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. The display panel comprises a substrate, a conductive layer, an insulating layer and a first electrode. The conductive layer is located on one side of the substrate, and the conductive layer comprises a conductive trace. The insulating layer is located on a side of the conductive layer away from the substrate, and along a direction parallel to the substrate, the insulating layer comprises a first insulating part and a second insulating part. Along the thickness direction of the substrate, the thickness of the second insulating part is smaller than the thickness of the first insulating part. The second insulating part is provided with a via hole penetrating through the second insulating part. The first electrode is located on a side of the insulating layer away from the substrate, and the first electrode is electrically connected with the conductive trace through the via hole. The via hole exposes part of the conductive trace. The application can reduce the depth of the via hole, so that the first electrode located at the via hole is more flat on the side away from the substrate, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the display panel, and an electronic device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body, and wide range of applications, becoming the mainstream of display panels.

[0003] However, there are still some problems with the display panel that need to be addressed. Summary of the Invention

[0004] To overcome the technical problems mentioned in the background, this application provides a display panel, which includes:

[0005] Substrate;

[0006] A conductive layer is located on one side of the substrate, and the conductive layer includes conductive traces;

[0007] An insulating layer is located on the side of the conductive layer away from the substrate, along a direction parallel to the substrate. The insulating layer includes a first insulating portion and a second insulating portion. Along the thickness direction of the substrate, the thickness of the second insulating portion is less than the thickness of the first insulating portion. A via is provided on the second insulating portion, and the via exposes a portion of the conductive trace.

[0008] The first electrode is located on the side of the insulating layer away from the substrate, and the first electrode is electrically connected to the conductive trace through the via.

[0009] In some possible implementations, the first electrode is the anode;

[0010] Preferably, the first electrode covers the first insulating portion and a portion of the second insulating portion.

[0011] In some possible implementations, the first insulating portion includes a first insulator portion and a second insulator portion stacked in a direction away from the substrate, the first insulator portion and the second insulator portion comprising different materials, and the second insulator portion or the first insulator portion and the second insulating portion being disposed in the same layer;

[0012] Preferably, the second insulator portion and the second insulating portion are disposed in the same layer, and the second insulator portion and the second insulating portion are integrally formed;

[0013] Preferably, the material of the second insulator portion is the same as the material of the second insulating portion;

[0014] Preferably, along a direction perpendicular to the substrate, the thickness of the second insulator portion is equal to the thickness of the second insulating portion;

[0015] Preferably, the first insulator portion is surrounded to form a groove penetrating the first insulator portion, and the second insulating portion is located within the groove;

[0016] Preferably, the display panel further includes a planarization layer located between the first electrode and the conductive layer, and the first insulator portion includes the planarization layer.

[0017] In some possible implementations, the thickness of the first insulating portion is greater than or equal to 1.75 μm and less than or equal to 3.1 μm along a direction perpendicular to the substrate;

[0018] Preferably, along a direction perpendicular to the substrate, the thickness of the second insulating portion is greater than or equal to 0.15 μm and less than or equal to 0.6 μm;

[0019] Preferably, along a direction perpendicular to the substrate, the thickness of the first insulator portion is greater than or equal to 1.6 μm and less than or equal to 2.5 μm;

[0020] Preferably, the material of the first insulator portion includes an organic material;

[0021] Preferably, the material of the second insulating part includes an inorganic material;

[0022] Preferably, the material of the second insulating portion includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0023] In some possible implementations, the material of the first insulating portion and the material of the second insulating portion are the same;

[0024] Preferably, the materials of the first insulating portion and the second insulating portion both include organic materials;

[0025] Preferably, the first insulating part and the second insulating part are integrally formed;

[0026] Preferably, along a direction perpendicular to the substrate, the thickness of the first insulating portion is greater than or equal to 1.6 μm and less than or equal to 2.5 μm;

[0027] Preferably, along a direction perpendicular to the substrate, the thickness of the second insulating portion is greater than or equal to 0.5 μm and less than or equal to 1.5 μm;

[0028] Preferably, the display panel further includes a planarization layer located between the first electrode and the conductive layer, and the insulating layer includes the planarization layer.

[0029] In some possible implementations, it also includes:

[0030] A pixel defining layer is located on the side of the first electrode and the insulating layer away from the substrate, the pixel defining layer including a pixel opening that exposes a portion of the first electrode;

[0031] Preferably, the orthographic projection of the via on the substrate is located within the orthographic projection of the pixel opening on the substrate;

[0032] Preferably, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the second insulating portion on the substrate.

[0033] In some possible implementations, it also includes:

[0034] An isolation structure is located on the side of the pixel defining layer away from the substrate, the isolation structure encloses an isolation opening, and the isolation opening communicates with the pixel opening;

[0035] Preferably, it further includes a light-emitting portion and a second electrode stacked on the side of the first electrode away from the substrate, the second electrode extending to be electrically connected to the isolation structure.

[0036] In some possible implementations, it also includes:

[0037] A first encapsulation layer is located on the side of the second electrode away from the substrate. The first encapsulation layer includes a plurality of encapsulation units spaced apart, at least a portion of the encapsulation units extending from the side of the isolation structure toward the isolation opening to the side of the isolation structure away from the substrate.

[0038] Preferably, the plurality of the packaging units are spaced apart on the side of the isolation structure away from the substrate;

[0039] Preferably, there is a gap between the packaging unit located on the side of the isolation structure away from the substrate and the side of the isolation structure away from the substrate;

[0040] Preferably, it further includes:

[0041] The second encapsulation layer is located on the side of the first encapsulation layer away from the substrate;

[0042] The third encapsulation layer is located on the side of the second encapsulation layer away from the substrate;

[0043] Preferably, the materials of both the first encapsulation layer and the third encapsulation layer include inorganic materials;

[0044] Preferably, the material of the second encapsulation layer includes an organic material.

[0045] In some possible implementations, the isolation structure includes a first isolation portion and a second isolation portion stacked sequentially in a direction away from the substrate, wherein the orthographic projection of the side of the first isolation portion away from the substrate on the substrate is located within the orthographic projection of the second isolation portion on the substrate;

[0046] Preferably, the second electrode is electrically connected to the first isolation portion; and / or, the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the substrate, and the second electrode is electrically connected to the third isolation portion;

[0047] Preferably, the material of the third isolation portion includes molybdenum; and / or, the material of the first isolation portion includes aluminum; and / or, the material of the second isolation portion includes titanium.

[0048] In some possible implementations, this application also provides a display panel, the display panel comprising:

[0049] Substrate;

[0050] A conductive layer is located on one side of the substrate, and the conductive layer includes conductive traces;

[0051] An insulating layer is located on the side of the conductive layer away from the substrate. Along the thickness direction of the substrate, the insulating layer has a groove penetrating the insulating layer, and at least a portion of the conductive traces have their orthogonal projections on the substrate located within the orthogonal projections of the corresponding grooves on the substrate.

[0052] A barrier layer is located on the side of the insulating layer away from the substrate. The barrier layer extends into the groove. Along the thickness direction of the substrate, the barrier layer located in the groove has a via that penetrates the barrier layer. The via exposes a portion of the conductive trace.

[0053] A light-emitting unit is located on the side of the barrier layer away from the substrate. The light-emitting unit includes a first electrode, which is electrically connected to the conductive trace through the via.

[0054] In some possible implementations, the thickness of the insulating layer is greater than the thickness of the barrier layer in a direction perpendicular to the substrate;

[0055] Preferably, the thickness of the barrier layer is greater than or equal to 0.15 μm and less than or equal to 0.6 μm;

[0056] Preferably, the material of the barrier layer includes at least one of silicon nitride, silicon oxide, or silicon oxynitride;

[0057] Preferably, it further includes:

[0058] An isolation structure is located on the side of the insulating layer away from the substrate, the isolation structure encloses and forms an isolation opening, and the orthographic projection of the via on the substrate is located within the orthographic projection of the isolation opening on the substrate.

[0059] In some possible implementations, this application also provides a method for manufacturing a display panel, the method comprising:

[0060] Provide substrate;

[0061] A conductive layer is formed on one side of the substrate, the conductive layer including conductive traces;

[0062] An insulating layer is formed on the side of the conductive layer away from the substrate. Along a direction parallel to the substrate, the insulating layer includes a first insulating portion and a second insulating portion. Along the thickness direction of the substrate, the thickness of the second insulating portion is less than the thickness of the first insulating portion. A via is provided on the second insulating portion, and the via exposes a portion of the conductive trace.

[0063] A first electrode is formed on the side of the insulating layer away from the substrate, and the first electrode is electrically connected to the conductive trace through the via.

[0064] In some possible implementations, the step of forming an insulating layer on the side of the conductive layer away from the substrate includes:

[0065] A first insulator portion is formed on the side of the conductive layer away from the substrate, and a groove penetrating the first insulator portion is provided along the thickness direction of the substrate;

[0066] A second insulator portion is formed on the side of the first insulator portion away from the substrate, the second insulator portion extending into the groove to form a second insulating portion located within the groove, the first insulator portion and the second insulator portion comprising different materials.

[0067] In some possible implementations, the step of forming an insulating layer on the side of the conductive layer away from the substrate includes:

[0068] An insulating material layer is formed on the side of the conductive layer away from the substrate;

[0069] An insulating layer comprising a first insulating portion and a second insulating portion is formed using a semi-transparent mask.

[0070] In some possible implementations, this application also provides an electronic device, which includes the display panel described in this application, or a display panel prepared by the method for preparing the display panel described in this application.

[0071] Compared with the prior art, this application has the following beneficial effects:

[0072] This application provides a display panel, a method for manufacturing the display panel, and an electronic device. By setting the thickness of the second insulating portion to be less than the thickness of the first insulating portion, and by setting the via on the second insulating portion, the depth of the via can be reduced, thereby making the side of the first electrode located at the via that is away from the substrate flatter, and thus improving the display effect of the display panel. Attached Figure Description

[0073] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 A cross-sectional schematic diagram of the display panel in the related technology provided in the embodiments of this application;

[0075] Figure 2 The insulating layer of the display panel provided in the embodiments of this application includes one of the cross-sectional schematic diagrams of a first insulating portion and a second insulating portion;

[0076] Figure 3 A cross-sectional schematic diagram of a display panel including driving transistors provided in an embodiment of this application;

[0077] Figure 4 The insulating layer of the display panel provided in the embodiments of this application includes a first insulating portion and a second insulating portion, as shown in the second cross-sectional schematic diagram.

[0078] Figure 5 A top view of the first insulator portion provided in an embodiment of this application;

[0079] Figure 6 One of the cross-sectional schematic diagrams of a display panel including a pixel defining layer provided in the embodiments of this application;

[0080] Figure 7 A second cross-sectional schematic diagram of a display panel including a pixel delimiting layer provided in an embodiment of this application;

[0081] Figure 8 One of the cross-sectional schematic diagrams of the display panel provided in the embodiments of this application includes an isolation structure;

[0082] Figure 9 A second cross-sectional schematic diagram of the display panel including the isolation structure provided in the embodiments of this application;

[0083] Figure 10 One of the cross-sectional schematic diagrams of a display panel including a first encapsulation layer provided in the embodiments of this application;

[0084] Figure 11 A second cross-sectional schematic diagram of the display panel provided in the embodiments of this application, including the first encapsulation layer;

[0085] Figure 12 One of the cross-sectional schematic diagrams of the display panel provided in the embodiments of this application, including a second encapsulation layer and a third encapsulation layer;

[0086] Figure 13 A second cross-sectional schematic diagram of the display panel provided in the embodiments of this application, including a second encapsulation layer and a third encapsulation layer;

[0087] Figure 14 A cross-sectional view of another display panel provided in an embodiment of this application;

[0088] Figure 15 A schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0089] Figure 16 A schematic cross-section showing a first insulator portion formed on the side of the conductive layer away from the substrate, as provided in an embodiment of this application.

[0090] Figure 17 A schematic cross-sectional view of a second insulator portion formed on the side of the first insulator portion away from the substrate, provided for an embodiment of this application;

[0091] Figure 18 A cross-sectional schematic diagram showing an insulating material layer formed on the side of the conductive layer away from the substrate, provided for an embodiment of this application;

[0092] Figure 19 This is a schematic diagram of a cross-section of an insulating layer including a first insulating portion and a second insulating portion, formed by a semi-transparent mask, as provided in an embodiment of this application.

[0093] Reference numerals: 1. Substrate; 2. Conductive layer; 21. Conductive trace; 3. Planarization layer; 31. Via; 4. First electrode; 5. Insulating layer; 51. First insulating portion; 511. First insulator portion; 5111. Groove; 512. Second insulator portion; 52. Second insulating portion; 521. Via; 6. Driving transistor; 7. Pixel defining layer; 71. Pixel opening; 8. Isolation structure; 81. First isolation portion; 82. Second isolation portion; 83. Third isolation portion; 9. Isolation opening; 10. Light-emitting portion; 11. Second electrode; 12. First encapsulation layer; 121. Encapsulation unit; 13. Second encapsulation layer; 14. Third encapsulation layer; 15. Barrier layer; 16. Light-emitting unit; 17. Insulating material layer. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0095] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0096] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0097] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0098] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0099] Increasing the density of light-emitting units (i.e., pixel density) in a display panel is a crucial way to improve display quality. However, current display panels manufactured using Fine Metal Mask (FMM) technology are limited by technological constraints, preventing further increases in light-emitting unit density. Through long-term research, the inventors discovered that to address this technical challenge, some display panels incorporate isolation structures. During the full-layer vapor deposition of the light-emitting functional layer and the second electrode, the light-emitting functional layer and the second electrode can be disconnected at the isolation structure. By employing multiple vapor deposition and etching processes (i.e., light-emitting unit patterning), light-emitting units of different colors can be formed within different isolation openings.

[0100] Among them, patents CN118251982A, 202410864269.8, PCT / CN2024 / 098407, PCT / CN2024 / 102783, PCT / CN2024 / 098217, PCT / CN2024 / 099419, PCT / CN2024 / 099072, CN117979755A, and CN1179 CN117062489A, CN117580403A, CN116583155A, CN116669477A, ​​CN117396039A, CN116669480A, CN116600606A, and CN117500332A describe relevant technical solutions for isolation structures, the contents of which are incorporated herein by reference.

[0101] Please see Figure 1 The display panel in the related technology includes a substrate 1, a conductive layer 2 located on one side of the substrate 1, a planarization layer 3 located on the side of the conductive layer 2 away from the substrate 1, and a light-emitting unit located on the side of the planarization layer 3 away from the substrate 1. The planarization layer 3 is provided with a through hole 31 that exposes part of the conductive trace 21 in the conductive layer 2. The first electrode 4 of the light-emitting unit is electrically connected to the conductive trace 21 through the through hole 31.

[0102] Because the planarization layer 3 is relatively thick, the via 31 on the planarization layer 3 is relatively deep. The first electrode 4 is recessed to a greater depth towards the substrate 1 on the side away from the substrate 1 at the via 31. This results in the first electrode 4 being uneven on the side away from the substrate 1 at the via 31, which causes the corresponding light-emitting unit to produce color shift, ultimately affecting the display effect of the display panel.

[0103] To address the aforementioned technical problems, the inventors have innovatively designed the following technical solutions, which will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of the inventors' practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below are contributions made by the inventors to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0104] Please see Figure 2 This embodiment provides a display panel, which includes a substrate 1, a conductive layer 2, an insulating layer 5, and a first electrode 4.

[0105] The conductive layer 2 is located on one side of the substrate 1, and the conductive layer 2 includes conductive traces 21.

[0106] The insulating layer 5 is located on the side of the conductive layer 2 away from the substrate 1. Along the direction parallel to the substrate 1, the insulating layer 5 includes a first insulating portion 51 and a second insulating portion 52. Along the thickness direction Z of the substrate 1, the thickness H3 of the second insulating portion 52 is less than the thickness H2 of the first insulating portion 51. A via 521 is provided on the second insulating portion 52, and the via exposes a portion of the conductive trace 21.

[0107] The first electrode 4 is located on the side of the insulating layer 5 away from the substrate 1, and the first electrode 4 is electrically connected to the conductive trace 21 through the via 521.

[0108] The thickness H2 of the first insulating portion 51 is equal to the thickness H1 of the planarization layer 3 in the related art. Since the thickness H3 of the second insulating portion 52 is less than the thickness H2 of the first insulating portion 51, the thickness H3 of the second insulating portion 52 is less than the thickness H1 of the planarization layer 3 in the related art.

[0109] Thus, the depth of the via 521 on the second insulating portion 52 is less than the depth of the via 31 on the planarization layer 3 in the related art. The first electrode 4 can more easily fill the via 521 on the second insulating portion 52. The side of the first electrode 4 located at the via 521 away from the substrate 1 is flatter, so that the corresponding light-emitting unit is less likely to produce color shift, thereby improving the display effect of the display panel.

[0110] Based on the above design, this embodiment sets the thickness of the second insulating part 52 to be less than the thickness of the first insulating part 51, and sets the via 521 on the second insulating part 52. This reduces the depth of the via 521, thereby making the side of the first electrode 4 located at the via 521 away from the substrate 1 flatter, which in turn improves the display effect of the display panel.

[0111] For some possible implementations, please refer to Figure 3 It also includes a pixel driving circuit, which is located between the conductive layer 2 and the substrate 1. The pixel driving circuit includes a driving transistor 6, and the first electrode 4 is electrically connected to the corresponding driving transistor 6 through a conductive trace 21.

[0112] The display panel also includes a buffer layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer, sequentially stacked on one side of the substrate 1. The semiconductor layer includes a source region, a drain region, and a channel region. The first conductive layer includes a gate and a first capacitor plate. The second conductive layer includes a second capacitor plate, which together form a capacitor. The third conductive layer includes a drain and a source, with the drain electrically connected to the drain region and the source electrically connected to the source region. The gate, source, and drain form a driving transistor 6. In this embodiment, the conductive trace 21 is located on the fourth conductive layer. The side of the conductive trace 21 closest to the substrate 1 is electrically connected to the drain of the driving transistor 6, and the side of the conductive trace 21 furthest from the substrate 1 is electrically connected to the first electrode 4 through a via 521. Thus, the signal driving the transistor 6 can be transmitted to the first electrode 4 through the conductive trace 21 to illuminate the corresponding light-emitting unit 16.

[0113] Preferably, the first electrode 4 covers the first insulating portion 51 and part of the second insulating portion 52. The first electrode 4 extends from the side of the second insulating portion 52 away from the substrate 1 through the sidewall of the first insulating portion 51 toward the via 521 to the side of the first insulating portion 51 away from the substrate 1.

[0114] Optionally, the side of the first electrode 4 located at the via 521 away from the substrate 1 includes a flat surface. This can further improve the flatness of the side of the first electrode 4 located at the via 521 away from the substrate 1.

[0115] The following describes two specific implementation methods.

[0116] In the first embodiment, please refer again. Figure 3 The material of the first insulating part 51 is the same as the material of the second insulating part 52.

[0117] Optionally, the materials of the first insulating part 51 and the second insulating part 52 both include organic materials.

[0118] Optionally, the first insulating part 51 and the second insulating part 52 are integrally formed.

[0119] In this embodiment, the first insulating part 51 and the second insulating part 52 are formed through the same film layer. Specifically, a semi-transparent mask can be used to form the second insulating part 52 in the thinner part of the insulating layer 5, while the remaining part is the first insulating part 51. This can improve the efficiency of forming the first insulating part 51 and the second insulating part 52.

[0120] Preferably, please see again. Figure 2 Along the direction Z perpendicular to the substrate 1, the thickness H2 of the first insulating portion 51 is greater than or equal to 1.6 μm and less than or equal to 2.5 μm. For example, the thickness H2 can be 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm or 2.5 μm, etc.

[0121] Preferably, along the direction Z perpendicular to the substrate 1, the thickness H3 of the second insulating portion 52 is greater than or equal to 0.5 μm and less than or equal to 1.5 μm. For example, the thickness H3 can be 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.4 μm or 1.5 μm, etc.

[0122] By reasonably setting the difference between thickness H3 and thickness H2, and by reasonably setting the thickness H3, the depth of via 521 can be reasonably set, thereby further improving the flatness of the first electrode 4 located at via 521 on the side away from the substrate 1.

[0123] Preferably, the display panel further includes a planarization layer 3 located between the first electrode 4 and the conductive layer 2, and the insulating layer 5 includes the planarization layer 3.

[0124] In this embodiment, by processing the planarization material layer with a semi-transparent mask, an insulating layer 5 including a first insulating portion 51 and a second insulating portion 52 can be formed simultaneously.

[0125] In the second embodiment, please refer to Figure 4 The first insulating portion 51 includes a first insulator portion 511 and a second insulator portion 512 stacked in a direction away from the substrate 1. The first insulator portion 511 and the second insulator portion 512 are made of different materials. The second insulator portion 512 or the first insulator portion 511 and the second insulating portion 52 are disposed in the same layer.

[0126] In this embodiment, the second insulator portion 512 or the first insulator portion 511 and the second insulating portion 52 are formed through the same film layer. Thus, the second insulating portion 52 can be formed at the same time as the second insulator portion 512 or the first insulator portion 511, which makes it easier to form the second insulating portion 52.

[0127] Furthermore, the second insulator portion 512 and the second insulating portion 52 are disposed in the same layer, and the second insulator portion 512 and the second insulating portion 52 are integrally formed.

[0128] Optionally, the material of the second insulator portion 512 is the same as the material of the second insulator portion 52.

[0129] Optionally, the thickness of the second insulator portion 512 is equal to the thickness of the second insulating portion 52 along the direction Z perpendicular to the substrate 1.

[0130] In this embodiment, the second insulator portion 512 and the second insulating portion 52 are formed through the same film layer. Thus, the second insulating portion 52 can be formed at the same time as the second insulator portion 512, making it easier to form the second insulating portion 52.

[0131] Preferably, please refer to Figure 4 and Figure 5 The first insulator portion 511 surrounds and forms a groove 5111 that penetrates the first insulator portion 511, and the second insulating portion 52 is located inside the groove 5111.

[0132] Optionally, the first insulator portion 511 includes a planarization layer.

[0133] After patterning the planarization material layer, a planarization layer is formed including multiple arrayed grooves 5111. The portion of the planarization layer without grooves 5111 forms the first insulator portion 511. Then, material for the second insulator portion 512 is formed on the planarization layer. The material of the second insulator portion 512 located within the grooves 5111 forms the second insulating portion 52. The portion of the first insulator portion 511 located away from the substrate 1 forms the second insulator portion 512. In this way, the second insulator portion 512 and the second insulating portion 52 can be formed more easily, and the depth of the via 521 can be reduced more easily.

[0134] In some possible implementations, please refer again. Figure 4 Along the direction Z perpendicular to the substrate 1, the thickness D1 of the first insulating portion 51 is greater than or equal to 1.75 μm and less than or equal to 3.1 μm. For example, the thickness D1 can be 1.75 μm, 1.8 μm, 2 μm, 2.5 μm, 3 μm or 3.1 μm, etc.

[0135] Preferably, along the direction Z perpendicular to the substrate 1, the thickness D2 of the second insulating portion 52 is greater than or equal to 0.15 μm and less than or equal to 0.6 μm. For example, the thickness D2 can be 0.15 μm, 0.2 μm, 3 μm, 0.4 μm, 0.5 μm or 0.6 μm, etc.

[0136] Preferably, along the direction Z perpendicular to the substrate 1, the thickness D3 of the first insulator portion 511 is greater than or equal to 1.6 μm and less than or equal to 2.5 μm. For example, the thickness D3 can be 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm or 2.5 μm, etc.

[0137] By reasonably setting the difference between thickness D1 and thickness D2, and by reasonably setting the thickness D2, the depth of via 521 can be reasonably set, thereby further improving the flatness of the first electrode 4 located at via 521 on the side away from the substrate 1.

[0138] Preferably, the material of the first insulator portion 511 includes an organic material, and the material of the second insulator portion 52 includes an inorganic material.

[0139] Specifically, the material of the second insulating part 52 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0140] Moisture is easily transported in organic materials but not easily in inorganic materials. In this embodiment, the materials of the second insulator 512 and the second insulator 52 include inorganic materials, which can prevent moisture in the first insulator 511 from entering the light-emitting material layer of the light-emitting unit. This reduces the risk of dark spots in the light-emitting unit caused by moisture in the first insulator 511, and further improves the display effect of the display panel.

[0141] For some possible implementations, please refer to Figure 6 and Figure 7 The display panel also includes a pixel defining layer 7, which is located on the side of the first electrode 4 and the insulating layer 5 away from the substrate 1. The pixel defining layer 7 includes a pixel opening 71, which exposes a portion of the first electrode 4.

[0142] Optionally, the orthogonal projection of the via 521 on the substrate 1 lies within the orthogonal projection of the pixel opening 71 on the substrate 1.

[0143] Optionally, the orthographic projection of the pixel opening 71 on the substrate 1 is located within the orthographic projection of the second insulating portion 52 on the substrate 1.

[0144] Thus, the film layer in the light-emitting unit 16 located within the pixel opening 71 is flatter, making the light-emitting unit 16 less prone to color shift.

[0145] For some possible implementations, please refer to Figure 8 and Figure 9 The display panel also includes an isolation structure 8, which is located on the side of the pixel defining layer 7 away from the substrate 1. The isolation structure 8 encloses and forms an isolation opening 9, which is connected to the pixel opening 71. The light-emitting unit 16 also includes a light-emitting part 10 and a second electrode 11 stacked on the side of the first electrode 4 away from the substrate 1. The second electrode 11 extends to be electrically connected to the isolation structure 8.

[0146] The isolation structure 8 allows the display panel to form film layers of different colors of light-emitting units 16 in different isolation openings 9 without the need for a fine mask. When forming the light-emitting material layer, the isolation structure 8 separates the light-emitting material layer into multiple spaced-apart light-emitting portions 10. When forming the second electrode material layer, the isolation structure 8 separates the second electrode material layer into multiple spaced-apart second electrodes 11. The isolation structure 8 includes a conductive material, and the second electrodes 11 are electrically connected to the isolation structure 8. A first electrode 4, a light-emitting portion 10, and a second electrode 11 form a light-emitting unit 16. The first electrode 4 can be an anode, and the second electrode 11 can be a cathode.

[0147] In this way, different light-emitting units 16 can be made independent of each other, thereby reducing crosstalk between adjacent light-emitting units 16 and improving the display effect of the display panel. At the same time, due to the presence of the isolation structure 8, the light-emitting material layer and the second electrode material layer in each color light-emitting unit 16 in the display panel can be prepared as a whole before patterning, thereby eliminating the need for a fine mask and saving the manufacturing cost of the display panel.

[0148] For some possible implementations, please refer to Figure 10 and Figure 11 The display panel also includes a first encapsulation layer 12, which is located on the side of the second electrode 11 away from the substrate 1. The first encapsulation layer 12 includes a plurality of encapsulation units 121 spaced apart. At least some of the encapsulation units 121 extend from the side of the isolation structure 8 toward the isolation opening 9 to the side of the isolation structure 8 away from the substrate 1. The plurality of encapsulation units 121 are spaced apart on the side of the isolation structure 8 away from the substrate 1.

[0149] Optionally, the packaging unit 121 located on the side of the isolation structure 8 away from the substrate 1 has a gap with the side of the isolation structure 8 away from the substrate 1.

[0150] During the patterning process of the light-emitting unit 16, the encapsulation unit 121 is disconnected at the isolation structure 8 to form the encapsulation unit 121. The encapsulation unit 121 can completely and independently encapsulate the corresponding light-emitting unit 16, thereby improving the display characteristics of the display panel.

[0151] Preferably, please refer to Figure 12 and Figure 13 The display panel also includes a second encapsulation layer 13 and a third encapsulation layer 14. The second encapsulation layer 13 is located on the side of the first encapsulation layer 12 away from the substrate 1, and the third encapsulation layer 14 is located on the side of the second encapsulation layer 13 away from the substrate 1.

[0152] Optionally, the materials of the first encapsulation layer 12 and the third encapsulation layer 14 both include inorganic materials, and the material of the second encapsulation layer 13 includes organic materials.

[0153] For example, the first encapsulation layer 12 and the third encapsulation layer 14 can be formed by chemical vapor deposition (CVD), and the second encapsulation layer 13 can be formed by inkjet printing (IJP). The second encapsulation layer 13 and the third encapsulation layer 14 can achieve a better encapsulation effect on the light-emitting unit 16, thereby further improving the encapsulation quality of the display panel.

[0154] In some possible implementations, please refer again. Figure 12 The isolation structure 8 includes a first isolation portion 81 and a second isolation portion 82 stacked sequentially along the direction away from the substrate 1. The orthographic projection of the side of the first isolation portion 81 away from the substrate 1 on the substrate 1 is located within the orthographic projection of the second isolation portion 82 on the substrate 1.

[0155] Since the second isolation portion 82 is located on the side of the first isolation portion 81 away from the substrate 1, and on a plane parallel to the substrate 1, the lateral width of the second isolation portion 82 is greater than the lateral width of the first isolation portion 81. Therefore, the second isolation portion 82 causes the light-emitting material layer and the second electrode material layer to be disconnected at the isolation structure 8. In this way, the isolation structure 8 formed by the first isolation portion 81 and the second isolation portion 82 makes it easier to independently package each light-emitting unit 16, thereby improving the packaging yield of the display panel.

[0156] Please see again Figure 12 The second electrode 11 is electrically connected to the first isolation portion 81; the first isolation portion 81 includes a conductive material, and the second electrode 11 extends to contact the side wall of the first isolation portion 81 to achieve electrical connection between the second electrode 11 and the first isolation portion 81.

[0157] Please see again Figure 13 The isolation structure 8 also includes a third isolation portion 83 located on the side of the first isolation portion 81 facing the substrate 1, and the second electrode 11 is electrically connected to the third isolation portion 83.

[0158] The third isolation portion 83 includes a conductive material, and the second electrode 11 extends to contact the sidewall of the third isolation portion 83 to achieve electrical connection between the second electrode 11 and the third isolation portion 83.

[0159] Specifically, the material of the third isolation portion 83 includes molybdenum; and / or, the material of the first isolation portion 81 includes aluminum; and / or, the material of the second isolation portion 82 includes titanium. Thus, when the isolation structure 8 isolates the second electrode material layer as the second electrode 11, the second electrode 11 is more easily electrically connected to the first isolation portion 81 and / or the third isolation portion 83.

[0160] The orthographic projection of the light-emitting portion 10 onto the substrate 1 is outside the orthographic projection of the third isolation portion 83 and / or the first isolation portion 81 onto the substrate 1. In this way, the light-emitting portion 10 does not overlap with the isolation structure 8, thereby effectively improving the crosstalk problem between the light-emitting units 16.

[0161] For some possible implementations, please refer to Figure 14 This application also provides another display panel, which includes a substrate 1, a conductive layer 2, an insulating layer 5, a barrier layer 15, and a light-emitting unit 16.

[0162] The conductive layer 2 is located on one side of the substrate 1, and the conductive layer 2 includes conductive traces 21.

[0163] The insulating layer 5 is located on the side of the conductive layer 2 away from the substrate 1. Along the thickness direction Z of the substrate 1, the insulating layer 5 has a groove 5111 that penetrates the insulating layer 5. At least part of the conductive trace 21 is projected onto the substrate 1 in the same direction as the corresponding groove 5111.

[0164] The barrier layer 15 is located on the side of the insulating layer 5 away from the substrate 1. The barrier layer 15 extends into the groove 5111. Along the thickness direction Z of the substrate 1, the barrier layer 15 located in the groove 5111 has a through hole 521 that penetrates the barrier layer 15. The through hole exposes a portion of the conductive trace 21.

[0165] The light-emitting unit 16 is located on the side of the barrier layer 15 away from the substrate 1. The light-emitting unit 16 includes a first electrode 4, which is electrically connected to the conductive trace 21 through a via 521.

[0166] Moisture is easily transported in organic materials but not easily in inorganic materials. In this embodiment, a barrier layer 15 is provided on the side of the insulating layer 5, which includes organic materials, away from the substrate 1. The barrier layer 15 can prevent moisture in the insulating layer 5 from entering the light-emitting material layer of the light-emitting unit 16, thereby reducing the risk of dark spots in the light-emitting unit 16 caused by moisture in the insulating layer 5, and further improving the display effect of the display panel.

[0167] In some possible implementations, please refer again. Figure 14 Along the direction Z perpendicular to the substrate 1, the thickness of the insulating layer 5 is greater than the thickness of the barrier layer 15.

[0168] In related technologies, vias 521 are disposed on insulating layer 5. In this embodiment, vias 521 are disposed on barrier layer 15, which has a thinner film thickness. This reduces the depth of vias 521, making it easier for the first electrode 4 to fill vias 521 on barrier layer 15. The side of the first electrode 4 located at via 521 that is away from substrate 1 is flatter, making it less likely for the corresponding light-emitting unit 16 to produce color shift, thereby further improving the display effect of the display panel.

[0169] Preferably, the thickness W of the barrier layer 15 is greater than or equal to 0.15 μm and less than or equal to 0.6 μm. For example, the thickness W can be 0.15 μm, 0.2 μm, 3 μm, 0.4 μm, 0.5 μm or 0.6 μm, etc.

[0170] Optionally, the material of the barrier layer 15 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0171] By properly setting the thickness W and material of the barrier layer 15, the flatness of the first electrode 4 located at the via 521 away from the substrate 1 can be improved, while the barrier layer 15 can also improve the effect of blocking water vapor in the insulating layer 5.

[0172] The remaining solutions for the display panel in this embodiment are the same as those in the above embodiments, and will not be described again here.

[0173] For some possible implementations, please refer to Figure 15 This application also provides a method for manufacturing a display panel, the method comprising:

[0174] S10: Provide substrate 1.

[0175] S11: A conductive layer 2 is formed on one side of the substrate 1. The conductive layer 2 includes conductive traces 21.

[0176] S12: An insulating layer 5 is formed on the side of the conductive layer 2 away from the substrate 1. Along the direction parallel to the substrate 1, the insulating layer 5 includes a first insulating portion 51 and a second insulating portion 52. Along the thickness direction Z of the substrate 1, the thickness of the second insulating portion 52 is less than the thickness of the first insulating portion 51. A via 521 is provided on the second insulating portion 52, and the via 521 exposes part of the conductive trace 21.

[0177] S13: A first electrode 4 is formed on the side of the insulating layer 5 away from the substrate 1. The first electrode 4 is electrically connected to the conductive trace 21 through the via 521.

[0178] The depth of the via 521 on the second insulating portion 52 in the display panel formed by the above method is less than the depth of the via 521 in the related art. The first electrode 4 can more easily fill the via 521 on the second insulating portion 52. The side of the first electrode 4 located at the via 521 that is away from the substrate 1 is flatter, so that the corresponding light-emitting unit is less likely to produce color shift, thereby improving the display effect of the display panel.

[0179] In some embodiments, the step of forming an insulating layer 5 on the side of the conductive layer 2 away from the substrate 1 includes:

[0180] Please see Figure 16A first insulator portion 511 is formed on the side of the conductive layer 2 away from the substrate 1. Along the thickness direction Z of the substrate 1, a groove 5111 penetrating the first insulator portion 511 is provided on the first insulator portion 511.

[0181] Please see Figure 17 A second insulator portion 512 is formed on the side of the first insulator portion 511 away from the substrate 1. The second insulator portion 512 extends into the groove 5111 to form a second insulating portion 52 located in the groove 5111. The first insulator portion 511 and the second insulator portion 512 are made of different materials.

[0182] In this embodiment, after patterning the planarization material layer, a planarization layer including multiple arrayed grooves 5111 is formed. The portion of the planarization layer without grooves 5111 forms the first insulator portion 511. Then, material for the second insulator portion 512 is formed on the planarization layer. The material of the second insulator portion 512 located within the grooves 5111 forms the second insulating portion 52. The portion of the first insulator portion 511 located away from the substrate 1 forms the second insulator portion 512. This makes it easier to form the second insulator portion 512 and the second insulating portion 52, and also makes it easier to reduce the depth of the via 521.

[0183] In other embodiments, the step of forming an insulating layer 5 on the side of the conductive layer 2 away from the substrate 1 includes:

[0184] Please see Figure 18 An insulating material layer 17 is formed on the side of the conductive layer 2 away from the substrate 1.

[0185] Please see Figure 19 An insulating layer 5, comprising a first insulating portion 51 and a second insulating portion 52, is formed through a semi-transparent mask.

[0186] In this embodiment, the first insulating part 51 and the second insulating part 52 are formed through the same film layer. Specifically, a semi-transparent mask (i.e., a halftone mask) can be used to form the second insulating part 52 in the thinner part of the insulating layer 5, while the remaining part is the first insulating part 51. In this way, the efficiency of forming the first insulating part 51 and the second insulating part 52 can be improved.

[0187] In some possible implementations, this application also provides an electronic device that includes the display panel described in this application, or includes a display panel prepared by the method described in this application. This electronic device may include a device with image processing capabilities, such as a server, personal computer, laptop computer, etc. Because this electronic device includes the display panel described in this application, its display effect is better.

[0188] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0189] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: Substrate; A conductive layer is located on one side of the substrate, and the conductive layer includes conductive traces; An insulating layer is located on the side of the conductive layer away from the substrate, along a direction parallel to the substrate. The insulating layer includes a first insulating portion and a second insulating portion. Along the thickness direction of the substrate, the thickness of the second insulating portion is less than the thickness of the first insulating portion. A via is provided on the second insulating portion, and the via exposes a portion of the conductive trace. The first electrode is located on the side of the insulating layer away from the substrate, and the first electrode is electrically connected to the conductive trace through the via.

2. The display panel according to claim 1, characterized in that, The first electrode is the anode; Preferably, the first electrode covers the first insulating portion and a portion of the second insulating portion.

3. The display panel according to claim 1, characterized in that, The first insulating portion includes a first insulator portion and a second insulator portion stacked in a direction away from the substrate. The first insulator portion and the second insulator portion are made of different materials. The second insulator portion or the first insulator portion and the second insulating portion are disposed in the same layer. Preferably, the second insulator portion and the second insulating portion are disposed in the same layer, and the second insulator portion and the second insulating portion are integrally formed; Preferably, the material of the second insulator portion is the same as the material of the second insulating portion; Preferably, along a direction perpendicular to the substrate, the thickness of the second insulator portion is equal to the thickness of the second insulating portion; Preferably, the first insulator portion is surrounded to form a groove penetrating the first insulator portion, and the second insulating portion is located within the groove; Preferably, the display panel further includes a planarization layer located between the first electrode and the conductive layer, and the first insulator portion includes the planarization layer.

4. The display panel according to claim 3, characterized in that, Along a direction perpendicular to the substrate, the thickness of the first insulating portion is greater than or equal to 1.75 μm and less than or equal to 3.1 μm; Preferably, along a direction perpendicular to the substrate, the thickness of the second insulating portion is greater than or equal to 0.15 μm and less than or equal to 0.6 μm; Preferably, along a direction perpendicular to the substrate, the thickness of the first insulator portion is greater than or equal to 1.6 μm and less than or equal to 2.5 μm; Preferably, the material of the first insulator portion includes an organic material; Preferably, the material of the second insulating part includes an inorganic material; Preferably, the material of the second insulating portion includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

5. The display panel according to claim 1, characterized in that, The material of the first insulating part is the same as the material of the second insulating part; Preferably, the materials of the first insulating portion and the second insulating portion both include organic materials; Preferably, the first insulating part and the second insulating part are integrally formed; Preferably, along a direction perpendicular to the substrate, the thickness of the first insulating portion is greater than or equal to 1.6 μm and less than or equal to 2.5 μm; Preferably, along a direction perpendicular to the substrate, the thickness of the second insulating portion is greater than or equal to 0.5 μm and less than or equal to 1.5 μm; Preferably, the display panel further includes a planarization layer located between the first electrode and the conductive layer, and the insulating layer includes the planarization layer.

6. The display panel according to any one of claims 1-5, characterized in that, Also includes: A pixel defining layer is located on the side of the first electrode and the insulating layer away from the substrate, the pixel defining layer including a pixel opening that exposes a portion of the first electrode; Preferably, the orthographic projection of the via on the substrate is located within the orthographic projection of the pixel opening on the substrate; Preferably, the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the second insulating portion on the substrate.

7. The display panel according to claim 6, characterized in that, Also includes: An isolation structure is located on the side of the pixel defining layer away from the substrate, the isolation structure encloses an isolation opening, and the isolation opening communicates with the pixel opening; Preferably, it further includes a light-emitting portion and a second electrode stacked on the side of the first electrode away from the substrate, the second electrode extending to be electrically connected to the isolation structure.

8. The display panel according to claim 7, characterized in that, Also includes: A first encapsulation layer is located on the side of the second electrode away from the substrate. The first encapsulation layer includes a plurality of encapsulation units spaced apart, at least a portion of the encapsulation units extending from the side of the isolation structure toward the isolation opening to the side of the isolation structure away from the substrate. Preferably, the plurality of the packaging units are spaced apart on the side of the isolation structure away from the substrate; Preferably, there is a gap between the packaging unit located on the side of the isolation structure away from the substrate and the side of the isolation structure away from the substrate; Preferably, it further includes: The second encapsulation layer is located on the side of the first encapsulation layer away from the substrate; The third encapsulation layer is located on the side of the second encapsulation layer away from the substrate; Preferably, the materials of both the first encapsulation layer and the third encapsulation layer include inorganic materials; Preferably, the material of the second encapsulation layer includes an organic material.

9. The display panel according to claim 7, characterized in that, The isolation structure includes a first isolation portion and a second isolation portion stacked sequentially along a direction away from the substrate, wherein the orthogonal projection of the side of the first isolation portion away from the substrate on the substrate is located within the orthogonal projection of the second isolation portion on the substrate. Preferably, the second electrode is electrically connected to the first isolation portion; and / or, the isolation structure further includes a third isolation portion located on the side of the first isolation portion facing the substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum; and / or, the material of the first isolation portion includes aluminum; and / or, the material of the second isolation portion includes titanium.

10. A display panel, characterized in that, The display panel includes: Substrate; A conductive layer is located on one side of the substrate, and the conductive layer includes conductive traces; An insulating layer is located on the side of the conductive layer away from the substrate. Along the thickness direction of the substrate, the insulating layer has a groove penetrating the insulating layer, and at least a portion of the conductive traces have their orthogonal projections on the substrate located within the orthogonal projections of the corresponding grooves on the substrate. A barrier layer is located on the side of the insulating layer away from the substrate. The barrier layer extends into the groove. Along the thickness direction of the substrate, the barrier layer located in the groove has a via that penetrates the barrier layer. The via exposes a portion of the conductive trace. A light-emitting unit is located on the side of the barrier layer away from the substrate. The light-emitting unit includes a first electrode, which is electrically connected to the conductive trace through the via.

11. The display panel according to claim 10, characterized in that, Along a direction perpendicular to the substrate, the thickness of the insulating layer is greater than the thickness of the barrier layer; Preferably, the thickness of the barrier layer is greater than or equal to 0.15 μm and less than or equal to 0.6 μm; Preferably, the material of the barrier layer includes at least one of silicon nitride, silicon oxide, or silicon oxynitride; Preferably, it further includes: An isolation structure is located on the side of the insulating layer away from the substrate, the isolation structure encloses and forms an isolation opening, and the orthographic projection of the via on the substrate is located within the orthographic projection of the isolation opening on the substrate.

12. A method for manufacturing a display panel, characterized in that, The method includes: Provide substrate; A conductive layer is formed on one side of the substrate, the conductive layer including conductive traces; An insulating layer is formed on the side of the conductive layer away from the substrate. Along a direction parallel to the substrate, the insulating layer includes a first insulating portion and a second insulating portion. Along the thickness direction of the substrate, the thickness of the second insulating portion is less than the thickness of the first insulating portion. A via is provided on the second insulating portion, and the via exposes a portion of the conductive trace. A first electrode is formed on the side of the insulating layer away from the substrate, and the first electrode is electrically connected to the conductive trace through the via.

13. The method for manufacturing a display panel according to claim 12, characterized in that, The step of forming an insulating layer on the side of the conductive layer away from the substrate includes: A first insulator portion is formed on the side of the conductive layer away from the substrate, and a groove penetrating the first insulator portion is provided along the thickness direction of the substrate; A second insulator portion is formed on the side of the first insulator portion away from the substrate, the second insulator portion extending into the groove to form a second insulating portion located within the groove, the first insulator portion and the second insulator portion comprising different materials.

14. The method for manufacturing a display panel according to claim 12, characterized in that, The step of forming an insulating layer on the side of the conductive layer away from the substrate includes: An insulating material layer is formed on the side of the conductive layer away from the substrate; An insulating layer comprising a first insulating portion and a second insulating portion is formed using a semi-transparent mask.

15. An electronic device, characterized in that, The electronic device includes a display panel as described in any one of claims 1-11, or a display panel prepared by the method for preparing a display panel as described in any one of claims 12-14.

Images