Array substrate, display device and electronic equipment
By setting an included angle of 10° to 20° in the via design of the planar layer, the problems of electrode layer breakage and incomplete connection in the via area are solved, thereby improving the product yield and display effect of the display device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- ZHEJIANG LAIBAO DISPLAY TECHNOLOGY CO LTD
- Filing Date
- 2025-08-28
- Publication Date
- 2026-06-30
AI Technical Summary
The electrode layer of the display device is prone to breakage and incomplete connection in the via area, which leads to increased impedance and affects the display effect.
By setting the angle between the first horizontal plane and the first inclined plane of the flat layer to 10° to 20°, the slope angle of the via sidewall is reduced, the via volume is increased, air and photoresist residues are prevented, and the integrity of the electrode layer is ensured.
This reduces the risk of electrode layer breakage in the via area, improves product yield, and ensures good display performance of the display device.
Smart Images
Figure CN224436734U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to an array substrate, display device, and electronic device. Background Technology
[0002] With the development of technology, display devices have been widely used in people's lives. For example, liquid crystal displays and electronic paper displays are used in various electronic devices.
[0003] In related technologies, the array substrate of a display device includes a substrate, a switching board, a planarization layer, and an electrode layer stacked sequentially. The planarization layer has vias, and the electrode layer is electrically connected to the switching board through these vias. However, during manufacturing, the electrode layer is prone to breakage in the via area due to stress, and air residue can remain between the via sidewall and the electrode layer. This can lead to electrode oxidation or photoresist residue within the vias, resulting in incomplete connection of the electrode layer in the via area or damage from foreign objects. This increases the impedance of the electrode layer, affecting the display effect. Utility Model Content
[0004] This application proposes an array substrate, a display device, and an electronic device to solve the technical problem that incomplete connection of the electrode layer in the via area of the planarization layer or damage by foreign objects increases the impedance of the electrode layer, thus affecting the display effect.
[0005] On one hand, this application provides an array substrate for a display device, the array substrate comprising:
[0006] Substrate;
[0007] A switchboard is stacked on the substrate;
[0008] A planar layer is stacked on the side of the switch plate opposite to the substrate;
[0009] An electrode layer is stacked on the side of the flat layer opposite to the switch plate;
[0010] The planarization layer has a first via, and the electrode layer is electrically connected to the switch plate through the first via. The planarization layer includes a first horizontal surface away from the switch plate and a first inclined surface facing the first via and connected to the first horizontal surface. The angle between the first horizontal surface and the first inclined surface is greater than or equal to 10° and less than or equal to 20°.
[0011] In one embodiment, the planarization layer further includes a first arc surface facing the first via, one end of the first arc surface being connected to the first horizontal plane, the other end of the first arc surface being connected to the first inclined plane, and the first arc surface being tangent to both the first horizontal plane and the first inclined plane.
[0012] In one embodiment, the planarization layer further includes a second inclined surface facing the first via, the second inclined surface being connected to the side of the first inclined surface away from the first horizontal plane, and the angle between the second inclined surface and the first horizontal plane being greater than or equal to 30° and less than or equal to 50°.
[0013] In one embodiment, the planarization layer further includes a second arc surface facing the first via, one end of the second arc surface being connected to the first inclined surface, the other end of the second arc surface being connected to the second inclined surface, and the second arc surface being tangent to both the first inclined surface and the second inclined surface.
[0014] In one embodiment, the planarization layer further includes a third arc surface facing the first via, one end of the third arc surface being connected to the second inclined surface, the other end of the third arc surface being connected to the switch plate, and the third arc surface being tangent to both the second inclined surface and the switch plate.
[0015] In one embodiment, the switch board includes a gate layer, a first insulating layer, a semiconductor layer, a source-drain layer, and a second insulating layer stacked sequentially. The gate layer is stacked on the substrate, and the planarization layer is stacked on the side of the second insulating layer opposite to the source-drain layer. The second insulating layer has a second via formed therein. The electrode layer is electrically connected to the source-drain layer through the first via and the second via. The orthographic projection of the second via on the source-drain layer is located within the orthographic projection of the first via on the source-drain layer.
[0016] In one embodiment, the second insulating layer includes a third inclined surface toward the second via, the angle between the third inclined surface and the first horizontal plane being greater than or equal to 40° and less than or equal to 70°.
[0017] In one embodiment, the gate layer includes a plurality of parallel-spaced scan lines, and the source-drain layer includes a plurality of parallel-spaced data lines. The scan lines and the data lines are intersected to form a plurality of pixel units arranged in an array.
[0018] The gate layer further includes a plurality of gates, each of which is disposed within a corresponding pixel unit and electrically connected to the scan line;
[0019] The source-drain layer further includes multiple sources and multiple drains. Each source is disposed in the corresponding pixel unit and electrically connected to the data line. Each drain is spaced apart from the corresponding source.
[0020] The semiconductor layer includes a plurality of semiconductors, each of which is connected to a corresponding source and a corresponding drain.
[0021] The electrode layer includes a plurality of pixel electrodes, each of which is disposed in the corresponding pixel unit and electrically connected to the corresponding drain electrode through the first via and the second via.
[0022] On the other hand, this application also provides a display device, including a display substrate and an array substrate as described above, wherein the display substrate and the array substrate are disposed opposite to each other.
[0023] In another aspect, this application also provides an electronic device, including the display device described above.
[0024] As can be seen from the above technical solution, the array substrate provided in this application reduces the slope angle of the first via sidewall by setting the angle between the first horizontal plane and the first inclined plane to 10° to 20°. This reduces the stress on the electrode layer in the first via area and lowers the risk of the electrode layer breaking in the first via area. Furthermore, it increases the volume of the first via, making it easier for air to escape and for the first via to be cleaned. This prevents air from remaining between the first inclined plane and the electrode layer and prevents photoresist from remaining in the first via, thereby preventing incomplete connection of the electrode layer in the first via area or damage from foreign objects. This improves product yield while ensuring that the display device has a good display effect. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0026] Figure 1 This is a cross-sectional view of the array substrate in one embodiment of this application.
[0027] Figure 2 yes Figure 1 Enlarged view of point A in the middle.
[0028] Figure 3 This is a cross-sectional view of the array substrate in another embodiment of this application.
[0029] Figure 4 yes Figure 3 Enlarged view of section B in the middle.
[0030] Figure 5 This is a cross-sectional view of the array substrate in another embodiment of this application.
[0031] Figure 6 This is a top view of the array substrate in one embodiment of this application. Detailed Implementation
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0034] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0035] like Figures 1-6As shown, this application provides an array substrate 10 for a display device. The array substrate 10 includes a substrate 100, a switching element plate 200, a planarization layer 300, and an electrode layer 400. The switching element plate 200 is stacked on the substrate 100, the planarization layer 300 is stacked on the side of the switching element plate 200 opposite to the substrate 100, and the electrode layer 400 is stacked on the side of the planarization layer 300 opposite to the switching element plate 200. The planarization layer 300 has a first via 310, and the electrode layer 400 is electrically connected to the switching element plate through the first via 310. The planarization layer 300 includes a first horizontal surface 320 on the side opposite to the switching element plate 200 and a first inclined surface 330 facing the first via 310 and connected to the first horizontal surface 320. The included angle α between the first horizontal surface 320 and the first inclined surface 330 is greater than or equal to 10° and less than or equal to 20°. Compared with related technologies, the array substrate 10 provided in this application reduces the slope angle of the sidewall of the first via 310 by setting the included angle α between the first horizontal plane 320 and the first inclined plane 330 to 10° to 20°. This reduces the stress on the electrode layer 400 in the area of the first via 310 and lowers the risk of breakage of the electrode layer 400 in the area of the first via 310. Furthermore, it can increase the volume of the first via 310, making it easier for air to escape and for the first via 310 to be cleaned. This prevents air from remaining between the first inclined plane 330 and the electrode layer 400 and prevents photoresist from remaining in the first via 310. This prevents the electrode layer 400 from being incompletely connected or damaged by foreign objects in the area of the first via 310, improves product yield, and ensures that the display device has a good display effect.
[0036] For example, substrate 100 is made of a light-transmitting rigid material, such as glass or acrylic, thereby giving substrate 100 a certain degree of rigidity and flatness. It should be noted that in other embodiments, substrate 100 may also be made of a light-transmitting flexible material, such as PET (polyethylene terephthalate), PEN (polyethylene naphthalate), or PI (polyimide), thereby giving substrate 100 a certain degree of flexibility to improve comfort and enhance user experience.
[0037] Optional, such as Figure 1 As shown, the switch board 200 includes a gate layer 210, a first insulating layer 220, a semiconductor layer 230 and a source / drain layer 240 stacked sequentially, with the gate layer 210 stacked on the substrate 100.
[0038] Furthermore, such as Figure 1 and Figure 6As shown, the gate layer 210 includes a plurality of parallel spaced scan lines 211, and the source and drain layers 240 include a plurality of parallel spaced data lines 241. The scan lines 211 and the data lines 241 are intersected to form a plurality of pixel units 250 arranged in an array.
[0039] The gate layer 210 also includes a plurality of gates 212, each gate 212 being disposed within a corresponding pixel unit 250 and electrically connected to a scan line 211. The source-drain layer 240 also includes a plurality of sources 242 and a plurality of drains 243, each source 242 being disposed within a corresponding pixel unit 250 and electrically connected to a data line 241, and each drain 243 being spaced apart from a corresponding source 242.
[0040] The semiconductor layer 230 includes a plurality of semiconductors 231, each semiconductor 231 being connected to a corresponding source 242 and a corresponding drain 243. It should be noted that an ohmic contact layer may also be provided between each semiconductor 231 and its corresponding source 242 and its corresponding drain 243 to reduce contact resistance.
[0041] The gate layer 210 is formed on the substrate 100 in a certain pattern by photolithography. The specific process of photolithography is as follows:
[0042] A first metal layer is deposited on substrate 100 (by physical sputtering or by plasma-enhanced chemical vapor deposition). The first metal layer may be Al or Cu as the core metal layer, and other metal materials such as Ti, Mo, Nb, etc. need to be added on Al or Cu to form a composite metal material.
[0043] Photoresist is coated on the first metal layer, and the photoresist is exposed and developed through a photomask with a specific pattern. The photoresist exposed to ultraviolet light dissolves into the developing solution, so that the photoresist after exposure and development is consistent with the specific pattern on the photomask.
[0044] The first metal layer is etched (by wet etching or dry etching) to remove the first metal layer that is not protected by the photoresist. At this time, the first metal layer is consistent with the specific pattern on the photomask.
[0045] The photoresist stacked on the first metal layer is stripped using a chemical solution to form a gate layer 210 that matches a specific pattern on the photomask.
[0046] The first insulating layer 220 is formed on the gate layer 210 in a specific pattern using photolithography. The specific process of photolithography is the same as described above and will not be repeated here. Optionally, the first insulating layer 220 is made of materials such as SiNx, SiOx, PI, or PS. It should be noted that since the gate layer 210 is only stacked on a portion of the substrate 100, the first insulating layer 220 is partially stacked on the gate layer 210 and partially stacked on the substrate 100.
[0047] The semiconductor layer 230 is formed on the first insulating layer 220 in a specific pattern using photolithography. The specific process of photolithography is the same as described above and will not be repeated here. Optionally, the semiconductor layer 230 is made of materials such as a-Si, IGZO, or LTPS.
[0048] The source / drain layer 240 is formed on the semiconductor layer 230 in a specific pattern using photolithography. The specific process of photolithography is the same as described above and will not be repeated here. The source / drain layer 240 can use Al or Cu as the core metal layer, and other metal materials such as Ti, Mo, and Nb need to be added on top of Al or Cu to form a composite metal material. It can be understood that since the semiconductor layer 230 is only stacked on a portion of the first insulating layer 220, the source / drain layer 240 is partially stacked on the semiconductor layer 230 and partially stacked on the first insulating layer 220.
[0049] The planarization layer 300 is formed on the source / drain layer 240 in a specific pattern using photolithography. The specific process of photolithography is the same as described above and will not be repeated here. Optionally, the planarization layer 300 can be made of organic or inorganic insulating materials. For example, if the planarization layer 300 is made of organic insulating material, organic materials have a lower dielectric constant, and the process thickness can reach 1.5 to 2.5 μm, thereby reducing the pixel storage capacitance. It is understood that since the source / drain layer 240 is only stacked on a portion of the first insulating layer 220, and the source 242 and drain 243 are spaced apart, the planarization layer 300 is partially stacked on the source / drain layer 240, partially stacked on the semiconductor layer 230, and partially stacked on the first insulating layer 220.
[0050] The electrode layer 400 is formed on the planarization layer 300 in a specific pattern using photolithography. The specific process of photolithography is the same as described above and will not be repeated here. Optionally, the electrode layer 400 is made of conductive materials such as metal, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), or indium gallium zinc oxide.
[0051] Furthermore, such as Figure 1 and Figure 6As shown, the electrode layer 400 includes a plurality of pixel electrodes 410, each pixel electrode 410 being disposed within a corresponding pixel unit 250.
[0052] like Figure 1 , Figure 2 and Figure 6 As shown, the planarization layer 300 forms a first via 310 in each pixel unit 250, and each pixel electrode 410 is electrically connected to the corresponding drain 243 through the corresponding first via 310; the planarization layer 300 includes a first horizontal surface 320 on the side away from the drain 243 and a first inclined surface 330 facing the first via 310 and connected to the first horizontal surface 320; the included angle α between the first horizontal surface 320 and the first inclined surface 330 is greater than or equal to 10° and less than or equal to 20°. By setting the included angle α between the first horizontal plane 320 and the first inclined plane 330 to 10° to 20°, the slope angle of the sidewall of the first via 310 is reduced. This reduces the stress on the electrode layer 400 within the region of the first via 310, lowering the risk of breakage. Furthermore, it increases the volume of the first via 310, making it easier for air to escape and for the via 310 to be cleaned. This prevents air residue between the first inclined plane 330 and the electrode layer 400, and prevents photoresist residue within the via 310, thus preventing incomplete connection or damage to the electrode layer 400 by foreign objects within the region of the first via 310. This improves product yield while ensuring good display performance. It should be noted that the included angle α between the first horizontal plane 320 and the first inclined plane 330 is the smallest positive angle formed when the first horizontal plane 320 and the first inclined plane 330 intersect.
[0053] Furthermore, such as Figure 3 and Figure 4 As shown, the planarization layer 300 also includes a first arc surface 340 facing the first via 310. One end of the first arc surface 340 is connected to the first horizontal surface 320, and the other end is connected to the first inclined surface 330. The first arc surface 340 is tangent to both the first horizontal surface 320 and the first inclined surface 330, thereby making the first horizontal surface 320 smoothly connected to the first inclined surface 330 through the first arc surface 340. This reduces the stress on the electrode layer 400 at the junction of the first horizontal surface 320 and the first inclined surface 330, and reduces the risk of the electrode layer 400 breaking at the junction of the first horizontal surface 320 and the first inclined surface 330.
[0054] Furthermore, the planarization layer 300 also includes a second inclined surface 350 facing the first via 310. The second inclined surface 350 is connected to the side of the first inclined surface 330 facing away from the first horizontal surface 320. The included angle β between the second inclined surface 350 and the first horizontal surface 320 is greater than or equal to 30° and less than or equal to 50°. The provision of the second inclined surface 350 can prevent the volume of the first via 310 from being too large, and avoid the planarization layer 300 from being too thin at the positions corresponding to the semiconductor layer 230 and the source / drain layer 240.
[0055] Optionally, the planarization layer 300 further includes a second arc surface 360 facing the first via 310. One end of the second arc surface 360 is connected to the first inclined surface 330, and the other end of the second arc surface 360 is connected to the second inclined surface 350. The second arc surface 360 is tangent to both the first inclined surface 330 and the second inclined surface 350, thereby making the first inclined surface 330 and the second inclined surface 350 smoothly connected. This reduces the stress on the electrode layer 400 at the transition point between the first inclined surface 330 and the second inclined surface 350, and reduces the risk of the electrode layer 400 breaking at the transition point between the first inclined surface 330 and the second inclined surface 350.
[0056] Furthermore, the planarization layer 300 also includes a third arc surface 370 facing the first via 310. One end of the third arc surface 370 is connected to the second inclined surface 350, and the other end of the third arc surface 370 is connected to the drain electrode 243. The third arc surface 370 is tangent to the second inclined surface 350 and the drain electrode 243, thereby making the second inclined surface 350 and the drain electrode 243 smoothly connected. This reduces the stress on the electrode layer 400 at the transition point between the second inclined surface 350 and the drain electrode 243, and reduces the risk of the electrode layer 400 breaking at the transition point between the second inclined surface 350 and the drain electrode 243.
[0057] Optional, such as Figure 5 As shown, the switch board 200 also includes a second insulating layer 260, which is formed on the source and drain layers 240 in a specific pattern using photolithography. In this embodiment, a planarization layer 300 is stacked on the second insulating layer 260.
[0058] Furthermore, the second insulating layer 260 forms a second via 261 in each pixel unit 250. The pixel electrode 410 is electrically connected to the corresponding drain 243 through the corresponding first via 310 and the corresponding second via 261. The orthographic projection of the second via 261 on the drain 243 is located within the orthographic projection of the first via 310 on the drain 243.
[0059] Furthermore, the second insulating layer 260 includes a third inclined surface 262 facing the second via 261, and the angle γ between the third inclined surface 262 and the first horizontal surface 320 is greater than or equal to 40° and less than or equal to 70°.
[0060] Understandably, when the planarization layer 300 does not include the second inclined surface 350, one end of the third inclined surface 262 is connected to the side of the first inclined surface 330 facing away from the first horizontal surface 320, and the other end of the third inclined surface 262 is connected to the drain 243. In this case, a first arcuate surface tangent to both the first inclined surface 330 and the third inclined surface 262 can be formed between them, allowing for a smooth connection between the first inclined surface 330 and the third inclined surface 262. A second arcuate surface tangent to both the third inclined surface 262 and the drain 243 can also be formed between the third inclined surface 262 and the drain 243, allowing for a smooth connection between the third inclined surface 262 and the drain 243.
[0061] When the planarization layer 300 includes the second inclined surface 350, one end of the third inclined surface 262 is connected to the side of the second inclined surface 350 away from the first inclined surface 330, and the other end of the third inclined surface 262 is connected to the drain electrode 243. At this time, a third arc-shaped surface tangent to the second inclined surface 350 and the third inclined surface 262 can be formed between the second inclined surface 350 and the third inclined surface 262, so that the second inclined surface 350 and the third inclined surface 262 are smoothly connected.
[0062] This application also provides a display device, which includes a display substrate and an array substrate 10 as described above, with the display substrate and the array substrate 10 disposed opposite to each other.
[0063] Furthermore, the display device also includes a display material and a frame adhesive, which are respectively disposed between the display substrate and the array substrate 10. When the display material is liquid crystal material, the display device is a liquid crystal display device. When the display material is electronic paste, the display device is an electronic paper display device. The frame adhesive is bonded to the outer edges of the display substrate and the array substrate 10 to connect the display substrate and the array substrate 10 together and seal the display substrate and the array substrate 10.
[0064] Furthermore, the display device also includes a barrier wall disposed between the display substrate and the array substrate 10, and the barrier wall is disposed corresponding to the scan line 211 and the data line 241 to isolate adjacent pixel units 250.
[0065] This application also provides an electronic device, which includes the display device described above. The electronic device may be an e-book, a mobile phone, or a computer, etc.
[0066] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An array substrate for a display device, characterized in that, The array substrate includes: Substrate; A switchboard is stacked on the substrate; A planar layer is stacked on the side of the switch plate opposite to the substrate; An electrode layer is stacked on the side of the flat layer opposite to the switch plate; The planarization layer has a first via, and the electrode layer is electrically connected to the switch plate through the first via. The planarization layer includes a first horizontal surface away from the switch plate and a first inclined surface facing the first via and connected to the first horizontal surface. The angle between the first horizontal surface and the first inclined surface is greater than or equal to 10° and less than or equal to 20°.
2. The array substrate as described in claim 1, characterized in that, The planarization layer further includes a first arc surface facing the first through hole, one end of the first arc surface is connected to the first horizontal plane, the other end of the first arc surface is connected to the first inclined plane, and the first arc surface is tangent to the first horizontal plane and the first inclined plane respectively.
3. The array substrate as described in claim 1 or 2, characterized in that, The planarization layer further includes a second inclined surface facing the first via, the second inclined surface being connected to the side of the first inclined surface away from the first horizontal plane, and the angle between the second inclined surface and the first horizontal plane being greater than or equal to 30° and less than or equal to 50°.
4. The array substrate as described in claim 3, characterized in that, The planarization layer further includes a second arc surface facing the first via, one end of the second arc surface is connected to the first inclined surface, the other end of the second arc surface is connected to the second inclined surface, and the second arc surface is tangent to both the first inclined surface and the second inclined surface.
5. The array substrate as described in claim 3, characterized in that, The planarization layer further includes a third arc surface facing the first via, one end of the third arc surface being connected to the second inclined surface, the other end of the third arc surface being connected to the switch plate, and the third arc surface being tangent to both the second inclined surface and the switch plate.
6. The array substrate as claimed in claim 1, characterized in that, The switching board includes a gate layer, a first insulating layer, a semiconductor layer, a source and drain layer, and a second insulating layer stacked sequentially. The gate layer is stacked on the substrate, and the planarization layer is stacked on the side of the second insulating layer opposite to the source and drain layer. The second insulating layer has a second via formed therein. The electrode layer is electrically connected to the source and drain layer through the first via and the second via. The orthographic projection of the second via on the source and drain layer is located within the orthographic projection of the first via on the source and drain layer.
7. The array substrate as described in claim 6, characterized in that, The second insulating layer includes a third inclined surface facing the second via, the angle between the third inclined surface and the first horizontal plane being greater than or equal to 40° and less than or equal to 70°.
8. The array substrate as described in claim 6, characterized in that, The gate layer includes a plurality of parallel and spaced scan lines, and the source and drain layers include a plurality of parallel and spaced data lines. The scan lines and the data lines are intersected to form a plurality of pixel units arranged in an array. The gate layer further includes a plurality of gates, each of which is disposed within a corresponding pixel unit and electrically connected to the scan line; The source-drain layer further includes multiple sources and multiple drains. Each source is disposed in the corresponding pixel unit and electrically connected to the data line. Each drain is spaced apart from the corresponding source. The semiconductor layer includes a plurality of semiconductors, each of which is connected to a corresponding source and a corresponding drain. The electrode layer includes a plurality of pixel electrodes, each of which is disposed in the corresponding pixel unit and electrically connected to the corresponding drain electrode through the first via and the second via.
9. A display device, characterized in that, It includes a display substrate and an array substrate as described in any one of claims 1 to 8, wherein the display substrate and the array substrate are disposed opposite to each other.
10. An electronic device, characterized in that, Includes the display device as described in claim 9.