Test key structure and test method thereof, wafer structure

Abstract

The application provides a test key structure, a test method thereof and a wafer structure. The test key structure comprises a plurality of spaced-apart pads, the plurality of pads comprising at least one first pad and a plurality of second pads; a test lead wire, the first pad and the corresponding test lead wire being electrically connected, the second pad and the test lead wire being insulated; the test lead wire comprising a plurality of lead wire segments arranged in the same layer as the pads, the first pad and at least one lead wire segment around the first pad being connected to each other, the second pad and all the lead wire segments around the second pad being spaced apart; and at least one lead wire segment around each pad and the adjacent lead wire segment being spaced apart from each other. When the test key structure and a probe are used to detect a wafer structure, whether a position offset occurs between the probe and the pad can be detected through the test lead wire; in addition, electromagnetic induction in the test lead wire can be alleviated or eliminated, so that the detection accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and in particular to a test bond structure and its test method, and a wafer structure. Background Technology

[0002] Wafer structures require multiple inspections during manufacturing to ensure the quality of the final product. During inspection, probes on a probe card are connected to the test pads on the dicing tracks of the wafer structure. Inspection allows for the identification of any abnormalities in the wafer structure. However, current test pad structures, due to their inherent design limitations, cannot detect probe abnormalities during testing, resulting in low accuracy of the test results. Summary of the Invention

[0003] The first aspect of this application provides a test key structure, which includes a plurality of spaced-apart pads, the plurality of pads including at least one first pad and a plurality of second pads; a test wire, wherein the first pads and the corresponding test wires are electrically connected, and the second pads and the test wires are insulated; the test wires include a plurality of wire segments disposed on the same layer as the pads, the first pads being interconnected with at least one of the wire segments surrounding them, and the second pads being spaced apart from all the wire segments surrounding them; and at least one wire segment surrounding each pad is spaced apart from adjacent wire segments.

[0004] In an embodiment of the first aspect of this application, any two adjacent conductor segments are spaced apart from each other, and the test conductor further includes at least one connecting segment disposed on a different layer from the conductor segments, and the conductor segment surrounding the second pad is electrically connected to the first pad through the connecting segment.

[0005] In an embodiment of the first aspect of this application, the conductor segment is provided on the same side of the first pad and the second pad.

[0006] In an embodiment of the first aspect of this application, in each of the test key structures, the pads are arranged in a row, and for each row of pads, a conductor segment is provided on at least one side of the pad along a first direction, wherein the first direction is perpendicular to the direction of the row.

[0007] In an embodiment of the first aspect of this application, in each test key structure, the pads are arranged in multiple rows. For each row of pads, along a first direction, the conductor segments are arranged in multiple rows, with the row containing the conductor segments corresponding one-to-one with the row containing the pads and arranged alternately; or the conductor segments are arranged in multiple rows, with corresponding conductor segments provided on both opposite sides of the pads, and a row of conductor segments arranged between adjacent rows of pads; or the conductor segments are arranged in multiple rows, with corresponding conductor segments provided on both opposite sides of the pads, and two rows of conductor segments arranged between adjacent rows of pads; wherein, the first direction is perpendicular to the direction of the row.

[0008] In an embodiment of the first aspect of this application, in each of the test key structures, the pads are arranged in at least one row. For each row of pads, a conductor segment is provided on the same side of all the pads along a second direction; or the conductor segment is provided on both opposite sides of the pads, and one conductor segment is provided between each adjacent pad; or the conductor segment is provided on both opposite sides of the pads, and two conductor segments are provided between adjacent pads; wherein the second direction is parallel to the direction of the row.

[0009] In an embodiment of the first aspect of this application, the size of the conductor segment and the size of the corresponding pad are equal along the extension direction of the conductor segment.

[0010] In an embodiment of the first aspect of this application, the spacing between the pads and the corresponding conductor segments is equal, and the spacing is 5 to 25 micrometers.

[0011] The second aspect of this application provides a wafer structure having dicing channels, within which a plurality of test bond structures mentioned in the first aspect are disposed.

[0012] A third aspect of this application provides a testing method for the test key structure mentioned in the first aspect above. The testing method includes: providing a probe card, causing the probes of the probe card to pierce the first pad and the second pad; obtaining an electrical signal between the current loop formed by the first pad, the second pad, and the probe card; determining that the probe is aligned with the first pad and the second pad when the value of the electrical signal is less than a threshold; and determining that the probe is offset relative to the first pad and the second pad when the value of the electrical signal is greater than or equal to the threshold. Attached Figure Description

[0013] Figure 1 The diagram shows a planar structure of the test key.

[0014] Figure 2This is a schematic diagram of another planar structure of the test bond structure shown.

[0015] Figure 3 for Figure 2 The cross-sectional view of the test key structure is shown.

[0016] Figure 4 for Figure 2 The diagram shows a test key structure in one detection state.

[0017] Figure 5 for Figure 2 The diagram shows the test key structure under another detection state.

[0018] Figure 6 This is a schematic diagram of the planar structure of the test key structure provided in an embodiment of this application under one design.

[0019] Figure 7 This is a schematic diagram of a planar structure of the test key structure provided in an embodiment of this application under another design.

[0020] Figure 8 This is a schematic diagram of a planar structure of the test key structure provided in an embodiment of this application under another design.

[0021] Figure 9 This is a schematic diagram of a planar structure of the test key structure provided in an embodiment of this application under another design.

[0022] Figure 10 This is a schematic diagram of a planar structure of the test key structure provided in an embodiment of this application under another design.

[0023] Figure 11 This is a schematic diagram of a planar structure of the test key structure provided in an embodiment of this application under another design.

[0024] Figure 12 The figure shown is a schematic diagram of a planar structure of a wafer structure provided in an embodiment of this application.

[0025] Figure 13 for Figure 1 An enlarged view of the S1 region of the wafer structure shown.

[0026] The reference numerals in the attached figures are explained as follows:

[0027] 100 - Pad; 111 - First pad; 112 - Second pad; 200 - Test lead; 210, 210a~210d - Lead segments; 220 - Connector segment; 230 - Insulating layer; 300 - Pin drop area; 301 - First pin drop area; 302 - Second pin drop area; 1 - Wafer structure; 10 - Test bond structure; 11 - Chip; 12 - Die-scribing path. Detailed Implementation

[0028] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0029] During wafer structure testing, probes on a probe card are used to connect to pads for testing bond structures. Therefore, any abnormality in the probe placement directly affects the test results. In practice, after testing the wafer structure, if the test data is abnormal, it is necessary to further determine whether the probe placement is abnormal. Specifically, a new probe card is used to repeat the test, and the data from the repeated measurements is used to determine whether the previous data anomaly was caused by a probe placement malfunction. This method cannot directly determine whether the previous data anomaly was caused by probe damage; furthermore, repeating the wafer structure test not only significantly increases testing time and labor costs but also increases the risk of wafer structure damage.

[0030] In the embodiments of this application, please refer to the following for details. Figure 1 The test key structure 10 can arrange wires 200 around the pads 100, and select a first pad 111 from the pads 100 so that the first pad 111 is connected to the wires 200, while the second pad 112 is spaced apart from the wires 200. Thus, during testing, if the probe is aligned with the pads 100, an open circuit will be formed between the second pad 112 and the first pad 111; if the probe is not aligned with the second pad 112 but is connected to the wire, a short circuit will be formed between the second pad 112 and the first pad 111. Based on this, it can be determined whether the probe is aligned with the pads 100 and whether there is any abnormality in the probe's insertion.

[0031] In the process scenarios described above, factors such as test operations and moving wafer structures can easily cause charge to accumulate on the wires. To avoid the risk of electromagnetic induction in the wires leading to interference with test results or damage to the wafer structure, the wires can be designed to avoid forming a closed loop shape while surrounding the pads, as follows:

[0032] This application provides a test bond structure and its testing method, as well as a wafer structure, to at least solve the aforementioned technical problems. The test bond structure includes multiple spaced-apart pads, each pad including at least one first pad and multiple second pads; test leads, with the first pads electrically connected to their corresponding test leads, and the second pads insulated from the test leads; the test leads include multiple conductor segments disposed on the same layer as the pads, with the first pad connected to at least one conductor segment around it, and the second pads spaced apart from all conductor segments around them; and at least one conductor segment around each pad is spaced apart from adjacent conductor segments. A scribe line is provided on the wafer structure, and at least one test bond structure is disposed within the scribe line. When testing the wafer structure using this test key structure and probes, the positional offset between the probe and the pad can be detected by the wire segments, thereby determining whether there is any abnormality in the probe's insertion. In addition, at least one of the wire segments around each pad is spaced apart from the adjacent wire segments, so that multiple wire segments arranged in the same layer do not form a complete closed loop structure. This can alleviate or eliminate electromagnetic induction between test wires in the same layer, thereby improving the accuracy of the test results and avoiding damage to the wafer structure caused by electromagnetic induction.

[0033] The test bond structure, its testing method, and the wafer structure according to the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that in the following embodiments, the wafer structure is described directly to simultaneously explain the specific design of the test bond structure and the principle of solving the technical problem.

[0034] Furthermore, in these figures, a spatial rectangular coordinate system is established with the plane of the wafer structure (e.g., the plane of the substrate it includes) as the reference to more intuitively present the positional relationship of related structures in the wafer structure. In this spatial rectangular coordinate system, the X-axis and Y-axis are parallel to the plane of the wafer structure, and the Z-axis (not shown in the figure) is perpendicular to the plane of the wafer structure.

[0035] like Figures 2 to 11 As shown, the test key structure 10 provided in this embodiment includes a plurality of spaced-apart pads 100, each pad 100 including at least one first pad 111 and a plurality of second pads 112; test leads 200, the first pads 111 and the corresponding test leads 200 are electrically connected, and the second pads 112 and the test leads 200 are insulated; the test leads 200 include a plurality of lead segments 210 disposed on the same layer as the pads 100, the first pads 111 and at least one of the lead segments 210 on their periphery are interconnected, and the second pads 112 and all the lead segments 210 on their periphery are spaced apart; and at least one lead segment 210 on the periphery of each pad 100 is spaced apart from the adjacent lead segments 210.

[0036] In the embodiments of this application, such as Figure 3 As shown, any two adjacent conductor segments 210 can be spaced apart from each other, and each conductor segment 210 is electrically connected to the first pad 111 directly or indirectly. A direct connection means the first pad 111 is directly connected to the conductor segment 210, while an indirect connection means the first pad 111 and the conductor segment 210 are electrically connected through other conductive structures. The second pad 112 is insulated from the conductor segment 210; for example, the second pad 112 is spaced apart from the conductor segment 210. Thus, during testing, no part of the test conductor 200 will form a closed loop structure. This avoids electromagnetic induction in the test conductor 200 when testing the wafer structure 1 with a probe, thereby further improving the accuracy of the test results and further preventing damage to the wafer structure 1 caused by electromagnetic induction.

[0037] In this embodiment, a trace can be configured to achieve an electrical connection between the conductor segment 210 and the first pad 111. The configuration of this trace is not limited in this embodiment and can be selected according to the actual process requirements.

[0038] In the embodiments of this application, such as Figure 3 As shown, the test lead 200 also includes at least one connecting segment 220 disposed on a different layer from the lead segment 210. The lead segment surrounding the second pad 112 is electrically connected to the first pad 111 through the connecting segment 220. This reduces the area occupied by the test lead 200 (i.e., the area occupied by the projection of all test leads 200 onto the wafer structure surface), thereby reducing the width occupied by the test lead 200. For example, different connecting segments 220 are separated by an insulating layer 230, and vias are provided in the insulating layer 230 to allow the connecting segment 220 to connect to the corresponding lead segment 210. Furthermore, when the number of pads is greater than the number of metal layers, metal layers can be reused. For example, if there are 24 pads, and the wafer structure itself has 6 metal layers and an upper metal layer, pads 1-6 are sequentially connected to the 6 metal layers, pads 7-12 are then sequentially connected to the same 6 layers, and pads 13-18 and pads 19-24 are similarly configured. The fact that the pads 100 are on the same layer and form a frame will also generate electromagnetic induction. Using the connecting segments 220 of different layers for the conductor segments 210 corresponding to the pads 100 can minimize the impact of electromagnetic induction.

[0039] Based on the above-described scheme of this application, the working principle of determining whether the probe malfunctions while testing the wafer structure 1 can be as follows: Figure 5 and Figure 6 As shown, the details are as follows:

[0040] like Figure 4As shown, the probe landing area 301 (which can be called the pin mark) of the probe card falls within the pad 100, which indicates that the probe can be aligned with each pad 100. In this case, the probe will not contact the wire segment 210. Therefore, the test results of the circuit used for testing at the first pad 111 and the second pad 112 show an open circuit. It can be determined that the probe is completely aligned with the pad 100 and there is no abnormality of the probe.

[0041] like Figure 5 As shown, in the area where the third pad 100 is located, the probe landing area 300 includes a first landing area 301 that lands inside the pad 100 and a second landing area 302 that lands outside the pad 100 to contact the wire segment 210 corresponding to the pad 100. Landing in the second landing area 302 indicates that the probe at this position is not aligned with each pad 100. In this case, the circuit used for testing shows a short circuit (which can be understood as a closed circuit) at the third first pad 111 and the second pad 112. Therefore, it is determined that the probe is not completely aligned with the pad 100 at this location, and the probe is abnormal at this location.

[0042] For example, the current for determining whether a short circuit has occurred can be set to 1 microamp (1E-6A). If the current is equal to or exceeds this value, a short circuit is determined to have occurred, resulting in the probe being misaligned with the pad (e.g., the second pad). Conversely, if the current does not exceed this value, the probe is determined to be aligned with the pad.

[0043] In the embodiments of this application, the arrangement of the wire segments can be determined according to actual needs, as long as it can determine whether the probe is abnormal during the test and alleviate or eliminate electromagnetic induction. Several arrangements of the wire segments are illustrated below.

[0044] In the embodiments of this application, please refer again. Figure 2 Using the Y-axis (the first direction below) as the vertical direction, all pads 100 have tracer segments 210 on their upper and lower sides; that is, all pads 100 have tracer segments 210 on the same side. It should be noted that even if all pads 100 have tracer segments 210 on their upper sides but not on their lower sides, it is still considered that all pads 100 have tracer segments 210 on the same side. Thus, during testing, if the probe is offset relative to the pad, it is more likely to cause positional shifts on the same side of the pads 100 when testing them sequentially. Arranging the tracer segments 210 according to this pattern can improve the accuracy of the test results.

[0045] In this embodiment, the pads are arranged in a row. In each test key structure, the pads are arranged in a row. For each row of pads, wire segments are respectively provided on two opposite sides of the pads along a first direction, which is perpendicular to the direction of the row. For example, see [link to previous document]. Figure 2 In each test key structure 10, the pads 100 are arranged in at least one row (the row direction is parallel to the X-axis), and the two opposite sides of the row containing the pads 100 ( Figure 3 Conductor segments 210 are provided on both the upper and lower sides of the pad 100. In this way, the alignment between the pad 100 and the test probe can be detected on both the upper and lower sides of the pad 100, thereby further improving the accuracy of the test results.

[0046] In other embodiments of this application, the pads are arranged in a row. In each test key structure, the pads are arranged in a row. For each row of pads, a conductor segment is provided on one side of the pad along a first direction, which is perpendicular to the direction of the row. For example, as... Figure 6 As shown, the conductor segment 210 on the lower side of the pad 100 is deleted, so that the pad 100 is arranged in at least one row, and the conductor segment 210 is only provided on one side of the row where the pad 100 is located.

[0047] In other embodiments of this application, in each test key structure, the pads are arranged in multiple rows. For each row of pads, along a first direction, conductor segments are arranged in multiple rows. The row containing the conductor segments corresponds one-to-one with the row containing the pads and is arranged alternately. The first direction is perpendicular to the direction of the row. Figure 7 As shown, along the Y-axis, pads 100 and conductor segments 210 are arranged in multiple rows. Only one row of conductor segments 210 is arranged between adjacent rows of pads 100, and only one row of pads 100 is arranged between adjacent rows of conductor segments 210. Thus, each row of pads 100 corresponds to only one row of conductor segments 210.

[0048] In this embodiment of the application, in each test key structure, the pads are arranged in multiple rows. For each row of pads, along a first direction, conductor segments are arranged in multiple rows. Corresponding conductor segments are respectively provided on both opposite sides of the pads, and two rows of conductor segments are arranged between adjacent rows of pads. The first direction is perpendicular to the direction of the row. Figure 8 As shown, along the Y-axis, the pads 100 and conductor segments 210 are arranged in multiple rows, with two rows of conductor segments 210 arranged between adjacent rows of pads 100. Thus, each row of pads 100 corresponds to two rows of conductor segments 210 on the upper and lower sides.

[0049] In some embodiments of this application, in each test key structure, the pads are arranged in multiple rows. For each row of pads, along a first direction, conductor segments are arranged in multiple rows. Corresponding conductor segments are respectively provided on both opposite sides of the pads, and a row of conductor segments is arranged between adjacent rows of pads. The first direction is perpendicular to the direction of the row. Specifically, along the Y-axis direction, conductor segments 210 are respectively provided on both opposite sides of the pads 100. Both the pads 100 and the conductor segments 210 are arranged in multiple rows, and a row of conductor segments 210 is arranged between adjacent rows of pads 100.

[0050] It should be noted that when the pads are arranged in multiple rows, during testing, the pads in each row can be pinned sequentially, or the pads in all rows can be pinned simultaneously.

[0051] In this embodiment, in each test key structure, the pads are arranged in at least one row. For each row of pads, a conductor segment is provided on both sides of the pads along a second direction, and a conductor segment is provided between each adjacent pad. The second direction is parallel to the direction of the row. This allows for the detection of alignment between the pads and the test probes on both sides of the pads, further improving the accuracy of the detection results. Figure 9 As shown, in each test key structure, the pads 100 are arranged in at least one row. For each row of pads 100, along the row direction (the second direction, i.e., the direction of the X-axis), the opposite sides of the pads 100 ( Figure 9 Conductor segments 210 are respectively set on both the left and right sides of the pad 100. In this way, the alignment between the pad 100 and the test probe can be detected on both the left and right sides of the pad 100, so as to further improve the accuracy of the test results.

[0052] In this embodiment, in each test key structure, the pads are arranged in at least one row. For each row of pads, a conductor segment is provided on the same side of all pads along a second direction, parallel to the direction of the row. This allows for detection of alignment between the pads and the test probes on both sides of the pads, further improving the accuracy of the detection results. For example, as... Figure 10 As shown, in each test key structure 10, the pads 100 are arranged in at least one row. For each row of pads 100, a conductor segment 210 is provided on the same side of all pads 100 along the X-axis direction (second direction). For example, the conductor segment 210 is provided only on the left or right side of the pads 100.

[0053] In the embodiments of this application, it is possible to... Figure 9The structure shown is modified so that in each test key structure 10, the pads 100 are arranged in at least one row. For each row of pads 100, a conductor segment 210 is provided on each opposite side of the pad 100 along a second direction, and two conductor segments 210 are provided between adjacent pads 100. The second direction is parallel to the direction of the row. In this way, the alignment between the pads 100 and the test probes can be detected from both sides of the pads 100, thereby further improving the accuracy of the test results.

[0054] In this embodiment, along the extending direction of the conductor segment 210, the size of the conductor segment 210 is equal to the size of the corresponding pad 100. This ensures that the probe will contact the conductor segment 210 even when offset from the pad 100, thereby improving the accuracy of the detection results. Specifically, as... Figure 9 As shown, for pads 100 and conductor segments 210 arranged along a direction perpendicular to the row direction (Y-axis direction), the orthographic projection of pad 100 onto conductor segment 210 along the Y-axis direction coincides with conductor segment 210; correspondingly, for pads 100 and conductor segments 210 arranged along the row direction (X-axis direction), the orthographic projection of pad 100 onto conductor segment 210 along the X-axis direction coincides with conductor segment 210.

[0055] In the embodiments of this application, such as Figure 9 As shown, in each test key structure 10, the pads 100 are arranged in at least one row. In each row of pads 100, the pad 100 at the beginning or end of the row is the first pad 111, and the other pads 100 are the second pads 112. It should be noted that the position of the first pad 111 can be designed according to actual needs and is not limited to being set at the beginning or end of the row.

[0056] In the embodiments of this application, such as Figures 4 to 10 As shown, the spacing between pad 100 and the corresponding conductor segment 210 is equal. This improves the accuracy of the detection results.

[0057] In the embodiments of the first aspect of this application, such as Figure 10 As shown, the distance between the pad 100 and the corresponding conductor segment 210 is no greater than a first preset value. This allows the probe to contact the conductor segment 210 even when it is not aligned with the pad 100, preventing the probe's piercing area from falling between the pad 100 and the conductor segment 210 if the distance between them is too large, thus improving the accuracy of the detection results.

[0058] For example, the first preset value can be approximately half the size of the needle-drop area (which may be called the needle mark). For example, the first preset value can be 5–25 micrometers, specifically 10 micrometers, 15 micrometers, 20 micrometers, etc. It should be noted that the first preset value can be designed according to the actual testing requirements and is therefore not limited to the above-mentioned numerical range.

[0059] It should be noted that the needle insertion area is ideally roughly circular (with equal dimensions in both the X and Y axes). However, in actual needle insertion tests, the probe will slip, resulting in a shape that is approximately as shown below. Figure 4 and Figure 5 The ellipse shown. In this case, when the first preset value is designed based on the size of the pin drop area, it needs to be designed according to the size generated by the direction of probe sliding (e.g., the size of the major axis of the ellipse). For example, the first preset value can be about 1 / 2 of the size of the pin drop area (which may be called the pin mark), where "size" is: the size of the pin drop area along the direction from the pad to the corresponding conductor segment (the direction in which the probe slides).

[0060] In this embodiment, the wafer structure 1 is configured to use a probe card for monitoring and testing, and the distance between the pad 100 and the corresponding lead segment 210 is no greater than the size of the probe on the probe card. This allows the probe to contact the lead segment 210 even when it is not aligned with the pad 100, preventing the probe from failing to contact the pad 100 and lead segment 210 if the distance between the pad 100 and the lead segment 210 is too large. Therefore, limiting the range of this distance improves the accuracy of the test results.

[0061] It should be noted that, in the embodiments of this application, the arrangement of the wire segments included in the test wire and whether they need to be connected to each other can be designed according to actual needs, and are not limited to the situation shown in the above embodiments.

[0062] For example, in the embodiments of this application, such as Figure 11 As shown, each second pad 112 is surrounded by a conductor segment 210. The conductor segments 210 surrounding the same second pad 112 are connected end to end in sequence. At least one conductor segment 210 located on the periphery of each pad is spaced apart from the adjacent conductor segments 210. The conductor segments 210 corresponding to each second pad 112 are electrically connected together. In this way, the test wire 200 will not experience electromagnetic induction during testing. In addition, the conductor segment 210 corresponding to the second pad 112 is closer to the first pad 111, thereby reducing the distance between the conductor segment 210 corresponding to the second pad 112 and the first pad 111, thus reducing the routing difficulty. For example: Figure 11Taking the second pad 112 on the far left as an example, it is surrounded by four conductor segments 210a to 210d. The conductor segments 210a to 210d are connected one after the other, with conductor segment 210a at the beginning and conductor segment 210d at the end. There is a gap between conductor segment 210a and the adjacent conductor segment 210d. Thus, the pattern formed by the conductor segments 210a to 210d surrounding the second pad 112 is a non-closed ring.

[0063] For example, in Figure 11 In the structure shown, the conductor segment 210 corresponding to the first pad 111 can also be configured to have the same form as the conductor segment 210 corresponding to the second pad 112. The conductor segment 210 corresponding to the first pad 111 can be directly connected to the conductor segment 210 corresponding to the second pad 112, so that no additional traces are needed to connect the conductor segment 210 corresponding to the second pad 112 and the first pad 111.

[0064] In the embodiments of this application, see Figure 13 The wafer structure 1 has multiple chips 11, and scribe lines 12 are provided between adjacent chips 11. Test bond structures 10 are located in the scribe lines 12. When the wafer structure 1 is tested and then diced, the pads 100 and test leads 200 in these test bond structures 10 are removed along with the dicing of the scribe lines 12, and thus will not be formed on the chips 11.

[0065] This application provides a method for testing a wafer structure. The method includes: providing a probe card, and having probes on the probe card pierce a first pad and a second pad; obtaining an electrical signal between the current circuit formed by the first pad, the second pad, and the probe card; determining that the probe is aligned with the first pad and the second pad when the value of the electrical signal is less than a threshold; and determining that the probe is offset relative to the first pad and the second pad when the value of the electrical signal is greater than or equal to the threshold. The specific structure of this wafer structure can be found in the descriptions in the foregoing embodiments, and the principle of the testing method can be found in the foregoing descriptions of... Figure 4 and Figure 5 The relevant descriptions in the illustrated embodiments will not be repeated here.

[0066] In this application, references to "one embodiment" or "some embodiments" mean that a feature, structure, or characteristic described in connection with that embodiment is included in an embodiment or at least some embodiments of this application. Therefore, the appearance of the phrases "in one embodiment" or "in some embodiments" throughout this application does not necessarily refer to the same or the same embodiments. Furthermore, in one or more embodiments, features, structures, or characteristics can be combined in any suitable combination and / or sub-combination.

[0067] While specific embodiments of this application have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of this application. The embodiments of this application can be combined in any way without departing from the spirit and scope of this application. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this application. The scope of this application is defined by the appended claims.

Claims

1. A test key structure, characterized in that, include: Multiple pads arranged at intervals, the multiple pads including at least one first pad and multiple second pads; The test lead has a first pad and a corresponding test lead that are electrically connected, and a second pad and the test lead are insulated from each other. The test lead includes multiple lead segments disposed on the same layer as the pad. The first pad is interconnected with at least one lead segment on its periphery. The second pad is spaced apart from all lead segments on its periphery. Furthermore, at least one lead segment on the periphery of each pad is spaced apart from adjacent lead segments.

2. The test key structure according to claim 1, characterized in that, Any two adjacent conductor segments are spaced apart from each other, and the test conductor also includes at least one connecting segment disposed on a different layer from the conductor segment. The conductor segment surrounding the second pad is electrically connected to the first pad through the connecting segment.

3. The test key structure according to claim 2, characterized in that, The conductor segment is provided on the same side of the first pad and the second pad.

4. The test key structure according to claim 3, characterized in that, In each of the test key structures, the pads are arranged in a row, and for each row of pads, along the first direction, The conductor segment is provided on at least one side of the pad. Wherein, the first direction is perpendicular to the direction of the row.

5. The test key structure according to claim 3, characterized in that, In each of the test key structures, the pads are arranged in multiple rows. For each row of pads, along a first direction, The conductor segments are arranged in multiple rows, with each row containing a conductor segment corresponding one-to-one with the row containing a pad, and the rows are arranged alternately; or The conductor segments are arranged in multiple rows, and corresponding conductor segments are respectively provided on both opposite sides of the pads, and a row of conductor segments is arranged between adjacent rows of pads; The conductor segments are arranged in multiple rows, and corresponding conductor segments are respectively provided on both opposite sides of the pads, and two rows of conductor segments are arranged between adjacent rows of pads; Wherein, the first direction is perpendicular to the direction of the row.

6. The test key structure according to any one of claims 3 to 5, characterized in that, In each of the test key structures, the pads are arranged in at least one row, and for each row of pads, along the second direction, The conductor segment is provided on the same side of all the pads; or The conductive segments are respectively provided on both sides of the pads, and one conductive segment is provided between each adjacent pad; or The conductive line segment is provided on both sides of the pad, and two conductive line segments are provided between adjacent pads. The second direction is parallel to the direction of the row.

7. The test key structure according to claim 3, characterized in that, Along the extension direction of the conductor segment, the size of the conductor segment is equal to the size of the corresponding pad.

8. The test key structure according to any one of claims 1 to 5, characterized in that, The spacing between the pads and the corresponding conductor segments is equal, and the spacing is 5 to 25 micrometers.

9. A wafer structure, characterized in that, The wafer structure is provided with dicing channels, and the dicing channels are provided with test bond structures as described in any one of claims 1 to 8.

10. A test method for the test bond structure according to any one of claims 1 to 8, characterized in that, include: A probe card is provided, which enables the probes of the probe card to make pins to the first pad and the second pad; Obtain the electrical signal between the current loop formed by the first pad, the second pad, and the probe card; When the value of the electrical signal is less than the threshold, it is determined that the probe is aligned with the first pad and the second pad; when the value of the electrical signal is greater than or equal to the threshold, it is determined that the probe is offset relative to the first pad and the second pad.

Images