Semiconductor chip and method of manufacturing the same, semiconductor package structure and method of manufacturing the same

Abstract

The application discloses a semiconductor chip and a preparation method thereof, a semiconductor packaging structure and a preparation method thereof. The semiconductor chip comprises a chip body, a back surface, a metallization structure layer, and a palladium capping layer. The palladium capping layer is arranged on the side surface of the metallization structure layer away from the chip body. The palladium capping layer is used for bonding with an indium-based thermal interface material to form a palladium-indium intermetallic compound layer. The palladium capping layer in the application reacts with indium to form a palladium-indium intermetallic compound layer. Compared with a brittle and easy-to-crack gold-indium intermetallic compound, the palladium-indium intermetallic compound has slower growth kinetics and better mechanical integrity, can realize lower interface thermal resistance, higher bonding strength, and significantly improve the resistance to thermal cycling and long-term thermal aging. In addition, the process of generating the palladium-indium intermetallic compound by the palladium-indium reaction is slow, so that it can exhibit higher resistance under repeated thermal shock and high-temperature assembly processes.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor chip and its fabrication method, and a semiconductor packaging structure and its fabrication method. Background Technology

[0002] To efficiently conduct the heat generated by the chip during operation to a heat dissipation device (such as a heat spreader), a thermal interface material (TIM) is typically filled between the back of the chip and the integrated heat spreader (IHS). Among the many TIM materials, indium (In) and indium-based alloys are currently the preferred thermal interface materials due to their extremely high thermal conductivity, excellent ductility, and relatively low processing temperature.

[0003] In existing technologies, to promote and ensure good wetting, bonding, and long-term reliability between indium-based metallized indium immersion membranes (TIMs) and the back side of semiconductor chips, the industry commonly fabricates specific metallization structures on the back side of the chip, known as backside metallization (BSM). Traditional BSM solutions often employ a nickel / gold (Ni / Au) based stacked structure. In this structure, the nickel layer primarily acts as a diffusion barrier layer, while the top gold layer provides an inert, easily wettable surface.

[0004] However, the aforementioned BSM (Ball Grid Array) solution has gradually revealed significant drawbacks in practical applications. During bonding and subsequent thermal exposure, gold and indium readily react to rapidly form a continuous intermetallic compound (IMC) layer, with the AuIn2 phase being the primary and highly detrimental product. The AuIn2 phase is characterized by high brittleness and low fracture toughness. Under conditions of chip power cycling, repeated reflow soldering (such as in ball grid array packaging), or long-term high-temperature service, this continuous and brittle IMC layer becomes a mechanical weak point at the interface, easily leading to crack initiation and propagation, ultimately resulting in interface delamination, a sharp increase in thermal resistance, and even the failure of heat dissipation. Summary of the Invention

[0005] This application aims to address one of the technical problems in related technologies to a certain extent. To this end, this application provides a semiconductor chip and its fabrication method, as well as a semiconductor packaging structure and its fabrication method.

[0006] To achieve the above objectives, this application adopts the following technical solution: a semiconductor chip, comprising...

[0007] The chip body has a back side;

[0008] A metallized structural layer is disposed on the back side;

[0009] The palladium capping layer is disposed on the surface of the metallized structure layer opposite to the chip body;

[0010] The palladium capping layer is located on the outermost layer of the semiconductor chip and is used to bond with an indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

[0011] The application of this application offers the following advantages: Using a palladium capping layer instead of a gold layer as the contact layer for bonding with indium-based thermal interface materials allows the palladium capping layer to react with indium during the bonding process to form a palladium-indium intermetallic compound layer, such as Pd₂In, PdIn, Pd₃In₇, or other Pd-In intermetallic phases. Compared to the brittle and easily cracked gold-indium intermetallic compounds, the palladium-indium intermetallic compound exhibits slower growth kinetics and superior mechanical integrity. Therefore, a semiconductor chip with a palladium capping layer as provided in this application can achieve lower interfacial thermal resistance, higher bonding strength, and significantly improved resistance to thermal cycling and long-term thermal aging after bonding with a heat dissipation device through an indium-based thermal interface material. Furthermore, unlike the gold-indium reaction, which readily reacts and rapidly forms continuous intermetallic compounds, the palladium-indium reaction produces palladium-indium intermetallic compounds very slowly. This results in greater resilience to repeated thermal shocks and high-temperature assembly processes. Consequently, the semiconductor packaging structure of the semiconductor chip provided in this application is suitable not only for indium-based thermal interface materials undergoing only one reflow soldering (such as LGA packaging) but also for indium-based thermal interface materials requiring multiple reflow solderings and higher peak temperatures (such as BGA packaging), improving process adaptability. Simultaneously, using a palladium capping layer can reduce surface oxidation of the semiconductor chip during storage and transportation, and significantly reduce the difficulty of surface reduction treatment before packaging.

[0012] Optionally, the thickness of the palladium capping layer is in the range of 10 nm to 500 nm.

[0013] Optionally, the thickness of the palladium capping layer is in the range of 30 nm to 300 nm.

[0014] Optionally, the thickness of the palladium capping layer is in the range of 50 nm to 200 nm.

[0015] Optionally, the metallization structure layer includes an adhesion layer and a diffusion barrier layer stacked from the chip body toward the palladium capping layer. The metal material of the adhesion layer is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel. The metal material of the diffusion barrier layer is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel.

[0016] Optionally, the adhesion layer includes a titanium layer disposed on the back side and a nickel layer disposed on the titanium layer, and the diffusion barrier layer includes a vanadium-containing nickel layer.

[0017] Furthermore, this application also provides a semiconductor packaging structure, including a packaging substrate and a heat sink, wherein the heat sink is disposed on the packaging substrate and the two cooperate to form a mounting chamber. The semiconductor packaging structure further includes a semiconductor chip as described in any one of the above technical solutions, wherein the semiconductor chip is disposed in the mounting chamber. The semiconductor chip is electrically connected to the packaging substrate through its active surface, and the palladium capping layer in the semiconductor chip is bonded to the heat sink through an indium-based thermal interface material, and the palladium capping layer and the indium-based thermal interface material are bonded to form a palladium-indium intermetallic compound layer.

[0018] The semiconductor packaging structure provided in this application has a similar reasoning process to the aforementioned semiconductor chip's beneficial effects, and will not be repeated here.

[0019] Optionally, the palladium-indium intermetallic compound layer comprises one or more of the following intermetallic phases: Pd2In, PdIn, and Pd3In7.

[0020] Optionally, the heat sink includes a connection portion for connecting to a semiconductor chip, the connection portion including:

[0021] Connecting substrate;

[0022] A nickel plating layer is disposed on the side surface of the bonding substrate facing the semiconductor chip;

[0023] A palladium layer is disposed on the side of the nickel layer facing the semiconductor chip;

[0024] The palladium layer is bonded to the indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

[0025] Optionally, the palladium layer is deposited on the nickel plating layer by an electroplating process.

[0026] Furthermore, this application also provides a method for fabricating a semiconductor chip, the method comprising the following steps:

[0027] Provide a chip body with a back side;

[0028] A metallization structure layer is provided on the back side of the chip body;

[0029] A palladium capping layer is disposed on the side of the metallized structure layer facing away from the chip body. The palladium capping layer is used to bond with an indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

[0030] The method for preparing the semiconductor chip provided in this application is similar to the reasoning process of the aforementioned beneficial effects of the semiconductor chip, and will not be repeated here.

[0031] Optionally, the provision of a metallization structure layer on the back side of the chip body includes:

[0032] A metallized structure layer is formed on the back side of the chip body in a single process using physical vapor deposition or evaporation in a high vacuum environment.

[0033] Optionally, the provision of a palladium capping layer on the surface of the metallized structure layer facing away from the chip body includes:

[0034] In the high vacuum environment, a palladium capping layer is formed in one step on the side of the metallized structure layer away from the chip body through physical vapor deposition or evaporation processes.

[0035] Optionally, the thickness of the palladium capping layer is in the range of 10 nm to 500 nm.

[0036] Optionally, the thickness of the palladium capping layer is in the range of 30 nm to 300 nm.

[0037] Optionally, the thickness of the palladium capping layer is in the range of 50 nm to 200 nm.

[0038] Optionally, this application also provides a method for fabricating a semiconductor packaging structure, the method being used to fabricate a semiconductor chip as described in any of the above technical solutions, the method comprising:

[0039] Provide a semiconductor chip as described in any of the above technical solutions;

[0040] The palladium capping layer in the semiconductor chip is subjected to surface activation treatment;

[0041] Provide a heatsink cover;

[0042] An indium-based thermal interface material is disposed between the palladium capping layer and the heat dissipation cap;

[0043] The palladium capping layer and the heat sink are bonded and fixed together using the indium-based thermal interface material via a bonding process. The fabrication method of the semiconductor packaging structure provided in this application is similar to the reasoning process for the beneficial effects of the aforementioned semiconductor chip, and will not be repeated here.

[0044] Optionally, the surface activation treatment includes at least one of the following: mild acid treatment process, formic acid-based reducing atmosphere treatment process, hydrogen-containing atmosphere treatment process, plasma activation treatment process, or residue-free chemical activation treatment process.

[0045] Optionally, the bonding process is a reflow bonding process or a thermocompression bonding process, and the temperature of the bonding process is between 180°C and 260°C.

[0046] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description

[0047] The following description, in conjunction with the accompanying drawings, further illustrates this application:

[0048] Figure 1 A schematic diagram of a semiconductor chip provided for the first aspect of the present invention;

[0049] Figure 2 This is a schematic diagram of a semiconductor packaging structure before fabrication, as provided in the second aspect of the present invention.

[0050] Figure 3 This is a schematic diagram of the semiconductor packaging structure after fabrication.

[0051] Figure 4 A flowchart illustrating the fabrication process of a semiconductor chip, which is a third aspect of the present invention;

[0052] Figure 5 A flowchart illustrating the fabrication process of a semiconductor packaging structure provided in the fourth aspect of this invention;

[0053] The components are as follows: 1. Chip body; 2. Metallization structure layer; 20. Adhesion layer; 200. Titanium layer; 201. Nickel layer; 21. Diffusion barrier layer; 3. Palladium sealing layer; 5. Packaging substrate; 6. Heat sink; 60. Connecting substrate; 61. Nickel plating layer; 62. Palladium layer; 63. Annular protrusion; 7. Indium-based thermal interface material; 8. Palladium-indium intermetallic compound layer; 9. Thermally conductive adhesive. Detailed Implementation

[0054] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.

[0055] The terms "an embodiment," "example," or "example" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this application. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0056] In the description of this application, it should be understood that the terms "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In the description of this application, "a plurality of" means two or more, unless otherwise precisely specified.

[0057] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected," "linked," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a connection through an intermediary, or a connection within two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0058] The first aspect of this invention provides a semiconductor chip, and the second aspect provides a semiconductor packaging structure, wherein the semiconductor chip can be applied to the semiconductor packaging structure. Figure 1 The semiconductor chip comprises a chip body 1, a metallization layer 2, and a palladium capping layer 3. The chip body 1 has a back side, which is easily understood to be combined with... Figure 2 The semiconductor package structure shown has a chip body 1 with an active surface for electrical connection to a package substrate 5. The back side refers to the surface of the chip body 1 that is opposite to the active surface. A metallization layer 2 is disposed on the back side, and a palladium capping layer 3 is disposed on the surface of the metallization layer 2 that is opposite to the chip body 1. In this application, the palladium capping layer 3 is located at the outermost layer of the semiconductor chip and is used to bond with an indium-based thermal interface material 7 to form a palladium-indium intermetallic compound layer 8.

[0059] In this application, a palladium capping layer 3 is used instead of a gold layer as the contact layer for bonding with the indium-based thermal interface material 7. During the bonding process, [the material is bonded / combined / etc.]. Figure 2 and Figure 3As shown, the palladium capping layer 3 reacts with indium to form a palladium-indium intermetallic compound layer 8, such as Pd2In, PdIn, Pd3In7, or other Pd-In intermetallic phases. Compared to the brittle and easily cracked gold-indium intermetallic compounds, the palladium-indium intermetallic compound exhibits slower growth kinetics and superior mechanical integrity. Therefore, a semiconductor chip with a palladium capping layer 3, as provided in this application, can achieve lower interfacial thermal resistance, higher bonding strength, and significantly improved resistance to thermal cycling and long-term thermal aging after bonding with a heat dissipation device via an indium-based thermal interface material 7. Furthermore, unlike the gold-indium reaction, which readily reacts and rapidly forms continuous intermetallic compounds, the palladium-indium reaction generates palladium-indium intermetallic compounds very slowly. This allows it to exhibit higher tolerance to repeated thermal shocks and high-temperature assembly processes. Consequently, the semiconductor packaging structure of the semiconductor chip provided in this application is suitable not only for packaging forms where the indium-based thermal interface material 7 undergoes only one reflow soldering (such as LGA packaging), but also for packaging forms where the indium-based thermal interface material 7 requires multiple reflow solderings and higher peak temperatures (such as BGA packaging), thus improving process adaptability.

[0060] Furthermore, the use of palladium capping layer 3 can also reduce surface oxidation of the semiconductor chip during storage and transportation, significantly reducing the difficulty of performance restoration processing before packaging. Specifically, in the actual semiconductor packaging process, the surface oxidation problem of semiconductor chips is not limited to the storage or transportation stage after metallization. Before the semiconductor chip is bonded and attached to the indium-based thermal interface material 7, surface oxidation or contamination may occur repeatedly in various upstream packaging processes, such as back cleaning of semiconductor chips, overall dicing, temporary storage, pre-baking, chip mounting, underfill application and curing, substrate-level SMT processes (including reflow soldering exposure related to SMT assembly), substrate attachment, and other assembly-related steps.

[0061] Therefore, since the bonding of the semiconductor chip to the indium-based thermal interface material 7 typically occurs in the later stages of the packaging assembly process, any oxide layer formed in these upstream packaging steps must be removed or reduced in time before the semiconductor chip is bonded to the indium-based thermal interface material 7 to ensure reliable wetting and bonding during the bonding process. Thus, from a manufacturing and reliability perspective, the palladium capping layer 3 on the back side of the semiconductor chip not only suppresses oxidation formation but also allows for the effective removal or reduction of oxide layers formed in upstream processes through mild activation conditions compatible with the packaging process before the semiconductor chip is bonded to the indium-based thermal interface material 7.

[0062] Prior art has shown that silver (Ag) and tin (Sn) can be used as optional top layers and bonded to indium preforms or other indium-based thermal interface materials. However, compared to palladium, silver and tin are less inert and more prone to surface degradation during storage and handling. In particular, silver is susceptible to oxidation and sulfidation, and both silver and tin can undergo rapid interfacial reactions with indium, leading to uncontrolled growth of intermetallic compounds and surface instability. In contrast, palladium is more inert than silver under typical packaging conditions. Although palladium may form a thin surface oxide layer or adsorbed oxygen layer, this layer is generally thinner and more stable than silver oxide and can be easily removed or reduced under common assembly conditions, such as mild acid cleaning, formic acid-based reducing atmospheres, or other residue-free activation processes.

[0063] Nickel, on the other hand, readily forms a relatively stable NiO / Ni(OH)x oxide layer. Without aggressive cleaning or activation methods, this would severely weaken the wetting and bonding properties of the indium-based thermal interface material 7. Therefore, palladium offers a balance: it is more inert than silver but far more manageable than nickel, while avoiding the problem of excessive growth of intermetallic compounds in the gold-indium system.

[0064] In this embodiment, the thickness of the palladium capping layer 3 is 60 nm. Several factors need to be considered when setting the thickness of the palladium capping layer 3. Firstly, the thickness of the palladium capping layer 3 cannot be too thin to avoid discontinuous sections during actual formation, which would prevent complete coverage of the metallization structure layer 2. Secondly, the palladium capping layer 3 also needs to reach a certain thickness to meet the required oxidation resistance. Additionally, the thickness of the palladium capping layer 3 cannot be too thick to avoid increasing thermal resistance. Through testing, in optional embodiments, the thickness of the palladium capping layer 3 is between 10 nm and 500 nm. More preferably, the thickness of the palladium capping layer 3 is between 30 nm and 300 nm. Even more preferably, the thickness of the palladium capping layer 3 is between 50 nm and 200 nm.

[0065] In this embodiment, the metallization structure layer 2 includes an adhesion layer 20 and a diffusion barrier layer 21 stacked from the chip body 1 toward the palladium capping layer 3. The metal material of the adhesion layer 20 is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel; the metal material of the diffusion barrier layer 21 is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel. Specifically, in this embodiment, the adhesion layer 20 includes a titanium layer 200 disposed on the back side and a nickel layer 201 disposed on the titanium layer 200, and the diffusion barrier layer 21 includes a vanadium-containing nickel layer. In this embodiment, the thickness of the titanium layer 200 is 50 nm, the thickness of the nickel layer 201 is 300 nm, and the thickness of the vanadium-containing nickel layer is 120 nm. Optionally, the thickness of the titanium layer 200 is between 20 nm and 200 nm, the thickness of the nickel layer 201 is between 50 nm and 600 nm, and the thickness of the vanadium-containing nickel layer is between 100 nm and 400 nm. The material selection and thickness design of the metallized structural layer 2 can be chosen according to process requirements and performance needs such as preparation process, surface roughness requirements, storage and transportation requirements, thermal reliability requirements, and mechanical reliability requirements.

[0066] like Figure 2 and Figure 3 As shown, the semiconductor packaging structure provided by the second aspect of the present invention includes a packaging substrate 5, a heat sink 6, and a semiconductor chip provided by the first aspect of the present invention. The heat sink 6 is disposed on the packaging substrate 5, and the heat sink 6 and the packaging substrate 5 cooperate to form a mounting chamber, in which the semiconductor chip is disposed. The semiconductor chip is electrically connected to the packaging substrate 5 through its active surface. The palladium capping layer 3 in the semiconductor chip is bonded to the heat sink 6 through an indium-based thermal interface material 7, and the palladium capping layer 3 and the indium-based thermal interface material 7 are bonded to form a palladium-indium intermetallic compound layer 8.

[0067] In this embodiment, the heat sink 6 includes a connecting portion and an annular protrusion 63 formed on the edge of the connecting portion. The annular protrusion 63 cooperates with the connecting portion and the packaging substrate 5 to form the aforementioned mounting chamber. The end face of the annular protrusion 63 is bonded and fixed to the packaging substrate 5 using thermally conductive adhesive 9. During packaging, the semiconductor chip can first be electrically connected to the packaging substrate 5 through its active surface, then the heat sink 6 is placed on the semiconductor chip, the annular protrusion 63 is bonded and fixed to the packaging substrate 5 using thermally conductive adhesive 9, and the connecting portion is bonded to the semiconductor chip using an indium-based thermal interface material 7. Alternatively, the connecting portion can be first bonded to the semiconductor chip using the indium-based thermal interface material 7 to form an integral structure, and then the integral structure is connected to the packaging substrate 5.

[0068] The connecting portion includes a connecting substrate 60, a nickel plating layer 61, and a palladium layer 62. The nickel plating layer 61 is disposed on the surface of the connecting substrate 60 facing the semiconductor chip, and the palladium layer 62 is disposed on the surface of the nickel plating layer 61 facing the semiconductor chip. The palladium layer 62 is bonded to the indium-based thermal interface material 7 to form a palladium-indium intermetallic compound layer 8. Specifically, in this embodiment, the connecting substrate 60 is made of copper. A nickel plating layer 61 is formed by plating nickel on the outer surface of the connecting substrate 60, and then the palladium layer 62 is formed by electroplating on the outer surface of the nickel plating layer 61.

[0069] like Figure 3 As shown, after the palladium capping layer 3 and the heat sink 6 in the semiconductor chip are bonded together through the indium-based thermal interface material 7, the palladium capping layer 3 and the indium-based thermal interface material 7 form a palladium-indium intermetallic compound layer 8. Simultaneously, the palladium layer 62 in the heat sink 6 also forms a palladium-indium intermetallic compound layer 8 with the indium-based thermal interface material 7. The aforementioned palladium-indium intermetallic compound layer 8 contains one or more of the following intermetallic phases: Pd₂In, PdIn, and Pd₃In₇.

[0070] It should be noted that research has found a certain relationship between the thickness design of the palladium capping layer 3 or the palladium layer 62 and the process conditions during fabrication, and the type and proportion of intermetallic phases included in the palladium-indium intermetallic compound layer 8. The type and proportion of intermetallic phases included in the palladium-indium intermetallic compound layer 8, in turn, affect its performance. For example, when the proportion of Pd3In7 is larger, the palladium-indium intermetallic compound layer 8 exhibits better tolerance under high-temperature assembly conditions. Experimental analysis shows that, using the same fabrication process, designing the thickness of the palladium capping layer 3 to be between 50 nm and 200 nm significantly increases the proportion of Pd3In7 in the resulting palladium-indium intermetallic compound layer 8.

[0071] The indium-based component in the suitable indium-based thermal interface material 7 includes, but is not limited to, indium (In), indium-silver (In-Ag), indium-tin (In-Sn), indium-lead (In-Pb), or combinations thereof. The indium-based thermal interface material 7 can be provided in the form of a preform, foil, sheet, or deposited layer. The thickness of the indium-based thermal interface material 7 can be selected based on package power density, the gap between the chip and the IHS, and mechanical compliance requirements. For example, in many high-performance CPU and GPU packaging applications, the indium-based thermal interface material 7 typically has a thickness ranging from approximately 150 μm to 400 µm. In a broader range of alternative embodiments, the thickness of the indium-based thermal interface material 7 can be in the range of approximately 100 μm to 800 µm. Thinner indium-based thermal interface materials 7 are suitable for scenarios requiring the lowest interface thermal resistance and strict flatness control; while thicker indium-based thermal interface materials 7 are beneficial for absorbing surface irregularities, chip warpage, thermal expansion coefficient mismatch, and assembly stress. By reasonably selecting the thickness of the indium-based thermal interface material 7 within the above range, a balance can be achieved between low thermal resistance, mechanical compliance, and long-term reliability.

[0072] A third aspect of this invention provides a method for fabricating a semiconductor chip, such as... Figure 4 As shown, the preparation method includes the following steps:

[0073] Provide a chip body 1 with a back side;

[0074] A metallization structure layer 2 is provided on the back side of the chip body 1; specifically, the metallization structure layer 2 can be formed on the back side of the chip body 1 in a one-time process by physical vapor deposition or evaporation in a high vacuum environment.

[0075] A palladium capping layer 3 is disposed on the surface of the metallized structure layer 2 facing away from the chip body 1. The palladium capping layer 3 is used to bond with the indium-based thermal interface material 7 to form a palladium-indium intermetallic compound layer 8. Specifically, the palladium capping layer 3 can be formed in a single step on the surface of the metallized structure layer 2 facing away from the chip body 1 in a high vacuum environment using physical vapor deposition or evaporation processes.

[0076] Similarly, in this application, the thickness of the palladium capping layer 3 on the semiconductor chip prepared by this method is between 10 nm and 500 nm. Preferably, the thickness of the palladium capping layer 3 is between 30 nm and 300 nm. More preferably, the thickness of the palladium capping layer 3 is between 50 nm and 200 nm.

[0077] In other alternative embodiments, the palladium capping layer 3 can also be formed on the metallized structural layer 2 by means of electroplating, electroless plating, sputtering, or other methods.

[0078] In a preferred embodiment, the metallized structural layer 2 and the palladium capping layer 3 are formed continuously in a single process using physical vapor deposition (PVD) or evaporation in a high-vacuum environment. Specifically, under the same vacuum environment, the metallized structural layer 2 is first formed using PVD or evaporation, and then the palladium capping layer 3 is continuously formed on the metallized structural layer 2 using PVD or evaporation. The entire process is conducted without exposure to air, resulting in high-quality, pollution-free surfaces of both the metallized structural layer 2 and the palladium capping layer 3. This significantly improves the interface integrity between the metallized structural layer 2 and the palladium capping layer 3, enhancing the bonding stability between the palladium capping layer 3 and the metallized structural layer 2, and facilitating subsequent integration of the palladium capping layer 3 with the indium-based thermal interface material 7. This process differs fundamentally from the wet electroplating process typically used in integrated heat spreaders (IHS), which is usually performed at or near atmospheric pressure. Therefore, the palladium capping layer 3 formed using the continuous high-vacuum PVD or evaporation process described above exhibits higher surface quality and stability, particularly beneficial for its subsequent integration with the indium-based thermal interface material 7.

[0079] A fourth aspect of the present invention provides a method for fabricating a semiconductor packaging structure, such as... Figure 5 As shown, the preparation method includes:

[0080] Provide the aforementioned semiconductor chips;

[0081] The palladium capping layer 3 in the semiconductor chip is subjected to surface activation treatment; specifically, the surface activation treatment includes at least one of the following: mild acid treatment process, formic acid-based reducing atmosphere treatment process, hydrogen-containing atmosphere treatment process, plasma activation treatment process, or residue-free chemical activation treatment process.

[0082] Provides heat dissipation cover 6;

[0083] An indium-based thermal interface material 7 is disposed between the palladium capping layer 3 and the heat dissipation cover 6;

[0084] The palladium capping layer 3 and the heat sink 6 are bonded and fixed together using an indium-based thermal interface material 7 via a bonding process. The bonding process can be either reflow soldering or thermoforming, and the bonding temperature is between 180°C and 260°C. It is easy to understand that the bonding temperature depends on the package design and assembly conditions.

[0085] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.

Claims

1. A semiconductor chip, characterized in that, include The chip body has a back side; A metallized structural layer is disposed on the back side; The palladium capping layer is disposed on the surface of the metallized structure layer opposite to the chip body; The palladium capping layer is located on the outermost layer of the semiconductor chip and is used to bond with an indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

2. The semiconductor chip as described in claim 1, characterized in that, The thickness of the palladium capping layer is in the range of 10 nm to 500 nm.

3. The semiconductor chip as described in claim 2, characterized in that, The thickness of the palladium capping layer is in the range of 30 nm to 300 nm.

4. The semiconductor chip as described in claim 3, characterized in that, The thickness of the palladium capping layer is in the range of 50 nm to 200 nm.

5. The semiconductor chip according to any one of claims 1 to 4, characterized in that, The metallization structure layer includes an adhesion layer and a diffusion barrier layer stacked from the chip body toward the palladium capping layer. The metal material of the adhesion layer is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel. The metal material of the diffusion barrier layer is selected from one or more of the following materials: copper, nickel, titanium, chromium, tungsten, and vanadium-containing nickel.

6. The semiconductor chip as described in claim 5, characterized in that, The adhesion layer includes a titanium layer disposed on the back side and a nickel layer disposed on the titanium layer, and the diffusion barrier layer includes a vanadium-containing nickel layer.

7. A semiconductor packaging structure, comprising a packaging substrate and a heat sink, wherein the heat sink is disposed on the packaging substrate and the two cooperate to form a mounting cavity, characterized in that, The semiconductor packaging structure further includes a semiconductor chip as described in any one of claims 1 to 6, the semiconductor chip being disposed within the mounting cavity; The semiconductor chip is electrically connected to the packaging substrate through its active surface. The palladium capping layer in the semiconductor chip is bonded to the heat sink through an indium-based thermal interface material, and the palladium capping layer and the indium-based thermal interface material are bonded to form a palladium-indium intermetallic compound layer.

8. The semiconductor packaging structure as described in claim 7, characterized in that, The palladium-indium intermetallic compound layer comprises one or more of the following intermetallic phases: Pd2In, PdIn, and Pd3In7.

9. The semiconductor packaging structure as described in claim 7, characterized in that, The heat sink includes a connection portion for connecting to a semiconductor chip, the connection portion including: Connecting substrate; A nickel plating layer is disposed on the side surface of the bonding substrate facing the semiconductor chip; A palladium layer is disposed on the side of the nickel layer facing the semiconductor chip; The palladium layer is bonded to the indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

10. The semiconductor packaging structure as described in claim 9, characterized in that, The palladium layer is deposited on the nickel plating layer by an electroplating process.

11. A method for fabricating a semiconductor chip, characterized in that, The preparation method is used to prepare a semiconductor chip as described in any one of claims 1 to 6, and the preparation method includes the following steps: Provide a chip body with a back side; A metallization structure layer is provided on the back side of the chip body; A palladium capping layer is disposed on the side of the metallized structure layer facing away from the chip body. The palladium capping layer is used to bond with an indium-based thermal interface material to form a palladium-indium intermetallic compound layer.

12. The method for fabricating a semiconductor chip as described in claim 11, characterized in that, The provision of a metallization structure layer on the back side of the chip body includes: A metallized structure layer is formed on the back side of the chip body in a single process using physical vapor deposition or evaporation in a high vacuum environment.

13. The method for fabricating a semiconductor chip as described in claim 12, characterized in that, The provision of a palladium capping layer on the side of the metallized structure layer facing away from the chip body includes: In the high vacuum environment, a palladium capping layer is formed in one step on the side of the metallized structure layer away from the chip body through physical vapor deposition or evaporation processes.

14. The method for fabricating a semiconductor chip as described in claim 12, characterized in that, The thickness of the palladium capping layer is in the range of 10 nm to 500 nm.

15. The method for fabricating a semiconductor chip as described in claim 14, characterized in that, The thickness of the palladium capping layer is in the range of 30 nm to 300 nm.

16. The method for fabricating a semiconductor chip as described in claim 15, characterized in that, The thickness of the palladium capping layer is in the range of 50 nm to 200 nm.

17. A method for fabricating a semiconductor packaging structure, characterized in that, The preparation method includes: Provide a semiconductor chip as described in any one of claims 1 to 6; The palladium capping layer in the semiconductor chip is subjected to surface activation treatment; Provide a heatsink cover; An indium-based thermal interface material is disposed between the palladium capping layer and the heat dissipation cap; The palladium capping layer and the heat sink are bonded and fixed together using the indium-based thermal interface material through a bonding process.

18. The method for fabricating a semiconductor packaging structure as described in claim 17, characterized in that, The surface activation treatment includes at least one of the following: mild acid treatment process, formic acid-based reducing atmosphere treatment process, hydrogen-containing atmosphere treatment process, plasma activation treatment process, or residue-free chemical activation treatment process.

19. The method for fabricating a semiconductor packaging structure as described in claim 17, characterized in that, The bonding process is a reflow bonding process or a thermocompression bonding process, and the temperature of the bonding process is between 180°C and 260°C.

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