Solder forming method and wafer

Abstract

The present application relates to a solder forming method, comprising the following steps: depositing a seed layer on a substrate; using an electroplating process to make a solder upper structure on the seed layer, the solder upper structure being located directly above a solder arrangement area of the substrate; making a protective shell on the seed layer, the protective shell at least covering the side of the solder upper structure; removing the seed layer material outside the projection range of the protective shell; and removing the protective shell. The present application also relates to a wafer with solder made based on the solder forming method. By introducing the protective shell as a mask in the seed layer material removal operation, the present application accurately determines the removal area of the seed layer, so that the seed layer directly below the solder upper structure is completely retained, and the solder upper structure is well protected, avoiding the phenomenon of side removal of the seed layer and the solder upper structure (such as a buffer layer), fundamentally eliminating the device weak point, enabling the solder to withstand high-pressure cleaning and other process stresses, and eliminating the risk of falling off; for wafer-level packaging, based on the above method, the solder is formed, which can greatly improve the reliability of the packaging and maintain the high vacuum state inside the device for a long time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a solder forming method and a wafer for fabricating solder based on the solder forming method. Background Technology

[0002] In wafer-level packaging or micro-packaging, metal solder rings are typically used for hermetically sealed packaging to maintain high vacuum levels inside devices such as detectors. AuSn solder is widely used due to its excellent properties.

[0003] The typical manufacturing process steps for existing AuSn solder include:

[0004] (1) A Cu seed layer is deposited on a substrate (such as a silicon wafer). PVD coating is generally used, and the thickness of the seed layer is generally 500 Å to 4000 Å.

[0005] (2) Electroplating pattern photolithography, including spraying, exposure and development processes, to define solder patterns;

[0006] (3) Electroplating Cu layer (as buffer layer 12), Ni layer (as barrier layer 13), Au layer 14 and Sn layer 15 in sequence;

[0007] (4) Photoresist removal is generally achieved through a cleaning process;

[0008] (5) Remove the seed layer Cu material from the exposed area to obtain the formed seed layer 11, which is generally done by wet etching process;

[0009] (6) AuSn solder is formed by high-temperature bonding process, generally at a temperature >290℃, so that Au / Sn solder eutectic is formed to form stable AuSn solder.

[0010] In the above process, during wet etching of the seed layer Cu material, due to the isotropic nature of the wet process, it can lead to side erosion of the seed layer Cu and buffer layer Cu materials (e.g. Figure 1 As shown, the buffer layer 12 and the forming seed layer 11 are significantly narrower than the Ni layer 13 / Au layer 14 / Sn layer 15, which reduces the adhesion between the forming seed layer 11 and the substrate. The solder ring is easy to fall off under high pressure cleaning conditions. At the same time, the side hole position is a weak position of the device, and gas can easily diffuse from the weak position into the device, causing the device vacuum to fail.

[0011] In addition, the poor bonding between the seed layer material (such as Ti / Cu) and the silicon substrate may cause the interface to become a channel for gas leakage or structural failure under thermal or mechanical stress, further affecting the long-term reliability of the package. Summary of the Invention

[0012] This invention relates to a solder forming method and a wafer, which can at least solve some of the defects of the prior art.

[0013] This invention relates to a solder forming method, the method comprising the following steps:

[0014] Deposit a seed layer on the substrate;

[0015] An upper solder layer structure is fabricated on the seed layer using an electroplating process, and the upper solder layer structure is located directly above the solder arrangement area of ​​the substrate;

[0016] A protective shell is formed on the seed layer, such that the protective shell at least covers the sidewalls of the upper solder layer structure;

[0017] Remove seed layer material outside the projection range of the protective shell;

[0018] Remove the protective shell.

[0019] As one implementation method, the protective shell is manufactured using photolithography.

[0020] As one embodiment, the protective shell is a cover-type shell that covers the side walls and top surface of the upper structure of the solder.

[0021] As one implementation method, a wet etching process is used to remove the seed layer material.

[0022] As one embodiment, the solder upper layer structure includes a buffer layer, a barrier layer and a solder layer stacked sequentially from bottom to top.

[0023] As one implementation method, the buffer layer and the seed layer are made of the same material.

[0024] As one embodiment, the solder layer includes an Au layer formed on the barrier layer and a Sn layer formed on the Au layer;

[0025] After removing the protective shell, the method further includes: fusing the Au layer and the Sn layer at a set temperature to form AuSn solder.

[0026] As one implementation method, multiple grooves are provided in the solder arrangement area before depositing the seed layer.

[0027] As one implementation method, the groove is made using photolithography and etching processes, and the opening size of the groove is not less than the minimum resolvable feature size of the photolithography machine.

[0028] The present invention also relates to a wafer, comprising a wafer body and solder, wherein the solder is manufactured using the solder forming method described above.

[0029] The present invention has at least the following beneficial effects:

[0030] This invention introduces a protective shell as a mask during the seed layer material removal process, precisely defining the removal area of ​​the seed layer. This ensures the complete preservation of the seed layer directly beneath the solder overlay structure, effectively protecting the solder overlay structure and preventing side-penetration of the seed layer and the solder overlay structure (e.g., buffer layer). The intact seed layer guarantees its adhesion to the substrate, fundamentally eliminating weak points in the device and enabling the solder to withstand process stresses such as high-pressure cleaning, thus eliminating the risk of detachment. For wafer-level packaging, forming solder using this method can significantly improve packaging reliability and maintain a high vacuum state inside the device for extended periods. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A schematic diagram of existing AuSn solder provided for the background art;

[0033] Figure 2 This is a schematic diagram of the structure of AuSn solder provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic flowchart of the solder forming method provided in an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of a base with grooves provided in an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] like Figure 3 This invention provides a solder forming method, the method comprising the following steps:

[0038] Seed layer 110 is deposited on substrate 2;

[0039] An upper solder structure 10 is fabricated on the seed layer 110 using an electroplating process. The upper solder structure 10 is located directly above the solder arrangement area 20 of the substrate 2.

[0040] A protective shell 32 is formed on the seed layer 110, such that the protective shell 32 at least covers the sidewalls of the solder upper layer structure 10;

[0041] Remove the seed layer material outside the projection range of the protective shell 32 to obtain the shaped seed layer 11;

[0042] Remove the protective shell 32.

[0043] In one embodiment, the substrate 2 is a silicon substrate, such as a silicon wafer.

[0044] In one embodiment, the seed layer 110 is made of Cu material, including but not limited to depositing the seed layer 110 by PVD coating.

[0045] Furthermore, the seed layer material is removed using a wet etching process.

[0046] In one embodiment, such as Figure 2 and Figure 3 The aforementioned upper solder structure 10 includes a buffer layer 12, a barrier layer 13, and a solder layer stacked sequentially from bottom to top.

[0047] Preferably, the buffer layer 12 and the seed layer 110 are made of the same material. For example, for the Cu seed layer 110, the buffer layer 12 is made of Cu material, including but not limited to being made by electroplating.

[0048] Optionally, the barrier layer 13 is made of Ni material, including but not limited to being made using an electroplating process.

[0049] Preferably, the solder is AuSn solder, such as... Figure 2 and Figure 3 The solder layer includes an Au layer 14 formed on the barrier layer 13 and a Sn layer 15 formed on the Au layer 14, including but not limited to being made by electroplating process; accordingly, after removing the protective shell 32, the method further includes: fusing the Au layer 14 and the Sn layer 15 at a set temperature (generally greater than 290°C) to form AuSn solder.

[0050] Furthermore, such as Figure 3 When fabricating the upper solder structure 10, an electroplating pattern photolithography operation is first performed, which specifically includes: coating photoresist 31 on the seed layer 110, exposing and developing it, defining the solder pattern (e.g., a ring), and then electroplating the buffer layer 12, the barrier layer 13, and the solder layer in sequence.

[0051] The aforementioned protective shell 32 may only cover the side perimeter of the upper solder structure 10. Correspondingly, the protective shell 32 is a double-wall structure. Taking a ring-shaped solder as an example, the protective shell 32 includes an inner ring wall and an outer ring wall. The projection of the inner ring wall onto the seed layer 110 is the inner ring projection, and the projection of the outer ring wall onto the seed layer 110 is the outer ring projection. Therefore, the area within the inner ring projection plus the area outside the outer ring projection constitutes the area outside the projection range of the protective shell 32. Furthermore, as... Figure 3 The protective shell 32 is a cover-type shell that covers the side and top of the solder upper structure 10. This method provides better protection for the solder upper structure 10, and the manufacturing difficulty is also lower when the protective shell 32 is made using photolithography.

[0052] In one embodiment, the protective shell 32 is fabricated using photolithography, including but not limited to photoresist, hard masks (e.g., metal-based hard masks such as titanium dioxide and tin oxide, inorganic hard masks such as silicon nitride and silicon oxide), and block copolymers (e.g., polystyrene-polymethyl methacrylate). Photoresist is particularly suitable for this embodiment due to its readily available materials and ease of removal. The fabrication of the protective shell 32 mainly includes steps such as spraying, exposure, and development. Taking a cover-type shell using photoresist as an example, this step includes: coating photoresist onto the seed layer 110 and the solder upper structure 10, performing exposure and development to form a patterned photoresist layer covering the solder upper structure 10 as the protective shell 32.

[0053] In this embodiment, by introducing a protective shell 32 as a mask in the seed layer material removal operation, the removal area of ​​the seed layer 110 is accurately determined, ensuring that the forming seed layer 11 directly below the solder upper layer structure 10 is completely preserved. This also effectively protects the solder upper layer structure 10, preventing the lateral removal of the forming seed layer 11 and the solder upper layer structure 10 (e.g., buffer layer 12). The intact forming seed layer 11 ensures its bonding with the substrate 2, fundamentally eliminating weak points in the device and enabling the solder to withstand process stresses such as high-pressure cleaning, thus eliminating the risk of detachment. For wafer-level packaging, forming solder based on the above method can greatly improve the reliability of the package and maintain a high vacuum state inside the device for a long time.

[0054] For the removal of the protective shell 32, the appropriate removal process can be selected according to its material. For example, for the protective shell 32 made of photoresist, a wet removal process or a dry removal process (such as a photoresist remover or an etching machine) can be used.

[0055] like Figure 2 and Figure 3Based on the masking effect of the protective shell 32, after removing the protective shell 32, the width of the forming seed layer 11 is greater than the width of the solder upper structure 10. This ensures the bonding reliability of the forming seed layer 11-substrate 2 and the forming seed layer 11-solder upper structure 10, further improving the anti-detachment capability and sealing reliability of the forming solder. Even if the forming seed layer 11 has a certain degree of side hollowing, its function will not be affected due to its extra width.

[0056] In one embodiment, such as Figure 4 Before depositing the seed layer 110, a plurality of grooves 21 are provided in the solder placement area 20. Thus, when the seed layer 110 is deposited, the seed layer material fills these grooves 21, thereby increasing the bonding area between the seed layer 110 and the substrate 2. Moreover, the seed layer 110 and the substrate 2 interlock, resulting in an order-of-magnitude increase in the bonding force between them. This greatly enhances the mechanical anchoring effect of the formed seed layer 11 and the interfacial bonding strength between the formed seed layer 11 and the substrate 2, further ensuring the long-term stability of the packaged device in harsh environments.

[0057] In particular, based on the above-mentioned ability to completely preserve the molding seed layer 11 or even increase the width of the molding seed layer 11, combined with the interlocking effect between the molding seed layer 11 and the substrate 2, a dense and robust sealing barrier is formed, which effectively prevents gas leakage and greatly improves the reliability of the packaging.

[0058] The cross-section of the groove 21 can be square, rhomboid, circular, etc.

[0059] Preferably, the groove 21 is fabricated using photolithography and etching processes. For example, the precise pattern and position of the groove 21 are first defined on the surface of the silicon substrate 2 using photolithography, then the groove 21 is etched into deep silicon, and finally the photoresist and byproducts are removed by cleaning. Furthermore, the opening size of the groove 21 is not less than the minimum resolvable feature size of the photolithography machine (for example, for a square groove, its length and width are not less than the minimum resolvable feature size of the photolithography machine; for a circular groove, its diameter is not less than the minimum resolvable feature size of the photolithography machine), and is generally designed to be 2~3μm, and is arranged at equal intervals to maximize the contact area between the silicon substrate 2 and the seed layer 110.

[0060] This invention also provides a wafer, including a wafer body and solder, wherein the solder is manufactured using the solder forming method described above.

[0061] Push-pull force tests were conducted on the wafer-level packaged devices fabricated using the aforementioned wafers, and their bonding strength was significantly improved compared to traditional flat-chip processes (without grooves 21, but with side cutouts). In reliability tests such as high-pressure cleaning and temperature cycling, no solder ring detachment or excessive package leakage occurred, and the internal vacuum level of the device remained stable over a long period.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A solder forming method, characterized in that, The method includes the following steps: Deposit a seed layer on the substrate; An upper solder layer structure is fabricated on the seed layer using an electroplating process, and the upper solder layer structure is located directly above the solder arrangement area of ​​the substrate; A protective shell is formed on the seed layer, such that the protective shell at least covers the sidewalls of the upper solder layer structure; Remove seed layer material outside the projection range of the protective shell; Remove the protective shell.

2. The solder forming method as described in claim 1, characterized in that: The protective shell is manufactured using photolithography.

3. The solder forming method as described in claim 1, characterized in that: The protective shell is a dome-shaped shell that covers the side walls and top surface of the upper structure of the solder.

4. The solder forming method as described in claim 1, characterized in that: The seed layer material is removed using a wet etching process.

5. The solder forming method according to any one of claims 1 to 4, characterized in that: The upper solder structure includes a buffer layer, a barrier layer, and a solder layer stacked sequentially from bottom to top.

6. The solder forming method as described in claim 5, characterized in that: The buffer layer and the seed layer are made of the same material.

7. The solder forming method as described in claim 5, characterized in that, The solder layer includes an Au layer formed on the barrier layer and a Sn layer formed on the Au layer; After removing the protective shell, the method further includes: fusing the Au layer and the Sn layer at a set temperature to form AuSn solder.

8. The solder forming method as described in claim 1, characterized in that: Before depositing the seed layer, multiple grooves are provided in the solder placement area.

9. The solder forming method as described in claim 8, characterized in that: The groove is fabricated using photolithography and etching processes, and the opening size of the groove is not less than the minimum resolvable feature size of the photolithography machine.

10. A wafer, comprising a wafer body and solder, characterized in that: The solder is manufactured using the solder forming method as described in any one of claims 1 to 9.

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