Effective use of synchronization primitives in multiprocessor computing systems

Abstract

A compiler creates a dependency graph for functions in an input program. The dependency graph includes nodes corresponding to commands within the functions and edges corresponding to dependencies between commands. The compiler performs forward reachability analysis on the dependency graph to eliminate redundant dependencies. The compiler also adds a minimum set of back edges to the dependency graph to enforce circular resource dependencies in the input program. Then, based on the contents of the dependency graph, the compiler assigns synchronization primitives (such as semaphores) provided by the multiprocessor computing system to commands within the functions of the input program.

Description

Background Technology

[0001] A multiprocessor computing system comprises multiple processors that work together to perform computations. For example, a multiprocessor computing system may include a control processor and one or more other dedicated processors, such as processors for performing scalar or vector operations, processors for performing matrix multiplication, and processors for performing direct memory access operations. The control processor issues commands to the other processors to perform processing operations.

[0002] To achieve better performance, the control processor in a multiprocessor computing system can issue commands to other processors asynchronously. This means that the control processor does not wait for the processors to complete their commands before issuing the next command. Issuing new commands without waiting for previously issued commands to complete can improve the performance of multiprocessor computing systems by allowing independent commands to be executed concurrently on different processors.

[0003] However, there are scenarios where commands are not independent and therefore cannot be executed simultaneously by different processors. For example, a command to move two operands into memory must be completed before commands to perform arithmetic operations on the operands can begin.

[0004] Mechanisms exist for coordinating the asynchronous execution of commands in multiprocessor computing systems (such as those described above). However, program code must typically be manually optimized to take advantage of these mechanisms. Manually optimizing programs to utilize these mechanisms can be very difficult and time-consuming. Additionally, manual optimization may lead to suboptimal utilization of computational resources used to coordinate the asynchronous execution of commands, thus resulting in poor performance. Summary of the Invention

[0005] This document discloses techniques for effectively utilizing synchronization primitives in multiprocessor computing systems. Through the implementation of the disclosed techniques, resources used to coordinate the execution of asynchronous commands in a multiprocessor computing system (referred to herein as "synchronization primitives") can be utilized more optimally than previously possible, resulting in improved execution performance. Furthermore, through the implementation of the disclosed techniques, program code can be optimized automatically to effectively utilize available synchronization primitives, thereby eliminating the need for difficult and time-consuming manual optimization. Other technical benefits not specifically mentioned herein can also be achieved through the implementation of the disclosed subject matter.

[0006] To provide the various aspects of the functionality disclosed herein, the compiler (such as a language compiler or graph compiler) creates a dependency graph for functions in the input program. The dependency graph includes nodes corresponding to commands within functions and edges corresponding to dependencies between nodes. According to various embodiments disclosed herein, the compiler uses shared queue analysis, input / output analysis, allocation overlap analysis, and / or other types of dependency analysis to identify dependencies between nodes.

[0007] In one embodiment, the compiler also minimizes the edges in the dependency graph corresponding to dependencies between nodes. For example, but not limited to, in one embodiment, the compiler adds artificial resource dependencies between consecutive pairs of nodes with the same command type and performs forward reachability analysis on the dependency graph to eliminate redundant dependencies. The compiler then adds edges to the dependency graph for the dependencies that remain after eliminating redundant dependencies.

[0008] In an embodiment, the compiler also adds a minimized set of back edges to the dependency graph to enforce resource dependencies carried by loops in the input program. For example, but not limited to, the compiler may add a first back edge from a leaf node to the root node of the dependency graph associated with the loop (i.e., a back edge added to a subset of the function's dependency graph consisting only of nodes / commands inside the loop), and a second back edge from a leaf node to another root node of the dependency graph associated with the loop.

[0009] The compiler then assigns synchronization primitives provided by the multiprocessor computing system to commands within the input program's functions, based on the edges in the dependency graph. For example, in one embodiment, the compiler assigns synchronization primitives provided by the multiprocessor computing system to commands within the input program's functions to optimally coordinate the asynchronous execution of commands. This assignment is performed in a manner that allows for the reuse of synchronization primitives, maximizing the efficient utilization of the finite pool of synchronization primitives provided by the multiprocessor computing system.

[0010] The foregoing subject matter is implemented in various embodiments disclosed herein as a computer-controlled apparatus, a computer-implemented method, a processing system, or an article of manufacture (such as a computer-readable storage medium). These and other various features will become apparent from the following detailed description and a review of the associated drawings.

[0011] This synopsis is provided to provide a simplified description of some aspects of the disclosed technology, which will be further described in the detailed description below. This synopsis is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Furthermore, the claimed subject matter is not limited to implementations that address any or all of the shortcomings pointed out in any part of this disclosure. Attached Figure Description

[0012] Figure 1 This is a computing system diagram illustrating various aspects of a multiprocessor computing system according to an embodiment, which provides an illustrative operating environment for the techniques disclosed herein.

[0013] Figure 2 This is a software architecture diagram illustrating various aspects of the configuration and operation of a compiler used to provide the functions disclosed herein, according to an embodiment.

[0014] Figure 3 This is a flowchart illustrating a routine that provides an overview of the mechanisms disclosed herein for effectively utilizing synchronization primitives in a multiprocessor computing system, according to an embodiment.

[0015] Figure 4A This is a data structure diagram illustrating various aspects of a mechanism for determining dependencies between commands in an intermediate representation program using shared queue analysis according to an embodiment.

[0016] Figure 4B This is a data structure diagram illustrating various aspects of a mechanism for determining dependencies between commands in an intermediate representation program using input / output analysis according to an embodiment;

[0017] Figure 4C This is a data structure diagram illustrating various aspects of a mechanism for determining dependencies between commands in an intermediate representation program using allocation overlap analysis according to an embodiment.

[0018] Figure 5 This is a flowchart illustrating aspects of a routine according to an embodiment for determining dependencies between nodes in a dependency graph that correspond to commands in functions of an intermediate representation program.

[0019] Figure 6A This is a data structure diagram illustrating aspects of a mechanism disclosed herein for minimizing the number of forward dependencies in a dependency graph, according to an embodiment.

[0020] Figure 6B This is a data structure diagram illustrating aspects of another mechanism disclosed herein for minimizing the number of forward dependencies in a dependency graph, according to an embodiment.

[0021] Figure 6C This is a data structure diagram illustrating aspects of another mechanism disclosed herein for minimizing the number of forward dependencies in a dependency graph, according to an embodiment.

[0022] Figure 7 This is a flowchart illustrating aspects of a routine for minimizing the number of forward dependencies in a dependency graph according to an embodiment;

[0023] Figure 8This is a data structure diagram illustrating various aspects of the mechanism disclosed herein for modeling circularly carried dependencies in a dependency graph, according to an embodiment.

[0024] Figure 9 This is a data structure diagram illustrating how, according to an embodiment, back edges are added from leaf nodes to multiple root nodes in a subgraph targeting a loop to model the dependencies carried by the loop.

[0025] Figure 10 This is a data structure graph illustrating a scenario where no back edges need to be added to the dependency graph according to an embodiment, because all forward edges in the dependency graph are between nodes associated with the same work queue;

[0026] Figure 11 This is a data structure diagram illustrating, according to an embodiment, aspects of a minimum flow test used to determine the next node / leaf node pair around which a back edge is added in a dependency graph;

[0027] Figure 12 This is a data structure diagram illustrating, according to an embodiment, the aspects used to determine the maximum benefit test of the next node / leaf node pair around which a back edge is added in a dependency graph;

[0028] Figure 13 This is a flowchart illustrating aspects of a routine for adding a minimized set of back edges to a dependency graph to enforce a loop carrying dependencies, according to an embodiment.

[0029] Figure 14 This is an illustration of a method of use according to an embodiment for reference. Figures 4A to 13 The flowchart describes how the dependency graph is created to allocate various aspects of the routines for synchronization primitives;

[0030] Figure 15A This is a flowchart illustrating various aspects of the forward pass of a two-pass algorithm for creating a dependency graph, according to an embodiment.

[0031] Figure 15B This is a flowchart illustrating various aspects of a two-pass algorithm for creating a dependency graph, according to an embodiment.

[0032] Figure 16 This is a computer architecture diagram illustrating the computer hardware and software architecture of a processing system for implementing various aspects of the techniques presented herein, as shown in the embodiments; and

[0033] Figure 17 The illustration in the embodiments is a network diagram of an example distributed computing environment in which various aspects of the disclosed technology are implemented. Detailed Implementation

[0034] The following detailed description relates to techniques for the efficient use of synchronization primitives in multiprocessor computing systems. As briefly discussed above, implementations of the disclosed techniques enable the more optimized use of synchronization primitives in multiprocessor computing systems than previously possible, resulting in improved execution performance. Furthermore, the implementations of the disclosed techniques allow for automated optimization of program code to effectively utilize available synchronization primitives, eliminating the need for difficult and time-consuming manual optimization. Other technical benefits not specifically mentioned herein can also be achieved through implementations of the disclosed subject matter.

[0035] Figure 1 This is a computing system diagram illustrating various aspects of a multiprocessor computing system 100 according to an embodiment, which provides an illustrative operating environment for the techniques disclosed herein. In this respect, it should be understood that... Figure 1 The multiprocessor computing system 100 shown has been simplified for ease of discussion. The multiprocessor computing system 100 may include... Figure 1 Other components not specifically shown may not include Figure 1 All components shown, or those that can be used with Figure 1 The different architectures shown in the diagram are implemented using different architectures.

[0036] As briefly discussed above, multiprocessor computing systems (such as...) Figure 1 The illustrated multiprocessor computing system 100 includes multiple processors that work together to perform computations. For example, in the illustrated embodiment, the multiprocessor computing system 100 includes a control processor (“CP”) 102 and one or more other dedicated processors 104A to 104N (collectively referred to herein as “processor 104”). Processor 104 may be a processor for performing scalar or vector operations, a processor for performing matrix multiplication, a processor for performing direct memory access (“DMA”) operations, or a processor for performing other types of computations and operations.

[0037] In this embodiment, processor 104 has associated work queues 106A to 106N (collectively referred to herein as "work queue 106"). Figure 1 In the illustrated embodiment, work queue 106 is external to processor 104. However, it should be understood that in other embodiments, work queue 106 may be implemented internally to processor 104 or in another location. According to embodiments, work queue 106 may be implemented in hardware, software, or a combination of hardware and software.

[0038] During the execution of program 114, CP 102 sends commands 108A to 108N (collectively referred to herein as "command 108") to processor 104 to perform the operations specified by program 114. For example, in an embodiment, CP 102 places commands 108 on their respective work queues 106 of processor 104. Processor 104 then dequeues commands 108 from their respective work queues 106 and executes the specified commands 108 independently.

[0039] In the multiprocessor computing system 100, the CP 102 can asynchronously issue commands 108 to the processor 104, meaning that the CP 102 does not wait for command 108 to complete before issuing the next command 108. Issuing new commands 108 without waiting for previously issued commands 108 to complete can improve the performance of the multiprocessor computing system 100 by enabling independent commands 108 to be executed concurrently on different processors 104.

[0040] As described above, there are scenarios where commands 108 are not independent and therefore cannot be executed simultaneously. For example, command 108 for moving two operands from host memory to memory 110 of the multiprocessor computing system 100 must be executed before command 108 performing arithmetic operations on the operands can begin. Another example is the case where the memory ranges utilized by two commands 108 overlap. In this scenario, commands 108 cannot be executed simultaneously because they may overwrite the memory locations currently being used by each other. In this regard, it should be understood that although Figure 1 Only a single memory 110 shared by processors 104A to 104N is shown, but according to embodiments, each processor 104 may have its own memory 110.

[0041] As briefly discussed above, there are methods for coordinating multiprocessor computing systems (such as...). Figure 1 The execution of command 108 (as shown) employs mechanisms to optimize the asynchronous execution of command 108. However, program 114 typically requires manual optimization to take advantage of these mechanisms, which can be very difficult and time-consuming. Additionally, manual optimization may lead to suboptimal utilization of computational resources used to coordinate the execution of command 108, resulting in poor performance.

[0042] To address the technical limitations and other potential limitations of the aforementioned prior solutions, the multiprocessor computing system 100 is configured with synchronization primitives 112. Synchronization primitives 112 are software or hardware resources that can be signaled or waited for to coordinate the asynchronous execution of command 108. In embodiments, synchronization primitives 112 are semaphores, which are variables or abstract data types used to control access to shared resources such as memory 110. However, it should be understood that other types of synchronization primitives 112 may be utilized in other embodiments, such as mutexes, barriers, spinlocks, or other types of locks.

[0043] As will be described in more detail below, the techniques disclosed herein can automatically determine the optimal utilization of the synchronization primitive 112 for the asynchronous execution of command 108 in program 114, resulting in improved execution performance compared to previous solutions that relied on manual optimization. Furthermore, through the implementation of the disclosed techniques, program 114 can be optimized automatically to effectively utilize the available synchronization primitive 112, thereby eliminating the need for difficult and time-consuming manual optimization. Details regarding these aspects will be provided below. Figures 2 to 13 And thus provided.

[0044] Figure 2 This is a software architecture diagram illustrating various aspects of the configuration and operation of a compiler 200 used to provide the functions disclosed herein, according to an embodiment. In this embodiment, compiler 200 is a graph compiler. However, it should be understood that in other embodiments, compiler 200 may be a language compiler or another type of compiler. Additionally, in other embodiments, other types of program components may be configured to provide the functions disclosed herein that are performed by compiler 200, such as, for example, non-compiler analysis tools.

[0045] like Figure 2 As shown, in this embodiment, an input program 202, which has not yet been optimized for optimal asynchronous execution of command 108 on the multiprocessor computing system 100, is provided to compiler 200. The input program 202 includes information regarding... Figure 1 The described method refers to a function that issues command 108 to processor 104. Input program 202 can be expressed using programming languages ​​such as, but not limited to, TRITON, C, C#, or PYTHON. In other embodiments, input program 202 can be expressed using other programming languages.

[0046] In one embodiment, the output of compiler 200 is program 114 optimized for optimal asynchronous execution of command 108 on multiprocessor computing system 100. In another embodiment, compiler 200 or another type of program outputs program analysis report 208, which specifies how to modify input program 202 for optimized asynchronous execution of command 108 in input program 202 on multiprocessor computing system 100. In other embodiments, compiler 200 or other types of programs provide other types of output.

[0047] To optimize the input program 202 for asynchronous execution, the compiler 200 creates a function dependency graph 206 for the input program 202 by targeting the function traversal IR program 204. The IR program 204 is a data structure or other type of code used internally by the compiler 200 to represent the input program 202. In one embodiment, the IR program 204 is expressed using a multi-level intermediate representation (“MLIR”). In other embodiments, the compiler 200 utilizes other types of IR.

[0048] During the function traversal IR program 204, compiler 200 creates nodes and edges between nodes in dependency graph 206. Dependency graph 206 encodes command 108 for the function along with synchronization primitives 112 provided by multiprocessor computing system 100 for optimizing asynchronous execution of command 108.

[0049] More specifically, compiler 200 creates nodes in dependency graph 206 for commands 108 that require synchronization within a function, such as commands 108 issued by CP 102 to processor 104 for performing scalar or vector operations, commands 108 for performing matrix multiplication, commands 108 for performing DMA operations, or commands 108 for performing other types of computations or operations. Compiler 200 creates root nodes in dependency graph 206 representing incoming dependencies from outside the function, and another node capturing outgoing dependencies.

[0050] In dependency graph 206, edges represent synchronization primitives 112 (e.g., semaphores, mutexes, barriers, spinlocks, or other types of locks) where a source command 108 (represented by a source node) signals and a destination command 108 (represented by a destination node) waits. Dependencies represented by edges can be categorized as data dependencies between commands 108 (e.g., when the output of command 108 is used as the input of another command 108) or resource dependencies (e.g., when two commands 108 operate on a buffer with the same memory address). Compiler 200 can utilize multiple analyses to determine the dependencies between nodes in dependency graph 206, examples of which are described below. Figures 4A to 5 And is described.

[0051] When source command 108 and destination command 108 share input or output, edges corresponding to data dependencies are added to dependency graph 206. Edges in dependency graph 206 representing data dependencies specify the values ​​they represent. If there are data dependencies that feed values ​​to two or more dependent nodes, multiple edges with the same value can exist. Edges corresponding to resource dependencies have no associated values.

[0052] Edges corresponding to resource dependencies can specify memory resource dependencies, synchronization primitive dependencies, or dependencies on another type of resource. When source command 108 and destination command 108 read or write to overlapping memory regions, edges specifying memory resource dependencies are added to dependency graph 206.

[0053] For command 108, which is part of a loop, edges specifying synchronization primitive dependencies are added to dependency graph 206 to prevent two independent loop iterations from simultaneously signaling the same synchronization primitive 112. As described in more detail below, the edges in dependency graph 206 are typically forward edges, except for edges corresponding to synchronization primitive dependencies (these are back edges).

[0054] The nodes in the dependency graph 206 for the function can be simultaneous or non-simultaneous. Simultaneous nodes simultaneously signal all their output synchronization primitives 112, while non-simultaneous nodes can independently signal their output synchronization primitives 112.

[0055] Once the dependency graph 206 has been created and optimized for all functions in input program 202, compiler 200 assigns a synchronization primitive 112 to each edge in dependency graph 206 and appends it to the corresponding command 108 in IR program 204. IR program 204 can then be compiled to generate optimized output program 114. (Regarding the above...) Figure 2 Additional details about the briefly described features will be provided below. Figures 3 to 13 And thus provided.

[0056] Figure 3 This is a flowchart illustrating an overview of a routine 300 provided herein, according to an embodiment, for implementing a mechanism for efficiently utilizing synchronization primitive 112 in a multiprocessor computing system 100. Routine 300 begins at operation 302, where compiler 200 creates a function dependency graph 206 for input program 202. Using dependency graph 206 to represent dependencies between asynchronous functions in input program 202, the following is implemented regarding… Figures 4A to 15B The optimizations described enable synchronization primitives to be utilized more optimally than previously possible, resulting in improved execution performance of input procedure 202. Previous solutions, such as directly using MLIR with dominance tests, do not support the optimizations described below.

[0057] As briefly discussed above, in order to create dependency graph 206, compiler 200 can utilize multiple different analyses to determine the dependencies between nodes in dependency graph 206. In this embodiment, compiler 200 utilizes shared queue analysis (see below for details). Figure 4A (Described), Input / Output Analysis (below about) Figure 4B The description), and the assignment overlap analysis (below about) Figure 4C The description indicates that the dependencies between nodes in dependency graph 206 are determined. In other embodiments, the compiler utilizes analysis of alternative or additional types to identify the dependencies between nodes in dependency graph 206.

[0058] In this embodiment, each analysis used to identify dependencies between nodes in dependency graph 206 operates in isolation. As a result, redundant or duplicate dependencies may be added to dependency graph 206. In one embodiment, compiler 200 optimizes redundant or duplicate dependencies in operation 304.

[0059] Compiler 200 can use the following information about Figure 7 The mechanism described is to minimize the number of forward edges 404 in the dependency graph 206. Regarding Figure 7 The described mechanism makes it easy to extend compiler 200 with different components to perform dependency identification, without requiring each component to guarantee that the dependencies it identifies are globally optimal. Figures 6A to 6C Explanation is shown Figure 7 The mechanism shown is an example of how edges can be added between commands in the same queue (i.e., via the exposed shared queue analysis) to identify cases where all redundant forward edges are present.

[0060] From operation 304, routine 300 proceeds to operation 306, where compiler 200 adds a minimized set of back edges to dependency graph 206 to enforce cyclic dependency carrying. Details on this aspect are provided below. Figures 8 to 13 Provided.

[0061] From operation 306, routine 300 proceeds to operation 308, where compiler 200 allocates synchronization primitive 112 to input program 204 based on the contents of dependency graph 206 created in operations 302 to 306. Details regarding this are provided below. Figure 14 Provided. From operation 308, routine 300 proceeds to operation 310, and routine 300 ends at operation 310.

[0062] Create a dependency graph

[0063] Figure 4AThis is a data structure diagram illustrating various aspects of the mechanism for determining dependencies between commands 108 in a function of IR procedure 204 using shared queue analysis according to an embodiment. In this embodiment, commands 108 of the same type are placed in the same work queue 106, where they are executed one after another in a first-in-first-out (“FIFO”) order. This shared use of work queue 106 creates resource dependencies between each command 108 of the same type.

[0064] To model the dependencies generated by the shared work queue 106, compiler 200 performs shared queue analysis. The shared queue analysis creates a resource dependency edge 404 between the current node 402 and the nearest node 402 in the dependency graph 206 corresponding to the same command type.

[0065] Figure 4A The example fragment of dependency graph 206 shown illustrates various aspects of the shared queue analysis described above. Specifically, Figure 4A The simplified IR 204 shown includes three commands 108. Therefore, the corresponding dependency graph 206 includes three nodes 402A to 402C, each corresponding to one of the three commands 108. Because the commands 108 are of the same type, compiler 200 adds edge 404A between nodes 402A and 402B, and edge 404B between nodes 402B and 402C.

[0066] It should be understood that in embodiments where the multiprocessor computing system 100 enforces the FIFO execution order of command 108 in work queue 106, it is not necessary to use synchronization primitive 112 to enforce shared queue dependencies. However, as will be described in more detail below, defining shared queue dependencies in dependency graph 206 can help identify redundant dependencies (i.e., edge 404) in dependency graph 206.

[0067] Figure 4B This is a data structure diagram illustrating various aspects of the mechanism for determining the dependencies between commands 108 in a function of IR program 204 using input / output analysis, according to an embodiment. Figure 4B The illustrated input / output analysis identifies data dependencies between commands 108 based on usage (i.e., when the buffer is read) and definition (i.e., when the buffer is written).

[0068] The input / output analysis performed by compiler 200 considers three main types of usage-based dependencies: read-after-write; write-after-read; and write-after-write. In the case of a read-after-write dependency (also known as a "use-after-definition" dependency), compiler 200 adds a data dependency edge 404 to node 402 in dependency graph 206 corresponding to command 108, which has recently defined a buffer.

[0069] Figure 4B The example fragment of dependency graph 206 shown illustrates the aspects of the input / output analysis briefly described above. Figure 4B In the example shown, for instance, command 108, represented by node 402E, reads the buffer that is the target of copy command 108 associated with node 402D. Therefore, compiler 200 adds a data dependency edge 404C between nodes 402D and 402E to account for this data dependency. The value of the created data dependency edge 404C is set to the buffer involved in the dependency (i.e., %2).

[0070] In the case of a read-after-write dependency (also known as a "use-after-defined" dependency), compiler 200 adds a data dependency edge 404 to node 402 in dependency graph 206 corresponding to the most recent command 108 that used the buffer since it was last defined. Figure 4B In the example shown, for instance, a data dependency edge 404D has been added between nodes 402E and 402F to account for writing to buffer %3 by command 108 associated with node 402F after reading buffer %3 by command 108 associated with node 402E.

[0071] In the case of a write-after-write dependency (also known as a "definition-after-defined" dependency), compiler 200 adds a dependency edge 404 to node 402 corresponding to the most recently defined command 108 of the buffer. In one embodiment, for example, if there have been no reads since the buffer was last written, compiler 200 instead adds a dependency edge 404 to node 402 corresponding to the most recently defined command 108 of the buffer to account for the write-after-write dependency.

[0072] In this embodiment, only the most recent use of each work queue 106 is considered to reduce the number of edges 404 required. For example, if two commands 108 have used the buffer since it was last defined, only the most recent command 108 is considered. Ignoring the other command 108 is effective because the two commands 108 are inherently synchronized by the shared queue dependency in the manner described above.

[0073] Figure 4C This is a data structure diagram illustrating various aspects of the mechanism for determining dependencies between commands 108 in a function of IR program 204 using allocation overlap analysis according to an embodiment. In this embodiment, compiler 200 efficiently utilizes memory 110 by reclaiming previously used memory address ranges when allocating new buffers. Specifically, in this embodiment, compiler 200 adds resource dependency edges 404 between nodes 402 corresponding to commands 108 in shared memory address ranges.

[0074] Figure 4C The simplified IR 204 shown includes three commands. Therefore, Figure 4C The example fragment of dependency graph 206 shown includes three nodes 402G to 402I, each of which corresponds to command 108 in simplified IR 204. Additionally, because Figure 4C In the simplified IR 204 shown, command 108 utilizes overlapping memory address ranges, and compiler 200 adds edges 404E, 404F, and 404G to dependency graph 206 to reflect these dependencies.

[0075] It should be understood that there is a resource dependency between each use of a memory address range and all uses of any overlapping range throughout the function. To avoid O(N) behavior, in the embodiment, compiler 200 adds edges 404 only to dependency graph 206, if any, between node 402 (corresponding to command 108 utilizing the memory address range) and node 402 (corresponding to recently used command 108 with overlapping range), and between node 402 (corresponding to command 108 utilizing the range) and node 402 (corresponding to recently used command 108 with overlapping memory address range in the current loop of simplified IR 204). This finite set of edges 404 is sufficient to conservatively represent the allocation overlap dependencies carried forward and in the loop.

[0076] Figure 5 This is a flowchart illustrating aspects of a routine 500, according to an embodiment, for determining dependencies between nodes 402 in dependency graph 206 corresponding to command 108 in IR program 204. It can be executed against all functions or subsets of functions in input program 202. Figure 5 The operation is illustrated in the diagram.

[0077] Example 500 begins with operation 502, where compiler 200 executes the above-mentioned... Figure 4A The described shared queue analysis identifies dependencies between commands 108 within functions of IR program 204. Specifically, as described above, during shared queue analysis, compiler 200 creates resource dependency edges 404 between the current node 402 and the nearest node 402 in dependency graph 206 corresponding to the same command type.

[0078] From operation 502, routine 500 proceeds to operation 504, where compiler 200 executes the above-mentioned... Figure 4BThe described input / output analysis identifies dependencies between commands 108 in IR program 204. Specifically, as described above, during input / output analysis, compiler 200 identifies data dependencies between commands 108 based on usage (i.e., when a buffer is read) and definition (i.e., when a buffer is written). Compiler 200 then adds dependency edges 404 between nodes 402 to account for these dependencies. Routine 500 then proceeds from operation 504 to operation 506.

[0079] In operation 506, compiler 200 executes the above regarding... Figure 4C The described allocation overlap analysis identifies dependencies between commands 108 in IR program 204. Specifically, as described above, compiler 200 adds resource dependency edges 404 between nodes 402 corresponding to commands 108 in shared memory address ranges.

[0080] From operation 506, routine 500 proceeds to operation 508, where compiler 200 may perform one or more additional dependency analyses to identify dependencies between commands 108 in functions of IR program 204. From operation 508, routine 500 proceeds to operation 510, where routine 500 ends.

[0081] As described above, the analysis performed in operations 502 to 508 to identify the dependencies between nodes 402 in dependency graph 206 is operated in isolation in this embodiment. As a result, redundant or duplicate dependencies may exist that are added to dependency graph 206. In this embodiment, this is achieved through the following... Figure 7 The mechanism described optimizes redundant or duplicated dependencies. As mentioned above, this mechanism makes it easy to extend compiler 200 with different components to perform dependency identification, without requiring each component to guarantee that the identified dependencies are globally optimal.

[0082] Optimize forward dependencies in the dependency graph

[0083] As briefly discussed above, once it is about Figures 4A to 5 The description creates a dependency graph 206, which can be analyzed to determine the synchronization primitives 112 required to enforce forward dependencies (i.e., dependencies that do not span multiple iterations of a loop). Since the dependency graph 206 for functions describes the forward dependencies between commands 108, one approach to assigning synchronization primitives 112 to these dependencies is to generate one synchronization primitive 112 for each edge 404 in the dependency graph 206. However, this approach may result in the use of more synchronization primitives 112 than necessary.

[0084] To minimize the utilization of synchronization primitives 112 (the number of which may be finite), the embodiments disclosed herein eliminate redundant forward edges 404 in the dependency graph 206. A synchronization primitive 112 is then assigned for each retained edge 404.

[0085] According to an embodiment, when there are multiple valid dependency paths between nodes 402, when node 402 follows another node 402 sharing the same work queue 106 in lexicographical order, and when the target node 402 is a descendant of another node 402 (which follows its parent node 402 in lexicographical order and shares the same work queue 106), edge 404 can be eliminated from dependency graph 206. The following is about... Figures 6A to 6C Description examples, these examples illustrate Figure 7 The mechanism shown and described below can be used to add edges between commands in the same queue (i.e., via the disclosed shared queue analysis) to identify all cases of redundant forward edges.

[0086] exist Figure 6A In the example shown, the example depends on fragments of graph 206 including nodes 402J to 402L and edges 404G to 404I. In this example, as Figure 6A The “X” indicates that edge 404G can be eliminated from dependency graph 206 because there is another valid dependency path between nodes 402J and 402L (i.e., the path from node 402J to 402L via edges 404I and 404H). In this way, edge 404 is removed from dependency graph 206 in the case that there is another valid dependency path between the two nodes 402 under consideration.

[0087] exist Figure 6B In the example shown, another example of a fragment of the dependency graph 206 includes nodes 402M to 402P and edges 404L to 404M. Edge 404L is an implicit edge that has been added to the dependency graph 206 between nodes using the same queue (i.e., work queue "C" in the illustrated example).

[0088] exist Figure 6B In the example shown, such as Figure 6BAs indicated by the "X" in the graph, edge 404J can be eliminated from the fragment of dependency graph 206 because node 402N follows node 402O in lexicographical order, and nodes 402N and 402O share the same work queue 106. Since commands 108 placed in work queue 106 are implicitly ordered in the manner described above, the command 108 associated with node 402N will not be executed before the preceding node 402O that shares the same work queue 106. Therefore, edge 404J between the parent (i.e., node 402M) and the child (i.e., node 402N) is redundant and can be removed from dependency graph 206.

[0089] Another example depends on a fragment of Figure 206. Figure 6C The graph is illustrated, comprising nodes 402P to 402R and edges 404N to 404Q. Edge 404O is an implicit edge added between nodes using the same queue (i.e., work queue "A" in the illustrated example). In this example, as... Figure 6C The “X” indicates that edge 404N can be eliminated from the fragment dependent on graph 206 because the target node 402Q of edge 404N is a descendant of node 402R, which follows its parent node 402P in lexicographical order and shares the same work queue 106 with it (i.e., work queue “A” in the illustrated example).

[0090] It should be understood that, in the embodiments, the above regarding Figures 6A to 6C The described edge minimization mechanism considers edge 404 redundant only if there exists an existing path starting from edge 404 that signals simultaneously with the considered edge 404. For simultaneous node 402, this can be any edge 404. For non-simultaneous nodes, in the embodiment, only data-dependent edges 404 with the same value as the current edge 404 are considered.

[0091] It should be understood that by using the shared queue analysis described herein, it is not necessary to separately identify the cases of "reachable nodes," "covered queues," and "replaced queues." The resource dependencies added by the shared queue analysis make node 402N reachable from node 402O, and node 402R reachable from node 402P. As a result, all three cases (i.e., reachable nodes, covered queues, and replaced queues) can be detected simultaneously using forward reachability analysis. This analysis provides benefits compared to previous optimization techniques, such as, but not limited to, higher computational efficiency and accuracy.

[0092] Figure 7 This is a flowchart illustrating various aspects of a routine 700 for minimizing the number of forward dependencies in dependency graph 206 according to an embodiment. The following is about... Figure 7The described mechanism utilizes a modified reachability analysis to minimize the set of forward edges in dependency graph 206. However, it should be understood that in other embodiments, other mechanisms may be used to minimize the number of forward dependencies in dependency graph 206, such as, for example, transitive reduction algorithms.

[0093] Routine 700 begins with operation 702, which iterates through input program 202 and identifies data and resource dependencies between nodes 402. Artificial resource dependencies are also added between each pair of consecutive nodes of the same type. These artificial resource dependencies reflect the fact that commands of the same type are implicitly serialized because they are issued on the same work queue 106. (The above is about...) Figures 4A to 5 A mechanism for identifying dependencies between nodes is described. Other mechanisms, such as network flow algorithms, may be utilized in other embodiments.

[0094] From operation 702, routine 700 proceeds to operation 704, where a forward reachability analysis is performed on dependency graph 206. During the forward reachability analysis, if source node 402 has already reached destination node 402 via a different path through dependency graph 206, edge 404 is eliminated.

[0095] From operation 704, routine 700 proceeds to operation 706, where edge 404 is added to dependency graph 206 for any remaining dependencies not eliminated in operation 706. Artificial dependencies created in operation 702 are ignored during this operation. From operation 706, routine 700 proceeds to operation 708, where routine 700 terminates.

[0096] Forced circular carrying of resource dependencies

[0097] The loops generated by input procedure 202 typically do not include loop-carrying data dependencies between iterations. However, loop-carrying dependencies may still exist due to the use of shared hardware resources (such as memory addresses and synchronization primitives 112) across iterations.

[0098] As will be described in more detail below, the mechanism disclosed herein includes an algorithm for detecting circular dependencies and generating an optimal set of synchronization primitives 112 that enforce them. The disclosed mechanism can derive the optimal set of synchronization primitives 112 without user input, thus eliminating the need for difficult and time-consuming manual optimization. The disclosed mechanism also optimizes the derived set of synchronization primitives 112 to avoid unnecessary use of synchronization primitives 112 for high performance.

[0099] Before discussing these algorithms, it should be understood that there is a symmetric relationship between cyclic carry dependencies and forward dependencies. Therefore, each forward dependency in a loop has a corresponding cyclic carry dependency.

[0100] Since all data and resource dependency edges 404 in dependency graph 206 are synchronization primitives 112, all dependency edges 404 in a cycle introduce a corresponding cyclically carried dependency. Additionally, the cyclically carried dependency involves the same node 402 as its corresponding forward dependency, but in the opposite direction. For example, if the first node 402 has a dependency on the second node 402, then the second node 402 will have a cyclically carried dependency on the first node 402, representing the resources consumed by the second node 402 in previous iterations of the cycle.

[0101] One mechanism disclosed in this paper models cycle-carrying dependencies by adding a mirrored back edge to each forward edge 404 in the dependency graph 206 for cycles. For example, in Figure 8 In the example fragment of dependency graph 206 shown on the left, resources A and B do not carry synchronization in a cycle. Figure 8 In the example shown in the middle, resources A and B have been synchronized separately across the loop iteration by adding back edges 802A and 802B to dependency graph 206.

[0102] In this embodiment, only the leaf nodes and root node 402 of the cyclic subgraph are linked using back edges 802 to reduce the required number of back edges 802. Figure 8 In the example shown on the right-hand side, for example, by adding a single back edge 802C, resources A and B are synchronized together across the loop iteration.

[0103] In a cyclic dependency graph 206 (i.e., a subgraph consisting only of commands within a loop) with multiple root nodes 402 and leaf nodes 402, cyclic dependency back edges 802 may be required from each leaf node 402 to each root node 402. These back edges 802 represent synchronization primitives 112 that the command 108 associated with the root node 402 should wait for to prevent the current iteration of the loop from overwriting resources still used by previous iterations of the loop. For example, Figure 9 The illustrative circular dependency graph 206 shown illustrates the addition of a back edge 802D from a leaf node to the first root node and a back edge 802E from a leaf node to the second root node.

[0104] Optimize the circular carry set of synchronization primitives

[0105] As discussed above, it may be necessary to add back edges 802 between each root / leaf node pair in the cyclic dependency graph 206. However, some cyclically carried dependencies may already be inherently synchronized due to the serial nature of the same work queue 106 commands 108 occurring within the cycle. In such a scenario, adding a root / leaf node pair back edge 802 might make another back edge 802 redundant.

[0106] To address the aforementioned possibilities, the mechanism disclosed herein for inserting synchronization primitives determines the optimal set of cyclically carrying synchronization primitives 112 by adding a minimum number of back edges 802, such that the cyclically carrying dependencies of all forward edges 404 in the dependency graph 206 are synchronized. In an embodiment, this is implemented by a greedy algorithm that identifies forward edges 404 in the cyclically carrying dependencies of the dependency graph 206 that are inherently synchronized and removes them from consideration. Then, back edges 802 are added around the root / leaf pairs until the cyclically carrying dependencies of all forward edges 404 are synchronized. All other root / leaf pairs (if any) are ignored.

[0107] The inherent synchronous circular carrying dependency relationship

[0108] As briefly discussed above, if forward edge 404 lies on the path between any two nodes 402 referencing the same work queue 106, then the cyclic carry dependencies for that edge 404 are inherently synchronized. Due to the FIFO nature of work queue 106, the top node 402 associated with work queue 106 cannot begin execution before the previous iteration of the bottom node 402 associated with the same work queue 106 has been completed. This results in the synchronization of all cyclic carry dependencies between two nodes 402 associated with the same work queue 106. This concept is further elaborated in... Figure 10 The diagram is shown in which back edge 802 is not needed because all forward edges 404 in the illustrated dependency graph 206 are between two nodes associated with work queue A or work queue B.

[0109] Optimal selection order of root / leaf pairs

[0110] In this embodiment, the greedy algorithm adds back edges 802 to the dependency graph 206 in an order identified by minimum flow tests and maximum profit tests, which determine around which root / leaf node pairs to add back edges 802. The minimum flow test prioritizes root / leaf node pairs with the smallest minimum flow. The minimum flow of a root / leaf node pair is the flow value of the edge with the minimum flow between that root and leaf. The flow value of an edge is the number of root / leaf node pairs around that edge in the cycle-dependent dependency graph 206. Figure 11 The diagram illustrates an example with a minimum flow pair of 1. The optimal solution for this example is to add a back edge 802F.

[0111] Maximum profit test

[0112] When there are more than one root / leaf node pair with the minimum flow, the maximum gain test is used. This test prioritizes root / leaf node pairs that have the most unsynchronized cyclically carrying dependencies.

[0113] Figure 12 The example fragment of the dependency graph shown illustrates the case where a back edge 802G is added in the previous step to synchronize all cyclically carrying dependencies between A and C. Only the two rightmost edges remain unsynchronized. In this scenario, the maximum benefit test ensures that the path between B and D with two unsynchronized edges is chosen, rather than the paths between A and D with only one unsynchronized edge and between B and C. A back edge 802H is added between B and D.

[0114] Figure 13 This is a flowchart illustrating aspects of a minimized set for adding back edges to dependency graph 206 according to an embodiment to enforce routine 1300 for any loop carrying dependencies. In one embodiment, routine 1300 is executed for each loop in IR program 204.

[0115] Routine 1300 begins with operation 1302, where compiler 200 determines the subgraph for the current loop. The subgraph is a graph consisting only of nodes 402 for commands 108 within the loop. Routine 1300 then proceeds from operation 1302 to operation 1304, where compiler 200 identifies all possible paths from the root node 402 of the loop subgraph to the leaf nodes 402 of the loop subgraph. Routine 1300 then proceeds from operation 1304 to operation 1306.

[0116] In operation 1306, compiler 200 computes an initial set of data and resource dependencies for the cyclic subgraph. In the embodiment, utilizing the above information... Figure 5 The described mechanism determines the initial set of dependencies for node 402 in the cyclic subgraph.

[0117] From operation 1306, routine 1300 proceeds to operation 1308, where compiler 200 identifies dependencies that are inherently synchronized across loop iterations and removes them from consideration. In an embodiment, a dependency is considered inherently synchronized if it lies on any path between two nodes 402 associated with the same command type 108 in the loop subgraph.

[0118] From operation 1308, routine 1300 proceeds to operation 1310, where compiler 200 selects the path with the smallest minimum flow from the paths identified in operation 1304. If multiple paths have the same smallest minimum flow (i.e., as mentioned above regarding...), ... Figure 11 The minimum flow test described above), then compiler 200 selects the path containing the most dependencies that have not yet been removed from consideration (i.e., the path mentioned above regarding...). Figure 12 (Description of the maximum benefit test).

[0119] Then, routine 1300 proceeds from operation 1310 to operation 1312, where compiler 200 adds a back edge 802 around the path selected in operation 1310 and removes other dependencies on that path from further consideration. Then, routine 1300 proceeds from operation 1312 to operation 1314, where compiler 200 repeats operations 1310 and 1312 until all dependencies have been removed from consideration, or until all paths identified in operation 1304 have been exhausted. From operation 1314, routine 1300 proceeds to operation 1316, where routine 1300 terminates.

[0120] Use dependency graphs to optimize the use of synchronization primitives.

[0121] Figure 14 This illustrates the use of the embodiment in relation to... Figures 4A to 13 The flowchart describes the process of creating a dependency graph 206 to allocate various aspects of the routine 1400 of the synchronization primitive 112. Figure 14 The mechanism shown and described below allows for the reuse of synchronization primitive 112, which in turn enables the execution of a larger input program 202 while remaining within the constraints of a finite pool of synchronization primitive 112, something that could not be achieved using previous solutions.

[0122] In relation to Figure 14 In the described embodiment, the dependency graph 206, created in the manner described above, is analyzed to determine the distribution of the synchronization primitive 112 optimized on edges 404 of the dependency graph 206. In this regard, it should be understood that other mechanisms for allocating resources using the dependency graph 206 can be utilized, such as, but not limited to, a modified banker's algorithm.

[0123] Routine 1400 begins at operation 1402, where compiler 200 assigns a maximum virtual synchronization primitive identifier (“ID”) of zero to each type of command 108 referenced by dependency graph 206. Routine 1400 then proceeds from operation 1402 to operation 1404, where compiler performs a breadth-first backward traversal of dependency graph 206, starting from node 402 corresponding to the last command 108 of input program 202.

[0124] During the traversal of input program 202, compiler 200 examines the edges 404 of each node 402 in operation 1406 and assigns a virtual synchronization primitive ID to each edge 404. The virtual synchronization primitive ID for each node 402 is taken from the other edge 404 reachable along any path starting from the initial edge. If not found, the virtual synchronization primitive ID used is the current virtual synchronization primitive ID assigned to that command type 108, and this maximum value is incremented in operation 1408.

[0125] In this embodiment, reachability from back edge 802 does not include edge 404 reachable from back edge 802. Additionally, when reusing the virtual synchronization primitive ID for edge 404 within a loop, only edge 404 with inherent synchronization as described above is considered. From operation 1408, routine 1400 proceeds to operation 1410, and routine 1400 ends at operation 1410.

[0126] Two-pass algorithm for creating dependency graph

[0127] In one embodiment, compiler 200 utilizes an efficient incremental algorithm to create dependency graph 206 with reused synchronization primitive 112 as described above. This algorithm is executed twice on IR program 204: forward pass (see below for details). Figure 15A (described) and backpropagation (below about) Figure 15B (As described). This enables the above functionality to be provided based on only two passes of the IR procedure 204 (i.e., forward and backward passes). Previous solutions required more than two passes, and therefore consumed more computational resources (e.g., CPU time, power, etc.) than the mechanism disclosed herein.

[0128] Figure 15A This is a flowchart illustrating various aspects of a routine 1500 for creating a forward pass of a two-pass algorithm dependent on Figure 206, according to an embodiment. Routine 1500 begins at operation 1502, where, during the forward pass of IR program 204, compiler 200 determines whether command 108 has been encountered. If so, routine 1500 proceeds from operation 1502 to operation 1504.

[0129] In operation 1504, compiler 200 creates a new node 402 in dependency graph 206 for the encountered command 108. Then, routine 1500 proceeds from operation 1504 to operation 1506, where compiler 200 determines the data and resource dependencies of the new node 402 relative to other previously created nodes 402 in the manner described above. Then, routine 1500 proceeds from operation 1506 to operation 1508, where the compiler adds artificially created queue dependencies to dependency graph 206 in the manner also described above. Then, routine 1500 proceeds from operation 1508 to operation 1510.

[0130] In operation 1510, compiler 200 computes backward dependency reachability information for the new current node 402. This backward dependency reachability information is used in conjunction with forward dependency reachability information to determine the edge 404 between the two nodes 402. If node 402 is part of a cycle, compiler 200 updates information about whether the current node 402 is a leaf node of the cycle's subgraph.

[0131] Then, routine 1500 proceeds from operation 1512 to operation 1514, where it is determined whether the forward pass of IR procedure 204 is complete. If the forward pass is complete, routine 1514 proceeds from operation 1514 to operation 1522, where routine 1514 ends. If the forward pass is not complete, routine 1500 proceeds from operation 1514 to operation 1516, as described below.

[0132] If, in operation 1502, compiler 200 determines that instruction 108 has not been encountered, then routine 1500 proceeds from operation 1502 to operation 1516. In operation 1516, compiler 200 determines whether a loop has been encountered in IR program 204. If no loop has been encountered, routine 1500 returns from operation 1516 to operation 1502, where the forward pass of IR program 204 continues.

[0133] If a loop is encountered in operation 1516, routine 1500 proceeds from operation 1516 to operation 1518, where compiler 200 propagates the information needed to determine resource dependencies related to overlapped memory allocation to the parent loop (if it exists). Then, routine 1500 proceeds from operation 1516 to operation 1520, where compiler 200 propagates information about the leaf nodes of the loop subgraph to the parent loop. Then, routine 1500 returns from operation 1520 to operation 1502, where the forward pass of IR program 204 continues.

[0134] Figure 15B This is a flowchart illustrating various aspects of routine 1550, which is used to create the backpass of the two-pass algorithm for dependency graph 206. Routine 1550 begins at operation 1552, where, during the backpass of IR program 204, compiler 200 determines whether command 108 has been encountered. If so, routine 1550 proceeds from operation 1552 to operation 1554.

[0135] In operation 1554, the compiler obtains the above information regarding... Figure 15A The node 402 corresponding to the command 108 encountered during the described forward pass is created. Then, routine 1550 proceeds to operation 1556, where compiler 200 calculates the forward dependency reachability for node 402 acquired in operation 1554. Then, routine 1550 proceeds from operation 1556 to operation 1558, where compiler 200 updates information about the inherent synchronization dependencies for the current loop. Then, routine 1550 proceeds from operation 1558 to operation 1560.

[0136] In operation 1560, if the current node 402 is part of a cycle, compiler 200 updates the information about whether the current node 402 is the root node of the subgraph of the cycle. Then, routine 1550 proceeds to operation 1562, where compiler 200 optimizes any dependencies as described above and constructs the forward edge 404 for node 402. Compiler 200 in operation 1564 updates the information about the current node 402 as described above. Figure 14 The description involves assigning virtual synchronization primitive IDs to all edges 404 of node 402. Then, routine 1550 proceeds from operation 1564 to operation 1566.

[0137] In operation 1566, compiler 200 determines whether the backpass of IR program 204 is complete. If the backpass is complete, routine 1550 proceeds from operation 1566 to operation 1576, and routine 1550 ends at operation 1576. However, if the backpass is not complete, routine 1550 proceeds from operation 1566 to operation 1568.

[0138] In operation 1568, compiler 200 determines whether a loop has been encountered in IR program 204. If no loop is encountered, routine 1550 returns to operation 1552, where the backward pass of IR program 204 continues as described above. However, if a loop is encountered in operation 1568, routine 1550 proceeds from operation 1568 to operation 1570.

[0139] In operation 1570, compiler 200 propagates information about the root node of the cyclic subgraph and information about inherent synchronization dependencies to the parent loop. Then, routine 1550 proceeds to operation 1572, where compiler 200 determines and optimizes the back edge 802 for the loop in the manner described above.

[0140] Routine 1550 proceeds from operation 1572 to operation 1574, where compiler 200 also assigns virtual synchronization primitive IDs to all back edges 802 of the loop in the manner described above. From operation 1574, routine 1550 returns to operation 1552, where the backward pass of IR program 204 continues in the manner described above.

[0141] Figure 16 This is a computer architecture diagram illustrating the illustrative computer hardware and software architecture of a processing system 1600 for implementing the various techniques presented herein, as shown in the embodiments. Specifically, in the embodiments, Figure 16 The illustrated architecture is used to implement aspects of a computing system capable of providing the functionality disclosed herein for effectively utilizing the synchronization primitive 112 in a multiprocessor computing system 100. For example, but not limited to, the processing system 1600 can be used to execute a compiler 200 that implements the aspects described above.

[0142] In an embodiment, Figure 16 The illustrated processing system 1600 includes a central processing unit 1602 (“CPU”), system memory 1604 (including random access memory 1606 (“RAM”) and read-only memory (“ROM”) 1608), and a system bus 1610 coupling the system memory 1604 to the CPU 1602. In embodiments, firmware includes basic routines (such as those during startup) that facilitate the transfer of information between components within the processing system 1600. Figure 16 (Not shown) is stored in ROM 1608.

[0143] In embodiments, the processing system 1600 also includes a mass storage device 1612 for storing the operating system 1622, applications (such as compiler 200), and other types of programs (some of which have been described herein). In embodiments, the mass storage device 1612 is also configured to store other types of programs and data.

[0144] In one embodiment, the mass storage device 1612 is connected to a mass storage controller (connected to bus 1610). Figure 16 (Not shown) is connected to CPU 1602. Mass storage device 1612 and its associated computer-readable media provide non-volatile storage for processing system 1600. Although the description of computer-readable media contained herein refers to mass storage devices such as hard disks, optical disc read-only memory (“CD-ROM”) drives, digital versatile optical disc read-only memory (“DVD-ROM”) drives, or Universal Serial Bus (“USB”) storage keys, computer-readable media are any available computer-readable storage or communication media accessible to processing system 1600.

[0145] Communication media include computer-readable instructions, data structures, program modules, or other data in modulated data signals (such as carrier waves or other transmission mechanisms), and include any delivery medium. The term "modulated data signal" means a signal whose characteristics are set or altered in a manner that encodes information in the signal. As examples, communication media include wired media (such as wired networks or direct wired connections) and wireless media (such as acoustic, radio frequency, infrared, and other wireless media). Any combination of the above is also included within the scope of computer-readable media.

[0146] In embodiments, as an example, a computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. For example, a computer-readable storage medium includes RAM, ROM, erasable programmable ROM (“EPROM”), electrical EPROM (“EEPROM”), flash memory or other solid-state memory technologies, CD-ROM, DVD-ROM, HD-DVD, BLU-RAY® or other optical storage devices, magnetic tape cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that stores desired information and is accessible to the processing system 1600. For the purposes of the claims, the phrase “computer-readable storage medium” and its variations do not include waves or signals themselves, nor do they include communication media.

[0147] Depending on the configuration, the processing system 1600 operates in a networked environment using a logical connection to the remote computer 1614 via a network (such as network 1620). In one embodiment, the processing system 1600 is connected to network 1620 via a network interface unit 1616 connected to bus 1610. In another embodiment, the network interface unit 1616 is used to connect to other types of networks and remote computer systems.

[0148] In an embodiment, the processing system 1600 further includes an input / output controller 1618 for inputting data from many other devices (including keyboards, mice, touch input, electronic styluses, etc.). Figure 16 (As shown in the image) or physical sensor 1624 (such as a camera) receives and processes input. Similarly, in embodiments, the input / output controller 1618 sends input to a display screen or other type of output device (also not shown in the image). Figure 16 (As shown in the image) provides the output.

[0149] When the software components described herein are loaded into and executed, they transform the CPU 1602 and the entire processing system 1600 from a general-purpose computing device into a dedicated processing system tailored to facilitate the functions presented herein. In embodiments, the CPU 1602 is composed of transistors or other discrete circuit elements, which individually or collectively present any number of states.

[0150] More specifically, in an embodiment, CPU 1602 operates as a finite state machine in response to executable instructions contained within the software modules disclosed herein. These computer-executable instructions transform CPU 1602 by specifying how CPU 1602 transitions between states, thereby transforming the transistors or other discrete hardware elements constituting CPU 1602.

[0151] In embodiments, the software modules presented herein also transform the physical structure of the computer-readable medium presented herein. The specific transformation of the physical structure depends on various factors in different implementations of this specification. Examples of these factors include the technology used to implement the computer-readable medium, whether the computer-readable medium is characterized as a primary storage device or a secondary storage device, etc.

[0152] For example, in an embodiment, if the computer-readable medium is implemented as a semiconductor-based memory, the software disclosed herein is encoded on the computer-readable medium by transforming the physical state of the semiconductor memory. For example, in an embodiment, the software transforms the state of transistors, capacitors, or other discrete circuit elements constituting the semiconductor memory. In an embodiment, the software transforms the physical state of these components in order to store data thereon.

[0153] As another example, in embodiments, the computer-readable medium disclosed herein is implemented using magnetic or optical techniques. In such implementations, when software is encoded therein, program components presented herein transform the physical state of the magnetic or optical medium. In embodiments, these transformations include altering the magnetic properties of specific locations within a given magnetic medium. In embodiments, these transformations also include altering the physical characteristics or properties of specific locations within a given optical medium to change the optical properties of those locations. Transformations of other physical media are possible without departing from the scope and spirit of this specification; the foregoing examples are provided merely to facilitate the discussion.

[0154] It should be understood that Figure 16 The architecture or similar architecture shown for processing system 1600 is suitable for implementing other types of computing devices, including handheld computers, video game devices, embedded computer systems, mobile devices (such as smartphones and tablets), augmented reality (“AR”), mixed reality (“MR”), and virtual reality (“VR”) devices, as well as other types of computing devices known to those skilled in the art. According to embodiments, processing system 1600 may also not include... Figure 16 All components shown, including Figure 16 Other components not explicitly shown in the document, or those utilizing [the following]. Figure 16 The architecture shown is completely different.

[0155] Figure 17 This is a network diagram illustrating a distributed network computing environment 1700 in which various aspects of the disclosed technology are implemented according to the various embodiments presented herein. Figure 17As shown, one or more server computers 1700A are interconnected with a number of client computing devices (such as tablet computers 1700B, game consoles 1700C, smartwatches 1700D, phones 1700E (such as smartphones), personal computers 1700F, and AR / VR devices 1700G) via a network 1620 (which can be any or a combination of the following: fixed or WLAN, wide area network (“WAN”), intranet, extranet, peer-to-peer network, VPN, Internet, Bluetooth® communication network, proprietary low voltage communication network, or other communication network).

[0156] In a network environment where network 1620 is the Internet, for example, server computer 1700A is a dedicated server computer operable to transmit data to or from client computing devices 1700B to 1700G via any of a number of known protocols such as Hypertext Transfer Protocol (“HTTP”), File Transfer Protocol (“FTP”), or Simple Object Access Protocol (“SOAP”).

[0157] Additionally, in embodiments, the network computing environment 1700 utilizes various data security protocols, such as Secure Sockets Layer (“SSL”) or Good Privacy (“PGP”). In embodiments, each client computing device in client computing devices 1700B through 1700G is equipped with an OS (such as OS 1622) operable to support one or more computing applications or terminal sessions, such as a web browser ( Figure 17 (not shown in the image), Graphical UI ( Figure 17 (not shown in the image), or mobile desktop environment ( Figure 17 (not shown in the image) to gain access to the server computer 1700A.

[0158] In this embodiment, the server computer 1700A is communicatively coupled to other computing environments ( Figure 17 (not shown in the image), and receives data about the interactions of the participating users. In illustrative operations, the user ( Figure 17 (Not shown) Interacts with computing applications running on client computing devices 1700B to 1700G to obtain desired data and / or perform other computing applications.

[0159] In this embodiment, data and / or computing applications are stored on server 1700A and communicated to collaborating users via network 1620 through client computing devices 1700B to 1700G. Participating users ( Figure 17(Not shown) A request is made to access specific data and applications, all or part of which are hosted on server computer 1700A. In one embodiment, this data is transferred between client computing devices 1700B-1700G and server computer 1700A for processing and storage.

[0160] In this embodiment, server computer 1700A hosts applications such as those described above. Figures 1 to 1 The computational applications, processes, and applets described in 5, which generate, authenticate, encrypt, and communicate data and applications, and are used in conjunction with other server computing environments ( Figure 17 (not shown in the image), third-party service providers ( Figure 17 (not shown in the image) as well as Network Attached Storage (“NAS”) and Storage Area Network (“SAN”) (also not shown in the image) Figure 17 (As shown in the image) Collaboration to achieve application / data transactions.

[0161] Figure 16 The computing architecture shown and Figure 17 The distributed network computing environment illustrated has been simplified for ease of discussion. In the embodiments, the computing architecture and distributed computing network include and utilize more computing components, devices, software programs, network devices, and other components than specifically described herein. Those skilled in the art will also understand that the subject matter described herein can be interpreted differently. Figure 16 and Figure 17 Other computer system configurations shown are to be practiced, including handheld devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, computing or processing systems embedded in devices such as wearable computing devices, automobiles, home automation, etc., minicomputers, mainframes, etc.

[0162] To further understand, the operations of the routines and methods disclosed herein are not presented in any particular order, and it is possible and contemplated to perform some or all of the operations in an alternative order. For ease of description and illustration, the operations have been presented in the order shown. Operations may be added, omitted, and / or performed concurrently without departing from the scope of the appended claims. The illustrated routines and methods may end at any time and do not need to be fully performed.

[0163] In embodiments, some or all of the operations and / or substantially equivalent operations in the method are performed by execution of computer-readable instructions contained on a computer-readable storage medium (as defined herein). The term "computer-readable instructions" and variations thereof are used extensively herein to include routines, applications, application modules, program modules, programs, program components, data structures, algorithms, etc. Computer-readable instructions are implemented on a variety of system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, personal computers, handheld computing devices, microprocessor-based programmable consumer electronics, combinations thereof, etc.

[0164] According to embodiments, the logical operations described herein are implemented as (1) a sequence of computer-implemented actions or program modules running on a computing system, and / or (2) interconnected machine logic circuits or circuit modules within the computing system. This implementation is a matter of choice depending on the performance and other requirements of the computing system. Therefore, the logical operations described herein are referred to as states, operations, structural devices, actions, or modules. According to embodiments, these operations, structural devices, actions, and modules are implemented in software, firmware, dedicated digital logic, and any combination thereof.

[0165] For example, operations illustrated in sequence diagrams and flowcharts and described herein are implemented, at least in part, by modules that implement the features disclosed herein, such as dynamic link libraries (“DLLs”), static link libraries, functions provided by APIs, network services, compilers, interpreters, scripts, or any other set of executable instructions. In embodiments, data is stored in data structures within one or more memory components. In embodiments, data is retrieved from data structures by addressing links or references to the data structures.

[0166] The methods and routines described herein can also be implemented in many other ways. In embodiments, for example, the routines and methods are implemented at least in part by the processor or local circuitry of another remote computer. Furthermore, in embodiments, one or more operations in the routines or methods are alternatively or additionally implemented at least in part by a chipset that works alone or in combination with other software modules.

[0167] The disclosure presented herein also covers the topics set forth in the following clauses:

[0168] Clause 1. A computer-implemented method comprising: minimizing edges in a dependency graph for functions in an input program, the dependency graph including nodes corresponding to commands in the functions and edges corresponding to dependencies between the nodes; adding a minimized set of back edges to the dependency graph to enforce cyclic resource dependencies in the input program; and, based on the dependency graph, assigning synchronization primitives provided by a multiprocessor computing system to the commands in the functions of the input program.

[0169] Clause 2. The computer-implemented method according to Clause 1, wherein the dependencies between the nodes are identified using shared queue analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

[0170] Clause 3. A computer-implemented method according to any one of Clauses 1 or 2, wherein the dependencies between the nodes are identified using input / output analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

[0171] Clause 4. A computer-implemented method according to any one of Clauses 1 to 3, wherein the dependencies between the nodes are identified using allocation overlap analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range and the second node corresponding to a second command using all or part of the memory address range.

[0172] Clause 5. A computer-implemented method according to any one of Clauses 1 to 4, wherein minimizing the edges in the dependency graph corresponding to the dependencies between the nodes comprises: performing forward reachability analysis on the dependency graph to eliminate one or more dependencies; and adding edges to the dependency graph for dependencies other than artificial dependencies that remain after the forward reachability analysis.

[0173] Clause 6. A computer-implemented method according to any one of Clauses 1 to 5, wherein the minimized set of back edges comprises: a first back edge from a leaf node in a dependency graph for a cycle to a first root node in the dependency graph for the cycle, and a second back edge from the leaf node to a second root node in the dependency graph for the cycle.

[0174] Clause 7. A computer-implemented method according to any one of Clauses 1 to 6, wherein the synchronization primitives provided by a multiprocessor computing system include semaphores.

[0175] Clause 8. A computer-readable storage medium storing computer-executable instructions that, when executed by a processing system, cause the processing system to: create a dependency graph for functions in an input program, the dependency graph including nodes corresponding to commands in the functions and edges corresponding to dependencies between the nodes; remove at least one edge from the dependency graph; add at least one back edge to the dependency graph to enforce circular resource dependencies in the input program; and, based on the dependency graph, assign synchronization primitives provided by a multiprocessor computing system to the commands in the functions of the input program.

[0176] Clause 9. The computer-readable storage medium according to Clause 8, wherein the dependencies between the nodes are identified using a shared queue analysis that creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

[0177] Clause 10. A computer-readable storage medium according to any one of Clauses 8 or 9, wherein the dependencies between the nodes are identified using input / output analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

[0178] Clause 11. A computer-readable storage medium according to any one of Clauses 8 to 10, wherein the dependencies between the nodes are identified using allocation overlap analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range and the second node corresponding to a second command using all or part of the memory address range.

[0179] Clause 12. A computer-readable storage medium according to any one of Clauses 8 to 11, wherein eliminating at least one edge from the dependency graph comprises: performing forward reachability analysis on the dependency graph to eliminate one or more dependencies; and adding an edge to the dependency graph for dependencies other than artificial dependencies that remain after the forward reachability analysis.

[0180] Clause 13. A computer-readable storage medium according to any one of Clauses 8 to 12, wherein the at least one back edge comprises a back edge from a leaf node to the root node in the dependency graph.

[0181] Clause 14. A computer-readable storage medium according to any one of Clauses 8 to 13, wherein the synchronization primitive provided by a multiprocessor computing system includes a semaphore.

[0182] Clause 15. A processing system comprising: a processor; and a computer-readable storage medium storing computer-executable instructions, which, when executed by the processing system, cause the processing system to: create a dependency graph for functions in an input program, the dependency graph including nodes corresponding to commands in the functions and edges corresponding to dependencies between the nodes; remove at least one edge from the dependency graph; add at least one back edge to the dependency graph to enforce circular resource dependencies in the input program; and, based on the dependency graph, assign synchronization primitives provided by a multiprocessor computing system to the commands in the functions of the input program.

[0183] Clause 16. The processing system according to Clause 15, wherein the dependencies between the nodes are identified using shared queue analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

[0184] Clause 17. The processing system according to any one of Clauses 15 or 16, wherein the dependencies between the nodes are identified using input / output analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

[0185] Clause 18. A processing system according to any one of Clauses 15 to 17, wherein the dependencies between the nodes are identified using allocation overlap analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range and the second node corresponding to a second command using all or part of the memory address range.

[0186] Clause 19. A processing system according to any one of Clauses 15 to 18, wherein eliminating at least one edge from the dependency graph comprises: performing forward reachability analysis on the dependency graph to eliminate one or more dependencies; and adding edges to the dependency graph for dependencies other than artificial dependencies that remain after the forward reachability analysis.

[0187] Clause 20. The processing system according to any one of Clauses 15 to 19, wherein the at least one back edge comprises a back edge from a leaf node to the root node in the dependency graph.

[0188] This document discloses techniques for efficiently utilizing synchronization primitive 112 in a multiprocessor computing system 100. Although the subject matter presented herein is described in language specific to computer architecture features, methods and transformative actions, particular computing machinery, and computer-readable media, it should be understood that the subject matter set forth in the appended claims is not limited to the specific features, actions, or media described herein. Rather, the specific features, actions, and media are disclosed as exemplary forms of implementing the claimed subject matter.

[0189] The foregoing subject matter is provided for illustrative purposes only and should not be construed as limiting. Various modifications and changes may be made to the subject matter described herein without departing from the scope of this disclosure, which is set forth in the following claims, without following the example configurations and applications described and illustrated.

Claims

1. A computer-implemented method, comprising: Minimize the edges (404) in the dependency graph (206) for functions in the input program (202), the dependency graph (206) including nodes (402) corresponding to commands (108) in the function and edges (404) corresponding to dependencies between the nodes (402). Add a minimized set of back edges (802) to the dependency graph (206) to enforce the cyclic resource dependencies in the input procedure (202); as well as Based on the dependency graph (206), the synchronization primitive (112) provided by the multiprocessor computing system (100) is assigned to the command (108) in the function of the input program (202).

2. The computer-implemented method of claim 1, wherein the dependencies between the nodes are identified using shared queue analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

3. The computer-implemented method of claim 1, wherein the dependencies between the nodes are identified using input / output analysis, the input / output analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

4. The computer-implemented method of claim 1, wherein the dependencies between the nodes are identified using allocation overlap analysis, the allocation overlap analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range, and the second node corresponding to a second command using all or part of the memory address range.

5. The computer-implemented method of claim 1, wherein minimizing the edges in the dependency graph corresponding to the dependencies between the nodes comprises: Perform forward reachability analysis on the dependency graph to eliminate one or more dependencies; as well as For dependencies that are retained after the forward reachability analysis, other than manually assigned dependencies, add edges to the dependency graph.

6. The computer-implemented method of claim 1, wherein the minimized set of back edges comprises: A first back edge from a leaf node in the dependency graph for the cycle to a first root node in the dependency graph for the cycle, and a second back edge from the leaf node to a second root node in the dependency graph for the cycle.

7. The computer-implemented method of claim 1, wherein the synchronization primitive provided by the multiprocessor computing system includes a semaphore.

8. A computer-readable storage medium (1612) storing computer-executable instructions that, when executed by a processing system (1600), cause the processing system (1600) to: Create a dependency graph (206) for functions in the input program (202), the dependency graph (206) including nodes (402) corresponding to commands (108) in the functions and edges (404) corresponding to dependencies between the nodes (402). Eliminate at least one edge from the edges (404) in the dependency graph (206); Add at least one back edge (802) to the dependency graph (206) to enforce the circular resource dependencies in the input procedure (202); and Based on the dependency graph (206), the synchronization primitive (112) provided by the multiprocessor computing system (100) is assigned to the command (108) in the function of the input program (202).

9. The computer-readable storage medium of claim 8, wherein the dependencies between the nodes are identified using shared queue analysis, the shared queue analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

10. The computer-readable storage medium of claim 8, wherein the dependencies between the nodes are identified using input / output analysis, the input / output analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

11. The computer-readable storage medium of claim 8, wherein the dependencies between the nodes are identified using allocation overlap analysis, the allocation overlap analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range, and the second node corresponding to a second command using all or part of the memory address range.

12. The computer-readable storage medium of claim 8, wherein eliminating at least one edge from the dependency graph comprises: Perform forward reachability analysis on the dependency graph to eliminate one or more dependencies; as well as For dependencies that are retained after the forward reachability analysis, other than manually assigned dependencies, add edges to the dependency graph.

13. The computer-readable storage medium of claim 8, wherein the at least one back edge comprises a back edge from a leaf node to the root node in the dependency graph.

14. The computer-readable storage medium of claim 8, wherein the synchronization primitive provided by the multiprocessor computing system includes a semaphore.

15. A processing system (1600), comprising: Processor (1602); as well as A computer-readable storage medium (1612) storing computer-executable instructions that, when executed by the processing system (1600), cause the processing system (1600) to: Create a dependency graph (206) for functions in the input program (202), the dependency graph (206) including nodes (402) corresponding to commands (108) in the functions and edges (404) corresponding to dependencies between the nodes (402). Eliminate at least one edge from the edges (404) in the dependency graph (206); Add at least one back edge (802) to the dependency graph (206) to enforce the circular resource dependencies in the input program (202); as well as Based on the dependency graph (206), the synchronization primitive (112) provided by the multiprocessor computing system (100) is assigned to the command (108) in the function of the input program (202).

16. The processing system of claim 15, wherein the dependencies between the nodes are identified using shared queue analysis, which creates an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command and the second node corresponding to a second command, the first command and the second command having the same command type.

17. The processing system of claim 15, wherein the dependencies between the nodes are identified using input / output analysis, the input / output analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a buffer and the second node corresponding to a second command using the buffer.

18. The processing system of claim 15, wherein the dependencies between the nodes are identified using allocation overlap analysis, the allocation overlap analysis creating an edge between a first node and a second node in the dependency graph, the first node corresponding to a first command using a memory address range, and the second node corresponding to a second command using all or part of the memory address range.

19. The processing system of claim 15, wherein eliminating at least one edge from the dependency graph comprises: Perform forward reachability analysis on the dependency graph to eliminate one or more dependencies; as well as For dependencies that are retained after the forward reachability analysis, other than manually assigned dependencies, add edges to the dependency graph.

20. The processing system of claim 15, wherein the at least one back edge comprises a back edge from a leaf node to the root node in the dependency graph.

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