A method and system for fast response to interrupts in embedded system code
By storing critical data and interrupt vector tables in a high-speed storage area and employing a priority sorting mechanism, the problem of slow interrupt response in embedded systems is solved, enabling fast interrupt response and efficient multi-interrupt request processing, thereby improving system stability and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 联想长风科技(北京)有限公司
- Filing Date
- 2026-03-06
- Publication Date
- 2026-06-05
AI Technical Summary
Existing embedded systems rely on slow storage media to store critical data and interrupt vector tables, resulting in slow interrupt response speeds and a lack of effective priority sorting mechanisms. This makes it impossible to efficiently handle multiple interrupt requests, affecting stability and performance in environments with high real-time requirements.
Critical data and interrupt vector tables are stored in high-speed storage areas, and a priority sorting mechanism is used to optimize the interrupt handling process. By configuring the first and second storage areas, the VTOR register is used to locate the copy of the interrupt vector table from the high-speed storage area to achieve fast response.
It improves interrupt response speed and multi-interrupt request handling capabilities, enhancing system stability and performance in environments with high real-time requirements.
Smart Images
Figure CN122152468A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of code interruption response technology, and in particular to a fast interruption response method and system for embedded system code. Background Technology
[0002] As embedded systems are widely used in applications with high real-time requirements, increasingly stringent demands are being placed on the speed and accuracy of interrupt responses. Interrupts, as a mechanism to interrupt the execution of the current program and respond to external events, are a crucial means of achieving real-time processing in embedded systems. To ensure a rapid response to external interrupt signals, many embedded systems employ a memory block partitioning design, storing critical code and data in high-speed memory areas for quick access upon interrupt triggering.
[0003] Currently, existing embedded systems typically store all program data in Flash memory. While this ensures data persistence and stability, Flash memory access speed is relatively slow, especially when faced with multiple interrupt requests. Traditional storage solutions often cannot provide sufficient access speed, causing delays in locating the interrupt vector table and executing interrupt service routines. Furthermore, the priority handling mechanism for system interrupt requests is insufficient in traditional solutions, failing to effectively prioritize interrupt requests. This results in high-priority interrupt handling tasks not being executed in a timely manner, directly impacting the overall system responsiveness.
[0004] In summary, existing technologies suffer from technical problems such as slow interrupt response speed due to reliance on slow storage media to store critical data and interrupt vector tables, and the lack of an effective priority sorting mechanism. This results in inefficient handling of multiple interrupt requests and further affects stability and performance in environments with high real-time requirements. Summary of the Invention
[0005] The purpose of this application is to provide a fast interrupt response method and system for embedded system code, in order to solve the technical problems in the prior art that rely on slow storage media to store critical data and interrupt vector tables and lack an effective priority sorting mechanism, resulting in slow interrupt response speed, inability to efficiently handle multiple interrupt requests, and further affecting the stability and performance in environments with high real-time requirements.
[0006] In view of the above problems, this application provides a fast interrupt response method and system for embedded system code.
[0007] In a first aspect, this application provides a fast interrupt response method for embedded system code, implemented through a fast interrupt response system for embedded system code, comprising: configuring a first storage region and a second storage region, wherein the response speed of the first storage region is less than that of the second storage region; reading the original data storage block of the first storage region, and copying the data in the original data storage block of the first storage region into the replica data storage block of the second storage region through initialization code; wherein, when the CPU core issues an interrupt access request, the interrupt vector table replica is located and accessed from the replica data storage block of the second storage region through the VTOR register.
[0008] Preferably, the method for fast interrupt response of embedded system code further includes: the original data storage block of the first storage area includes an original interrupt vector table and a key code segment; the copy data storage block of the second storage area includes a copy of the interrupt vector table and a copy of the key code segment written based on the copy of the initialization code; after locating the interrupt vector table from the copy data storage block of the second storage area, the data of the interrupt vector table copy is accessed by executing the copy of the key code segment.
[0009] Preferably, the method for rapid interrupt response of embedded system code further includes: the replica data storage block of the second storage area further includes a standard data segment, the standard data segment including a copy data segment and a zeroing data segment; after initializing the standard data segment, the data in the original data storage block of the first storage area is copied and written into the replica data storage block of the second storage area.
[0010] Preferably, the method for fast interrupt response of embedded system code further includes: the first storage area is a Flash area, and the second storage area is a RAM area.
[0011] Preferably, the method for rapid interrupt response of embedded system code further includes: assigning at least one target function to the initialization code through segment attribute tags; and copying data from the original data storage block of the first storage area to the replica data storage block of the second storage area through the initialization code.
[0012] Preferably, the method for rapid interrupt response of embedded system code further includes: the original data storage block of the first storage area further includes ordinary code segments and constant data segments.
[0013] Preferably, the method for rapid interruption response of embedded system code further includes: performing hash digest calculation on the key code segment of the first storage area to obtain hash digest data; performing integrity verification based on the hash digest data and the pre-stored digital signature; and executing the copy writing process after the verification is passed.
[0014] Preferably, the method for rapid interrupt response of embedded system code further includes: if there are multiple interrupt access requests, obtaining a request sorting queue according to priority identifiers; the VTOR register, according to the request sorting queue, locating the interrupt vector table copy from the copy data storage block of the second storage area and executing it in priority order.
[0015] Secondly, this application also provides an interrupt fast response system for embedded system code, used to execute an interrupt fast response method for embedded system code as described in the first aspect, comprising: a storage area configuration module for configuring a first storage area and a second storage area, wherein the response speed of the first storage area is less than that of the second storage area; and a data copy module for reading the original data storage block of the first storage area and copying the data in the original data storage block of the first storage area to the copy data storage block of the second storage area through initialization code; wherein, when the CPU core issues an interrupt access request, the interrupt vector table copy is located and accessed from the copy data storage block of the second storage area through the VTOR register.
[0016] The technical solution provided in this application has at least the following technical effects or advantages: by achieving the technical goal of storing key data and interrupt vector tables in a high-speed storage area and optimizing the interrupt handling process using a priority sorting mechanism, the system's stability and performance in environments with high real-time requirements are improved by increasing interrupt response speed and multi-interrupt request processing capability.
[0017] The above description is merely an overview of the technical solution of this application. To enable a clearer understanding of the technical means of this application and to facilitate its implementation according to the description, and to make the above and other objects, features, and advantages of this application more apparent, specific embodiments of this application are described below. It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent through the following description. Attached Figure Description
[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0019] Figure 1 This application presents a block diagram of system memory mapping and code movement for an embedded system code interrupt fast response system.
[0020] Figure 2 This application presents a flowchart of a key code RAM operation method for an embedded system code interrupt fast response system.
[0021] Figure 3 This is a comparative block diagram showing the optimization of interrupt response paths in an embedded system code interrupt fast response system according to this application.
[0022] Figure 4 This is a schematic diagram of the structure of an embedded system code interrupt fast response system according to this application.
[0023] Explanation of reference numerals in the attached diagram: Storage area configuration module 1, data copy module 2. Detailed Implementation
[0024] This application provides a fast interrupt response method and system for embedded system code, solving the technical problems in existing technologies where reliance on slow storage media for critical data and interrupt vector tables, coupled with a lack of effective priority sorting mechanisms, leads to slow interrupt response speeds, inefficient handling of multiple interrupt requests, and further impacts stability and performance in high real-time environments. The method achieves the technical goal of storing critical data and interrupt vector tables in high-speed storage areas and optimizing the interrupt handling process using a priority sorting mechanism, thereby improving interrupt response speed and multi-interrupt request handling capabilities, and ultimately enhancing the system's stability and performance in high real-time environments.
[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. It should be understood that this application is not limited to the exemplary embodiments described herein. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application. It should also be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all of them.
[0026] Example 1, please refer to Figure 1 , Figure 2 and Figure 3 This application provides a fast interrupt response method for embedded system code, applied to a fast interrupt response system for embedded system code, specifically including the following steps:
[0027] Configure a first storage region and a second storage region, wherein the response speed of the first storage region is less than that of the second storage region.
[0028] Specifically, in embedded systems, a storage area refers to a physical or logical storage unit used to store program code, data, and interrupt vector tables. The first and second storage areas correspond to two different types of storage units with varying performance. The slower response speed of the first storage area compared to the second means that the first storage area is suitable for storing large amounts of data or infrequently accessed data, while the second storage area is suitable for storing critical data or interrupt vector tables that require fast access, ensuring a rapid system response when an interrupt is triggered. The first storage area can be a Flash area, used to store the original image of all code and data, and may include: ordinary code segments (.text), constant data segments (.rodata), the original interrupt vector table (.isr_vector), and the storage image (LMA) of critical code segments (.ram_code). The second storage area can be a RAM area, the program execution space, and may contain: a copy of the interrupt vector table (.isr_vector_ram), a copy of the critical code segment (.ram_code VMA), and standard data segments (.data, .bss). By configuring two storage regions, critical data in the first storage region can be copied to the second storage region during the system initialization phase. The high-speed access characteristics of the second storage region can be used to provide interrupt handling and fast execution of critical functions, thereby improving the performance of the embedded system in high real-time scenarios.
[0029] Read the original data storage block of the first storage area, and copy the data in the original data storage block of the first storage area to the replica data storage block of the second storage area through initialization code.
[0030] Specifically, in embedded systems, the raw data storage block refers to the logical or physical storage unit in the first storage area containing, for example, program code, constant data, critical code segments, and interrupt vector tables. Its content constitutes the basic data required for system initialization and operation. Reading the raw data storage block involves sequentially accessing storage units from the first storage area, loading the stored program code, data, and interrupt vector table content into a processor-recognizable buffer or temporary register, providing a data source for subsequent copy operations. The copy data storage block refers to the logical or physical unit in the second storage area specifically used to store a high-speed copy of the data from the first storage area. By copying data from the raw data storage block into the copy data storage block through initialization code, the required data can be directly accessed from the high-speed storage area when an interrupt is triggered, improving interrupt response speed and execution efficiency. For example, the interrupt vector table (.isr_vector) and critical code segments (.ram_code) can be copied from the LMA in the Flash area to the corresponding VMA in the RAM area through initialization code.
[0031] Specifically, when the CPU core issues an interrupt access request, it locates and accesses the copy of the interrupt vector table from the copy data storage block of the second storage area through the VTOR register.
[0032] Specifically, the CPU core refers to the central processing unit in an embedded system that executes instructions and controls the operation of peripherals. Its functions include instruction decoding, arithmetic operations, data access, and interrupt response management, used to implement overall system logic control and task scheduling. An interrupt access request is a request issued by the CPU core to the system when it detects an external event or internal conditions that meet the interrupt triggering requirements. This request is used to suspend the current program execution and transfer the interrupt service routine to handle urgent tasks. The VTOR register is the vector table offset register. By storing the starting address of the interrupt vector table, it enables the CPU core to quickly locate the interrupt vector table, allowing the system to jump to the corresponding interrupt service routine based on the interrupt type. The copy data storage block is located in the second storage area and is used to store the interrupt vector table and critical code segments copied from the first storage area. By accessing the copy of the interrupt vector table in the copy data storage block, the CPU core can obtain the interrupt service entry address at high speed when an interrupt is triggered, thereby achieving fast interrupt response.
[0033] Furthermore, this application also includes: the original data storage block of the first storage area includes an original interrupt vector table and a key code segment; the replica data storage block of the second storage area includes a copy of the interrupt vector table and a copy of the key code segment written based on the copy of the initialization code; after locating the interrupt vector table from the replica data storage block of the second storage area, the data of the interrupt vector table copy is accessed by executing the copy of the key code segment.
[0034] Specifically, the raw data storage block of the first storage area refers to the basic program and data set set in a low-response-speed storage medium. The raw data storage block includes the raw interrupt vector table (.isr vector) and the critical code segment (.ram code). The raw interrupt vector table is used to record the service entry address corresponding to various interrupts, and the critical code segment is used to carry the core instruction logic that needs to be executed in high real-time during interrupt handling.
[0035] The replica data storage block of the second storage area refers to the data set set in a high-response-speed storage medium. The replica data storage block includes an interrupt vector table copy (.isr_vector_ram) and a critical code segment copy (.ram_code VMA) copied and written from the first storage area through initialization code. The initialization code is used to complete the data consistency copy during the system startup or reset phase to ensure the logical correspondence between the replica data and the original data.
[0036] After the data copy is completed, when the system needs to handle interrupt transactions, it locates the interrupt vector table copy from the copy data storage block of the second storage area, and obtains the entry information of the corresponding interrupt service routine through the interrupt vector table copy, thereby avoiding the delay caused by accessing the low-response-speed storage area and enabling the interrupt response to reach the theoretical fastest speed.
[0037] After locating the interrupt vector table copy, the data in the interrupt vector table copy is accessed by executing the critical code segment copy in the second storage area. The critical code segment copy is used to perform necessary scheduling, jump, and control operations in the interrupt context to ensure the speed and determinism of the interrupt service flow.
[0038] Furthermore, this application also includes: the replica data storage block of the second storage area further includes a standard data segment, the standard data segment including a copy data segment and a zeroing data segment; after initializing the standard data segment, the data in the original data storage block of the first storage area is copied and written into the replica data storage block of the second storage area.
[0039] Specifically, the replica data storage block of the second storage area refers to a logical storage set set in a high-speed storage medium, used to carry the data required for operation migrated from the low-speed storage area. The standard data segment (.data, .bss) is an important part of the replica data storage block and is used to support data initialization and state maintenance during program operation.
[0040] The standard data segment refers to the data area divided according to the embedded system program linking and loading rules. The standard data segment includes the copy data segment and the clear data segment. The copy data segment is used to store initialized global variables or static variables that need to be copied from the first storage area to the running storage area during the system startup phase. The clear data segment is used to store uninitialized global variables or static variables that need to be cleared uniformly during the system startup phase.
[0041] During system startup or reset, the standard data segment is initialized. The initialization operation includes loading the data corresponding to the copied data segment from the preset storage location to the second storage area, and performing zeroing processing on the storage space corresponding to the zeroed data segment, thereby establishing an initial data state that meets the requirements of program operation.
[0042] After the standard data segment initialization is completed, the data in the original data storage block of the first storage area is copied to the replica data storage block of the second storage area. The copying process includes the overall copying of the interrupt vector table, critical code segments and other necessary program data to ensure that the contents of the replica data storage block are consistent with the original data in terms of logical function.
[0043] Furthermore, this application also includes: the first storage area is a Flash area, and the second storage area is a RAM area.
[0044] Specifically, the first storage area is defined as the Flash area, which refers to non-volatile storage media used to store program code, interrupt vector tables, and constant data for a long time under power failure conditions. It has the characteristics of strong data retention capability, large storage capacity, but relatively high access latency, and is suitable for storing system-fixed programs and basic data.
[0045] The second storage area is defined as the RAM area. The RAM area refers to volatile storage media, which is used to provide high-speed read and write capabilities during system power-on operation. It has the characteristics of low access latency and high data throughput, but the data cannot be retained after power failure. It is suitable for storing program code and data copies that require frequent access or have high real-time requirements.
[0046] Furthermore, this application also includes: specifying at least one objective function to the initialization code through segment attribute tags; and copying data from the original data storage block of the first storage region to the replica data storage block of the second storage region through the initialization code.
[0047] Specifically, segment attribute tags refer to the attribute description information set for functions or code segments during the program compilation or linking stage. They are used to indicate the execution affiliation of the target function during the system startup or initialization stage. Here, the target function is the main function. Through segment attribute tags, at least one target function can be associated with the initialization code, so that the target function can be uniformly scheduled and executed in the system initialization process, thereby realizing centralized management and control of specific code segments.
[0048] After specifying the relationship between the target function and the initialization code, the initialization code performs a data reading operation on the original data storage block in the first storage area, and copies the program code, interrupt vector table and related data in the original data storage block into the replica data storage block in the second storage area according to the preset storage mapping rules, so as to construct a data replica for fast access during the runtime phase.
[0049] Furthermore, this application also includes: the original data storage block of the first storage area further includes ordinary code segments and constant data segments.
[0050] Specifically, the raw data storage block of the first storage area refers to the basic data set set in the system's non-volatile storage medium, which is used to centrally store various types of code and data content required for program operation. Among them, the ordinary code segment, as a component of the raw data storage block, is used to store regular function program instructions other than the critical code segment. The ordinary code segment, i.e. (.text), is usually used to implement the system's non-real-time control logic or background processing functions.
[0051] The constant data segment (.rodata) refers to the storage area that stores data that does not change during program execution. The constant data segment includes read-only data, configuration parameters, or fixed entries determined during the compilation phase. The constant data segment is set in the first storage area to ensure data stability and consistency, and to reduce the occupation of high-speed storage resources during operation.
[0052] Furthermore, this application also includes: performing hash digest calculation on the key code segment of the first storage area to obtain hash digest data; performing integrity verification based on the hash digest data and the pre-stored digital signature; and executing the copy writing process after the verification is passed.
[0053] Specifically, before the data copy operation is performed, a hash digest is calculated on the critical code segments in the first storage area. A hash digest calculation is a process that maps input data to a fixed-length output value, with the aim of generating a unique identifier for the data content. By performing a hash digest calculation on the critical code segments, it can be ensured that the code content has not changed during data transmission or storage.
[0054] After obtaining the hash digest data, the data is compared with the pre-stored digital signature for integrity verification. A digital signature is a cryptographic technique that uses a public-private key pair to ensure that the data has not been tampered with. By comparing the hash digest data and the digital signature, it is determined whether critical code segments have been tampered with or corrupted during storage or transmission.
[0055] Once the integrity check passes, it indicates that the data has not been tampered with, ensuring data integrity and reliability. Subsequently, the data copying and writing process is executed, successfully copying the data from the first storage area to the replica data storage block in the second storage area. This ensures that the data in the replica data storage block is consistent with the original data and provides reliable data support for subsequent system operation.
[0056] Furthermore, this application also includes: if there are multiple interrupt access requests, a request sorting queue is obtained according to the priority identifier; the VTOR register locates the interrupt vector table copy from the copy data storage block of the second storage area according to the request sorting queue and executes it in priority order.
[0057] Specifically, when the CPU core issues an interrupt access request, the interrupt needs to be handled according to a preset interrupt response mechanism. The interrupt request is triggered by an external event or internal condition. The CPU issues an interrupt request to inform the system to suspend the current program execution and enter the interrupt handling phase.
[0058] If there are multiple interruption access requests, they are sorted according to their priority to form a request sorting queue. The priority identifier is a numerical value assigned to each interruption request, indicating the urgency or processing order of the request; requests with higher priority will be processed first.
[0059] After the request sorting queue is formed, the VTOR register locates the interrupt vector table copy from the copy data storage block of the second storage area according to the priority order in the queue. The VTOR register is a register used to store the starting address of the interrupt vector table. It can quickly obtain the entry address of the corresponding interrupt service routine from the copy data storage block according to priority and execute the corresponding interrupt service routine in priority order.
[0060] In summary, the fast interrupt response method for embedded system code provided in this application has the following technical effects: by storing key data and interrupt vector tables in a high-speed storage area and optimizing the interrupt handling process using a priority sorting mechanism, the interrupt response speed and multi-interrupt request processing capability are improved, thereby enhancing the stability and performance of the system in environments with high real-time requirements.
[0061] Example 2: Based on the same inventive concept as the fast interrupt response method for embedded system code in the foregoing examples, this application also provides a fast interrupt response system for embedded system code. Please refer to the appendix. Figure 4 It includes: a storage area configuration module 1, used to configure a first storage area and a second storage area, wherein the response speed of the first storage area is less than that of the second storage area; and a data copy module 2, used to read the original data storage block of the first storage area and copy the data in the original data storage block of the first storage area to the replica data storage block of the second storage area through initialization code; wherein, when the CPU core issues an interrupt access request, the interrupt vector table replica is located and accessed from the replica data storage block of the second storage area through the VTOR register.
[0062] Furthermore, the embedded system code interrupt fast response system is also used for: the original data storage block of the first storage area includes an original interrupt vector table and a key code segment; the copy data storage block of the second storage area includes a copy of the interrupt vector table and a copy of the key code segment written based on the copy of the initialization code; after locating the interrupt vector table from the copy data storage block of the second storage area, the data of the interrupt vector table copy is accessed by executing the copy of the key code segment.
[0063] Furthermore, the embedded system code interrupt fast response system is also used for: the replica data storage block of the second storage area further includes a standard data segment, the standard data segment includes a copy data segment and a zeroing data segment; after initializing the standard data segment, the data in the original data storage block of the first storage area is copied and written into the replica data storage block of the second storage area.
[0064] Furthermore, the embedded system code interrupt fast response system is also configured such that: the first storage area is a Flash area, and the second storage area is a RAM area.
[0065] Furthermore, the embedded system code interrupt fast response system is also used to: assign at least one target function to the initialization code by segment attribute tagging; and copy data from the original data storage block of the first storage area to the replica data storage block of the second storage area by the initialization code.
[0066] Furthermore, the embedded system code interrupt fast response system is also used in that: the original data storage block of the first storage area further includes ordinary code segments and constant data segments.
[0067] Furthermore, the embedded system code interrupt fast response system is also used to: perform hash digest calculation on the key code segment of the first storage area to obtain hash digest data; perform integrity verification based on the hash digest data and the pre-stored digital signature; and execute the copy writing process after the verification is passed.
[0068] Furthermore, the embedded system code interrupt fast response system is also used to: if there are multiple interrupt access requests, obtain a request sorting queue according to priority identifiers; the VTOR register locates the interrupt vector table copy from the copy data storage block of the second storage area according to the request sorting queue and executes it in priority order.
[0069] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The fast interrupt response method and specific examples of embedded system code in the aforementioned embodiment one are also applicable to the fast interrupt response system of embedded system code in this embodiment. Through the foregoing detailed description of the fast interrupt response method of embedded system code, those skilled in the art can clearly understand the fast interrupt response system of embedded system code in this embodiment. Therefore, for the sake of brevity, it will not be described in detail here.
[0070] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0071] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of this application and its equivalents, this application also intends to include such modifications and variations.
Claims
1. A fast interrupt response method for embedded system code, characterized in that, The method includes: Configure a first storage region and a second storage region, wherein the response speed of the first storage region is less than the response speed of the second storage region; Read the original data storage block of the first storage area, and copy the data in the original data storage block of the first storage area to the replica data storage block of the second storage area through initialization code; Specifically, when the CPU core issues an interrupt access request, it locates and accesses the copy of the interrupt vector table from the copy data storage block of the second storage area through the VTOR register.
2. The method for fast interrupt response in embedded system code as described in claim 1, characterized in that, The original data storage block of the first storage area includes the original interrupt vector table and the key code segment; the copy data storage block of the second storage area includes a copy of the interrupt vector table and a copy of the key code segment written based on the copy of the initialization code. After locating the interrupt vector table from the copy data storage block of the second storage area, the data of the interrupt vector table copy is accessed by executing the copy of the critical code segment.
3. The method for fast interrupt response in embedded system code as described in claim 2, characterized in that, The replica data storage block of the second storage area also includes a standard data segment, which includes a copy data segment and a zeroing data segment; After initializing the standard data segment, the data in the original data storage block of the first storage area is copied and written to the replica data storage block of the second storage area.
4. The method for fast interrupt response in embedded system code as described in claim 1, characterized in that, The first storage area is a Flash area, and the second storage area is a RAM area.
5. The method for fast interrupt response in embedded system code as described in claim 1, characterized in that, At least one objective function is assigned to the initialization code by segment attribute tags; The initialization code copies the data from the original data storage block of the first storage area to the replica data storage block of the second storage area.
6. The method for fast interrupt response in embedded system code as described in claim 1, characterized in that, The original data storage blocks of the first storage area also include ordinary code segments and constant data segments.
7. The method for fast interrupt response in embedded system code as described in claim 2, characterized in that, Before copying data from the original data storage block of the first storage region to the replica data storage block of the second storage region, the method further includes: Perform hash digest calculation on the key code segment of the first storage area to obtain hash digest data; Integrity verification is performed based on the hash digest data and the pre-stored digital signature. Once the verification is successful, the copy writing process is executed.
8. The method for fast interrupt response in embedded system code as described in claim 5, characterized in that, When the CPU core issues an interrupt access request, the method also includes: If there are multiple interruption access requests, a request sorting queue is obtained according to the priority identifier; The VTOR register sorts the queue according to the request and locates the interrupt vector table replica from the replica data storage block of the second storage area to execute it in priority order.
9. A fast interrupt response system for embedded system code, characterized in that, The steps for implementing the interrupt fast response method for embedded system code according to any one of claims 1 to 8 include: A storage area configuration module is used to configure a first storage area and a second storage area, wherein the response speed of the first storage area is less than the response speed of the second storage area; The data copy module is used to read the original data storage block of the first storage area and copy the data in the original data storage block of the first storage area to the replica data storage block of the second storage area through initialization code; Specifically, when the CPU core issues an interrupt access request, it locates and accesses the copy of the interrupt vector table from the copy data storage block of the second storage area through the VTOR register.