Method for optimizing power device forward anti-single event radiation hardening based on dielectric engineering

Abstract

The application discloses a power device forward anti-single particle radiation reinforcement method based on medium engineering optimization, and is suitable for preparing or optimizing a power device containing a MOS structure. The method comprises the following steps: pre-treating a medium layer of a MOS sensitive area of the power device, adjusting the microstructure of the medium layer into a mixed-phase medium structure in which amorphous phases and crystalline phases coexist through annealing or laser processing, and passivating radiation-induced dielectric performance degradation from the material source; designing and optimizing geometric parameters of a terminal structure through TCAD simulation software to obtain the lowest and uniform electric field distribution in the medium area at the edge of the active area of the device, so as to buffer local electric field peaks caused by radiation; and selecting a high-thermal-conductivity crystal direction of a semiconductor material as a heat dissipation direction of a groove sidewall when the groove structure is prepared, so as to enhance heat dissipation and relieve transient thermal effects. Through multi-level forward synergistic design of materials, electric fields and heat management, the application systematically improves the anti-single particle burnout capability and gate wear threshold of the power device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for positive single-event radiation hardening of power devices based on dielectric engineering optimization. Background Technology

[0002] The rapid development of semiconductor technology has driven continuous improvements in device performance and integration, expanding its applications from traditional terrestrial electronic systems to extreme radiation environments such as space exploration, nuclear engineering, and high-energy physics. In these environments, semiconductor devices, especially power devices, are exposed to high-energy particle radiation (such as heavy ions in cosmic rays) for extended periods, facing severe reliability challenges. When heavy ions and other high-energy particles bombard devices, they interact with the dielectric layer and semiconductor materials, causing damage to the microstructure of the dielectric layer, such as induced crystallization transitions and grain boundary formation. This leads to degradation of the dielectric constant and nanoscale dielectric constant inhomogeneities in the micrometer-scale peak electric field region of the device. In areas of concentrated electric field, such as the active region edge and junction termination, the inhomogeneous degradation of dielectric properties further distorts the electric field distribution, causing a significant increase in local peak electric fields. This greatly increases the risk of single-event gate breakdown (SEGR) or single-event burnout (SEB), seriously threatening the long-term reliable operation of devices in radiation environments.

[0003] To address these challenges, existing technologies have proposed several hardening schemes to resist single-event radiation. For example, one scheme introduces a p-type buried layer and a p-type shielding layer into a SiC UMOSFET, and uses a high-dielectric-constant material (such as Al₂O₃) instead of traditional SiO₂ as the gate dielectric to reduce the gain of the parasitic BJT and increase the physical thickness of the dielectric, thereby suppressing single-event burn-out and increasing the gate breakdown threshold. Another scheme, based on simulation analysis, combines a field-plate structure β-Ga₂O₃ Schottky diode with a high thermal conductivity diamond coating, optimizing the electric field distribution and enhancing heat dissipation to improve the device's single-event resistance.

[0004] However, existing technical solutions still have significant shortcomings: either the hardening measures focus primarily on local optimization or post-event performance compensation at the device structure level, failing to proactively suppress radiation-induced microstructural damage and its impact on dielectric properties through the hardening of the dielectric material itself; or while they can improve specific failure indicators, they often introduce additional parasitic parameters (such as parasitic capacitance and inductance), leading to increased device dynamic losses and potentially causing new reliability issues. Most importantly, the above research largely focuses on simulation verification or mitigation of single failure modes, lacking a systematic, proactive, integrated hardening strategy for single-event burn-out problems, encompassing materials engineering, terminal structures, and thermoelectric design. This makes it difficult to comprehensively address device degradation and failure caused by multi-physics coupling in complex radiation environments. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a method for positive single-event radiation hardening of power devices based on dielectric engineering optimization. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a method for positive single-event radiation hardening of power devices based on dielectric engineering optimization, applicable to the fabrication or optimization of power devices containing MOS structures. The method includes: The dielectric layer of the MOS sensitive region of the power device is pretreated to regulate the microstructure of the dielectric layer into a mixed-phase dielectric structure in which amorphous and crystalline phases coexist. By using device modeling and simulation software, the geometric parameters of the power device terminal structure are designed and optimized to mitigate and reduce the electric field in the dielectric region at the edge of the active region of the power device, so as to obtain the lowest electric field peak and uniform electric field distribution, thereby reducing the electric field rise in the dielectric region at the edge of the active region of the power device induced by single-particle radiation and its impact on single-particle burn-off of the device. In the process of fabricating the trench structure of the power device, the crystal orientation with high thermal conductivity of the material is selected as the heat dissipation direction of the trench sidewall, thus forming a trench MOS structure with high sidewall thermal conductivity.

[0006] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The present invention provides a method for hardening power devices against single-event radiation based on dielectric engineering optimization. Starting with the design of the material's microstructure and synergistically optimizing the device's terminal electric field and thermal management, it preemptively strengthens the device's weak points before radiation occurs, fundamentally improving the device's inherent radiation resistance. By integrating material-level dielectric engineering optimization, device-level terminal electric field optimization, and system-level trench thermal management optimization, it addresses the physical induction mechanisms of single-event effects, such as dielectric degradation and inhomogeneity, electric field concentration, and thermal effects, forming a comprehensive and systematic solution with more comprehensive and reliable hardening effects.

[0007] 2. The forward single-event radiation hardening method for power devices based on dielectric engineering optimization of this invention, through simulation-driven terminal structure optimization, can precisely control the electric field distribution to the optimal state while ensuring static performance such as breakdown voltage, avoiding the performance loss or introduction of new parasitic parameters that may occur with traditional methods. Furthermore, the core principles of this invention—mixed-phase dielectric, electric field homogenization, and thermal management optimization—are applicable to various wide-bandgap semiconductor materials, such as β-Ga2O3 and SiC, and various power device structures such as MOSFETs, MOSCAPs, and MOS-Type trench diodes, exhibiting high versatility and portability.

[0008] 3. The dielectric engineering-optimized forward single-event radiation hardening method for power devices of this invention employs conventional or mature processes in semiconductor manufacturing, including dielectric pretreatment and device termination structure formation, without requiring the introduction of special or expensive equipment and materials. This optimization and integration based on existing process platforms makes the hardening technology easily integrated into existing production lines, providing a solid foundation for large-scale mass production and engineering applications, and effectively meeting the urgent needs of aerospace, military, and other fields for high-reliability radiation-resistant power devices.

[0009] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0010] Figure 1 This is a flowchart of a method for positive single-event radiation hardening of power devices based on dielectric engineering optimization, provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a β-Ga2O3MOS-Type trench diode device structure that includes only a groove terminal, provided by an embodiment of the present invention; Figure 3 This is an initial structural schematic diagram of a β-Ga2O3MOS-Type trench diode device with a grooved stepped field plate terminal provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a trench structure formation provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a dielectric engineering optimization and Schottky region formation structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a groove terminal forming structure provided in an embodiment of the present invention; Figure 7This is a schematic diagram of a grooved stepped field plate terminal structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of an optimized β-Ga2O3MOS-Type trench diode device structure provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of a β-Ga2O3MOS-Type trench diode device with a floating metal ring terminal provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a dielectric engineering optimization, Schottky region and floating metal ring region formation structure provided by an embodiment of the present invention. Detailed Implementation

[0011] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail, with reference to the accompanying drawings and specific embodiments, a method for positive single-particle radiation hardening of power devices based on dielectric engineering optimization proposed in accordance with the present invention.

[0012] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0013] This invention provides a method for positively resisting single-event radiation hardening of power devices based on dielectric engineering optimization. It is applicable to the fabrication or optimization of power devices containing MOS structures. It addresses the problems of decreased dielectric properties and dielectric inhomogeneity caused by heavy-ion radiation-induced transverse phonon scattering at grain boundaries, as well as the high electric field problem associated with single-event transient thermal effects in high-electric-field regions of semiconductor epitaxy. It integrates dielectric material engineering optimization, device terminal structure optimization, and thermoelectric design optimization to form a radiation hardening strategy, fundamentally solving the root cause problem of material radiation sensitivity related to single-event burn-out of power devices.

[0014] Please see Figure 1 , Figure 1 This is a flowchart of a method for hardening power devices against single-event radiation based on dielectric engineering optimization, provided in an embodiment of the present invention. Figure 1 As shown in this embodiment, the forward single-event radiation hardening method for power devices based on dielectric engineering optimization is a systematic forward design process, mainly including three parts: dielectric engineering optimization, terminal structure and electric field co-optimization, and trench thermal management optimization. Specifically, it includes the following steps: Step 1: Pre-process the dielectric layer of the MOS sensitive region of the power device to regulate the microstructure of the dielectric layer into a mixed-phase dielectric structure in which amorphous and crystalline phases coexist.

[0015] In an alternative embodiment, the power device may be a MOS-Type diode, a MOSCAP, or a MOSFET.

[0016] In this embodiment, by pre-processing the dielectric layer of the MOS sensitive region of the power device, the initial amorphous dielectric is modulated into a mixed-phase dielectric structure in which amorphous and crystalline phases coexist. This mixed-phase structure can effectively passivate the transverse phonon scattering at grain boundaries induced by heavy ion radiation, thereby suppressing the decrease in dielectric constant and uneven distribution of the dielectric caused by heavy ion radiation, fundamentally improving the single-particle breakdown threshold voltage of the MOS sensitive region, and realizing radiation hardening of the MOS sensitive region of the power device.

[0017] In an optional embodiment, the dielectric layer comprises a single-layer dielectric layer composed of one of HfO2, PZT, and HfCeO2, or a stacked dielectric layer composed of multiple dielectric materials. The dielectric layer can be grown by atomic layer deposition, radio frequency sputtering, pulsed laser deposition, or metal-organic molecular beam epitaxy.

[0018] For example, an HfO2 amorphous thin film of the target thickness is grown on a semiconductor as a dielectric layer using atomic layer deposition (ALD), followed by pretreatment.

[0019] In one alternative embodiment, the pretreatment may be annealing or laser treatment.

[0020] Optionally, the annealing process parameters include: heating to 600-1000°C at a heating rate of 5-20°C / min in an annealing atmosphere, and holding for 10-30 minutes, wherein the annealing atmosphere is one of air, oxygen, nitrogen or an inert gas.

[0021] For example, a sample with deposited HfO2 thin films is placed in an annealing furnace and heated to 600°C at a rate of approximately 10°C / min under a N2 atmosphere, with an annealing holding time of 30 min. This treatment induces partial crystallization of the amorphous HfO2 thin film, which contains nanoscale crystalline regions, such as m-HfO2, transforming the HfO2 thin film from its initial amorphous state into a mixed-phase dielectric structure where the amorphous phase (a-HfO2) and the crystalline phase (m-HfO2) coexist. This mixed-phase dielectric structure effectively passivates transverse phonon scattering at grain boundaries induced by heavy-ion radiation, thereby suppressing radiation-induced decreases in dielectric constant and uneven distribution, fundamentally improving the single-particle breakdown threshold voltage of the MOS sensitive region.

[0022] Optionally, the process parameters for laser processing include: the laser type is a KrF excimer laser with a wavelength of 248 nm, and the laser energy density is 80-150 mJ / cm². 2 The laser pulse frequency is 5-10Hz, the laser irradiation time is 5-15min, and the laser treatment atmosphere is O2.

[0023] For example, a sample with an amorphous HfO2 thin film deposited was placed in an oxygen atmosphere chamber. A KrF excimer laser with a wavelength of 248 nm was used, and the laser energy density was set to 80 mJ / cm². 2 The pulse frequency was 7 Hz. The laser beam was used to uniformly irradiate the entire sample surface, with the total irradiation time controlled within 10 minutes. The high-energy laser pulse was absorbed by the HfO2 thin film. After absorbing photons, the material underwent photoexcitation. Electrons absorbed photon energy and transitioned, releasing energy through coupling with lattice vibrations (phonons), which was converted into thermal vibrational energy of the lattice. The thermal energy generated by laser irradiation provided the driving force for atoms in the amorphous HfO2 thin film to overcome potential barriers and migrate and rearrange, promoting the formation of crystal structures. Furthermore, by controlling the laser irradiation area and laser energy density, localized selective crystallization of the material could be achieved.

[0024] Understandably, this hybrid phase structure formed by laser irradiation not only possesses passivation capabilities similar to thermal annealing for phonon scattering and defects caused by radiation-induced recrystallization, but also, thanks to its ultrafast action process and local energy deposition characteristics, can greatly reduce the thermal impact on underlying semiconductor materials and existing device structures. It is very suitable for back-end process integration or for local hardening of partially completed devices.

[0025] Step 2: Using device modeling and simulation software, design and optimize the geometric parameters of the power device terminal structure to mitigate and reduce the electric field in the dielectric region at the edge of the active region of the power device, so as to obtain the lowest electric field peak and uniform electric field distribution, thereby reducing the electric field rise in the dielectric region at the edge of the active region of the power device induced by single-particle radiation and its impact on single-particle burn-off of the device.

[0026] Alternatively, the geometric parameters of the power device termination structure can be designed and optimized using Sentaurus TCAD or Silvaco TCAD device modeling and simulation software.

[0027] In one alternative embodiment, the terminal structure includes a grooved stepped field plate terminal, a floating metal ring terminal, or a field limiting ring terminal.

[0028] Specifically, for the grooved stepped field plate terminal, the designed and optimized geometric parameters include: groove depth, groove width, stepped field plate thickness, and stepped field plate extension length; for the floating metal ring terminal, the designed and optimized geometric parameters include: floating metal ring width, distance between the floating metal ring and the anode, number of floating metal rings, and spacing between floating metal rings; for the field confinement ring terminal, the designed and optimized geometric parameters include: field confinement ring spacing, field confinement ring width, number of field confinement rings, field confinement ring depth, and field confinement ring doping concentration.

[0029] For example, taking a β-Ga2O3 MOS-Type trench diode device as an example for termination optimization, firstly, an initial power device model is established in Sentaurus TCAD software, with its termination structure set as a stepped field plate in a groove to be optimized. The optimization objective is to minimize the peak electric field in the dielectric region at the edge of the active region of the device and to achieve the most uniform electric field distribution. The core of the simulation is to systematically scan and optimize the geometric parameters of the termination structure, including the groove depth dt1, groove width t1, stepped field plate thickness (including the thickness of the first stepped field plate dt2 and the thickness of the second stepped field plate dt3), and stepped field plate extension length t3. Through a large number of simulation iterations, a set of geometric parameter combinations that achieves the optimal electric field distribution in the target region is found. This optimization process is equivalent to pre-verifying and mitigating electric field concentration, enabling the termination structure to have the ability to buffer the peak electric field in the dielectric region at the edge of the active region of the device induced by radiation.

[0030] This optimized design allows for the pre-emptive mitigation and reduction of the electric field concentration in the region. When the device is subjected to heavy ion irradiation, causing localized degradation of the dielectric properties in that area, the pre-optimized electric field distribution can effectively buffer and suppress the resulting abnormal increase in the electric field peak value, preventing the electric field peak value from exceeding the critical value, thereby significantly improving the single-particle burn-off threshold voltage of the device.

[0031] Step 3: In the process of fabricating the trench structure of the power device, the crystal orientation with high thermal conductivity of the material is selected as the heat dissipation direction of the trench sidewall, forming a trench MOS structure with high sidewall thermal conductivity.

[0032] In this embodiment, this step can improve the ability of trench power devices, such as MOSFETs and MOS-Type trench diodes, to resist transient thermal failure from a thermal management perspective.

[0033] For example, for semiconductor materials with anisotropic thermal conductivity, such as β-Ga2O3, the thermal conductivity along the

[100] crystal orientation is significantly higher than that along the

[010] crystal orientation. Therefore, the trench patterning direction is intentionally designed to be along the

[010] crystal orientation when designing the photomask. The resulting trench structure with high sidewall thermal conductivity provides an efficient heat conduction path for the channel and high electric field region. When heavy ion incident induces transient high-density electron-hole pairs and generates Joule heating, the heat can diffuse more efficiently to the substrate along the high thermal conductivity sidewall direction, avoiding local heat accumulation, mitigating transient thermal effects, and further synergistically improving the single-particle burn-off threshold of the device.

[0034] In this embodiment, the trench thermal management optimization in step 3 and the electric field optimization in step 2 complement each other. The electric field optimization reduces the peak electric field in the dielectric region at the edge of the active region of the device, while the trench thermal management optimization improves the heat dissipation efficiency. Together, they can significantly reduce the peak lattice temperature in single-event events and fundamentally alleviate thermal failure.

[0035] This invention presents a forward radiation hardening method for power devices based on dielectric engineering optimization. Through the synergistic design of the above three steps, a progressive forward radiation hardening system is constructed from three dimensions: material microstructure, device electric field distribution, and trench thermal management. This fundamentally enhances the intrinsic radiation resistance of the device. By integrating material-level dielectric engineering optimization, device-level terminal electric field optimization, and system-level trench thermal management optimization, a comprehensive and systematic solution is formed, addressing the physical inducing mechanisms of single-event effects such as dielectric degradation and inhomogeneity, electric field concentration, and thermal effects. The hardening effect is more comprehensive and reliable.

[0036] Furthermore, the present invention provides an exemplary description of the forward single-event radiation hardening method for power devices based on dielectric engineering optimization through specific embodiments.

[0037] Example 1 Taking a β-Ga2O3MOS-Type trench diode based on a grooved stepped field plate terminal as an example, this paper illustrates the specific implementation process of the forward single-event radiation hardening method for power devices based on dielectric engineering optimization.

[0038] S1: Radiation hardening of the MOS sensitive region of the device based on dielectric engineering optimization.

[0039] Specifically, a 60 nm amorphous HfO2 dielectric layer was deposited on the trench structure formed by the β-Ga2O3 drift layer using the ALD method. The deposited HfO2 sample underwent a pre-annealing process, annealing at 600 °C in an air-atmosphere annealing furnace for 30 minutes at a heating rate of 10 °C / min. After the pre-annealing process, the initial amorphous HfO2 dielectric layer was modulated into a mixed-phase HfO2 dielectric structure containing both amorphous and nanocrystalline (m-HfO2) phases.

[0040] S2: Device structure reinforcement against single-event burn-off based on device terminal structure optimization and thermoelectric design optimization.

[0041] S2.1: Design the optimal device structure and parameters for the grooved stepped field plate terminal using Sentaurus TCAD simulation software.

[0042] Specifically, by optimizing parameters such as groove depth, groove width, stepped field plate thickness, and stepped field plate extension length, a groove-stepped field plate termination structure with the lowest electric field peak and the most uniform electric field distribution is obtained. The device electric field peak is located in the dielectric region at the edge of the device's active region. This step aims to passivate the heavy ion-induced dielectric drop at the device edge and the increase in electric field peak caused by uneven drop, thereby improving the device's single-particle burn-off threshold voltage.

[0043] First, a structural model of a β-Ga2O3 MOS-Type trench diode device, containing only the grooved terminals, was created using Sentaurus TCAD simulation software. (See also...) Figure 2 , Figure 2 This is a schematic diagram of a β-Ga2O3 MOS-Type trench diode device structure that includes only a groove terminal, provided by an embodiment of the present invention. Figure 2 As shown, for Figure 2 The device structure was optimized for parameters (groove width). The filling material at the groove ends was set to SiO2. Different groove widths t1 were set, and the peak electric fields inside the Ga2O3 and SiO2 components of the device were obtained through simulation. The optimal groove width t1 was taken when the peak electric fields inside both Ga2O3 and SiO2 were minimized. The above process yielded the optimal groove width t1 for a β-Ga2O3 MOS-Type trench diode device structure containing only groove ends.

[0044] Please see Figure 3 , Figure 3 This is an initial structural schematic diagram of a β-Ga2O3 MOS-Type trench diode device with a stepped field plate terminal according to an embodiment of the present invention. Figure 3As shown, the optimal groove width t1 is fixed as the groove width at the end of the stepped field plate. Then, different stepped field plate extension lengths t3 and second-layer field plate lengths t4 are set. The electric field peak values ​​inside Ga2O3 and SiO2 of the device are obtained by simulation. The t3 and t4 corresponding to the minimum electric field peak values ​​inside Ga2O3 and SiO2 are taken as the optimal stepped field plate extension length t3 and the optimal second-layer field plate length t4. The optimal first-layer field plate length t2 is obtained, which is the sum of the optimal stepped field plate extension length t3 and the second-layer field plate length t4. Finally, different groove depths dt1, first-layer stepped field plate thicknesses dt2 and second-layer stepped field plate thicknesses dt3 were set, and the electric field peak values ​​inside Ga2O3 and SiO2 of the device were obtained through simulation. The dt1, dt2, and dt3 corresponding to the minimum electric field peak values ​​and the most uniform electric field distribution inside both Ga2O3 and SiO2 were taken as the optimal groove depth dt1, the optimal first-layer stepped field plate thickness dt2, and the optimal second-layer stepped field plate thickness dt3.

[0045] Step S2.1 optimizes parameters such as groove depth, groove width, stepped field plate thickness, and stepped field plate extension length to obtain optimal device geometric parameters, including: optimal groove width t1, optimal first-layer field plate length t2, optimal stepped field plate extension length t3, optimal second-layer field plate length t4, optimal groove depth dt1, optimal first-layer stepped field plate thickness dt2, and optimal second-layer stepped field plate thickness dt3. This yields the groove-stepped field plate termination structure with the lowest peak electric field and the most uniform electric field distribution for the β-Ga2O3 MOS-Type trench diode device. These optimal device geometric parameters are used in step S2.2 to fabricate the actual device parameters of the β-Ga2O3 MOS-Type trench diode with groove-stepped field plate termination.

[0046] S2.2: Gallium oxide (β-Ga2O3) MOS-Type trench diodes with HfO2 dielectric at the end of the groove stepped field plate are fabricated using a trench structure with high sidewall thermal conductivity.

[0047] For β-Ga2O3, the

[100] crystal orientation is selected as the heat dissipation direction of the trench sidewall. This step aims to fundamentally alleviate the thermal effect of the high electron-hole current induced by heavy ions under high electric field by optimizing the thermal properties of the material in the semiconductor channel and high electric field region, thereby improving the single-particle burn-off threshold voltage of the device.

[0048] It should be noted that during the device fabrication process, the dielectric layer of the MOS sensitive region is pretreated, and the radiation hardening of the optimized MOS sensitive period is usually carried out after the high sidewall thermal conductivity trench structure is fabricated.

[0049] Furthermore, based on the above-mentioned reinforcement method, the specific fabrication process of the β-Ga2O3 MOS-Type trench diode based on the grooved stepped field plate terminal is described. Specifically, it includes the following steps: Step a: Film cleaning and pretreatment.

[0050] All device structures were fabricated on a 650 μm thick β-Ga2O3 substrate. A 10 μm thick layer with a doping concentration of 1 × 10⁻⁶ was then fabricated on the substrate via hydride vapor phase epitaxy (HVPE). 16 cm -3 The β-Ga2O3 drift layer was ultrasonically cleaned with acetone and isopropanol for 5 minutes in sequence to remove surface organic impurities. Then it was rinsed with deionized water for 5 minutes and the surface of the wafer was dried with a nitrogen gun.

[0051] Step b: Formation of ohmic contacts on the back side.

[0052] A metal (Ti / Au) stacked layer was grown on the back side of a β-Ga2O3 substrate using a metal evaporation process and then subjected to rapid thermal annealing at 470°C for 1 min to form a cathode ohmic contact.

[0053] Step c: Trench structure formation.

[0054] Multiple uniformly spaced first Schottky metal layers (Ni / Au) are grown on the β-Ga2O3 drift layer along the

[100] crystal orientation using photolithography and metal evaporation processes to serve as hard masks for the etching trenches; areas on the β-Ga2O3 drift layer not protected by the hard mask are exposed, and a uniformly arranged array of 1μm deep trenches is formed on the β-Ga2O3 drift layer using RIE etching, with the protruding parts referred to as fins. Figure 4 As shown, Figure 4 This is a schematic diagram of a trench structure formation provided in an embodiment of the present invention.

[0055] Step d: Media engineering optimization (i.e., step S1 in Example 1 above) and Schottky region formation.

[0056] After completing step S1, photolithography and RIE etching processes are used to create openings in the dielectric layer of the middle portion of the fin to expose the Schottky region, such as... Figure 5 As shown, Figure 5 This is a schematic diagram of a media engineering optimization and Schottky region formation structure provided in an embodiment of the present invention.

[0057] Step e: Groove end formation.

[0058] The groove region is formed using photolithography and RIE etching processes, and SiO2 material is deposited on the entire wafer using the ALD method. The groove is also filled with SiO2. The groove width and depth are based on the optimal groove width t1 and optimal groove depth dt1 obtained in step S2.1. The SiO2 thickness is the sum of the optimal groove depth dt1, the optimal first-layer stepped field plate thickness dt2, and the optimal second-layer stepped field plate thickness dt3 obtained in step S2.1. Then, photolithography and RIE etching processes are used to remove the remaining SiO2, retaining only the SiO2 in the terminal region, forming the groove termination structure. Figure 6 As shown, Figure 6 This is a schematic diagram of a groove terminal forming structure provided in an embodiment of the present invention.

[0059] Step f: The stepped field plate is formed at the end.

[0060] Please see Figure 7 , Figure 7 This is a schematic diagram of a grooved stepped field plate terminal structure provided in an embodiment of the present invention. The field plate region pattern (including a first field plate and a second field plate) is formed using photolithography, and the remaining SiO2 is removed using RIE etching, retaining only the SiO2 in the field plate region, as shown below. Figure 7 As shown in the left figure, the field plate length is the optimal first-layer field plate length t2 obtained based on step S2.1, and the field plate thickness is the sum of the optimal first-layer stepped field plate thickness dt2 and the optimal second-layer stepped field plate thickness dt3 obtained based on step S2.1. The stepped field plate is then formed again using photolithography and RIE etching processes, where the width and thickness of the etched SiO2 are the optimal stepped field plate extension length t3 and the optimal second-layer stepped field plate thickness dt3, respectively, obtained based on step S2.1. This forms the grooved stepped field plate terminal structure, as shown... Figure 7 The structure shown in the right figure.

[0061] Step g: Prepare the second Schottky metal layer.

[0062] The second Schottky metal region is formed using photolithography, and the anode electrode is fabricated using metal evaporation and lift-off processes, consisting of a stacked Ni / Au metal layer. See also... Figure 8 , Figure 8 This is a schematic diagram of an optimized β-Ga2O3 MOS-Type trench diode device structure provided in an embodiment of the present invention, as shown below. Figure 8 The structure shown is the final β-Ga2O3MOS-Type trench diode device structure at the end of the grooved stepped field plate.

[0063] Example 2 The specific implementation process of the forward single-event radiation hardening method for power devices based on dielectric engineering optimization is illustrated using a β-Ga2O3 MOS-Type trench diode with a floating metal ring terminal as an example.

[0064] S1: Radiation hardening of the MOS sensitive region of the device based on dielectric engineering optimization.

[0065] Specifically, a 30 nm PZT amorphous dielectric layer was deposited on the trench structure formed by the β-Ga2O3 drift layer using pulsed laser deposition. The PZT-deposited sample was then laser-treated by placing it in an oxygen atmosphere chamber and using a 248 nm KrF excimer laser with a laser energy density of 80 mJ / cm². 2 The pulse frequency was 7 Hz. The laser beam was used to uniformly irradiate the entire sample surface, and the total irradiation time was controlled within 10 minutes. After laser treatment, the initial amorphous dielectric layer of the sample was modulated into a mixed-phase PZT dielectric structure in which PZT amorphous and nanocrystalline materials coexist.

[0066] S2: Device structure reinforcement against single-event burn-off based on device terminal structure optimization and thermoelectric design optimization.

[0067] S2.1 The optimal device structure and parameters of the floating metal ring terminal were designed using Silvaco TCAD simulation software.

[0068] Specifically, by optimizing parameters such as the width of the floating metal ring, the distance between the floating metal ring and the anode, the number of floating metal rings, and the spacing between the floating metal rings, a floating metal ring termination structure with the lowest peak electric field and the most uniform electric field distribution is obtained. The peak electric field is located in the dielectric region at the edge of the active region of the device. This step aims to passivate the increase in peak electric field caused by the dielectric drop and uneven drop of the dielectric at the device edge induced by heavy ions, thereby improving the single-particle burn-off threshold voltage of the device.

[0069] First, a structural model of a β-Ga2O3 MOS-Type trench diode device with a floating metal ring terminal was established using Silvaco TCAD simulation software. (See also...) Figure 9 , Figure 9 This is a schematic diagram of a β-Ga2O3 MOS-Type trench diode device with a floating metal ring terminal provided in an embodiment of the present invention. Figure 9 As shown, S1 represents the distance between the first floating metal ring and the anode, S... i+1 and L iLet S1, W1, S2, W2 represent the distance between the i-th and (i+1)-th floating metal rings, and S2 represent the width of the i-th floating metal ring (where i represents the i-th floating metal ring, i=1, 2, 3...). For example, the parameter combination (S1, W1, S2, W2) describes the case with two floating metal rings, and the parameter combination (S1, W1, S2, W2, S3, W3) describes the case with three floating metal rings. Different numbers of floating metal rings (FMR1, FMR2...), the distance between the first floating metal ring and the anode, and the distance S between the i-th and (i+1)-th floating metal rings are set. i+1 Floating metal ring width L i The peak electric fields inside the Ga2O3 and PZT devices were obtained through simulation. The parameters (S1, W1, S) corresponding to the minimum peak electric field and the most uniform electric field distribution inside both Ga2O3 and PZT devices were selected. i+1 W i+1 The optimal combination of parameters (i=1, 2, 3...) is used to obtain the optimal width of the floating metal ring, the optimal number of floating metal rings, the optimal spacing between the floating metal rings, and the optimal distance S1 between the first floating metal ring and the anode.

[0070] Step S2.1 optimizes parameters such as the width of the floating metal ring, the distance between the floating metal ring and the anode, the number of floating metal rings, and the spacing between the floating metal rings to obtain the optimal geometric parameters of the device. These optimal geometric parameters are used in step S2.2 to fabricate the actual device parameters of the β-Ga2O3 MOS-Type trench diode with floating metal ring terminals.

[0071] S2.2: Gallium oxide (β-Ga2O3) MOS-Type trench diodes with floating metal ring-terminated PZT dielectric are fabricated using a trench structure with high sidewall thermal conductivity.

[0072] For β-Ga2O3, the

[100] crystal orientation is selected as the heat dissipation direction of the trench sidewall. This step aims to fundamentally alleviate the thermal effect of the high electron-hole current induced by heavy ions under high electric field by optimizing the thermal properties of the material in the semiconductor channel and high electric field region, thereby improving the single-particle burn-off threshold voltage of the device.

[0073] Similar to Example 1, the optimized radiation hardening of the device's MOS sensitive region is typically performed after the high sidewall thermal conductivity trench structure has been fabricated.

[0074] Furthermore, based on the above-mentioned reinforcement method, the specific fabrication process of the β-Ga2O3 MOS-Type trench diode with a floating metal ring terminal is described. Specifically, it includes the following steps: Step ac is the same as in Example 1.

[0075] Step d: Medium engineering optimization (i.e., step S1 in Example 2 above) and formation of Schottky region and floating metal ring region.

[0076] After completing step S1, photolithography and RIE etching processes are used to create openings in the dielectric layer of the middle portion of the fin to expose the Schottky region and the floating metal ring region. For example... Figure 10 As shown, Figure 10 This is a schematic diagram of the structure formed by the media engineering optimization and the Schottky region and the floating metal ring region provided in the embodiment of the present invention.

[0077] Step e: The floating metal ring terminal is formed.

[0078] The anode electrode and floating metal ring terminal are fabricated using metal evaporation and lift-off processes, and consist of stacked metal (Ni / Au) layers. See also... Figure 9 , Figure 9 This is a schematic diagram of a β-Ga2O3 MOS-Type trench diode device with a floating metal ring terminal provided in an embodiment of the present invention, as shown below. Figure 9 The structure shown is the final β-Ga2O3MOS-Type trench diode device structure with a floating metal ring terminal.

[0079] The present invention provides a method for hardening power devices against single-event radiation based on dielectric engineering optimization. The dielectric pretreatment and device termination structure formation processes employed are all conventional or mature processes in the semiconductor manufacturing field, requiring no special or expensive equipment or materials. This optimization and integration based on existing process platforms makes this hardening technology easily integrated into existing production lines, providing a solid foundation for large-scale mass production and engineering applications. It effectively meets the urgent needs of aerospace, military, and other fields for high-reliability radiation-hardened power devices.

[0080] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0081] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0082] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for hardening power devices against single-event radiation based on dielectric engineering optimization, characterized in that, The method is suitable for fabricating or optimizing power devices containing MOS structures, and includes: The dielectric layer of the MOS sensitive region of the power device is pretreated to regulate the microstructure of the dielectric layer into a mixed-phase dielectric structure in which amorphous and crystalline phases coexist. By using device modeling and simulation software, the geometric parameters of the power device terminal structure are designed and optimized to mitigate and reduce the electric field in the dielectric region at the edge of the active region of the power device, so as to obtain the lowest electric field peak and uniform electric field distribution, thereby reducing the electric field rise in the dielectric region at the edge of the active region of the power device induced by single-particle radiation and its impact on single-particle burn-off of the device. In the process of fabricating the trench structure of the power device, the crystal orientation with high thermal conductivity of the material is selected as the heat dissipation direction of the trench sidewall, thus forming a trench MOS structure with high sidewall thermal conductivity.

2. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The dielectric layer includes a single-layer dielectric layer composed of one of the dielectric materials HfO2, PZT and HfCeO2, or a stacked dielectric layer composed of multiple dielectric materials.

3. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The dielectric layer is grown by atomic layer deposition, radio frequency sputtering, pulsed laser deposition, or metal-organic molecular beam epitaxy.

4. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The pretreatment includes annealing or laser treatment.

5. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 4, characterized in that, The annealing process parameters include: heating to 600-1000°C at a heating rate of 5-20°C / min in an annealing atmosphere, and holding for 10-30 minutes, wherein the annealing atmosphere is one of air, oxygen, nitrogen or an inert gas. The laser treatment process parameters include: laser type is KrF excimer laser with wavelength of 248nm, laser energy density is 80-150mJ / cm², laser pulse frequency is 5-10Hz, laser irradiation time is 5-15min, and the laser treatment atmosphere is oxygen.

6. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The terminal structure includes a grooved stepped field plate terminal, a field limiting ring terminal, or a floating metal ring terminal.

7. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, When the terminal structure is a grooved stepped field plate terminal, the geometric parameters include: groove depth, groove width, stepped field plate thickness, and stepped field plate extension length; When the terminal structure is a floating metal ring terminal, the geometric parameters include: the width of the floating metal ring, the distance between the floating metal ring and the anode, the number of floating metal rings, and the spacing between the floating metal rings; When the terminal structure is a field-limiting ring terminal, the geometric parameters include: field-limiting ring spacing, field-limiting ring width, number of field-limiting rings, field-limiting ring depth, and field-limiting ring doping concentration.

8. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The power devices include: MOS-Type trench diodes, MOSCAPs, or MOSFETs.

9. The method for hardening power devices against single-event radiation based on dielectric engineering optimization according to claim 1, characterized in that, The device modeling and simulation software is Sentaurus TCAD or Silvaco TCAD.

Images