Semiconductor device based on asymmetric l-shaped schottky contact and method of fabrication

Abstract

The application discloses a semiconductor device based on asymmetric L-shaped Schottky contact and a preparation method thereof. The device comprises: a buried oxygen layer buried below the surface of a Si substrate, the Si substrate being divided into an N well and a P well, the N well being provided with an n-type active region, and the P well being provided with a p-type active region; a differential gate being arranged above the n-type active region and the p-type active region, and an asymmetric L-shaped isolation side wall being arranged on both sides of the differential gate; polycrystalline silicon of the differential gate and a gate metal forming a Schottky contact, the Schottky contact and a MOS region forming a Schottky-MOS hybrid structure; source-drain contacts being arranged at the source-drain ends of the n-type active region and the p-type active region; and a passivation layer being arranged on the upper surface of the entire device. The asymmetric L-shaped isolation side wall is constructed, so that the device has stronger resistance to the movement of charges when heavy ions are incident, lower transient current peak value and collected charges, better anti-single event effect capability and a larger voltage application range.

Description

Technical Field

[0001] This application relates to the field of semiconductor device fabrication technology, and in particular to semiconductor devices based on asymmetric L-type Schottky contacts and their fabrication methods. Background Technology

[0002] SOI structure is a mature design concept for radiation-hardened devices. Due to its isolation effect on the substrate, it can significantly improve the single-event effect of the device and reduce the leakage current at the substrate, thereby reducing the power consumption of the device. However, because the insulating material isolates the substrate and the channel, the bottom of the channel cannot be directly grounded, forming a floating potential. This can easily lead to problems such as parasitic bipolar amplification effect and back-gate modulation, which is called floating body effect.

[0003] Researchers have already combined SOI and FinFET technologies to design new radiation-hardened devices. Pradhan et al. proposed a hybrid Wavy FinFET structure, which eliminates the gate oxide layer on top of the UTB, allowing direct contact between the gate metal and the channel to form a Schottky gate, while retaining the MOS structure on the Fin, resulting in a Schottky-MOS hybrid gate structure. Because this structure introduces a direct Schottky contact, the Schottky gate potentials on both sides are zero when the device is turned off, equivalent to introducing a body contact in the UTB. This effectively addresses the floating gate potential at the bottom of the Fin and stabilizes the channel potential, thus mitigating the floating effect of the device.

[0004] However, the Wavy structure described above has two problems: First, the Schottky contact uses the same gate connection as the MOSFET. When the gate voltage increases, the Schottky contact causes the channel potential to rise, which in turn creates a risk of conduction between the channel and the source-drain PN junction. At lower voltages, leakage current will occur; at higher voltages, a large current will be generated, interfering with the normal operation of the device. This means that the applicable range of this device should be smaller than the drain potential (typically, the maximum value is the supply voltage Vdd). The other problem is that the single-event transient current caused by heavy ion incidents will be shunt by the Schottky gate. This means that a transient current is introduced at the gate, which will affect the preceding circuitry as well, a problem particularly severe in circuits with feedback. Furthermore, the current will also disturb the gate potential, causing changes when the gate potential is floating.

[0005] In summary, existing Wavy structure SOI FinFET devices have a limited voltage range and suffer from severe single-event effects. Summary of the Invention

[0006] This application provides a semiconductor device based on an asymmetric L-type Schottky contact and its fabrication method, in order to solve the problems of the small voltage range and severe single-event effects of existing Wavy structure SOI FinFET devices.

[0007] On the one hand, this application provides a semiconductor device based on an asymmetric L-type Schottky contact, including: a Si substrate, a buried oxide layer, a differentiated gate, an asymmetric L-type isolation sidewall, a source / drain contact, and a passivation layer.

[0008] The buried oxide layer is buried below the surface of the Si substrate. The Si substrate is divided into N-wells and P-wells. The N-wells are provided with n-type active regions, and the P-wells are provided with p-type active regions.

[0009] The differentiated gate is disposed above the n-type active region and the p-type active region, and the asymmetric L-type isolation sidewall is disposed on both sides of the differentiated gate.

[0010] The polysilicon of the differentiated gate forms a Schottky contact with the gate metal, and the Schottky contact and the MOS region form a Schottky-MOS hybrid structure.

[0011] The source-drain contacts are located at the source-drain terminals of the n-type active region and the p-type active region.

[0012] The passivation layer is disposed on the upper surface of the entire device, which consists of a Si substrate, a buried oxide layer, a differentiated gate, an asymmetric L-shaped isolation sidewall, and source / drain contacts.

[0013] On the other hand, this application provides a method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact, which includes the following steps: Step 1: Select a Si substrate and implant oxygen ions to form an SOI substrate with a buried oxide layer.

[0014] Step 2: Shallow trench isolation STI fabrication and CMP planarization are performed on the SOI substrate.

[0015] Step 3: Prepare N-well, P-well, and contact region.

[0016] Step four: Stack the differentiated gate dielectric layers for the PMOS and NMOS regions.

[0017] Step 5: Form a differentiated gate through deposition and etching.

[0018] Step six: Asymmetric L-shaped isolation sidewalls are formed by deposition and etching.

[0019] Step 7: Form the LDD structure through photolithography and ion implantation.

[0020] Step 8: Prepare a Schottky-MOS hybrid structure by deposition.

[0021] Step nine: Form n-type and p-type active regions through epitaxial growth.

[0022] Step 10: Perform source / drain contact metallization and device passivation to obtain a semiconductor device with an asymmetric L-type Schottky contact.

[0023] In one possible implementation, step two, the shallow trench isolation STI fabrication includes: growing a layer of SiO2 on a cleaned SOI substrate, then depositing a layer of Si3N4, and forming a shallow trench isolation STI by photolithography and etching.

[0024] The CMP planarization includes: depositing SiO2 using CMP technology, followed by planarization.

[0025] In one possible implementation, step three includes: Remove the SiO2 grown and Si3N4 deposited in step two, and form N-wells and P-wells by photolithography and ion implantation.

[0026] The buried oxide layer at the N-well and P-well contact is removed by photolithography and etching.

[0027] The contact region between N-wells and P-wells is grown by selective epitaxy.

[0028] In one possible implementation, step four includes: Deposition of SiON, HfSiON, La2O3, and TiN metal capping layers.

[0029] The gate dielectric layer of the PMOS region is removed by photolithography and etching.

[0030] SiON, HfSiON, Al2O3, and TiN metal capping layers are deposited, and the gate dielectric layer deposited in the NMOS region is removed by photolithography and etching.

[0031] In one possible implementation, step five includes: Polysilicon is deposited over the differentiated gate dielectric layer.

[0032] SiO2 is deposited on top of polycrystalline silicon.

[0033] Hard mask layers are formed through photolithography and etching.

[0034] Differentiated gates are formed by etching.

[0035] In one possible implementation, step six includes: High-k gate dielectric material, including HfO2, is deposited and etched to form isolation sidewalls. At the same time, an asymmetric structure is formed, with one side being L-shaped and the other side remaining normal, resulting in an asymmetric L-shaped isolation sidewall.

[0036] In one possible implementation, step eight includes: Gate metal is deposited, and the gate metal forms a Schottky contact with the polysilicon to form a Schottky gate.

[0037] The MOS structure on the fin of the fin field-effect transistor is retained, forming a Schottky-MOS hybrid structure.

[0038] In one possible implementation, step nine includes: A layer of SiO2 is deposited, and the SiO2 in the NMOS region is removed by photolithography and etching. The Si substrate is etched by selective etching back to form a groove in the n-active region. The n-type active region of strained silicon material SiC is formed by epitaxial growth. The p-type active region is formed in the same way.

[0039] In one possible implementation, step ten includes: BPSG material is deposited on the entire substrate surface using CVD technology to form a dielectric layer.

[0040] The dielectric layer is etched using nitric acid and hydrofluoric acid to form NMOS source-drain contact holes and PMOS source-drain contact holes.

[0041] Metal W is deposited on the entire substrate surface using electron beam evaporation to form source / drain contacts.

[0042] Selective etching is used to etch the metal W in a designated area, and CMP is used for planarization.

[0043] SiN material is deposited on the entire substrate surface using CVD technology to passivate the dielectric and form a semiconductor device with an asymmetric L-type Schottky contact.

[0044] The semiconductor device and fabrication method based on the asymmetric L-type Schottky contact in this application have the following advantages: By constructing an asymmetric L-shaped isolation sidewall, the device has a stronger ability to prevent charge movement during heavy ion incident, lower transient current peak and collected charge, better resistance to single-event effects, and a wider voltage range.

[0045] The semiconductor device with the asymmetric L-type Schottky contact obtained in this application has an inverted T-type structure. Combined with strained silicon technology, it can improve the carrier migration efficiency and thus improve the driving capability of the device, while also being compatible with Si technology. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic diagram of the structure of a semiconductor device based on an asymmetric L-type Schottky contact provided in the embodiments of this application; Figure 2 3D schematic diagrams of Wavy-FinFET and AW-FinFET provided for embodiments of this application; Figure 3 This is a schematic diagram of the structure of the Si substrate provided in the embodiments of this application; Figure 4 This is a schematic diagram of the SOI substrate provided in an embodiment of this application; Figure 5 This is a schematic diagram of the device structure after shallow trench isolation STI fabrication provided in the embodiments of this application; Figure 6 This is a schematic diagram of the device structure after CMP planarization provided in an embodiment of this application; Figure 7 This is a schematic diagram of the device structure after forming N-wells and P-wells, provided in an embodiment of this application. Figure 8 A schematic diagram of the device structure after removing the buried oxide layer at the contact between the N-well and the P-well, provided in an embodiment of this application; Figure 9 A schematic diagram of the device structure after the contact region of the N-well and P-well has been grown, as provided in an embodiment of this application; Figure 10 A schematic diagram of the device structure after deposition of SiON, HfSiON, La2O3, and TiN metal capping layers provided in the embodiments of this application; Figure 11 This is a schematic diagram of the device structure after removing the gate dielectric layer of the PMOS region, provided in an embodiment of this application. Figure 12 A schematic diagram of the device structure after removing the secondary gate dielectric layer deposited in the NMOS region, provided in an embodiment of this application; Figure 13 This is a schematic diagram of the device structure after polysilicon deposition, provided in an embodiment of this application. Figure 14 This is a schematic diagram of the device structure after SiO2 is deposited on top of polycrystalline silicon, as provided in an embodiment of this application. Figure 15 This is a schematic diagram of the device structure after forming a hard mask layer, provided in an embodiment of this application. Figure 16 This is a schematic diagram of the device structure after forming a differentiated gate, provided in an embodiment of this application. Figure 17 This is a schematic diagram of the device structure after obtaining the asymmetric L-shaped isolation sidewall, provided in an embodiment of this application. Figure 18 This is a schematic diagram of the device structure after forming the LDD structure provided in the embodiments of this application; Figure 19 This is a schematic diagram of the device structure after forming a Schottky-MOS hybrid structure, provided in an embodiment of this application. Figure 20 A schematic diagram of the device structure after forming the n-type active region and the p-type active region provided in the embodiments of this application; Figure 21 This is a schematic diagram of the device structure after the dielectric layer is formed, provided in an embodiment of this application. Figure 22 A schematic diagram of the device structure after forming NMOS source-drain contact holes and PMOS source-drain contact holes, provided in an embodiment of this application; Figure 23 This is a schematic diagram of the device structure after the formation of source-drain contacts, provided in an embodiment of this application. Figure 24 This is a schematic diagram of the device structure after planarization using CMP process, as provided in an embodiment of this application.

[0048] Explanation of reference numerals in the attached figures: 001-Si substrate, 002-buried oxide layer, 003-Si3N4, 004-SiON, 005-HfSiON, 006-La2O3, 007-TiN, 008-Al2O3, 009-polycrystalline silicon, 010-HfO2, 011-gate metal, 012-n-type active region, 013-p-type active region, 014-dielectric layer, 015-metal W, 016-SiN material. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] like Figure 1 As shown, embodiments of this application provide a semiconductor device based on an asymmetric L-type Schottky contact, including: a Si substrate 001, a buried oxide layer 002, a differentiated gate, an asymmetric L-type isolation sidewall, a source / drain contact, and a passivation layer.

[0051] The buried oxide layer 002 is buried below the surface of the Si substrate 001. The Si substrate 001 is divided into N-wells and P-wells. The N-wells are provided with n-type active regions 012, and the P-wells are provided with p-type active regions 013.

[0052] The differentiated gate is disposed above the n-type active region 012 and the p-type active region 013, and the asymmetric L-type isolation sidewall is disposed on both sides of the differentiated gate.

[0053] The polysilicon 009 of the differentiated gate forms a Schottky contact with the gate metal 011, and the Schottky contact and the MOS region form a Schottky-MOS hybrid structure.

[0054] The source-drain contacts are located at the source-drain terminals of the n-type active region 012 and the p-type active region 013.

[0055] The passivation layer is disposed on the upper surface of the entire device, which consists of a Si substrate 001, a buried oxide layer 002, a differentiated gate, an asymmetric L-shaped isolation sidewall, and source / drain contacts.

[0056] Specifically, the asymmetric L-type Schottky contact semiconductor device proposed in this embodiment is an inverted T-type FinFET device structure. This structure deposits an ultrathin silicon layer on an insulating substrate, utilizing the inherent isolation distance between the fins to extend the lateral distance of the device. This structure can improve the device's drive current.

[0057] like Figure 2 As shown, Figure 2 (a) is a 3D schematic diagram of Wavy-FinFET. Figure 2 (b) is a 3D schematic diagram of AW-FinFET. This embodiment changes the original double-sided Schottky structure on the UTB to a single-sided Schottky structure, referred to as an Asymmetric wavy structure. Figure 2 The AW-SOI-FinFET structure allows for more flexible gate processing. When the device's gate operating voltage is low, a single gate metal can be used, unlike the traditional Tri-gate mode. In this embodiment, this is called the Single Gate Metal (SGM) mode, which is consistent with the gate structure operation of Wavy devices. When the device's gate operating voltage is high, or there are higher radiation resistance requirements, a different gate metal can be used. Figure 2 The Independent Double Gate (IDG) structure shown in (b) adjusts the irradiation performance of the device by grounding one end of the gate or using other potentials, while avoiding the conduction of parasitic diodes, thereby improving the circuit application performance of the device and solving the problem of the small applicable voltage range of the original device structure.

[0058] This application also provides a method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact, which includes the following steps: Step 1: Select a Si substrate 001, implant oxygen ions to form an SOI substrate with a buried oxide layer 002.

[0059] Step 2: Shallow trench isolation STI fabrication and CMP planarization are performed on the SOI substrate.

[0060] Step 3: Prepare N-well, P-well, and contact region.

[0061] Step four: Stack the differentiated gate dielectric layers for the PMOS and NMOS regions.

[0062] Step 5: Form a differentiated gate through deposition and etching.

[0063] Step six: Asymmetric L-shaped isolation sidewalls are formed by deposition and etching.

[0064] Step 7: Form the LDD structure through photolithography and ion implantation.

[0065] Step 8: Prepare a Schottky-MOS hybrid structure by deposition.

[0066] Step nine: n-type active region 012 and p-type active region 013 are formed through epitaxial growth.

[0067] Step 10: Perform source / drain contact metallization and device passivation to obtain a semiconductor device with an asymmetric L-type Schottky contact.

[0068] Specifically, in this embodiment, in step one, a Si substrate 001 is selected, such as... Figure 3 As shown.

[0069] Injection of oxygen ions typically requires O + The dose was 1.8 × 10 18 cm -2 The ion implantation dose is approximately [value missing], significantly higher than that used in typical integrated circuit fabrication processes. High-energy (200keV) implantation is employed to implant oxygen ions to a certain depth below the surface of the Si substrate (001). Following ion implantation, high-temperature annealing is performed to form an SOI substrate with a buried oxide layer (002), as shown below. Figure 4 As shown.

[0070] For example, in step two, the shallow trench isolation STI fabrication includes: growing a layer of SiO2 on a cleaned SOI substrate, then depositing a layer of Si3N4003, and forming a shallow trench isolation STI by photolithography and etching.

[0071] The CMP planarization includes: depositing SiO2 using CMP technology, followed by planarization.

[0072] Specifically, in this embodiment, in step two, a layer of Si3N4003 is deposited using low-pressure chemical vapor deposition (LPCVD), and shallow trench isolation STI is formed through photolithography and etching, such as... Figure 5 As shown.

[0073] SiO2 is deposited using CMP technology, followed by planarization, such as... Figure 6 As shown.

[0074] For example, step three includes: The SiO2 grown and Si3N4003 deposited in step two are removed, and N-wells and P-wells are formed by photolithography and ion implantation. For example... Figure 7 As shown.

[0075] The buried oxide layer 002 at the N-well and P-well contact is removed by photolithography and etching. For example... Figure 8 As shown.

[0076] The contact region between N-wells and P-wells is grown through selective epitaxy. For example... Figure 9 As shown.

[0077] For example, step four includes: Deposition of SiON004, HfSiON005, La2O3006, and TiN007 metal capping layers. For example... Figure 10 As shown.

[0078] The gate dielectric layer of the PMOS region is removed by photolithography and etching. For example... Figure 11 As shown.

[0079] SiON004, HfSiON005, Al2O3008, and TiN007 metal capping layers are deposited, and the secondary gate dielectric layer deposited in the NMOS region is removed by photolithography and etching. For example... Figure 12 As shown.

[0080] For example, step five includes: Polysilicon 009 is deposited above the differentiated gate dielectric layer. For example... Figure 13 As shown.

[0081] SiO2 is deposited on top of polycrystalline silicon 009. For example... Figure 14 As shown.

[0082] Hard mask layers are formed through photolithography and etching. For example... Figure 15 As shown.

[0083] Differentiated gates are formed through etching. For example... Figure 16 As shown.

[0084] For example, step six includes: High-k gate dielectric materials, including HfO2O10, are deposited and etched to form isolation sidewalls. Simultaneously, an asymmetric structure is created, with one side being L-shaped and the other side remaining normal, resulting in an asymmetric L-shaped isolation sidewall. For example... Figure 17 As shown.

[0085] For example, step eight includes: Gate metal 011 is deposited, and gate metal 011 forms a Schottky contact with polysilicon 009 to form a Schottky gate.

[0086] The MOS structure on the fins of the fin field-effect transistor is retained, forming a Schottky-MOS hybrid structure. For example... Figure 19 As shown.

[0087] For example, step nine includes: A layer of SiO2 is deposited, and the SiO2 in the NMOS region is removed by photolithography and etching. The Si substrate 001 is etched by selective etching back technology to form a groove in the n-active region. The n-type active region 012 of strained silicon material SiC is formed by epitaxial growth. The p-type active region 013 is formed in the same way.

[0088] Specifically, in this embodiment, in step nine, a layer of SiO2 is deposited using low-pressure chemical vapor deposition (LPCVD). The device structure after forming the n-type active region 012 and the p-type active region 013 in step nine is as follows... Figure 20 As shown.

[0089] For example, step ten includes: BPSG material was deposited on the entire substrate surface using a CVD process to form a dielectric layer 014.

[0090] The dielectric layer 014 is etched using nitric acid and hydrofluoric acid to form NMOS source-drain contact holes and PMOS source-drain contact holes.

[0091] Electron beam evaporation is used to deposit metal WO15 on the entire substrate surface to form source and drain contacts.

[0092] Selective etching is used to etch the metal W015 in a designated area, and planarization is performed using CMP.

[0093] SiN material 016 is deposited on the entire substrate surface using CVD technology to passivate the dielectric and form a semiconductor device with an asymmetric L-type Schottky contact.

[0094] Specifically, in this embodiment, in step ten, 30-50 nm of BPSG material is deposited on the entire substrate surface using a CVD process to form a dielectric layer 014. For example... Figure 21As shown.

[0095] The device structure after forming NMOS source-drain contacts and PMOS source-drain contacts is as follows: Figure 22 As shown.

[0096] A 20 nm thick layer of WO15 metal was deposited across the entire substrate surface using electron beam evaporation to form source / drain contacts. For example... Figure 23 As shown.

[0097] The device structure after planarization using CMP process is as follows: Figure 24 As shown.

[0098] A 20-30 nm thick layer of SiN material (016) is deposited on the entire substrate surface using CVD technology to passivate the dielectric and form an asymmetric L-type Schottky contact semiconductor device, known as an asymmetric L-type Schottky contact Wavy SOI FinFET device. For example... Figure 1 As shown.

[0099] The embodiments of this application construct an asymmetric L-shaped isolation sidewall, which makes the device more effective at preventing charge movement during heavy ion incident, with lower transient current peak and collected charge, better resistance to single-event effects and a wider voltage range.

[0100] The semiconductor device with the asymmetric L-type Schottky contact obtained in this application has an inverted T-type structure. Combined with strained silicon technology, it can improve the carrier migration efficiency and thus improve the driving capability of the device, while also being compatible with Si technology.

[0101] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0102] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A semiconductor device based on an asymmetric L-type Schottky contact, characterized in that, include: Si substrate, buried oxide layer, differentiated gate, asymmetric L-shaped isolation sidewall, source / drain contact, passivation layer; The buried oxide layer is buried below the surface of the Si substrate. The Si substrate is divided into N-wells and P-wells. The N-wells are provided with n-type active regions, and the P-wells are provided with p-type active regions. The differentiated gate is disposed above the n-type active region and the p-type active region, and the asymmetric L-type isolation sidewall is disposed on both sides of the differentiated gate; The polysilicon of the differentiated gate forms a Schottky contact with the gate metal, and the Schottky contact and the MOS region form a Schottky-MOS hybrid structure; The source-drain contacts are located at the source-drain terminals of the n-type active region and the p-type active region; The passivation layer is disposed on the upper surface of the entire device, which consists of a Si substrate, a buried oxide layer, a differentiated gate, an asymmetric L-shaped isolation sidewall, and source / drain contacts.

2. A method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact, used to fabricate the semiconductor device based on an asymmetric L-type Schottky contact as described in claim 1, characterized in that, Includes the following steps: Step 1: Select a Si substrate, implant oxygen ions to form an SOI substrate with a buried oxide layer; Step 2: Shallow trench isolation STI fabrication and CMP planarization are performed on the SOI substrate; Step 3: Prepare the N-well, P-well, and contact region; Step 4: Stack differentiated gate dielectric layers for the PMOS and NMOS regions; Step 5: Form a differentiated gate through deposition and etching; Step six: Asymmetric L-shaped isolation sidewalls are formed through deposition and etching; Step 7: Form the LDD structure through photolithography and ion implantation; Step 8: Prepare a Schottky-MOS hybrid structure by deposition; Step nine: Form n-type and p-type active regions through epitaxial growth; Step 10: Perform source / drain contact metallization and device passivation to obtain a semiconductor device with an asymmetric L-type Schottky contact.

3. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, In step two, the shallow trench isolation STI fabrication includes: growing a layer of SiO2 on a cleaned SOI substrate, then depositing a layer of Si3N4, and forming a shallow trench isolation STI by photolithography and etching; The CMP planarization includes: depositing SiO2 using CMP technology, followed by planarization.

4. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step three includes: Remove the SiO2 grown and Si3N4 deposited in step two, and form N-wells and P-wells by photolithography and ion implantation; The buried oxide layer at the N-well and P-well contact is removed by photolithography and etching; The contact region between N-wells and P-wells is grown by selective epitaxy.

5. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step four includes: Deposition of SiON, HfSiON, La2O3, and TiN metal capping layers; The gate dielectric layer of the PMOS region is removed by photolithography and etching. SiON, HfSiON, Al2O3, and TiN metal capping layers are deposited, and the gate dielectric layer deposited in the NMOS region is removed by photolithography and etching.

6. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step five includes: Polysilicon is deposited above the differentiated gate dielectric layer; SiO2 is deposited on top of polycrystalline silicon; Hard mask layers are formed through photolithography and etching; Differentiated gates are formed by etching.

7. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step six includes: High-k gate dielectric material, including HfO2, is deposited and etched to form isolation sidewalls. At the same time, an asymmetric structure is formed, with one side being L-shaped and the other side remaining normal, resulting in an asymmetric L-shaped isolation sidewall.

8. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step eight includes: Deposit gate metal, and the gate metal forms a Schottky contact with polysilicon to form a Schottky gate; The MOS structure on the fin of the fin field-effect transistor is retained, forming a Schottky-MOS hybrid structure.

9. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step nine includes: A layer of SiO2 is deposited, and the SiO2 in the NMOS region is removed by photolithography and etching. The Si substrate is etched by selective etching back to form a groove in the n-active region. The n-type active region of strained silicon material SiC is formed by epitaxial growth. The p-type active region is formed in the same way.

10. The method for fabricating a semiconductor device based on an asymmetric L-type Schottky contact according to claim 2, characterized in that, Step ten includes: BPSG material is deposited on the entire substrate surface using CVD technology to form a dielectric layer; The dielectric layer is etched using nitric acid and hydrofluoric acid to form NMOS source-drain contact holes and PMOS source-drain contact holes; Metal W is deposited on the entire substrate surface using electron beam evaporation to form source / drain contacts; Selective etching is used to etch the metal W in a designated area, and CMP is used to planarize it. SiN material is deposited on the entire substrate surface using CVD technology to passivate the dielectric and form a semiconductor device with an asymmetric L-type Schottky contact.

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