Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device according to one embodiment of the present application includes: a step of preparing a silicon substrate having a first main surface; a step of forming a silicon oxide film on the first main surface of the silicon substrate; a step of forming an amorphous silicon film on the silicon oxide film; a step of forming a metal layer on the amorphous silicon film; a step of converting the amorphous silicon film into a crystalline silicon film by annealing the silicon substrate on which the metal layer is formed; a step of forming a transistor in which a part of the crystalline silicon film serves as a channel; and a step of forming a capacitor adjacent to the transistor and electrically connected to the transistor in a direction perpendicular to the first main surface.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a semiconductor device. Background Technology

[0002] A technique is known in which an amorphous silicon film and a metal film are sequentially formed on a substrate and then annealed at a specified temperature to transform the amorphous silicon film into a crystalline silicon film (for example, see Patent Documents 1 and 2).

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2006-303218 Patent Document 2: Japanese Patent Application Publication No. 2002-313719 Summary of the Invention The problem that the invention aims to solve The present invention provides a technique for forming a semiconductor device comprising a transistor having a portion of a crystalline silicon film as a channel without using an SOI (Silicon On Insulator) substrate.

[0004] Methods for solving problems A method for manufacturing a semiconductor device according to an embodiment of the present invention includes: a step of preparing a silicon substrate having a first main surface; a step of forming a silicon oxide film on the first main surface of the silicon substrate; a step of forming an amorphous silicon film on the silicon oxide film; a step of forming a metal layer on the amorphous silicon film; a step of annealing the silicon substrate on which the metal layer is formed to transform the amorphous silicon film into a crystalline silicon film; a step of forming a transistor having a portion of the crystalline silicon film as a channel; and a step of forming a capacitor adjacent to and electrically connected to the transistor in a direction perpendicular to the first main surface.

[0005] The effects of the invention According to the present invention, a semiconductor device comprising a transistor having a portion of a crystalline silicon film as a channel can be formed without using an SOI substrate. Attached Figure Description

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[0042] Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the drawings, the same or corresponding components or parts are given the same or corresponding reference numerals, and repeated descriptions are omitted.

[0043] [First Implementation] Reference Figures 1 to 12 The manufacturing method of the semiconductor device 1 according to the first embodiment will be described. Figures 1 to 12This is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the first embodiment.

[0044] First, such as Figure 1 As shown, a silicon substrate 112 is prepared. The silicon substrate 112 has a first main surface 112a and a second main surface 112b. The second main surface 112b is the surface opposite to the first main surface 112a. In this embodiment, the silicon substrate 112 is a single-crystal silicon substrate.

[0045] Next, as Figure 2 As shown, a silicon oxide film 114, an amorphous silicon film 116, and a metal layer 118 are sequentially formed on the first main surface 112a of the silicon substrate 112. In this embodiment, firstly, a silicon oxide film 114 is formed on the first main surface 112a of the silicon substrate 112 by chemical vapor deposition (CVD), thermal oxidation, or the like. Next, an amorphous silicon film 116 is formed on the silicon oxide film 114 by CVD or the like. Then, a metal layer 118 is formed on the amorphous silicon film 116 by CVD, physical vapor deposition (PVD), or the like. The metal layer 118 is formed, for example, by nickel (Ni), nickel-aluminum alloy (Ni-Al), cobalt (Co), or palladium (Pd). Alloying annealing may then be performed. As a result, at least a portion of the metal layer 118 reacts with the silicon (Si) constituting the amorphous silicon film 116 to form a silicide.

[0046] Next, as Figure 3 As shown, the amorphous silicon film 116 is transformed into a crystalline silicon film 120 by annealing the silicon substrate 112 on which the metal layer 118 is formed. In this embodiment, the amorphous silicon film 116 is crystallized to form the crystalline silicon film 120 by means of metal-induced crystallization (MIC) or metal-induced lateral crystallization (MILC). Specifically, the silicon substrate 112 on which the metal layer 118 is formed is annealed at a specified temperature in an inert gas atmosphere. As a result, the metal constituting the metal layer 118 diffuses into the amorphous silicon film 116, and the amorphous silicon film 116 is crystallized by metal-induced crystallization or metal-induced lateral crystallization with the metal diffused into the amorphous silicon film 116 as the crystal nucleus, thereby forming the crystalline silicon film 120. At this time, the metal constituting the metal layer 118 may also diffuse into the silicon oxide film 114. Then, the metal layer 118 is removed by means of wet etching or the like.

[0047] Next, as Figure 4As shown, the crystalline silicon film 120 is processed into a columnar shape. In this embodiment, firstly, a thin film for a hard mask 122 is formed on the crystalline silicon film 120 by CVD or the like. The thin film for the hard mask 122 is, for example, a SiN film or a SiO2 film. Next, a photoresist mask with openings is formed by photolithography, the openings being areas other than the areas where the crystalline silicon film 120 remains. Next, the crystalline silicon film 120 is removed by etching using the photoresist mask. Then, the photoresist mask is removed. Thus, the crystalline silicon film 120 is processed into a columnar shape extending in a direction perpendicular to the first main surface 112a.

[0048] Next, as Figure 5 As shown, a gate stack structure is formed. In this embodiment, firstly, an insulating film 124 is formed on the silicon oxide film 114. The insulating film 124 is, for example, a SiN film, a SiOCN film, or a SiOC film. Next, an insulating film 126a for the gate insulating film 126 is formed on the side surface of the crystalline silicon film 120 by thermal oxidation, ALD, or the like. The insulating film 126a is, for example, a SiO2 film or a High-k film. Next, a metal film 128a for the gate electrode 128 is formed to cover the crystalline silicon film 120, the hard mask 122, the insulating film 124, and the insulating film 126a. The metal film 128a is, for example, formed of tungsten (W), cobalt, or molybdenum (Mo).

[0049] Next, as Figure 6 As shown, a gate insulating film 126 and a gate electrode 128 are formed. In this embodiment, firstly, the insulating film 126a and the metal film 128a are etched by means of etching back, leaving the insulating film 126a and the metal film 128a on a portion of the side surface of the crystalline silicon film 120. Next, the hard mask 122 is etched away by means of wet etching, dry etching, etc. Then, the insulating film 124 is etched away by means of wet etching, dry etching, etc. Thus, the gate insulating film 126 is formed from the insulating film 126a, and the gate electrode 128 is formed from the metal film 128a. The gate insulating film 126 and the gate electrode 128 are formed, for example, in the central portion of the crystalline silicon film 120 in a direction perpendicular to the first main surface 112a. The gate electrode 128 is electrically connected to a word line (not shown).

[0050] Next, as Figure 7As shown, an interlayer insulating film 130 is formed. In this embodiment, firstly, an insulating film for the interlayer insulating film 130 is formed to cover the silicon oxide film 114, the crystalline silicon film 120, the gate insulating film 126, and the gate electrode 128. The insulating film for the interlayer insulating film 130 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, the upper surface of the crystalline silicon film 120 is exposed by chemical mechanical polishing (CMP). Thus, the interlayer insulating film 130 is formed. Next, ion implantation is performed on the bit line 138 side of the crystalline silicon film 120. For example, a source region (not shown) is formed by ion implantation. In the ion implantation used to form the source region, ions of n-type impurities such as arsenic (As) and phosphorus (P) are implanted, for example. The source region is electrically connected to the bit line 138. Next, activation annealing is performed by RTA (Rapid Thermal Annealing), a furnace, or the like.

[0051] Next, as Figure 8 As shown, bit line 138 is formed. In this embodiment, firstly, an insulating film for interlayer insulating film 132 is formed on the crystalline silicon film 120 and the interlayer insulating film 130. The insulating film for interlayer insulating film 132 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 120 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 132 is etched away by dry etching or the like. As a result, a via 134 is formed, exposing the crystalline silicon film 120. Next, a metal film is formed to fill the via 134, and the surface is planarized by CMP or the like. As a result, a metal film 136 is formed inside the via 134. The metal film 136 is formed, for example, from titanium nitride (TiN), tungsten, cobalt, molybdenum, or ruthenium (Ru). Next, an insulating film (not shown) for insulating between bit lines 138 is formed on the interlayer insulating film 132 and the metal film 136. The insulating film for the interlayer insulating film is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings in the areas where bit lines 138 are to be formed is formed using photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms trenches exposing the interlayer insulating film 132 and the metal film 136. Next, a metal film for the bit lines 138 is formed to fill the trenches, and the surface is planarized by CMP or the like. This forms the bit lines 138 inside the trenches. The bit lines 138 are formed of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 140 is formed on the bit lines 138 and the interlayer insulating film for insulating between the bit lines 138. The interlayer insulating film 140 is, for example, a SiO2 film, a SiOCN film, or a SiOC film.

[0052] Next, as Figure 9 As shown, the first main surface 112a of the first substrate 110, to which the interlayer insulating film 140 has been formed, is bonded to a pre-prepared second substrate 190. In this embodiment, the second substrate 190 is a CMOS (Complementary Metal Oxide Semiconductor) substrate. The second substrate 190 has a CMOS portion 192 and a wiring portion 194. The CMOS portion 192 includes a silicon substrate 192a and a plurality of transistors 192b. The plurality of transistors 192b includes P-type transistors and N-type transistors. The wiring portion 194 includes wiring 194a and an interlayer insulating film 194b. The wiring 194a is formed in multiple layers. The interlayer insulating film 194b provides insulation between the wiring 194a. The first substrate 110 and the second substrate 190 are bonded such that the interlayer insulating film 140 contacts the wiring portion 194.

[0053] Next, as Figure 10As shown, the first substrate 110 is thinned by removing the silicon substrate 112 and the silicon oxide film 114 from the second main surface 112b side of the silicon substrate 112. In this embodiment, the silicon substrate 112 is first ground from the second main surface 112b side by sequential grinding and CMP. Then, the silicon substrate 112 is selectively etched away relative to the silicon oxide film 114 by wet etching, dry etching, or the like. Alternatively, the silicon substrate 112 can be removed by laser lift-off or by using a laser-based lift-off technique. When using laser lift-off, for example, a release layer is provided between the silicon substrate 112 and the silicon oxide film 114, and the release layer is removed by laser irradiation, thereby removing the silicon substrate 112 together with the release layer. When using a laser-based lift-off technique, for example, a modification layer is formed inside the silicon substrate 112 by laser irradiation, and the silicon substrate 112 is removed starting from the modification layer. Next, the silicon oxide film 114 is selectively etched away relative to the crystalline silicon film 120 and the interlayer insulating film 130. In this case, since any metal that may diffuse into the silicon oxide film 114 is removed along with the silicon oxide film 114, it will not remain in the final semiconductor device 1. Furthermore, it is easy to uniformize the length of the columnar crystalline silicon film 120 that does not overlap with the gate electrode 128 over the entire first substrate 110. In contrast, if etching is not selectively applied and the length of the crystalline silicon film 120 is controlled by stopping the etching midway, it is difficult to uniformize the length of the columnar crystalline silicon film 120 that does not overlap with the gate electrode 128 over the entire first substrate 110. Next, ion implantation is performed on the capacitor 160 side of the crystalline silicon film 120. For example, a drain region (not shown) is formed by ion implantation. Thus, a transistor 142 is formed that forms a channel (not shown) between the source region and the drain region of the crystalline silicon film 120. In the ion implantation used to form the drain region, ions of n-type impurities such as arsenic and phosphorus are implanted, for example. The drain region is electrically connected to capacitor 160. Next, activation annealing is performed using an RTA (Radio-Temperature Aerator) and a heating furnace.

[0054] Next, as Figure 11As shown, pads 154 for capacitor 160 are formed. In this embodiment, firstly, an insulating film for interlayer insulating film 144 is formed on the crystalline silicon film 120 and the interlayer insulating film 130. The insulating film for interlayer insulating film 144 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 120 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 144 is etched away by dry etching or the like. This forms a via 146 that exposes the crystalline silicon film 120. Next, a metal film is formed to fill the via 146, and the surface is planarized by CMP or the like. This forms a metal film 148 inside the via 146. The metal film 148 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for interlayer insulating film 150 is formed on the interlayer insulating film 144 and the metal film 148. The insulating film used for the interlayer insulating film 150 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the metal film 148 using photolithography. Then, using the photoresist mask, the insulating film used for the interlayer insulating film 150 is etched away by dry etching or the like. This forms an opening 152 that exposes the metal film 148. Next, a metal film is formed to fill the opening 152, and the surface is planarized using CMP or the like. This forms a pad 154 inside the opening 152. The pad 154 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0055] Next, as Figure 12 As shown, a capacitor 160 is formed adjacent to and electrically connected to the transistor 142 in a direction perpendicular to the first main surface 112a. In this embodiment, firstly, an insulating film for the interlayer insulating film 156 is formed on the interlayer insulating film 150 and the pad 154. The insulating film for the interlayer insulating film 156 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with an opening is formed on the pad 154 by photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film 156 is etched away by dry etching or the like. As a result, a capacitor hole 158 is formed that exposes the pad 154. Next, a capacitor 160 is formed inside the capacitor hole 158. The capacitor 160 has, for example, a structure in which an insulating film is sandwiched between metal films. Next, an insulating film 162 is formed covering the upper surface of the interlayer insulating film 156 and the upper surface of the capacitor 160.

[0056] Through the above processes, the semiconductor device 1 of the first embodiment is manufactured. The semiconductor device 1 is configured as a DRAM (Dynamic Random Access Memory) having a plurality of memory cells 164. Each memory cell 164 includes a transistor 142 and a capacitor 160 connected in series.

[0057] As described above, according to the manufacturing method of the semiconductor device 1 of the first embodiment, firstly, a silicon substrate 112 having a first main surface 112a is prepared. Next, a silicon oxide film 114, an amorphous silicon film 116, and a metal layer 118 are sequentially formed on the first main surface 112a of the silicon substrate 112. Then, by annealing the silicon substrate 112 on which the metal layer 118 is formed, the amorphous silicon film 116 is transformed into a crystalline silicon film 120. Next, a transistor 142 with a portion of the crystalline silicon film 120 serving as a channel is formed. Next, a capacitor 160 is formed adjacent to and electrically connected to the transistor 142 in a direction perpendicular to the first main surface 112a. In this case, a semiconductor device 1 including a transistor 142 with a portion of the crystalline silicon film 120 serving as a channel can be formed without using an SOI substrate.

[0058] [Second Implementation] Reference Figures 13 to 23 The manufacturing method of the semiconductor device 2 according to the second embodiment will be described. Figures 13 to 23 This is a cross-sectional view showing a method for manufacturing the semiconductor device 2 according to the second embodiment.

[0059] First, such as Figure 13 As shown, a silicon substrate 212 is prepared. The silicon substrate 212 has a first main surface 212a and a second main surface 212b. The second main surface 212b is the surface opposite to the first main surface 212a. In this embodiment, the silicon substrate 212 is a single-crystal silicon substrate.

[0060] Next, as Figure 14 As shown, a silicon oxide film 214, an amorphous silicon film 216, and a metal layer 218 are sequentially formed on the first main surface 212a of the silicon substrate 212. In this embodiment, firstly, a silicon oxide film 214 is formed on the first main surface 212a of the silicon substrate 212 by CVD, thermal oxidation, or the like. Next, an amorphous silicon film 216 is formed on the silicon oxide film 214 by CVD or the like. The amorphous silicon film 216 is deposited to be thicker than the crystalline silicon film 220 remaining in the final semiconductor device 2. For example, the thickness of the amorphous silicon film 216 can be more than twice the thickness of the crystalline silicon film 220 remaining in the final semiconductor device 2. Next, a metal layer 218 is formed on the amorphous silicon film 216 by CVD, PVD, or the like. The metal layer 218 can be formed in the same manner as the metal layer 118.

[0061] Next, as Figure 15 As shown, the amorphous silicon film 216 is transformed into a crystalline silicon film 220 by annealing the silicon substrate 212 on which the metal layer 218 is formed. The crystalline silicon film 220 can be formed in the same manner as the crystalline silicon film 120.

[0062] Next, as Figure 16 As shown, the crystalline silicon film 220 is processed into a columnar shape. In this embodiment, firstly, a thin film for a hard mask 222 is formed on the crystalline silicon film 220 by CVD or the like. The thin film for the hard mask 222 is, for example, a SiN film or a SiO2 film. Next, a photoresist mask with openings is formed by photolithography, the openings being areas other than the areas where the crystalline silicon film 220 remains. Next, the crystalline silicon film 220 is removed by etching using the photoresist mask. Then, the photoresist mask is removed. Thus, the crystalline silicon film 220 is processed into a columnar shape extending in a direction perpendicular to the first main surface 212a.

[0063] Next, as Figure 17 As shown, a gate insulating film 226 and a gate electrode 228 are formed. The gate insulating film 226 and the gate electrode 228 can be formed in the same manner as the gate insulating film 126 and the gate electrode 128. The gate insulating film 226 and the gate electrode 228 are formed, for example, in the central portion of the crystalline silicon film 220 along a direction perpendicular to the first main surface 212a.

[0064] Next, as Figure 18 As shown, an interlayer insulating film 230 is formed. In this embodiment, firstly, an insulating film for the interlayer insulating film 230 is formed to cover the silicon oxide film 214, the crystalline silicon film 220, the gate insulating film 226, and the gate electrode 228. The insulating film for the interlayer insulating film 230 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, the upper surface of the crystalline silicon film 220 is exposed by CMP or the like. Thus, the interlayer insulating film 230 is formed. At this time, the crystalline silicon film 220 is ground to near the gate electrode 228 to reduce the film thickness. In this case, the area near the starting region of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 220 is removed. Problems of poor crystallinity or uneven crystallinity are prone to occur near the starting region of metal-induced crystallization or metal-induced lateral crystallization. Therefore, by removing the area near the starting region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 220 with good crystallinity can be used as a channel. Next, ion implantation is performed on the bit line 238 side of the crystalline silicon film 220. For example, a source region (not shown) is formed by ion implantation. In ion implantation used to form the source region, ions of n-type impurities such as arsenic or phosphorus are implanted, for example. The source region is electrically connected to bit line 238. Next, activation annealing is performed using an RTA (Regenerative Thermal Aerator), a heating furnace, or the like.

[0065] Next, as Figure 19As shown, bit line 238 is formed. In this embodiment, firstly, an insulating film for interlayer insulating film 232 is formed on the crystalline silicon film 220 and the interlayer insulating film 230. The insulating film for interlayer insulating film 232 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 220 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 232 is etched away by dry etching or the like. As a result, a via 234 is formed, exposing the crystalline silicon film 220. Next, a metal film is formed to fill the via 234, and the surface is planarized by CMP or the like. As a result, a metal film 236 is formed inside the via 234. The metal film 236 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film (not shown) for insulating between bit lines 238 is formed on the interlayer insulating film 232 and the metal film 236. The insulating film for the interlayer insulating film is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings in the areas where bit lines 238 are to be formed is formed using photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms trenches that expose the interlayer insulating film 232 and the metal film 236. Next, a metal film for the bit lines 238 is formed to fill the trenches, and the surface is planarized by CMP or the like. This forms the bit lines 238 inside the trenches. The bit lines 238 are formed of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 240 is formed on the bit lines 238 and the interlayer insulating film for insulating between the bit lines 238. Interlayer insulating film 240 is, for example, SiO2 film, SiOCN film, or SiOC film.

[0066] Next, as Figure 20 As shown, the first main surface 212a side of the first substrate 210, to which the interlayer insulating film 240 has been formed, is bonded to a pre-prepared second substrate 290. In this embodiment, the second substrate 290 is a CMOS substrate. The second substrate 290 has a CMOS portion 292 and a wiring portion 294. The CMOS portion 292 includes a silicon substrate 292a and a plurality of transistors 292b. The plurality of transistors 292b includes P-type transistors and N-type transistors. The wiring portion 294 includes wiring 294a and an interlayer insulating film 294b. The wiring 294a is formed in multiple layers. The interlayer insulating film 294b provides insulation between the wiring 294a. The first substrate 210 and the second substrate 290 are bonded such that the interlayer insulating film 240 contacts the wiring portion 294.

[0067] Next, as Figure 21As shown, the first substrate 210 is thinned by removing a portion of the silicon substrate 212, silicon oxide film 214, crystalline silicon film 220, and interlayer insulating film 230 from the second main surface 212b side of the silicon substrate 212. In this embodiment, firstly, the silicon substrate 212, silicon oxide film 214, a portion of the crystalline silicon film 220, and a portion of the interlayer insulating film 230 are removed from the second main surface 212b side by sequential grinding and CMP. In this case, since any metal that may diffuse into the silicon oxide film 214 is removed along with the silicon oxide film 214, it will not remain in the final semiconductor device 2. When grinding a portion of the crystalline silicon film 220, the crystalline silicon film 220 is ground to the vicinity of the gate electrode 228 to reduce the film thickness. In this case, the area near the endpoint of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 220 is removed. Problems of poor crystallinity or uneven crystallinity are prone to occur near the endpoint of metal-induced crystallization or metal-induced lateral crystallization. Therefore, by removing the area near the endpoint of metal-induced crystallization or metal-induced lateral crystallization, a highly crystalline silicon film 220 can be used as a channel. Next, ion implantation is performed on the capacitor 260 side of the silicon film 220. For example, a drain region (not shown) is formed by ion implantation. Thus, a transistor 242 is formed, with the source and drain regions of the silicon film 220 forming a channel (not shown). In the ion implantation used to form the drain region, ions of n-type impurities such as arsenic and phosphorus are implanted, for example. The drain region is electrically connected to the capacitor 260. Next, activation annealing is performed using an RTA, a heating furnace, or the like.

[0068] Next, as Figure 22As shown, pads 254 for capacitor 260 are formed. In this embodiment, firstly, an insulating film for interlayer insulating film 244 is formed on the crystalline silicon film 220 and the interlayer insulating film 230. The insulating film for interlayer insulating film 244 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 220 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 244 is etched away by dry etching or the like. This forms vias 246 that expose the crystalline silicon film 220. Next, a metal film is formed to fill the vias 246, and the surface is planarized by CMP or the like. This forms a metal film 248 inside the vias 246. The metal film 248 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for interlayer insulating film 250 is formed on the interlayer insulating film 244 and the metal film 248. The insulating film used for the interlayer insulating film 250 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the metal film 248 using photolithography. Then, using the photoresist mask, the insulating film used for the interlayer insulating film 250 is etched away by dry etching or the like. This forms an opening 252 that exposes the metal film 248. Next, a metal film is formed to fill the opening 252, and the surface is planarized using CMP or the like. This forms a pad 254 inside the opening 252. The pad 254 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0069] Next, as Figure 23 As shown, a capacitor 260 is formed adjacent to and electrically connected to the transistor 242 in a direction perpendicular to the first main surface 212a. In this embodiment, firstly, an insulating film for the interlayer insulating film 256 is formed on the interlayer insulating film 250 and the pad 254. The insulating film for the interlayer insulating film 256 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the pad 254 by photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film 256 is etched away by dry etching or the like. As a result, a capacitor hole 258 is formed that exposes the pad 254. Next, a capacitor 260 is formed inside the capacitor hole 258. The capacitor 260 has, for example, a structure in which an insulating film is sandwiched between metal films. Next, an insulating film 262 is formed covering the upper surface of the interlayer insulating film 256 and the upper surface of the capacitor 260.

[0070] Through the above processes, the semiconductor device 2 of the second embodiment is manufactured. The semiconductor device 2 is configured as a DRAM having a plurality of memory cells 264. Each memory cell 264 includes a transistor 242 and a capacitor 260 connected in series.

[0071] As described above, according to the manufacturing method of the semiconductor device 2 of the second embodiment, firstly, a silicon substrate 212 having a first main surface 212a is prepared. Next, a silicon oxide film 214, an amorphous silicon film 216, and a metal layer 218 are sequentially formed on the first main surface 212a of the silicon substrate 212. Then, by annealing the silicon substrate 212 on which the metal layer 218 is formed, the amorphous silicon film 216 is transformed into a crystalline silicon film 220. Next, a transistor 242 with a portion of the crystalline silicon film 220 serving as a channel is formed. Next, a capacitor 260 is formed adjacent to and electrically connected to the transistor 242 in a direction perpendicular to the first main surface 212a. In this case, a semiconductor device 2 including a transistor 242 with a portion of the crystalline silicon film 220 serving as a channel can be formed without using an SOI substrate.

[0072] Furthermore, according to the manufacturing method of the semiconductor device 2 in the second embodiment, the areas near the starting and ending regions of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 220 are removed. In this case, the crystalline silicon film 220 with good crystallinity can be used as a channel.

[0073] [Third Implementation] Reference Figures 24 to 36 The manufacturing method of the semiconductor device 3 according to the third embodiment will be described. Figures 24 to 36 This is a cross-sectional view showing a method for manufacturing the semiconductor device 3 according to the third embodiment.

[0074] First, such as Figure 24 As shown, a silicon substrate 312 is prepared. The silicon substrate 312 has a first main surface 312a and a second main surface 312b. The second main surface 312b is the surface opposite to the first main surface 312a. In this embodiment, the silicon substrate 312 is a single-crystal silicon substrate.

[0075] Next, as Figure 25 As shown, a silicon oxide film 314 and an amorphous silicon film 316 are sequentially formed on the first main surface 312a of the silicon substrate 312. In this embodiment, firstly, a silicon oxide film 314 is formed on the first main surface 312a of the silicon substrate 312 by CVD, thermal oxidation, or the like. Next, an amorphous silicon film 316 is formed on the silicon oxide film 314 by CVD or the like. The amorphous silicon film 316 is deposited to, for example, the same thickness as the amorphous silicon film 216.

[0076] Next, as Figure 26As shown, the amorphous silicon film 316 is processed into a columnar shape. In this embodiment, firstly, a thin film for a hard mask 322 is formed on the amorphous silicon film 316 by CVD or the like. The thin film for the hard mask 322 is, for example, a SiN film or a SiO2 film. Next, a photoresist mask with openings is formed by photolithography, the openings being areas other than the areas where the amorphous silicon film 316 remains. Then, the amorphous silicon film 316 is etched away using the photoresist mask. Finally, the photoresist mask is removed. Thus, the amorphous silicon film 316 is processed into a columnar shape extending in a direction perpendicular to the first main surface 312a.

[0077] Next, as Figure 27 As shown, a getter film 372 and a metal layer 318 are formed. In this embodiment, firstly, the hard mask 322 is etched away by wet etching, dry etching, or the like. Next, a thin film for the getter film 372 is formed to cover the side and top surfaces of the amorphous silicon film 316. The thin film for the getter film 372 is, for example, a SiO2 film, a SiN film, or a polycrystalline silicon film with added impurities. Next, the top surface of the amorphous silicon film 316 is exposed by CMP or the like. Thus, the getter film 372 is formed. Next, a metal layer 318 is formed on the amorphous silicon film 316 and the getter film 372 by CVD, PVD, or the like. The metal layer 318 can be formed in the same manner as the metal layer 118.

[0078] Next, as Figure 28 As shown, an amorphous silicon film 316 is transformed into a crystalline silicon film 320 by annealing a silicon substrate 312 on which a metal layer 318 is formed. In this embodiment, the amorphous silicon film 316 is crystallized to form a crystalline silicon film 320 by metal-induced crystallization, metal-induced lateral crystallization, etc. Specifically, the silicon substrate 312 on which the metal layer 318 is formed is annealed at a specified temperature in an inert gas atmosphere. As a result, the metal constituting the metal layer 318 diffuses into the amorphous silicon film 316, and the amorphous silicon film 316 is crystallized by metal-induced crystallization or metal-induced lateral crystallization using the metal diffused into the amorphous silicon film 316 as crystal nuclei, thereby forming a crystalline silicon film 320. At this time, the metal constituting the metal layer 318 may remain in the crystalline silicon film 320. By annealing, the residual metal diffuses from the crystalline silicon film 320 into the silicon oxide film 114 and the getter film 372, thereby reducing the concentration of the residual metal in the crystalline silicon film 320. As a result, the reliability of the transistor 342, which uses the crystalline silicon film 320 as the channel, can be improved. Next, the metal layer 318 is removed by wet etching or the like.

[0079] Next, as Figure 29 As shown, the getter film 372 is removed by etching using dry etching, wet etching, or other methods. This prevents the metal in the getter film 372 from re-entering the crystalline silicon film 320.

[0080] Next, as Figure 30 As shown, a gate insulating film 326 and a gate electrode 328 are formed. The gate insulating film 326 and the gate electrode 328 can be formed in the same manner as the gate insulating film 126 and the gate electrode 128. The gate insulating film 326 and the gate electrode 328 are formed, for example, in the central portion of the crystalline silicon film 320 along a direction perpendicular to the first main surface 312a.

[0081] Next, as Figure 31 As shown, an interlayer insulating film 330 is formed. In this embodiment, firstly, an insulating film for the interlayer insulating film 330 is formed to cover the silicon oxide film 314, the crystalline silicon film 320, the gate insulating film 326, and the gate electrode 328. The insulating film for the interlayer insulating film 330 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, the upper surface of the crystalline silicon film 320 is exposed by CMP or the like. Thus, the interlayer insulating film 330 is formed. At this time, the crystalline silicon film 320 is ground to near the gate electrode 328 to reduce the film thickness. In this case, the area near the starting region of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 320 is removed. Problems of poor crystallinity or uneven crystallinity are prone to occur near the starting region of metal-induced crystallization or metal-induced lateral crystallization. Therefore, by removing the area near the starting region of metal-induced crystallization or metal-induced lateral crystallization, the crystalline silicon film 320 with good crystallinity can be used as a channel. Next, ion implantation is performed on the bit line 338 side of the crystalline silicon film 320. For example, a source region (not shown) is formed by ion implantation. In ion implantation used to form the source region, ions of n-type impurities such as arsenic or phosphorus are implanted, for example. The source region is electrically connected to bit line 338. Next, activation annealing is performed using an RTA (Regenerative Thermal Aerator), a heating furnace, or the like.

[0082] Next, as Figure 32As shown, bit line 338 is formed. In this embodiment, firstly, an insulating film for interlayer insulating film 332 is formed on the crystalline silicon film 320 and the interlayer insulating film 330. The insulating film for interlayer insulating film 332 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 320 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 332 is etched away by dry etching or the like. As a result, a via 334 is formed, exposing the crystalline silicon film 320. Next, a metal film is formed to fill the via 334, and the surface is planarized by CMP or the like. As a result, a metal film 336 is formed inside the via 334. The metal film 336 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film (not shown) for insulating between bit lines 338 is formed on the interlayer insulating film 332 and the metal film 336. The insulating film for the interlayer insulating film is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings in the areas where bit lines 338 are to be formed is formed using photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film is etched by dry etching or the like. This forms trenches that expose the interlayer insulating film 332 and the metal film 336. Next, a metal film for the bit lines 338 is formed to fill the trenches, and the surface is planarized by CMP or the like. This forms the bit lines 338 inside the trenches. The bit lines 338 are formed of titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an interlayer insulating film 340 is formed on the bit lines 338 and the interlayer insulating film for insulating between the bit lines 338. Interlayer insulating film 340 is, for example, SiO2 film, SiOCN film, or SiOC film.

[0083] Next, as Figure 33 As shown, the first main surface 312a side of the first substrate 310, to which the interlayer insulating film 340 has been formed, is bonded to a pre-prepared second substrate 390. In this embodiment, the second substrate 390 is a CMOS substrate. The second substrate 390 has a CMOS portion 392 and a wiring portion 394. The CMOS portion 392 includes a silicon substrate 392a and a plurality of transistors 392b. The plurality of transistors 392b includes P-type transistors and N-type transistors. The wiring portion 394 includes wiring 394a and an interlayer insulating film 394b. The wiring 394a is formed in multiple layers. The interlayer insulating film 394b provides insulation between the wiring 394a. The first substrate 310 and the second substrate 390 are bonded such that the interlayer insulating film 340 contacts the wiring portion 394.

[0084] Next, as Figure 34As shown, the first substrate 310 is thinned by removing a portion of the silicon substrate 312, silicon oxide film 314, crystalline silicon film 320, and interlayer insulating film 330 from the second main surface 312b side of the silicon substrate 312. In this embodiment, firstly, the silicon substrate 312, silicon oxide film 314, a portion of the crystalline silicon film 320, and a portion of the interlayer insulating film 330 are removed from the second main surface 312b side by sequential grinding and CMP. In this case, since any metal that may diffuse into the silicon oxide film 314 is removed along with the silicon oxide film 314, it will not remain in the final semiconductor device 3. When grinding a portion of the crystalline silicon film 320, the crystalline silicon film 320 is ground to the vicinity of the gate electrode 328 to reduce the film thickness. In this case, the area near the endpoint of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 320 is removed. Problems of poor crystallinity or uneven crystallinity are prone to occur near the endpoint of metal-induced crystallization or metal-induced lateral crystallization. Therefore, by removing the area near the endpoint of metal-induced crystallization or metal-induced lateral crystallization, a highly crystalline silicon film 320 can be used as a channel. Next, ion implantation is performed on the capacitor 360 side of the silicon film 320. For example, a drain region (not shown) is formed by ion implantation. Thus, a transistor 342 is formed, with the source and drain regions of the silicon film 320 forming a channel (not shown). In the ion implantation used to form the drain region, ions of n-type impurities such as arsenic and phosphorus are implanted, for example. The drain region is electrically connected to the capacitor 360. Next, activation annealing is performed using an RTA, a heating furnace, or the like.

[0085] Next, as Figure 35As shown, pads 354 for capacitor 360 are formed. In this embodiment, firstly, an insulating film for interlayer insulating film 344 is formed on the crystalline silicon film 320 and the interlayer insulating film 330. The insulating film for interlayer insulating film 344 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the crystalline silicon film 320 by photolithography. Then, using the photoresist mask, the insulating film for interlayer insulating film 344 is etched away by dry etching or the like. This forms vias 346 that expose the crystalline silicon film 320. Next, a metal film is formed to fill the vias 346, and the surface is planarized by CMP or the like. This forms a metal film 348 inside the vias 346. The metal film 348 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium. Next, an insulating film for interlayer insulating film 350 is formed on the interlayer insulating film 344 and the metal film 348. The insulating film used for the interlayer insulating film 350 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with openings is formed on the metal film 348 using photolithography. Then, using the photoresist mask, the insulating film used for the interlayer insulating film 350 is etched away by dry etching or the like. This forms an opening 352 that exposes the metal film 348. Next, a metal film is formed to fill the opening 352, and the surface is planarized using CMP or the like. This forms a pad 354 inside the opening 352. The pad 354 is formed, for example, from titanium nitride, tungsten, cobalt, molybdenum, or ruthenium.

[0086] Next, as Figure 36 As shown, a capacitor 360 is formed adjacent to and electrically connected to the transistor 342 in a direction perpendicular to the first main surface 312a. In this embodiment, firstly, an insulating film for the interlayer insulating film 356 is formed on the interlayer insulating film 350 and the pad 354. The insulating film for the interlayer insulating film 356 is, for example, a SiO2 film, a SiOCN film, or a SiOC film. Next, a photoresist mask with an opening is formed on the pad 354 by photolithography. Then, using the photoresist mask, the insulating film for the interlayer insulating film 356 is etched away by dry etching or the like. As a result, a capacitor hole 358 is formed that exposes the pad 354. Next, a capacitor 360 is formed inside the capacitor hole 358. The capacitor 360 has, for example, a structure in which an insulating film is sandwiched between metal films. Next, an insulating film 362 is formed covering the upper surface of the interlayer insulating film 356 and the upper surface of the capacitor 360.

[0087] Through the above processes, the semiconductor device 3 of the third embodiment is manufactured. The semiconductor device 3 is configured as a DRAM having a plurality of memory cells 364. Each memory cell 364 includes a transistor 342 and a capacitor 360 connected in series.

[0088] As described above, according to the manufacturing method of the semiconductor device 3 of the third embodiment, firstly, a silicon substrate 312 having a first main surface 312a is prepared. Next, a silicon oxide film 314, an amorphous silicon film 316, and a metal layer 318 are sequentially formed on the first main surface 312a of the silicon substrate 312. Then, by annealing the silicon substrate 312 on which the metal layer 318 is formed, the amorphous silicon film 316 is transformed into a crystalline silicon film 320. Next, a transistor 342 with a portion of the crystalline silicon film 320 serving as a channel is formed. Next, a capacitor 360 is formed adjacent to and electrically connected to the transistor 342 in a direction perpendicular to the first main surface 312a. In this case, a semiconductor device 3 including a transistor 342 with a portion of the crystalline silicon film 320 serving as a channel can be formed without using an SOI substrate.

[0089] Furthermore, according to the manufacturing method of the semiconductor device 3 in the third embodiment, the areas near the starting and ending regions of metal-induced crystallization or metal-induced lateral crystallization in the crystalline silicon film 320 are removed. In this case, the crystalline silicon film 320 with good crystallinity can be used as a channel.

[0090] The embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The above embodiments may be omitted, substituted, and modified in various forms without departing from the scope and spirit of the appended claims.

[0091] This international application claims priority based on Japanese Patent Application No. 2023-194952, filed on November 16, 2023, the entire contents of which are incorporated herein by reference.

[0092] [Explanation of Labels in the Attached Image] 1, 2, 3 Semiconductor devices 112, 212, 312 silicon substrates 112a, 212a, 312a First Main Face 114, 214, 314 silicon dioxide films 116, 216, 316 amorphous silicon films 118, 218, 318 metal layers 120, 220, 320 crystalline silicon films 142, 242, 342 transistors 160, 260, 360 capacitors

Claims

1. A method for manufacturing a semiconductor device, comprising: The process of preparing a silicon substrate with a first main surface. The process of forming a silicon oxide film on the first main surface of the silicon substrate. The process of forming an amorphous silicon film on the silicon oxide film, In the process of forming a metal layer on the amorphous silicon film, The process of converting the amorphous silicon film into a crystalline silicon film by annealing the silicon substrate on which the metal layer is formed. The process of forming a transistor using a portion of the crystalline silicon film as a channel, and The process of forming a capacitor adjacent to the transistor in a direction perpendicular to the first main surface and electrically connected to the transistor.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the transistor comprises: The process of bonding the first main surface of the silicon substrate to the second silicon substrate, and The process of removing the silicon substrate and the silicon oxide film from the second main surface side, which is opposite to the first main surface of the silicon substrate bonded to the second silicon substrate.

3. The method for manufacturing a semiconductor device according to claim 2, wherein the second silicon substrate is a CMOS substrate.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the crystalline silicon film has a first side in contact with the silicon oxide film and a second side opposite to the first side. The process of forming the transistor includes grinding the second side of the crystalline silicon film to reduce the film thickness.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the step of forming the transistor, after the step of removing the silicon substrate and the silicon oxide film, includes a step of grinding the first surface of the crystalline silicon film to reduce the film thickness.

6. The method for manufacturing a semiconductor device according to claim 2, wherein the step of removing the silicon substrate and the silicon oxide film includes removing the silicon substrate by laser peeling or by using a laser peeling technique.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein between the step of converting the crystalline silicon film and the step of forming the transistor, there is a step of processing the crystalline silicon film into a columnar shape extending in a direction perpendicular to the first main surface.

8. The method of manufacturing a semiconductor device according to any one of claims 1 to 6, wherein between the step of forming the amorphous silicon film and the step of forming the metal layer, there is a step of processing the amorphous silicon film into a columnar shape extending in a direction perpendicular to the first main surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein between the step of processing into the columnar shape and the step of forming the metal layer, there is a step of forming a getter film covering the side surface of the amorphous silicon film.

10. The method for manufacturing a semiconductor device according to claim 9, wherein after the step of forming the metal layer, a step of removing the getter film is performed.

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