A register access system based on a common address

Abstract

This invention relates to the field of chip design technology, and more particularly to a register access system based on a shared address, comprising a host subsystem and a chip subsystem. The host subsystem includes one physical functional module and N virtual functional modules. The chip subsystem includes a protocol conversion module, a register on-chip network, and M IP modules. Each IP module corresponds to a register address space, each register address space contains one or more register addresses, each register address corresponds to a register group, and each register group includes N+1 registers. Each of the N+1 registers in each register group corresponds one-to-one with the physical functional module and the N virtual functional modules. The host subsystem sends a register access request to the protocol conversion module through the physical functional module or the virtual functional module to access the target register. This invention can achieve effective isolation and flexible control between physical and virtual functions while ensuring efficient use of address resources.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a register access system based on a shared address. Background Technology

[0002] With the rapid development of data-intensive computing, some chips possess advantages such as powerful parallel computing capabilities, high memory and bandwidth, and broad open-source ecosystem support. For example, Graphics Processing Unit (GPU) chips play a crucial role in fields such as graphics rendering, deep learning, and scientific computing. Meanwhile, Single Root I / O Virtualization (SRIOV) technology provides an effective way to achieve efficient sharing and flexible allocation of chip hardware resources. This technology virtualizes a physical chip into multiple virtual chips, each containing a physical function (PF) and a virtual function (VF), enabling multiple virtual machines to easily share chip resources and meet the computing power needs of different users and applications.

[0003] In existing technologies, physical and virtual functions each have their own independent register address spaces to ensure accurate reading and writing of register data and precise isolation between functions. However, with the increasing complexity of chip functions and the ever-increasing resource sharing requirements of SRIOV, existing register address allocation methods can no longer meet current needs. On the one hand, the introduction of physical and virtual functions has significantly increased the demand for register addresses. Continuing to use independent address allocation would result in a huge waste of address space, limiting the number of functions the chip can support and the scalability of virtual machines. On the other hand, while sharing hardware resources, physical and virtual functions require strict functional isolation and independent control to ensure the security and stability between different virtual machines. Therefore, existing register address allocation methods struggle to achieve effective isolation and flexible control between physical and virtual functions while ensuring efficient use of address resources. Summary of the Invention

[0004] The purpose of this invention is to provide a register access system based on a shared address, which can achieve effective isolation and flexible control between physical and virtual functions while making efficient use of address resources.

[0005] According to a first aspect of the present invention, a register access system based on a shared address is provided, comprising a host subsystem and a chip subsystem, wherein the host subsystem includes a physical functional module and N virtual functional modules, and the chip subsystem includes a protocol conversion module, a register on-chip network, and M IP modules; Each IP module corresponds to a register address space, each register address space contains one or more register addresses, each register address corresponds to a register group, each register group includes N+1 registers, and the N+1 registers in each register correspond one-to-one with the physical functional module and N virtual functional modules. The host subsystem sends a register access request to the protocol conversion module through a physical function module or a virtual function module. The register access request includes a target access address and target function module information. The target function module information is used to identify the physical function module or virtual function module that sends the register access request. The protocol conversion module is used to convert the register access request into target transaction information that includes the information carried by the register access request and can access the register on-chip network, and then send it to the register on-chip network. The on-chip network of registers is used to send the target transaction information to the target IP module corresponding to the register address space of the target access address; The target IP module is used to determine the target register group based on the target access address and send the target transaction information to the target register group; The target register group is used to determine the target register based on the target functional module information and to send the target transaction information to the target register; The target register executes the register access request.

[0006] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the register access system based on a shared address provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It possesses at least the following beneficial effects: In the system described in this invention, one register address can correspond to a group of registers. The target register is determined based on the target access address and the target functional module information. The target register executes the target access information, enabling physical and virtual functions to access different hardware register resources while using the same register address. This achieves effective isolation and flexible control between physical and virtual functions while ensuring efficient use of address resources. Furthermore, during the chip front-end design process, it is not necessary to allocate large amounts of register address space separately for physical and virtual functions, thus freeing up more silicon area for functional modules. Fewer independent register address spaces result in a simpler and clearer internal wiring layout, reducing signal transmission delay and interference, improving data transmission stability and speed, and avoiding signal crosstalk problems caused by complex wiring. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 This is a schematic diagram of a register access system based on a shared address provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the register control submodule provided in an embodiment of the present invention. Detailed Implementation

[0009] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] This invention provides a register access system based on a shared address, such as... Figure 1 As shown, it includes a host subsystem and a chip subsystem. The host subsystem includes one physical function module (PF module) and N virtual function modules (VF modules). The physical function module and the N virtual function modules are generated based on single-root I / O virtualization technology.

[0011] A physical function module (PFM) is the primary functional representation of a physical device, representing a complete abstraction of the device and encompassing all its functions and characteristics. The software programs within a PFM manage the physical device, interacting directly with the physical hardware and handling operations such as device initialization, configuration, and interrupt handling. PFM controls the behavior of the entire physical device and is used to create and manage virtual function modules (VMs). Virtual function modules are created based on PFMs; each VM can be considered an independent logical device with its own resources and state. The drivers for VMs are software programs that provide services to the virtual functions, primarily handling routine operations such as data transmission and status queries. However, they do not directly interact with the physical hardware but rely on the PFM drivers to complete some low-level operations.

[0012] The chip subsystem includes a protocol conversion module, a Register Network-on-Chip (Register NoC) module, and M Intellectual Property (IP) modules. As an example, the chip subsystem is specifically configured as a Graphics Processing Unit (GPU) chip subsystem. The host subsystem and the chip subsystem can interact with each other based on the PCIe protocol, with the host subsystem accessing the protocol conversion module via the PCIe protocol.

[0013] To ensure that each IP module can operate independently, efficiently, and without interference, the register address space needs to be clearly divided and managed to distinguish different IP modules. Each IP module corresponds to a register address space, and each register address space contains one or more register addresses. In other words, a register address space corresponds to a range of register addresses, and a range of register addresses contains one or more register addresses. Each register address corresponds to a register group, and each register group includes N+1 registers. Within the same register group, each of the N+1 registers corresponds one-to-one with a physical functional module and N virtual functional modules. Each register within the same register group corresponds to one physical functional module or one virtual functional module without repetition; that is, each functional module of the physical functional module and the N virtual functional modules has a corresponding register in each register group.

[0014] It should be noted that the register set is used to store configuration information, status data, and intermediate calculation results during chip operation. Each register set is controlled by a reset signal, as well as its corresponding write enable and read enable signals. The registers corresponding to the physical function modules are associated with the chip's physical functions and are mainly used for global configuration, initialization, and management of the chip. The N registers corresponding to the N virtual function modules are a set of registers equipped for each virtual function instance of the chip. The N registers corresponding to the N virtual function modules are used to store configuration information, status data, and control parameters related to the virtual function, allowing each virtual function module to be initialized, configured, and operated independently, thereby realizing the sharing and isolation of chip resources by multiple virtual machines or operating systems.

[0015] The host subsystem sends a register access request to the protocol conversion module through a physical or virtual functional module. The register access request includes a target access address and target functional module information. The target functional module information is used to identify the physical or virtual functional module that sent the register access request, that is, to distinguish which physical or virtual functional module the register access originated from.

[0016] The protocol conversion module converts the register access request into target transaction information that includes the information carried by the register access request and enables access to the register on-chip network, and then sends it to the register on-chip network. The register on-chip network then sends the target transaction information to the target IP module corresponding to the register address space of the target access address. The target IP module determines the target register group based on the target access address, sends the target transaction information to the target register group, determines the target register based on the target functional module information, sends the target transaction information to the target register, and then executes the register access request based on the target register.

[0017] As one embodiment, the register access request further includes target access information, which may specifically include read access information, write access information, etc. Read access information includes the read access type. Write access information includes the write access type and the data to be written. The target access address is the destination address of this register access. The protocol conversion module is used to parse the register access request, obtain the target access address, target access information, and target functional module information, add the target access address to the address signal of the preset access protocol, add the target access information to the access signal of the preset access protocol, add the target functional module information to the custom signal of the preset access protocol, and generate target transaction information. The preset protocol is a protocol capable of accessing the on-chip network of registers. Specifically, the preset protocol can be the AXI protocol, and the custom signal is the awuser signal or the aruser signal. The awuser signal and the aruser signal are optional user-defined signals in the AXI bus protocol, specifically used to transmit additional control information in the write address channel and read address channel. Using the awuser signal or the aruser signal in the AXI protocol, it is possible to distinguish between register accesses corresponding to physical functional modules and virtual functional modules while reusing register addresses.

[0018] The chip subsystem consists of multiple IP modules working together to achieve powerful computing capabilities. As one embodiment, the IP modules include a register control submodule, such as... Figure 2 As shown, the register control submodule includes a register block selector and Q register blocks. Each register block includes a register routing unit and at least one register group. Each register block is configured with a corresponding register address space, and each register group corresponds to a register address. Figure 2 As shown in the example, each register group includes N+1 registers, namely REG_PF, REG_VF1, REG_VF2, ... REG_VFN, where REG_PF represents the register corresponding to the physical functional module in the register group, REG_VFn represents the register corresponding to the nth virtual functional module in the register group, and the value of n ranges from 1 to N. The register block selector is used to determine the target register block according to the register address space to which the target access address belongs, and send the target transaction information to the target register block. The register routing unit is used to determine the corresponding target register group in the target register block according to the target access address, and send the target transaction information to the target register group.

[0019] As one embodiment, the Q register blocks in each register control submodule are address-contiguous register blocks divided according to function. That is, registers with similar functions can be placed in adjacent positions.

[0020] As one embodiment, the on-chip register network is further configured to return a first exception message when the target access address does not belong to the register address space corresponding to any IP module. As another embodiment, the register block selector is further configured to return a second exception message when the target access address does not belong to the register address space corresponding to any target register block in the target IP module, or when the target functional module information is illegal functional module information. This function allows for the isolation of read / write register requests containing illegal addresses and illegal functional module information. It is understood that illegal functional module information refers to identifiers other than the physical functional module identifier or virtual functional module identifier corresponding to the register group.

[0021] It should be noted that after completing the target register access, the target register control submodule can generate response information and send it to the target IP module. The target IP module then returns the response to the host subsystem through the register chip network access and protocol conversion module.

[0022] In the system described in this invention embodiment, one register address corresponds to a group of registers, each of which has a corresponding read / write enable control signal. Taking the AXI protocol as an example, the value of the read / write enable signal corresponding to the register is determined by the address, read / write type, write data (valid when writing to the register), and functional module information in the AXI read / write transaction. The read / write enable signal then controls the writing and reading of specific registers. Ultimately, this allows physical and virtual functional modules to access different hardware register resources while using the same register address. Therefore, in the chip front-end design process, it is not necessary to allocate a large amount of register address space for physical and virtual functional modules separately, thus freeing up more silicon area for functional modules. Furthermore, fewer independent register address spaces result in a simpler and clearer internal wiring layout, reducing signal transmission delay and interference, improving data transmission stability and speed, and avoiding signal crosstalk problems caused by complex wiring. Although sharing register addresses increases the complexity of hardware logic, from a software-driven development perspective, a unified address can be used to access physical and virtual functional registers, reducing the management and maintenance work of different address spaces. Software developers can focus on functional implementation rather than complex address management issues. The simpler the software adapts to hardware registers, the fewer compatibility issues will be encountered when migrating and upgrading between different hardware platforms. This allows hardware devices that share register addresses for both physical and virtual functions to integrate more smoothly into new software ecosystems and adapt to new operating system versions.

[0023] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A register access system based on a shared address, characterized in that, It includes a host subsystem and a chip subsystem. The host subsystem includes one physical functional module and N virtual functional modules. The chip subsystem includes a protocol conversion module, a register-on-chip network, and M IP modules. Each IP module corresponds to a register address space, each register address space contains one or more register addresses, each register address corresponds to a register group, each register group includes N+1 registers, and the N+1 registers in each register correspond one-to-one with the physical functional module and N virtual functional modules. The host subsystem sends a register access request to the protocol conversion module through a physical function module or a virtual function module. The register access request includes a target access address and target function module information. The target function module information is used to identify the physical function module or virtual function module that sends the register access request. The protocol conversion module is used to convert the register access request into target transaction information that includes the information carried by the register access request and can access the register on-chip network, and then send it to the register on-chip network. The on-chip network of registers is used to send the target transaction information to the target IP module corresponding to the register address space of the target access address; The target IP module is used to determine the target register group based on the target access address, send the target transaction information to the target register group, determine the target register based on the target functional module information, send the target transaction information to the target register, and then execute the register access request based on the target register.

2. The system according to claim 1, characterized in that, The physical function module is used to manage the software program of the physical device corresponding to the chip, as well as to handle the initialization, configuration, interrupt handling, and creation and management of virtual function modules of the physical device; The virtual function module is used to manage the software programs corresponding to the virtual functions, as well as to handle data transmission and status queries.

3. The system according to claim 1, characterized in that, The register access request also includes target access information, which includes read access information and write access information. The protocol conversion module is used to parse the register access request, obtain the target access address, target access information, and target functional module information, add the target access address to the address signal of the preset access protocol, add the target access information to the access signal of the preset access protocol, add the target functional module information to the custom signal of the preset access protocol, and generate target transaction information. The preset protocol is a protocol that can access the register on-chip network.

4. The system according to claim 3, characterized in that, The preset protocol is the AXI protocol, and the custom signal is the awuser signal or the aruser signal.

5. The system according to claim 1, characterized in that, The host subsystem accesses the protocol conversion module based on the PCIe protocol.

6. The system according to claim 1, characterized in that, The IP module includes a register control submodule, which includes a register block selector and Q register blocks. Each register block includes a register routing unit and at least one register group. Each register block is configured with a corresponding register address space, and each register group corresponds to a register address. The register block selector is used to determine the target register block according to the register address space to which the target access address belongs, and to send the target transaction information to the target register block; The register routing unit is used to determine the corresponding target register group in the target register block according to the target access address, and send the target transaction information to the target register group.

7. The system according to claim 6, characterized in that, Each register control submodule contains Q register blocks, which are address-contiguous register blocks divided according to function.

8. The system according to claim 1, characterized in that, The on-chip network of registers is also used to return a first exception message when the target access address does not belong to the register address space corresponding to any IP module.

9. The system according to claim 1, characterized in that, The register block selector is also used to return a second exception message when the target access address does not belong to the register address space corresponding to any target register block in the target IP module or when the target functional module information is illegal functional module information.

10. The system according to claim 1, characterized in that, The chip subsystem is a GPU chip subsystem.

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