A semiconductor device failure prediction method, system, device and medium based on a time series graph neural network

Abstract

This invention relates to the field of semiconductor equipment manufacturing technology, specifically to a method, system, device, and medium for semiconductor equipment fault prediction based on a time-series graph neural network. The method first collects time-series operational data of each component of the equipment to form a data matrix. The data matrix is ​​then preprocessed and segmented to obtain standardized segments. Next, a time-series graph is constructed for each segment: using components as nodes, edge weights are determined based on physical connections and Pearson coefficients to form a time-series graph sequence. This sequence is then divided into training and testing sets, input into a time-series graph neural network model for training, and optimized using a cross-entropy loss function. Finally, real-time data, processed through the above steps, is input into the trained model, outputting the fault type and probability, and displaying and pushing the results. By constructing a time-series graph data structure and designing a dedicated time-series graph neural network model, accurate early fault prediction is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing equipment technology, and more specifically, to a semiconductor equipment fault prediction method, system, device, and medium based on a time-series graph neural network. Background Technology

[0002] Semiconductor manufacturing equipment is the core carrier of chip production. Its structure is extremely complex, typically consisting of thousands of precision components. These components are tightly coupled physically (e.g., pressure linkage between the vacuum system and the reaction chamber, power coordination between the RF power supply and the matching circuit) and dependent on data (e.g., dynamic correlation between temperature parameters and process power). The stability of the equipment's operating status directly determines the yield, efficiency, and production cost of chip manufacturing. Fault prediction, as a core technology for preventive maintenance of semiconductor equipment, directly impacts the continuity of industrial production—a single equipment downtime in the semiconductor manufacturing field can result in losses of hundreds of thousands of yuan. Therefore, the industry's core requirements for fault prediction focus on "high accuracy" (≥95%) and "sufficient lead time" (10-30 minutes) to achieve early identification and timely intervention of fault precursors.

[0003] Existing fault prediction methods are mainly divided into three categories, all of which have insurmountable technical limitations and cannot meet the high-end needs of the industry: The first category is rule-based or expert-experience-based methods, which rely on manually summarizing fault characteristic thresholds, such as "vacuum pressure > 10Pa for 5 seconds is judged as leakage". Essentially, this is a static matching of a single fault scenario, which cannot cover chain faults caused by inter-component correlations, such as RF power fluctuations → abnormal reaction chamber temperature → wafer defects. It has poor adaptability, weak generalization ability, and is difficult to cope with complex operating conditions during equipment operation. The second category is methods based on a single time-series model (LSTM, ARIMA, etc.), which only... Modeling time-series data for individual components completely ignores the spatial relationships between components, resulting in a high false negative rate for associated faults and a high false positive rate for normal fluctuations of individual components. It also fails to capture the gradual change in the relationships between components before a fault occurs. The third type is based on static graph neural networks (such as GCN). Although it can capture the spatial relationships between components, it can only extract features from static graphs at a single time point. It cannot handle the dynamic changes in time-series features during equipment operation (such as the gradual anomalies in the strength of component relationships during the fault precursor stage), resulting in insufficient fault prediction capabilities and failing to meet the industry's demand for fault lead time.

[0004] Temporal Graph Neural Networks (TGNNs), as an emerging algorithm in the field of artificial intelligence, possess the core advantage of simultaneously modeling "spatial correlations" and "temporal dynamics," providing a new technical path to address the aforementioned technical pain points. However, existing TGNN algorithms are mostly applied to fields such as traffic flow prediction and social network analysis, and have not been customized for the operational characteristics of semiconductor equipment (high dimensionality, strong coupling, temporal continuity, and the concealment of fault precursors). They cannot be directly adapted to the fault prediction scenario of semiconductor equipment. For example, the graph structure construction of existing algorithms does not take into account the physical connection characteristics of semiconductor equipment, the temporal feature extraction does not consider the slow and gradual changes in equipment fault precursors, and the model parameters are not optimized for the distribution characteristics of semiconductor equipment data. Therefore, they cannot be directly transferred to semiconductor equipment fault prediction tasks. Summary of the Invention

[0005] This invention addresses the problems of low fault prediction accuracy and insufficient lead time caused by existing prediction methods neglecting component spatial correlation and insufficient temporal dynamic capture. It proposes a semiconductor equipment fault prediction method, system, device, and medium based on a time-series graph neural network. The method first collects the temporal operation data of each component of the equipment to form a data matrix. The data matrix is ​​then preprocessed and segmented into standardized segments. Next, a time-series graph is constructed for each segment: using components as nodes, edge weights are determined based on physical connections and Pearson coefficients to form a time-series graph sequence. This sequence is then divided into training and testing sets, which are input into a time-series graph neural network model for training, optimized using a cross-entropy loss function. Finally, real-time data, processed in the above steps, is input into the trained model, outputting the fault type and probability, and displaying and pushing the results. By constructing a time-series graph data structure and designing a dedicated time-series graph neural network model, accurate early fault prediction is achieved.

[0006] The specific implementation details of this invention are as follows: A semiconductor device fault prediction method based on a time-series graph neural network specifically includes the following steps: Step S1: Collect timing data of semiconductor device components and generate a data matrix; Step S2: Preprocess the data matrix and perform timing segmentation to obtain standardized semiconductor component timing segments; Step S3: Using semiconductor components as nodes, determine the edge weights according to the set Pearson coefficients, and construct a timing graph sequence; Step S4: Divide the time series sequence into training set and test set, input them into the constructed time series neural network model for training, and optimize it through the cross-entropy loss function to obtain the trained time series neural network model; Step S5: Input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability; Step S6: Determine whether the semiconductor equipment is faulty based on the fault probability, and generate semiconductor equipment fault prediction results.

[0007] To better realize the present invention, step S1 further includes the following steps: Step S11: Based on the component distribution characteristics of the semiconductor equipment, deploy corresponding types of sensors on the key components of the equipment, and collect process parameter data through the equipment control system interface to obtain multi-source timing data; Step S12: Based on the component's feature dimensions, the number of key components of the device, and the set total time step, integrate the multi-source time series data into a three-dimensional data matrix.

[0008] To better realize the present invention, step S2 further includes the following steps: Step S21: Use the 3σ criterion to identify outliers in the three-dimensional data matrix and perform outlier cleaning; Step S22: Fill in the missing values ​​in the cleaned 3D data matrix to obtain the filled 3D data matrix; Step S23: Standardize the filled 3D data matrix to obtain a standardized 3D data matrix; Step S24: Divide the standardized three-dimensional data matrix according to the set time window to obtain the standardized semiconductor component timing segment.

[0009] To better realize the present invention, step S3 further includes the following steps: Step S31: Based on the standardized semiconductor component timing segments, determine whether there are physical connection edges between semiconductor components. If they exist, it is determined that there is an inherent relationship between the semiconductor components, and the edge weight is set to 1. If there are no physical connection edges, the Pearson coefficient is used to calculate the correlation of the semiconductor component timing data. Step S32: Determine whether there is a dynamic correlation between semiconductor components based on the Pearson coefficient. If there is a dynamic correlation, set the edge weight to the absolute value of the Pearson coefficient. If there is no dynamic correlation, set the edge weight to 0. Step S33: Using the key components of the semiconductor device as nodes, construct a timing graph according to the set edge weights to obtain a timing graph sequence.

[0010] To better realize the present invention, step S4 further includes the following steps: Step S41: Construct a temporal graph neural network; the temporal graph neural network includes a graph convolutional layer, a temporal feature extraction layer, and a classification layer; Step S42: Input the temporal graph sequence into the graph convolutional layer to extract high-order spatial features; Step S43: Input the high-order spatial features into the temporal feature extraction layer to obtain the fused features; Step S44: Input the fused features into the classification layer to obtain the probability distribution of the fault categories.

[0011] To better realize the present invention, step S42 further includes the following steps: Step S421: Input the time series diagram sequence into the first convolutional layer; the convolutional layer includes a first convolutional layer and a second convolutional layer; Step S422: Obtain the adjacency matrix based on the edge weight matrix of the time series graph; Step S423: Based on the normalized adjacency matrix, the degree matrix of the adjacency matrix, the set first weight matrix, the set first bias, and the set identity matrix, call the activation function to obtain the primary spatial features; Step S424: Input the primary spatial features into the second convolutional layer, and obtain the higher-order spatial features according to the set second weight matrix and second bias.

[0012] To better realize the present invention, step S6 further includes the following steps: Step S61: Preprocess the acquired real-time operating data of the semiconductor device and construct a real-time timing sequence. Step S62: According to the set window, input the real-time time series sequence into the trained time series neural network model to obtain the predicted state category and the probability of the corresponding category; Step S63: If the probability of the corresponding category is greater than or equal to the set warning threshold, and the status category is a fault type, a fault warning is determined and a fault prediction result is output; if the probability of the corresponding category is less than the set warning threshold or the status category is a normal state, the equipment is determined to be operating normally and a prediction result is output.

[0013] Based on the aforementioned semiconductor equipment fault prediction method based on temporal graph neural networks, and to better realize this invention, a semiconductor equipment fault prediction system based on temporal graph neural networks is further proposed to execute the aforementioned semiconductor equipment fault prediction method based on temporal graph neural networks; including a data acquisition module, a data preprocessing module, a graph structure construction module, a fault feature extraction and prediction module, a model training module, and a result output module; The data acquisition module is used to acquire timing operation data of semiconductor device components and generate a data matrix; The data preprocessing module is used to preprocess the data matrix and perform time-series segmentation to obtain standardized semiconductor component time-series segments. The graph structure construction module is used to construct a time series graph sequence by using semiconductor components as nodes and determining edge weights according to the set Pearson coefficients. The fault feature extraction and prediction module is used to divide the time series sequence into a training set and a test set, input them into the constructed time series neural network model for training, and optimize the model through the cross-entropy loss function to obtain the trained time series neural network model. The model training module is used to input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability. The result output module is used to determine whether the semiconductor device has a fault based on the fault probability and generate a semiconductor device fault prediction result.

[0014] Based on the aforementioned semiconductor device fault prediction method based on time-series graph neural networks, and to better realize the present invention, an electronic device is further provided, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, the aforementioned semiconductor device fault prediction method based on time-series graph neural networks is implemented.

[0015] Based on the aforementioned semiconductor device fault prediction method based on time-series graph neural networks, and to better realize the present invention, a computer-readable storage medium is further provided, wherein computer instructions are stored on the computer-readable storage medium; when the computer instructions are executed on the aforementioned electronic device, the aforementioned semiconductor device fault prediction method based on time-series graph neural networks is implemented.

[0016] The present invention has the following beneficial effects: (1) This invention uses a time-series graph construction method that integrates physical correlation and data correlation, and a GCN-LSTM hybrid architecture to deeply integrate spatial and temporal features. The model can fully capture the complex features of fault precursors. The accuracy is 12%-18% higher than that of the traditional LSTM model (ignoring spatial correlation) and 8%-15% higher than that of the static GCN model (ignoring temporal dynamics). The accuracy of the test set can be stably reached above 95%, and the F1 score of various fault types is ≥0.94. This effectively reduces the false alarm rate and false alarm rate, and meets the high accuracy requirements of the semiconductor manufacturing field.

[0017] (2) This invention uses the LSTM layer to accurately capture the dynamic features of the time series and the time series diagram sequence to dynamically depict the evolution of the component association. The model can identify the hidden precursor features 10-30 minutes before the fault occurs, which is 5-10 minutes ahead of the traditional rule-based method. The average prediction time can reach 22 minutes, providing engineers with sufficient maintenance time, effectively avoiding equipment downtime and reducing production costs.

[0018] (3) This invention does not require manual definition of fault rules. It automatically learns the operating characteristics and fault modes of the equipment through data-driven methods. At the same time, the graph structure construction and model parameters are customized and optimized for the characteristics of semiconductor equipment. It can be adapted to various complex semiconductor equipment such as lithography machines and etching machines. It does not require large-scale model reconstruction for different equipment, thus reducing application costs.

[0019] (4) The algorithm of this invention is simple and the parameter settings are reasonable. Data acquisition adopts conventional industrial sensors and equipment interfaces. Preprocessing and model training can be implemented on conventional industrial servers without complicated hardware upgrades. It is easy to promote and apply on a large scale in semiconductor manufacturing workshops and has extremely high engineering practical value. Attached Figure Description

[0020] Figure 1 The system architecture diagram of the semiconductor device fault prediction method based on time-series graph neural network provided by the present invention is shown.

[0021] Figure 2 The structure diagram of the time-series graph neural network model provided by this invention is shown.

[0022] Figure 3 The flowchart of the fault prediction method provided by the present invention. Detailed Implementation

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments, and therefore should not be regarded as a limitation on the scope of protection. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "set up," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0025] Example 1: This embodiment proposes a semiconductor device fault prediction method based on a time-series graph neural network, which specifically includes the following steps: Step S1: Collect timing data of semiconductor device components and generate a data matrix; Step S1 specifically includes the following steps: Step S11: Based on the component distribution characteristics of the semiconductor equipment, deploy corresponding types of sensors on the key components of the equipment, and collect process parameter data through the equipment control system interface to obtain multi-source timing data; Step S12: Based on the component's feature dimensions, the number of key components of the device, and the set total time step, integrate the multi-source time series data into a three-dimensional data matrix.

[0026] Step S2: Preprocess the data matrix and perform timing segmentation to obtain standardized semiconductor component timing segments; Step S2 specifically includes the following steps: Step S21: Use the 3σ criterion to identify outliers in the three-dimensional data matrix and perform outlier cleaning; Step S22: Fill in the missing values ​​in the cleaned 3D data matrix to obtain the filled 3D data matrix; Step S23: Standardize the filled 3D data matrix to obtain a standardized 3D data matrix; Step S24: Divide the standardized three-dimensional data matrix according to the set time window to obtain the standardized semiconductor component timing segment.

[0027] Step S3: Using semiconductor components as nodes, determine the edge weights according to the set Pearson coefficients, and construct a timing graph sequence; Step S3 specifically includes the following steps: Step S31: Based on the standardized semiconductor component timing segments, determine whether there are physical connection edges between semiconductor components. If they exist, it is determined that there is an inherent relationship between the semiconductor components, and the edge weight is set to 1. If there are no physical connection edges, the Pearson coefficient is used to calculate the correlation of the semiconductor component timing data. Step S32: Determine whether there is a dynamic correlation between semiconductor components based on the Pearson coefficient. If there is a dynamic correlation, set the edge weight to the absolute value of the Pearson coefficient. If there is no dynamic correlation, set the edge weight to 0. Step S33: Using the key components of the semiconductor device as nodes, construct a timing graph according to the set edge weights to obtain a timing graph sequence.

[0028] Step S4: Divide the time series sequence into training set and test set, input them into the constructed time series neural network model for training, and optimize it through the cross-entropy loss function to obtain the trained time series neural network model; Step S4 specifically includes the following steps: Step S41: Construct a temporal graph neural network; the temporal graph neural network includes a graph convolutional layer, a temporal feature extraction layer, and a classification layer; Step S42: Input the temporal graph sequence into the graph convolutional layer to extract high-order spatial features; Step S42 specifically includes the following steps: Step S421: Input the time series diagram sequence into the first convolutional layer; the convolutional layer includes a first convolutional layer and a second convolutional layer; Step S422: Obtain the adjacency matrix based on the edge weight matrix of the time series graph; Step S423: Based on the normalized adjacency matrix, the degree matrix of the adjacency matrix, the set first weight matrix, the set first bias, and the set identity matrix, call the activation function to obtain the primary spatial features; Step S424: Input the primary spatial features into the second convolutional layer, and obtain the higher-order spatial features according to the set second weight matrix and second bias.

[0029] Step S43: Input the high-order spatial features into the temporal feature extraction layer to obtain the fused features; Step S44: Input the fused features into the classification layer to obtain the probability distribution of the fault categories.

[0030] Step S5: Input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability; Step S6: Determine whether the semiconductor equipment is faulty based on the fault probability, and generate semiconductor equipment fault prediction results.

[0031] Step S6 specifically includes the following steps: Step S61: Preprocess the acquired real-time operating data of the semiconductor device and construct a real-time timing sequence. Step S62: According to the set window, input the real-time time series sequence into the trained time series neural network model to obtain the predicted state category and the probability of the corresponding category; Step S63: If the probability of the corresponding category is greater than or equal to the set warning threshold, and the status category is a fault type, a fault warning is determined and a fault prediction result is output; if the probability of the corresponding category is less than the set warning threshold or the status category is a normal state, the equipment is determined to be operating normally and a prediction result is output.

[0032] Working principle: This embodiment first collects the time-series operating data of each component of the equipment to form a data matrix; then performs outlier cleaning, missing value imputation, standardization, and time-series segmentation on the data matrix to obtain standardized segments; secondly, a time-series graph is constructed for each segment: with components as nodes, edge weights are determined based on physical connections and Pearson coefficients to form a time-series graph sequence; then the time-series graph sequence is divided into training and testing sets, and input into a time-series graph neural network model for training, optimized through the cross-entropy loss function until the accuracy of the testing set is ≥95%; finally, real-time data processed by the above steps is input into the trained model, which outputs the fault type and probability; when the fault probability is ≥0.8, an early warning is triggered, and the result is displayed and pushed.

[0033] This embodiment is designed with a customized and innovative approach to timing graph neural network algorithms, taking into account the operating characteristics of semiconductor devices. By combining the physical and data relationships of semiconductor device components, an adapted timing graph structure is constructed, and a dedicated timing graph neural network model is designed to achieve deep integration of spatial relationships and temporal dynamic features. This breaks through the technical limitations of existing methods and meets the high-end needs of the semiconductor manufacturing field for fault prediction.

[0034] Example 2: Based on Example 1 above, this embodiment achieves accurate early prediction of semiconductor device failures through customized timing graph construction and dedicated timing graph neural network model design.

[0035] Step S1: Data Acquisition.

[0036] First, multi-source time-series data acquisition is conducted to provide foundational data support for subsequent modeling. Considering the component distribution characteristics of semiconductor equipment, corresponding types of sensors, including temperature sensors, pressure sensors, voltage sensors, and vibration sensors, are deployed in key components such as RF power supplies, vacuum systems, reaction chambers, and gas flow controllers. Simultaneously, process parameter data is acquired through the equipment control system (PLC / SCADA) interface, forming a multi-source time-series data acquisition system. The acquisition frequency is dynamically adjusted according to the component response speed, ranging from 1Hz to 100Hz. For components with faster response speeds, such as RF power supplies and vacuum valves, the acquisition frequency is set to 10Hz to ensure the capture of rapidly fluctuating fault precursors; for components with slower response speeds, such as temperature and humidity sensors, the acquisition frequency is set to 1Hz to balance data integrity and computational efficiency. The acquired data is integrated into a three-dimensional matrix. Where N is the number of key components of the equipment (adjusted according to the type of equipment, usually 10-20), T is the total time step (e.g., 10 minutes × 60 seconds = 600 time points), and F is the feature dimension of each component (e.g., 3-5 features such as temperature, vibration, voltage, etc.). This matrix fully records the operating status of each component at different time points, providing a data foundation for subsequent time series diagram construction and feature extraction.

[0037] Step S2: Data preprocessing.

[0038] After data collection, the raw data undergoes targeted preprocessing to eliminate the impact of data noise, dimensional differences, and missing data on subsequent modeling. This is a crucial prerequisite for improving the model's prediction accuracy. The preprocessing process employs a differentiated algorithm design, executed step-by-step based on the characteristics of semiconductor equipment operating data: The first step is outlier cleaning. Outliers in semiconductor equipment operating data mainly originate from sensor malfunctions and electromagnetic interference, and their distribution conforms to a normal distribution. Therefore, the 3σ criterion is used for outlier identification. For any feature dimension of the observed value x, if it satisfies... (Where μ is the mean of the feature and σ is the standard deviation), then it is judged as an outlier. Considering the temporal continuity of semiconductor equipment operation data, the median of five consecutive normal observations is used for replacement to avoid bias caused by single interpolation. The replacement formula is: This method can both eliminate the influence of outliers and preserve the temporal continuity of the data. The second step is missing value imputation. Missing values ​​encountered during the data collection process are mainly divided into short-term missing values ​​(continuous missing length ≤ 5) and long-term missing values ​​(continuous missing length > 5). For short-term missing values, a linear interpolation formula is used. Imputation is performed to ensure the smoothness of time-series data. For long-term missing data, the historical average of the component is used for imputation to reduce the impact of missing data on feature extraction. Practical verification shows that this differentiated imputation strategy can reduce the missing data rate to below 1%, meeting modeling requirements. The third step is standardization. Since the data units of different types of sensors vary significantly (e.g., temperature in °C, pressure in Pa, voltage in V), it affects the training efficiency and prediction accuracy of the model. Therefore, Min-Max standardization is used to map all features to the [0,1] interval to eliminate unit differences. The standardization formula is... ,in and These are the minimum and maximum values ​​of the feature, respectively, and normalized separately according to component type (e.g., temperature features are mapped separately) to avoid mutual interference between features of different components. The fourth step is time series segmentation. To adapt to the needs of time series plot construction, the data is divided into segments according to a fixed time window W, with the window length W set to 60 seconds, balancing the integrity of time series features and computational efficiency, resulting in a set of data segments. ,in T represents the total time step, and each data segment corresponds to the operating status of the device within a certain time period, providing input for the subsequent construction of the time sequence diagram.

[0039] Step S3: Graph structure construction.

[0040] After preprocessing, the core innovation step is to construct a dynamic time-series graph that integrates physical and data relationships. The core of this approach is to ensure that the graph structure accurately reflects the inherent and dynamic relationships between semiconductor device components, providing a precise structural carrier for subsequent spatial feature extraction. The time-series graph construction uses key components of the semiconductor device as nodes, and the node set is defined as... (N is the same as the number of components in the data acquisition stage), and the characteristics of each node are the preprocessed time-series data segments of the corresponding component (i.e., (where k is the segment number). The design of graph edges and weights is the key innovation of this section. Unlike existing static graphs that only consider a single association, this embodiment combines the physical and data characteristics of semiconductor devices and adopts a dual association determination mechanism: one is physical connection edges, if the component... and If there is a direct mechanical, electrical, or pneumatic connection (such as RF power supply and matching unit, vacuum system and reaction chamber), then an inherent correlation is determined between the two, and the edge weight is set to 1 to reflect the stability and importance of the correlation. Secondly, for data-related edges, for components without a direct physical connection, the correlation between their time-series data is calculated using the Pearson coefficient to quantify the dynamic correlation strength between the components. The Pearson coefficient formula is... ,in , Components , Standardized data at time point t, , These are the means of the two. To avoid the interference of weak correlation on the graph structure, a correlation threshold of 0.7 is set. If so, it is determined that there is a dynamic relationship between the two, and the edge weight is set to... Otherwise, the edge weight is set to 0, meaning no edge is constructed. Through this dual association mechanism, each time window's data segment corresponds to a static graph. ,in The edge set of the k-th window is represented by the edge weight matrix, which is the adjacency matrix A of the graph, ultimately forming a time series graph sequence. This sequence can dynamically reflect the temporal evolution of component relationships during equipment operation, especially capturing the gradual change in component relationship strength during the early stages of faults, providing core support for subsequent fault prediction.

[0041] Step S4: Fault feature extraction and prediction.

[0042] After the time-series graph sequence is constructed, a dedicated time-series graph neural network model is designed for feature extraction and fault prediction. This model is another core innovation of this invention. It adopts a hybrid architecture of "Graph Convolutional Layer (GCN) + Temporal Feature Extraction Layer (LSTM) + Classification Layer", specifically adapted to the characteristics of semiconductor equipment fault precursors, and achieves deep fusion of spatial correlation and temporal dynamic features. The hierarchical design and algorithm details of the model are as follows: First is the graph convolutional layer (GCN), whose core function is to extract the spatial correlation features between components in each static graph. Considering that the correlation between semiconductor equipment components has high-order characteristics (such as component A is related to component B, component B is related to component C, and thus component A and component C are indirectly related), a two-layer GCN structure is used for high-order spatial feature extraction. The first layer of GCN fuses node features with the adjacency matrix to output primary spatial features. The calculation formula is: ,in The normalized adjacency matrix is ​​introduced by introducing the identity matrix I to preserve the characteristics of the nodes themselves and avoid excessive smoothing of the features; D is the degree matrix of the adjacency matrix A (the diagonal elements are the sum of the number of edges of each node, and the remaining elements are 0). The normalization operation can solve the problem of feature extraction bias caused by the degree difference of different nodes. This is the weight matrix of the first layer GCN. (Determined through multiple experiments and optimizations, balancing feature extraction accuracy and computational efficiency). For bias terms; The ReLU activation function is used to introduce nonlinear features, addressing the problem that linear models cannot capture complex relationships. The second layer of GCN further extracts higher-order spatial features based on the first layer. ,in The calculation formula is the same as that of the first layer, only the weight matrix is ​​different. and bias terms Unlike other methods, by stacking two layers of GCN, the direct and indirect correlation characteristics between components can be fully captured, especially the correlation anomalies in the pre-fault stage.

[0043] The high-order spatial features output from the convolutional layer are further input into the temporal feature extraction layer (LSTM). The core function is to capture the temporal dynamic changes of spatial features and uncover the temporal evolution patterns of fault precursors. Fault precursors in semiconductor equipment typically exhibit slow, gradual changes, requiring the model to possess the ability to capture long-term dependencies. Therefore, LSTM is chosen instead of a regular RNN, as its gating mechanism effectively avoids the gradient vanishing or exploding problems caused by long-term dependencies. The LSTM layer uses a two-layer structure, with the hidden layer dimension set to 128 (adapting to the dimension of high-order spatial features; experimental verification shows it optimally captures temporal dynamics). The spatial features output from the GCN are then processed... The data is input into the LSTM cells sequentially according to the time sequence. Let the hidden state at step t be... Cell state is The state update formula for the LSTM unit is as follows: in, , , These are the input gate, forget gate, and output gate of the LSTM. The input gate controls the input weights of the current spatial features, the forget gate controls the retention weights of the historical cell states, and the output gate controls the output weights of the cell states to the hidden states. The three work together to achieve accurate capture of long-term temporal dependencies. These are the weight matrices for the input features and the hidden states, respectively. For bias terms; Candidate cell state, The function is used to map the candidate cell state to the interval [-1,1] to avoid numerical overflow; This involves element-wise product operations; the final hidden state output by the LSTM layer. ( This is the final feature that integrates spatial correlation and temporal dynamics. This feature fully includes the spatial correlation information and temporal evolution information of the equipment's operating status, and can accurately depict the characteristic patterns of fault precursors.

[0044] The fused features are further input into the classification layer to determine the fault type and output the fault probability. The classification layer adopts a structure combining a fully connected layer and a softmax function to adapt to the fault classification requirements of semiconductor equipment. If the number of equipment fault types is C (typically 3-8 types of faults), then the output dimension of the classification layer is C+1 (covering C types of faults and 1 type of normal state), and the output result is the probability distribution of each category. ,in This is the weight matrix of the fully connected layer. This is the bias term; subsequently, the output Z is mapped to a probability distribution using the Softmax function. The calculation formula is: ,in Let be the probability of the k-th time series image segment corresponding to the c-th state. The output value corresponding to the c-th state of the fully connected layer is represented by the Softmax function, which ensures that the sum of the probabilities of all categories is 1, facilitating the determination of fault types and the setting of warning thresholds.

[0045] Step S5: Model training.

[0046] The model training process employs a data-driven approach, taking into account the imbalanced nature of semiconductor equipment fault samples (the number of normal samples far exceeds the number of fault samples) to optimize training parameters and the loss function, ensuring the model's generalization ability and prediction accuracy. The training dataset uses historical time-series graph sequences, covering samples of normal equipment operation and at least three typical fault states, divided into training and test sets in an 8:2 ratio. The training set is used for model parameter optimization, while the test set is used for model performance validation. The cross-entropy loss function is used during training, specifically adapted for multi-class classification tasks while also addressing the imbalanced fault sample problem. The loss function calculation formula is as follows: ,in The ground truth label for the k-th time-series image segment (using one-hot encoding, where the position corresponding to the true state is 1 and the rest are 0) is used. This loss function effectively measures the deviation between the model's predicted probability and the true label, guiding the model to optimize its parameters. The model training uses the Adam optimizer, which converges faster than the traditional SGD optimizer and can adaptively adjust the learning rate, avoiding gradient vanishing or exploding. The value was set to 0.001 (optimized through multiple experiments to balance convergence speed and model accuracy), the number of iterations E was set to 100 rounds, and the batch size B was set to 32 (to adapt to the scale of time series data and avoid memory overflow). During training, the prediction accuracy of the test set was monitored in real time. When the accuracy of the test set was ≥95% and there was no significant improvement for 5 consecutive rounds, training was stopped, and the trained fault prediction model was obtained. This training strategy can ensure that the model has sufficient prediction accuracy and generalization ability while taking into account training efficiency, and adapts to the complex operating conditions of semiconductor devices.

[0047] Step S6: Output the results.

[0048] After model training is completed, the real-time fault prediction stage begins. The real-time collected semiconductor equipment operation data is processed according to the above preprocessing procedures (outlier cleaning, missing value imputation, standardization, and time series segmentation) to construct a real-time time series diagram sequence. K is set to 5 windows (i.e., 5 minutes of data) to balance real-time performance and prediction accuracy. The real-time time series graph sequence is input into the trained model, which outputs the probability distribution of each state. Determine the predicted state category (i.e., fault type or normal state) and extract the probability of the corresponding category. To achieve early warning of faults, a warning threshold is set. (Can be dynamically adjusted according to equipment type and production needs), when and When the fault type is identified, it is determined as a fault warning. Simultaneously, considering the evolution trend of the timing characteristics, the estimated time of fault occurrence is estimated (usually 10-30 minutes). or When the status is normal, the equipment is considered to be operating normally, and real-time data is continuously monitored.

[0049] Finally, the fault prediction results are output. The output process mainly provides support for subsequent maintenance decisions. It does not require complex functional design. The core is to display the prediction results (fault type, fault probability, and expected occurrence time) through a visual interface. At the same time, it connects with the semiconductor equipment management system through the OPC UA protocol to push early warning signals and maintenance suggestions, so that engineers can carry out preventive maintenance in a timely manner and avoid equipment downtime.

[0050] Visualization: Displays real-time data curves of components, heatmaps of graph structure correlation strength, and time-series changes in fault prediction probability.

[0051] Interface: Sends early warning signals (including fault type and estimated occurrence time) to the device management system via the OPC UA protocol.

[0052] Working Principle: This embodiment achieves accurate early fault prediction through the fusion of data-driven and customized algorithms. The overall process is as follows: First, time-series operating data of key components of semiconductor equipment are collected through multi-source sensors. After outlier cleaning, missing value imputation, standardization, and differentiated preprocessing by time-series segmentation, a dynamic time-series graph sequence with dual correlations is constructed, using components as nodes and combining the physical connection relationship of components with the Pearson correlation of data. Then, a dedicated time-series graph neural network model with a hybrid architecture of "2-layer GCN + 2-layer LSTM" is adopted. The GCN layer extracts high-order spatial correlation features between components, and the LSTM layer captures the dynamic changes in time series. After training with the cross-entropy loss function and Adam optimizer until the accuracy of the test set is ≥95%, the time-series graph sequence constructed from the real-time preprocessed data is input into the model, and the fault type and probability are output. When the fault probability reaches a preset threshold, an early warning is triggered and the result is output, realizing accurate early prediction of semiconductor equipment faults. No manual definition of fault rules is required throughout the process, which is adapted to the operating characteristics of complex semiconductor equipment and effectively solves the limitations of existing methods that separate spatial and temporal feature modeling.

[0053] The feature extraction method in this embodiment takes the constructed dynamic time-series graph sequence as input and adopts a "GCN-LSTM" hierarchical connection technique to carry out feature extraction: First, each static graph in the time-series graph sequence is input into two layers of GCN. The high-order spatial correlation features between components are extracted by the fusion operation of the normalized adjacency matrix and node features. Then, the spatial features of each time window are input into two layers of LSTM in temporal order. The temporal dynamic evolution law of spatial features is captured by the gating mechanism. No additional feature screening operation is required. The final feature of deep fusion of spatial and temporal features is directly output, thus completing the technical feature extraction process.

[0054] The model training method in this embodiment follows a data-driven approach, and the brief process is as follows: The time series sequence is divided into a training set and a test set in an 8:2 ratio. The model parameters of "2-layer GCN + 2-layer LSTM + fully connected layer" are initialized. The cross-entropy loss function is used to measure the prediction bias. The Adam optimizer is selected to adaptively adjust the learning rate (set to 0.001). The model is trained with a batch size of 32 and a maximum number of iterations of 100. The accuracy of the test set is monitored in real time. When the accuracy is ≥95% and there is no significant improvement for 5 consecutive iterations, the training is stopped, and the model training process is completed.

[0055] The other parts of this embodiment are the same as those in Embodiment 1 above, so they will not be described again.

[0056] Example 3: This embodiment is based on any one of Embodiments 1-2 above, such as Figure 1 , Figure 2 , Figure 3As shown, a detailed explanation is given using semiconductor etching equipment (one of the most widely used semiconductor manufacturing equipment) as a specific application.

[0057] This application focuses on a certain type of semiconductor etching equipment, which mainly consists of 12 key components (RF power supply, matching unit, reaction chamber, vacuum pump, gas flow controller, cooling system, etc.). Common typical faults include five categories (power overload, vacuum leakage, insufficient gas flow, abnormal reaction chamber temperature, and unstable RF power). The goal is to achieve accurate prediction of these five types of faults, with a prediction accuracy ≥95% and a prediction lead time ≥10 minutes. To more clearly illustrate the purpose, technical solution, and advantages of this invention, specific examples will be provided below in conjunction with the accompanying drawings. It should be noted that the described embodiments are only for explaining the invention and do not limit the implementation of the invention.

[0058] Step S1: Data Modeling and Acquisition Example; Monitoring components: 12 key components (RF power supply, reaction chamber, vacuum pump, etc.).

[0059] Sensor parameters: temperature (-50~300℃, accuracy ±0.5℃), pressure (0~100Pa, accuracy ±0.1Pa), voltage (0~380V, accuracy ±0.5V), sampling frequency 10Hz.

[0060] Data set size: 3 months of data (including 50 cases of each of the 5 types of faults and 1000 normal cases), totaling 14400 time series segments (each segment is 60 seconds).

[0061] Hardware: Sensors (temperature, pressure, voltage, etc.) deployed on key components of the equipment, and interfaces of the equipment control system (PLC / SCADA).

[0062] Function: Real-time acquisition of multi-source time-series data, defined as a matrix. ,in: N: Number of components (e.g., 12 key components); T: Time step (e.g., 10 minutes × 60 seconds = 600 time points); F: The feature dimensions of each component (such as temperature, vibration, etc., 3 features).

[0063] Parameter: Sampling frequency (Dynamically adjusted according to component response speed, such as 10Hz for RF power supply and 1Hz for temperature).

[0064] Example Process: Data acquisition was implemented by deploying corresponding sensors on 12 key components: voltage and power sensors for the RF power supply and matching unit; temperature and pressure sensors for the reaction chamber; pressure and vibration sensors for the vacuum pump; flow sensor for the gas flow controller; and temperature sensor for the cooling system, totaling 12 sensors. Sensor parameters are as follows: temperature sensor measurement range -50~300℃, accuracy ±0.5℃; pressure sensor measurement range 0~100Pa, accuracy ±0.1Pa; voltage sensor measurement range 0~380V, accuracy ±0.5V; flow sensor measurement range 0~100sccm, accuracy ±0.1sccm; vibration sensor measurement range 0~50g, accuracy ±0.01g. The acquisition frequency was uniformly set to 10Hz (the etching equipment components have a fast response speed, and 10Hz can fully capture early signs of faults). The acquisition period was 3 months, collecting complete data covering the normal operation status of the equipment and 5 typical fault states. This included 1000 cases of normal state data and 50 cases of each type of fault state data. The collected data was integrated into a three-dimensional matrix. (N=12 components, T=3 months × 30 days × 24 hours × 3600s × 10Hz = 180,000 time steps, F=3 feature dimensions), and then segmented into 60s time windows to obtain 14,400 standardized time series data segments, which are used for subsequent time series graph construction and model training.

[0065] Step S2: Data preprocessing; Outliers: Identified and replaced using the 3σ criterion (approximately 3% of the data are outliers).

[0066] Missing values: linear interpolation (missing rate <1%).

[0067] Standardization: Normalize according to component type (e.g., temperature features are mapped separately to [0,1]).

[0068] The data preprocessing steps are illustrated in the following implementation: Outlier cleaning uses the 3σ criterion. After identification, approximately 3% of the original data were outliers (mainly due to electromagnetic interference from sensors), and these were replaced with the median of five adjacent normal data points. Missing value imputation uses a differentiated strategy. The original data missing rate was 0.8%, all of which were short-term missing values ​​(continuous missing length ≤ 3). Linear interpolation formulas were used for imputation, resulting in good temporal continuity of the data. Standardization uses Min-Max standardization, and normalization is performed according to component type (e.g., temperature features are mapped separately to [0,1], and pressure features are mapped separately to [0,1]) to eliminate dimensional differences. Time series segmentation is performed in 60-second windows, resulting in 14,400 data segments. Each segment corresponds to 600 time points (10Hz × 60s) of standardized data, providing input for time series plot construction.

[0069] Sub-step 1: Outlier cleaning uses the 3σ criterion: For feature x, if , The mean, If the value is less than the standard deviation, it is considered an outlier and replaced with the median of the five adjacent normal data points. .

[0070] Sub-step 2: Missing value imputation for consecutive missing lengths The data is obtained using linear interpolation: For missing length The data is filled with the historical average of the component for the same period.

[0071] Sub-step 3: Standardization maps the data to the [0,1] interval to eliminate the influence of dimensions. .

[0072] Sub-step 4: Time series segmentation: Divide the data according to the time window W (e.g., , obtain the fragment set ,in .

[0073] Step S3: Constructing the sequence diagram; Node definition: using device components as nodes (e.g., N=12).

[0074] Edge and weight definitions: Physical connection edge: If component and There are mechanical / circuit connections (such as RF power supply → matching unit), weighting ; Data association edges: The correlation between non-physically connected components is calculated using the Pearson coefficient. Weight ,otherwise Pearson coefficient formula: Time series data: Each time window corresponds to one static graph. ,in Let k be the set of edges of the k-th window. The node features are used to ultimately form a time series graph sequence. .

[0075] Nodes: 12 components (numbered 1-12).

[0076] Edge weight: Physical connection: For example, the weight of node 1 (RF power supply) and node 2 (matching unit) is 1; Data correlation: Pearson coefficient of node 3 (reaction chamber) and node 4 (vacuum pump) = 0.82 → weight = 0.82.

[0077] The sequence of time-series graphs consists of 14,400 static graphs, each containing 12 nodes and an average of 15 edges.

[0078] The timing diagram construction process follows an implementation example that integrates physical and data association mechanisms: There are 12 key components (numbered 1-12), where node 1 is the RF power supply, node 2 is the matching unit, node 3 is the reaction chamber, node 4 is the vacuum pump, and node 5 is the gas flow controller, etc. Edge weights are set as follows: For physical connections, components with direct physical connections, such as node 1 (RF power supply) and node 2 (matching unit), node 3 (reaction chamber) and node 4 (vacuum pump), and node 5 (gas flow controller) and node 3 (reaction chamber), have the following edge weights. All are set to 1. Regarding data association edges, the correlation between components without direct physical connections is calculated using the Pearson coefficient. For example, the Pearson coefficient between node 3 (reaction chamber) and node 4 (vacuum pump) is 0.82, and the Pearson coefficient between node 1 (RF power supply) and node 3 (reaction chamber) is 0.78, both greater than 0.7. Therefore, the edge weights are set to 0.82 and 0.78 respectively. The Pearson coefficient between node 6 (cooling system) and node 11 (stage) is 0.56, less than 0.7, so no edge is constructed. Ultimately, each time window's static graph contains 12 nodes and an average of 15 edges. A sequence of 14,400 static graphs forms the time series graph sequence, used for model training and testing. This time series graph sequence clearly reflects the temporal evolution of component relationships during the etching equipment's operation, especially the abnormal correlations in the pre-fault stage (e.g., before vacuum leakage, the edge weight between node 3 and node 4 gradually increases from 0.82 to 0.95).

[0079] The model structure of the temporal graph neural network module is as follows: Figure 2 As shown in the model structure diagram, it adopts an architecture of "graph convolutional layer + temporal feature extraction layer + classification layer": Graph Convolutional Layer (GCN): Capturing Spatial Relationships. The first GCN layer fuses node features with the adjacency matrix, outputting spatial features. : in: (A is the adjacency matrix, I is the identity matrix, and D is the degree matrix). For the weight matrix ( ), The ReLU activation function is used. The second layer of GCN further extracts higher-order spatial features. ( ).

[0080] Temporal Feature Extraction Layer (LSTM): Captures dynamic changes by inputting the spatial features output by GCN into the LSTM in a time series manner. Let the hidden state at step t be... Cell state is ,but: in These represent the input gate, forget gate, and output gate, respectively, and (W_*, U_*) is the weight matrix. For bias, This is an element-wise product. LSTM outputs temporal fusion features. ( ).

[0081] Classification layer: Outputs fault probability through a fully connected layer and a softmax function, outputting fault type probability. in (C represents the number of fault types, such as 5 types of faults + 1 type of normal).

[0082] Step S4: Model Training and Performance; Model training: The loss function uses cross-entropy. in The labels are real-world labels (one-hot encoded). The optimizer uses Adam, and the learning rate is... Number of iterations Batch size .

[0083] Input: Real-time time series diagram sequence ( (One window, i.e., 5 minutes of data).

[0084] Output: Fault Type and corresponding probabilities .

[0085] Warning triggered: When ( When the value is dynamically adjustable, it is considered a fault warning.

[0086] Model parameters: 2-layer GCN (64→128 dimensions), 2-layer LSTM (128-dimensional hidden layers), and fully connected layer (6-dimensional output).

[0087] Training results: Test set accuracy: 96.8% (80.2% for LSTM, 88.5% for static GCN); Average lead time: 22 minutes; F1 score for each fault type: all ≥0.94 (average 0.81 using traditional methods).

[0088] Example of model training: The temporal graph neural network model adopts an architecture of "2-layer GCN + 2-layer LSTM + 1-layer fully connected layer". The first layer of the GCN has an output dimension of 64, the second layer has an output dimension of 128, the LSTM has a hidden layer dimension of 128, and the fully connected layer has an output dimension of 6 (5 types of faults + 1 type of normal state). The training set and test set are divided in an 8:2 ratio, with 11,520 time-series image segments in the training set and 2,880 time-series image segments in the test set. The cross-entropy loss function is used, the optimizer is Adam, the learning rate is set to 0.001, the number of iterations is 100, and the batch size is 32. During training, the model loss function gradually decreases. At the 86th iteration, the accuracy on the test set reaches 96.8%, and there is no significant improvement for 5 consecutive iterations. Training is then stopped, resulting in the completed fault prediction model. After training, the model performance was validated, and the results are as follows: the test set accuracy was 96.8%, which is 16.6% higher than the traditional LSTM model (80.2%) and 8.3% higher than the static GCN model (88.5%); the F1 scores for the five types of faults were: power overload 0.95, vacuum leakage 0.97, insufficient gas flow 0.94, abnormal reaction chamber temperature 0.96, and unstable RF power 0.95, with an average F1 score of 0.95; the average advance prediction time was 22 minutes, which fully meets the implementation objectives.

[0089] Step S5: Fault Prediction Example; When a slow leak occurs in a vacuum system: Real-time data: The vacuum pressure (node ​​4) rises slowly, while the reaction chamber temperature (node ​​3) fluctuates abnormally. The correlation weight between the two increases from 0.82 to 0.95.

[0090] Model output: "Vacuum leak" probability 0.87 ≥ 0.8 → trigger warning, failure expected in 25 minutes.

[0091] Maintenance response: Engineers replaced the seals in advance to avoid downtime.

[0092] Fault Prediction Example: A real-time prediction verification was performed using a vacuum leak fault. When a slow leak occurred in the vacuum system of the etching equipment, real-time data showed that the pressure parameter of node 4 (vacuum pump) slowly increased, while the temperature parameter of node 3 (reaction chamber) fluctuated abnormally. The Pearson coefficients of both gradually increased from 0.82 in the normal state to 0.95, and the weights of the corresponding edges in the time series graph increased synchronously. After preprocessing and constructing the time series graph, the real-time data was input into the trained model. The model output a probability of 0.87 for the "vacuum leak" fault, which is greater than the warning threshold of 0.8, triggering a fault warning. Based on the evolution trend of the time series features, the estimated time of fault occurrence was 25 minutes. After receiving the warning signal, the engineer promptly inspected the vacuum system and found that the slow leak was caused by aging seals. The seals were replaced in advance, avoiding equipment downtime and verifying the practical effectiveness and applicability of the technical solution of this invention.

[0093] The results of this implementation show that the technical solution of this embodiment can accurately predict the faults of semiconductor etching equipment. The prediction accuracy and lead time meet the industry requirements. Moreover, it has strong engineering feasibility, can effectively reduce equipment downtime losses, improve production continuity, and can be directly promoted and applied to various semiconductor manufacturing equipment.

[0094] The other parts of this embodiment are the same as any one of the above embodiments 1-2, so they will not be described again.

[0095] Example 4: Based on any one of Embodiments 1-3 above, this embodiment proposes a semiconductor equipment fault prediction system based on a time-series graph neural network, used to execute the above-described semiconductor equipment fault prediction method based on a time-series graph neural network; it includes a data acquisition module, a data preprocessing module, a graph structure construction module, a fault feature extraction and prediction module, a model training module, and a result output module; The data acquisition module is used to acquire timing operation data of semiconductor device components and generate a data matrix; The data preprocessing module is used to preprocess the data matrix and perform time-series segmentation to obtain standardized semiconductor component time-series segments. The graph structure construction module is used to construct a time series graph sequence by using semiconductor components as nodes and determining edge weights according to the set Pearson coefficients. The fault feature extraction and prediction module is used to divide the time series sequence into a training set and a test set, input them into the constructed time series neural network model for training, and optimize the model through the cross-entropy loss function to obtain the trained time series neural network model. The model training module is used to input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability. The result output module is used to determine whether the semiconductor device has a fault based on the fault probability and generate a semiconductor device fault prediction result.

[0096] This embodiment also proposes an electronic device, including a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the above-described semiconductor device fault prediction method based on a time-series graph neural network.

[0097] This embodiment also proposes a computer-readable storage medium storing computer instructions; when the computer instructions are executed on the aforementioned electronic device, the aforementioned semiconductor device fault prediction method based on a time-series graph neural network is implemented.

[0098] The other parts of this embodiment are the same as any one of the embodiments 1-3 above, so they will not be described again.

[0099] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A semiconductor device fault prediction method based on a time-series graph neural network, characterized in that, Specifically, the following steps are included: Step S1: Collect timing data of semiconductor device components and generate a data matrix; Step S2: Preprocess the data matrix and perform timing segmentation to obtain standardized semiconductor component timing segments; Step S3: Using semiconductor components as nodes, determine the edge weights according to the set Pearson coefficients, and construct a timing graph sequence; Step S4: Divide the time series sequence into training set and test set, input them into the constructed time series neural network model for training, and optimize it through the cross-entropy loss function to obtain the trained time series neural network model; Step S5: Input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability; Step S6: Determine whether the semiconductor equipment is faulty based on the fault probability, and generate semiconductor equipment fault prediction results.

2. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 1, characterized in that, Step S1 specifically includes the following steps: Step S11: Based on the component distribution characteristics of the semiconductor equipment, deploy corresponding types of sensors on the key components of the equipment, and collect process parameter data through the equipment control system interface to obtain multi-source timing data; Step S12: Based on the component's feature dimensions, the number of key components of the device, and the set total time step, integrate the multi-source time series data into a three-dimensional data matrix.

3. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 1, characterized in that, Step S2 specifically includes the following steps: Step S21: Use the 3σ criterion to identify outliers in the three-dimensional data matrix and perform outlier cleaning; Step S22: Fill in the missing values ​​in the cleaned 3D data matrix to obtain the filled 3D data matrix; Step S23: Standardize the filled 3D data matrix to obtain a standardized 3D data matrix; Step S24: Divide the standardized three-dimensional data matrix according to the set time window to obtain the standardized semiconductor component timing segment.

4. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 1, characterized in that, Step S3 specifically includes the following steps: Step S31: Based on the standardized semiconductor component timing segments, determine whether there are physical connection edges between semiconductor components. If they exist, it is determined that there is an inherent relationship between the semiconductor components, and the edge weight is set to 1. If there are no physical connection edges, the Pearson coefficient is used to calculate the correlation of the semiconductor component timing data. Step S32: Determine whether there is a dynamic correlation between semiconductor components based on the Pearson coefficient. If there is a dynamic correlation, set the edge weight to the absolute value of the Pearson coefficient. If there is no dynamic correlation, set the edge weight to 0. Step S33: Using the key components of the semiconductor device as nodes, construct a timing graph according to the set edge weights to obtain a timing graph sequence.

5. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 1, characterized in that, Step S4 specifically includes the following steps: Step S41: Construct a temporal graph neural network; the temporal graph neural network includes a graph convolutional layer, a temporal feature extraction layer, and a classification layer; Step S42: Input the temporal graph sequence into the graph convolutional layer to extract high-order spatial features; Step S43: Input the high-order spatial features into the temporal feature extraction layer to obtain the fused features; Step S44: Input the fused features into the classification layer to obtain the probability distribution of the fault categories.

6. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 5, characterized in that, Step S42 specifically includes the following steps: Step S421: Input the time series diagram sequence into the first convolutional layer; the convolutional layer includes a first convolutional layer and a second convolutional layer; Step S422: Obtain the adjacency matrix based on the edge weight matrix of the time series graph; Step S423: Based on the normalized adjacency matrix, the degree matrix of the adjacency matrix, the set first weight matrix, the set first bias, and the set identity matrix, call the activation function to obtain the primary spatial features; Step S424: Input the primary spatial features into the second convolutional layer, and obtain the higher-order spatial features according to the set second weight matrix and second bias.

7. The semiconductor device fault prediction method based on a time-series graph neural network according to claim 1, characterized in that, Step S6 specifically includes the following steps: Step S61: Preprocess the acquired real-time operating data of the semiconductor device and construct a real-time timing sequence. Step S62: According to the set window, input the real-time time series sequence into the trained time series neural network model to obtain the predicted state category and the probability of the corresponding category; Step S63: If the probability of the corresponding category is greater than or equal to the set warning threshold, and the status category is a fault type, a fault warning is determined and a fault prediction result is output; if the probability of the corresponding category is less than the set warning threshold or the status category is a normal state, the equipment is determined to be operating normally and a prediction result is output.

8. A semiconductor device fault prediction system based on a time-series graph neural network, used to execute the semiconductor device fault prediction method based on a time-series graph neural network as described in claim 1; characterized in that, It includes a data acquisition module, a data preprocessing module, a graph structure construction module, a fault feature extraction and prediction module, a model training module, and a result output module; The data acquisition module is used to acquire timing operation data of semiconductor device components and generate a data matrix; The data preprocessing module is used to preprocess the data matrix and perform time-series segmentation to obtain standardized semiconductor component time-series segments. The graph structure construction module is used to construct a time series graph sequence by using semiconductor components as nodes and determining edge weights according to the set Pearson coefficients. The fault feature extraction and prediction module is used to divide the time series sequence into a training set and a test set, input them into the constructed time series neural network model for training, and optimize the model through the cross-entropy loss function to obtain the trained time series neural network model. The model training module is used to input the acquired real-time data into the trained time-series graph neural network model to obtain the fault type and fault probability. The result output module is used to determine whether the semiconductor device has a fault based on the fault probability and generate a semiconductor device fault prediction result.

9. An electronic device, characterized in that, It includes a memory and a processor; the memory stores a computer program; when the computer program is executed on the processor, it implements the semiconductor device fault prediction method based on a time-series graph neural network as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; when the computer instructions are executed on the electronic device as described in claim 9, they implement the semiconductor device fault prediction method based on a time-series graph neural network as described in any one of claims 1-7.

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