Highly selective and simple structure filter power amplifier and radio frequency integrated circuit

Abstract

The application provides a high-selectivity and simple-structure filter power amplifier and radio frequency integrated circuit, and relates to the field of power semiconductor devices.The application provides stable gate and drain bias voltages for the power amplifier transistor through a gate DC bias network and a drain DC bias network, and guarantees stable operation of the device.The input end and the output end impedance matching network are symmetrically arranged around the power amplifier transistor, both of which contain the same filter impedance transformer, and the layout is compact and simple, without additional independent filter module, effectively simplifying the circuit structure and improving the miniaturization level.Further, the filter impedance transformer is formed by cascading two λ / 4 parallel coupled microstrip lines and is matched with a λ / 2 open microstrip line, and based on the transmission line impedance transformation principle, the filter impedance transformer realizes fundamental real impedance matching, reduces signal transmission loss, forms transmission zero points in the stop band, and significantly improves the frequency selectivity.The overall circuit has high integration, excellent performance, and good engineering application and promotion value.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor devices, and more specifically to a highly selective and structurally simple filtered power amplifier and radio frequency integrated circuit. Background Technology

[0002] With the development of wireless communication and radio frequency microwave technology, communication systems are increasingly demanding lower loss, higher efficiency, smaller size, and higher selectivity from their RF front-ends. Filtered power amplifiers, which integrate filtering, impedance matching, and power amplification functions, have become a key technology for meeting the high-performance and integrated needs of modern communication systems.

[0003] In related technologies, existing filter power amplifiers use a filter output matching network based on coupled lines, which includes multiple impedance tuning lines and two sets of parallel coupled lines. By loading parallel coupled lines and short-circuit step impedance stubs in the impedance transformer, fundamental impedance matching and second harmonic suppression are achieved. The signal is output to the load from the drain of the amplifier transistor through the matching network.

[0004] However, the existing solutions mentioned above have obvious shortcomings: the circuit requires a large number of impedance tuning lines and has a complex topology, which is not conducive to miniaturization; the structure focuses on ultra-wideband matching and has insufficient frequency selectivity; complex branches and multi-stage tuning increase insertion loss, making it impossible to maintain high efficiency while taking into account simple structure, miniaturized size and high frequency selectivity. Summary of the Invention

[0005] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides a highly selective and simple-structured filter power amplifier and RF integrated circuit, solving the technical problems of existing filter power amplifiers, such as complex structure, low miniaturization, poor frequency selectivity, and high loss.

[0006] (II) Technical Solution To achieve the above objectives, the present invention provides the following technical solution: A highly selective and structurally simple filtered power amplifier includes a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor, and an output impedance matching network. The input terminal of the impedance matching network is the signal input port, and the output terminal is connected to the gate of the power amplifier transistor. The drain of the power amplifier transistor is connected to the input terminal of the output impedance matching network, and the output terminal of the output impedance matching network is a signal output port. The gate DC bias network is connected to the gate of the power amplifier transistor and is used to provide the gate bias voltage; The drain DC bias network is connected to the drain of the power amplifier transistor and is used to provide a drain bias voltage. The input impedance matching network and the output impedance matching network are symmetrically arranged about the power amplifier transistor, and both include filter impedance transformers with the same structure. The filter impedance converter is composed of two parallel coupled microstrip lines of length λ / 4 cascaded together and connected to an open-circuit microstrip line of length λ / 2; where λ is the center wavelength corresponding to the center frequency of the filter power amplifier.

[0007] Preferably, the gate DC bias network includes a first bias microstrip line with a length of λ / 2, a stabilizing resistor, and a first bypass filter capacitor; One end of the first bias microstrip line is connected to the gate bias voltage, and the other end is connected to the gate of the power amplifier transistor via the stabilizing resistor. One end of the first bypass filter capacitor is connected to the gate bias voltage input terminal, and the other end is grounded.

[0008] Preferably, the drain DC bias network includes a second bias microstrip line with a length of λ / 2 and a second bypass filter capacitor; One end of the second bias microstrip line is connected to the drain bias voltage, and the other end is connected to the drain of the power amplifier transistor. One end of the second bypass filter capacitor is connected to the input terminal of the drain bias voltage, and the other end is grounded.

[0009] Preferably, the input impedance matching network includes a first filter impedance transformer, a first tuned microstrip line, and a stabilizing capacitor. The first filter impedance transformer is composed of a first parallel-coupled microstrip line, a second parallel-coupled microstrip line, and a first open-circuit microstrip line. The first parallel-coupled microstrip line is provided with a first input port, a first stub connection port and a first cascade port. The first input port is connected to an external signal input port, the first stub connection port is connected to a first open-circuit microstrip line, and the first cascade port is connected to the input terminal of the second parallel-coupled microstrip line. The output terminal of the second parallel-coupled microstrip line is connected in series with the stabilizing capacitor and then connected to the gate of the power amplifier transistor. The first tuning microstrip line is connected to the path between the stabilizing capacitor and the gate of the power amplifier transistor.

[0010] Preferably, the output impedance matching network includes a second filter impedance transformer, a second tuned microstrip line, and a harmonic suppression open-circuit microstrip line. The second filter impedance transformer is composed of a third parallel-coupled microstrip line, a fourth parallel-coupled microstrip line, and a second open-circuit microstrip line. The input terminal of the third parallel-coupled microstrip line is connected in series with the second tuning microstrip line and then connected to the drain of the power amplifier transistor. The harmonic suppression open-circuit microstrip line is connected in parallel to the common node between the drain and the second tuned microstrip line; The fourth parallel-coupled microstrip line is provided with a second input port, a second stub connection port and a second cascade port. The second input port is connected to the output terminal of the third parallel-coupled microstrip line, the second stub connection port is connected to the second open-circuit microstrip line, and the second cascade port is led out to form a signal output port.

[0011] Preferably, the length of the harmonic suppression open-circuit microstrip line is λ / 12.

[0012] Preferably, the input impedance matching network is used to match the standard 50Ω port impedance to the optimal source impedance of the power amplifier transistor gate; The output impedance matching network is used to match the standard 50Ω port impedance to the optimal load impedance of the power amplifier transistor drain.

[0013] Preferably, the power amplifier transistor is a GaN HEMT CGH40010F.

[0014] A radio frequency integrated circuit integrates a highly selective and structurally simple filtered power amplifier as described above.

[0015] (III) Beneficial Effects This invention provides a highly selective and structurally simple filtered power amplifier. Compared with the prior art, it has the following advantages: This invention provides stable gate and drain bias voltages to the power amplifier transistor through gate DC bias networks and drain DC bias networks, respectively, ensuring stable device operation. The input and output impedance matching networks are symmetrically arranged around the power amplifier transistor, both containing identical filter impedance transformers. This compact and simple layout eliminates the need for additional independent filter modules, effectively simplifying the circuit structure and improving miniaturization. Furthermore, this filter impedance transformer is composed of two cascaded λ / 4 parallel-coupled microstrip lines, paired with a λ / 2 open-circuit microstrip line. Based on the transmission line impedance transformation principle, it achieves fundamental impedance matching, reducing signal transmission loss and creating a transmission zero in the stopband, significantly improving frequency selectivity. The overall circuit exhibits high integration and excellent performance, possessing significant engineering application and promotional value. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of a highly selective and simple filter power amplifier provided in an embodiment of the present invention; Figure 2 A topology diagram of a gate DC bias network and an input impedance matching network provided in an embodiment of the present invention; Figure 3 A topology diagram of a drain DC bias network and an output impedance matching network provided in an embodiment of the present invention; Figure 4 A schematic diagram of the S-parameter simulation results of a real impedance matching network for an input impedance transformer and an output impedance transformer provided in an embodiment of the present invention; Figure 5 The figure shows the simulation results of output power, drain efficiency and gain provided for an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention provides a highly selective, structurally simple, and highly integrated filter power amplifier. Its core technology integrates filtering and impedance matching functions, employing an input and output impedance matching network symmetrically distributed with respect to the power amplifier transistors. Fundamental impedance matching is achieved based on the transmission line impedance transformation principle. The filter impedance transformer is constructed using two λ / 4 parallel-coupled microstrip lines and a λ / 2 open-circuit microstrip line, creating a transmission zero in the stopband and improving frequency selectivity. Simultaneously, a dedicated branch is added at the output to suppress third harmonics, eliminating the complex architecture of traditional discrete filter and amplifier cascades, reducing circuit size, lowering insertion loss, and comprehensively improving power amplifier efficiency and harmonic suppression capabilities.

[0020] To clearly illustrate the circuit structure and facilitate understanding and implementation, such as Figures 1-3The related devices are uniformly numbered (this numbering is only used for the illustration of this embodiment and does not affect the scope of protection of the claims): parallel coupled microstrip lines are a special structure of microstrip lines and are numbered separately as CL1 to CL4; other types of microstrip lines are uniformly numbered as TL1 to TL7. Among them, the TL series microstrip lines include bias microstrip lines, open-circuit microstrip lines, and tuned microstrip lines. The numbering is clearly classified to facilitate the description and understanding of the subsequent implementation methods.

[0021] In this embodiment, the core structure of the filter power amplifier is as follows: The input impedance matching network and the output impedance matching network are symmetrically arranged about the power amplifier transistor. Both contain a filter impedance transformer with the same structure. This transformer is composed of two parallel coupled microstrip lines of length λ / 4 (corresponding to CL1~CL4) cascaded together and connected to open-circuit microstrip lines of length λ / 2 (corresponding to TL1 and TL5). Tuning microstrip lines (corresponding to TL2 and TL3) are configured on the input and output sides respectively to achieve impedance and phase auxiliary tuning. An additional dedicated harmonic suppression microstrip line (corresponding to TL4) of length λ / 12 is set at the output end, which is specifically used to suppress the third harmonic and optimize the output spectrum. The whole system realizes an integrated design of filtering and impedance matching.

[0022] Based on the transmission line impedance transformation principle, the aforementioned filter impedance transformer can match the standard 50Ω port impedance to the optimal operating impedance of the power amplifier transistor, eliminating the mismatch loss caused by complex impedance and ensuring efficient signal transmission. The λ / 2 open-circuit microstrip lines (corresponding to TL1 and TL5) and parallel-coupled microstrip lines (corresponding to CL1~CL4) work together to accurately form transmission zeros in the target stopband, significantly improving the circuit's frequency selectivity and out-of-band rejection level. The dedicated harmonic suppression microstrip line at the output end (corresponding to TL4) can specifically attenuate high-order spurious components, further purifying the output spectrum. Simultaneously, the gate DC bias network and drain DC bias network are respectively configured with dedicated bias microstrip lines (corresponding to TL6 and TL7) to provide stable bias and reliable static operating conditions for the power amplifier transistor. This solution eliminates the need for additional discrete filtering components, resulting in a compact and simple circuit topology with high integration, effectively overcoming the shortcomings of traditional RF amplifier circuits, such as complex structures, high losses, and insufficient harmonic suppression.

[0023] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0024] Example 1: like Figure 1 As shown, this embodiment of the invention provides a highly selective and structurally simple filtered power amplifier, including a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor, and an output impedance matching network.

[0025] The input terminal of the input impedance matching network is the signal input port, and the output terminal is connected to the gate of the power amplifier transistor. The drain of the power amplifier transistor is connected to the input terminal of the output impedance matching network, and the output terminal of the output impedance matching network is a signal output port. The gate DC bias network is connected to the gate of the power amplifier transistor and is used to provide the gate bias voltage; The drain DC bias network is connected to the drain of the power amplifier transistor and is used to provide a drain bias voltage. The input impedance matching network and the output impedance matching network are symmetrically arranged about the power amplifier transistor, and both include filter impedance transformers with the same structure. The filter impedance converter is composed of two parallel coupled microstrip lines of length λ / 4 cascaded together and connected to an open-circuit microstrip line of length λ / 2; where λ is the center wavelength corresponding to the center frequency of the filter power amplifier.

[0026] The embodiments of this invention are designed by combining the theory of filter impedance transformation and the theory of harmonic suppression. The input and output real impedance matching is achieved by using the same type of impedance transformer that is symmetrical about the power amplifier transistor, which is beneficial to circuit miniaturization and structural simplification.

[0027] The filtered power amplifier provided in this invention integrates filtering and impedance matching. By utilizing a symmetrical matching network with λ / 4 coupled microstrip lines and λ / 2 open-circuit microstrip lines, it simplifies the circuit and improves integration while taking into account impedance matching and high-frequency selectivity, ensuring stable operation of the power amplifier. In an optional implementation, the present invention provides a gate-specific bias microstrip line and a bypass filter structure to stabilize the gate power supply, suppress radio frequency interference, and ensure reliable transistor operation.

[0028] Correspondingly, such as Figure 1 As shown, the gate DC bias network includes a first bias microstrip line TL6 with a length of λ / 2, a stabilizing resistor R1, and a first bypass filter capacitor C. bypass-1 .

[0029] One end of the first bias microstrip line TL6 is connected to the gate bias voltage V. GS The other end is connected to the gate of the power amplifier transistor via the stabilizing resistor R1; The first bypass filter capacitor C bypass-1 One end is connected to the gate bias voltage V GS One end is the access point, and the other end is grounded.

[0030] In an optional implementation, the present invention provides a drain-biased microstrip line and a bypass capacitor to achieve stable DC power supply, isolate radio frequency signals, and reduce the impact of power supply noise.

[0031] Correspondingly, such as Figure 1 As shown, the drain DC bias network includes a second bias microstrip line TL7 with a length of λ / 2 and a second bypass filter capacitor C. bypass-2 .

[0032] One end of the second bias microstrip line TL7 is connected to the drain bias voltage V. DS The other end is connected to the drain of the power amplifier transistor; The second bypass filter capacitor C bypass-2 One end is connected to the drain bias voltage V DS One end is the access point, and the other end is grounded.

[0033] Furthermore, embodiments of the present invention also define a combined structure of an input-side filter converter, a tuned microstrip line, and a stabilizing capacitor to achieve input-side impedance matching and optimize signal input transmission characteristics.

[0034] Correspondingly, such as Figure 2 As shown, the input impedance matching network includes a first filter impedance transformer, a first tuned microstrip line TL2, and a stabilizing capacitor C1. The first filter impedance transformer is composed of a first parallel coupled microstrip line CL1 with a length of λ / 4, a second parallel coupled microstrip line CL2 with a length of λ / 4, and a first open-circuit microstrip line TL1 with a length of λ / 2.

[0035] The first parallel-coupled microstrip line CL1 is provided with a first input port, a first stub connection port and a first cascade port. The first input port is connected to an external signal input port IN. The first stub connection port is connected to a first open-circuit microstrip line TL1. The first cascade port is connected to the input terminal of the second parallel-coupled microstrip line CL2. The output terminal of the second parallel-coupled microstrip line CL2 is connected in series with the stabilizing capacitor C1 and then connected to the gate of the power amplifier transistor. The first tuning microstrip line TL2 is connected to the path between the stabilizing capacitor C1 and the gate of the power amplifier transistor.

[0036] It should be noted that in the above input topology, the stabilizing capacitor C1 and the stabilizing resistor R1 of the gate branch of the power amplifier transistor cooperate to form a stabilizing circuit on the gate side of the transistor, as shown below. Figure 2As shown, this stabilizing circuit can isolate the DC bias from the front-end RF path, preventing DC signal backflow from affecting the operation of the filter impedance converter; on the other hand, it can improve the low-frequency stability of the circuit, suppress the risk of self-oscillation, and optimize the phase and impedance matching effect of the input signal, ensuring the stable and reliable static operating point of the transistor.

[0037] Furthermore, to quantitatively analyze the impedance matching and transmission characteristics of this filter impedance converter, the matrix parameters of the core parallel-coupled microstrip line are derived as follows: The ABCD matrix of the first parallel coupled microstrip line CL1 is defined as follows: in, , The odd and even model sexual resistances of CL1 are respectively; Electric length; The imaginary unit; , These are the cosecant and cotangent trigonometric functions, respectively.

[0038] Similarly, when deriving the ABCD matrix of CL2, port 3 of the coupled line is defined as the theoretical open-circuit boundary, satisfying that there is no net conduction current at the port; port 4 is... Figure 2 The grounding terminal of CL2 is constrained so that its port voltage U4 = 0. Therefore, the ABCD matrix of CL2 is: in, , The odd and even mode sexual impedances of CL2 are respectively.

[0039] It is particularly important to clarify that ports 3 and 4, as defined in the above derivation, are not the input or output terminals of the second parallel-coupled microstrip line CL2 as previously specified: the input terminal of CL2 is the signal input port cascaded with CL1, used to receive the RF main signal transmitted from the front stage of the filter impedance converter; the output terminal of CL2 is the main signal output port leading to the right, connected to the stabilizing capacitor C1, and ultimately leading to the transistor gate; while ports 3 and 4 are an additional set of coupling auxiliary ports defined during the electromagnetic analysis of the parallel-coupled microstrip line itself, not the input / output ports of the RF main path. Port 3 is the theoretical open-circuit reference port on the coupling isolation side, and port 4 is... Figure 2 The actual grounding physical port at the bottom of CL2.

[0040] By adopting identical port boundary assumptions for CL1 and CL2, this embodiment of the invention ensures that the derivation rules and theoretical models of the ABCD matrix are completely consistent, greatly simplifying the parameter calculation of the overall impedance transformation network after the two coupled lines are cascaded, and accurately obtaining the matching conditions and zero-point distribution characteristics at the center frequency.

[0041] In electrical length Under the condition of 90° (λ / 4), the total ABCD matrix of the basic module formed by the cascaded CL1 and CL2 is simplified as follows: It should be noted that the total ABCD matrix of the above basic modules is in diagonal form, indicating that the corresponding modules are pure impedance transformation networks at the center frequency, without additional phase shift and loss.

[0042] From this, the reflection coefficient at the center frequency can be derived. : When center frequency matching is achieved, the following requirements are required. =0, satisfying the condition: in, The impedance transformation ratio is the square root; , These are the even-mode impedances of CL1 and CL2, respectively. , These are the odd-mode impedances of CL1 and CL2, respectively.

[0043] Given odd-mode impedance The even-mode impedance of the parallel-coupled microstrip line can be further obtained: in, The odd-mode impedance is set uniformly; This is the coupling coefficient corresponding to CL2.

[0044] At this point, it is clear that only the determination of... With coupling coefficient This allows for the design of all parameters of the filter impedance converter.

[0045] Furthermore, by loading a first open-circuit microstrip line TL1 with λ / 2 at the port of the second parallel-coupled microstrip line CL2, two transmission zeros can be introduced in the stopband, significantly improving out-of-band rejection and frequency selectivity.

[0046] Meanwhile, the embodiments of the present invention also define an output converter and a tuned microstrip line, and add a dedicated harmonic suppression branch to enhance the harmonic suppression capability while meeting the load impedance matching requirements.

[0047] Correspondingly, such as Figure 3As shown, the output impedance matching network includes a second filter impedance transformer, a second tuned microstrip line TL3, and a harmonic suppression open-circuit microstrip line TL4. The second filter impedance transformer is composed of a third parallel coupled microstrip line CL3 with a length of λ / 4, a fourth parallel coupled microstrip line CL4 with a length of λ / 4, and a second open-circuit microstrip line TL5 with a length of λ / 2.

[0048] The input terminal of the third parallel-coupled microstrip line CL3 is connected in series with the second tuning microstrip line TL3 and then connected to the drain of the power amplifier transistor. The harmonic suppression open-circuit microstrip line TL4 is connected in parallel to the common node between the drain and the second tuned microstrip line TL3; The fourth parallel-coupled microstrip line CL4 is provided with a second input port, a second stub connection port and a second cascade port. The second input port is connected to the output terminal of the third parallel-coupled microstrip line CL3, the second stub connection port is connected to the second open-circuit microstrip line TL5, and the second cascade port is led out to form a signal output port OUT.

[0049] It should be noted that, in the preferred embodiment described above, the length of the harmonic suppression open-circuit microstrip line TL4 is λ / 12, which can adjust the drain complex impedance of the power amplifier transistor to the real impedance, effectively suppress the second and third harmonic components, optimize the output spectrum, and achieve an integrated design of filtering and impedance matching.

[0050] Based on this, the standard 50Ω input impedance is matched to the optimal source impedance of the power amplifier transistor gate through the input impedance matching network, and the standard 50Ω load impedance is matched to the optimal load impedance of the drain through the output impedance matching network, thereby further improving the circuit efficiency.

[0051] It is understood that the embodiments of the present invention do not strictly limit the selection of the various components of the above-mentioned filter power amplifier. Those skilled in the art can make their own selections according to actual needs. For example, in an optional embodiment, the power amplifier transistor is GaN HEMT CGH40010F or other types.

[0052] To verify the feasibility and performance of the above technical solution, the filtering and impedance matching characteristics of the impedance transformer are explained below based on simulation results. See below for details. Figure 4 and Figure 5 : Figure 4 The diagram shows the S-parameter simulation results of the input impedance matching network and the filter impedance transformer included in the output impedance matching network; the red curve represents the input return loss (input reflection coefficient). The blue curve represents the forward insertion loss (forward transmission coefficient). The S-parameter simulation results show that the filter impedance transformer generates two transmission zeros and two parameter poles, which significantly improves frequency selectivity and enhances out-of-band filtering characteristics.

[0053] Figure 5 The simulation results for output power, drain efficiency, and gain are shown in the figure. The results show that the designed power amplifier has a drain efficiency of 75.1%-78.4% in the 3.3-3.6GHz frequency band, a saturated output power of 39.4-40.4dBm, and a gain of 10.4-11.4dB, demonstrating good performance indicators.

[0054] Example 2: This invention provides a radio frequency integrated circuit that integrates the highly selective and structurally simple filter power amplifier described in Embodiment 1.

[0055] It is understood that since the radio frequency integrated circuit provided in Embodiment 2 integrates the highly selective and structurally simple filter power amplifier device provided in Embodiment 1, the explanations, examples and beneficial effects of the relevant contents can be referred to the corresponding parts of the highly selective and structurally simple filter power amplifier device provided in Embodiment 1, and will not be repeated here.

[0056] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0057] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A highly selective and structurally simple filtered power amplifier, characterized in that, This includes a gate DC bias network, a drain DC bias network, an input impedance matching network, a power amplifier transistor, and an output impedance matching network. The input terminal of the impedance matching network is the signal input port, and the output terminal is connected to the gate of the power amplifier transistor. The drain of the power amplifier transistor is connected to the input terminal of the output impedance matching network, and the output terminal of the output impedance matching network is a signal output port. The gate DC bias network is connected to the gate of the power amplifier transistor and is used to provide the gate bias voltage; The drain DC bias network is connected to the drain of the power amplifier transistor and is used to provide a drain bias voltage. The input impedance matching network and the output impedance matching network are symmetrically arranged about the power amplifier transistor, and both include filter impedance transformers with the same structure. The filter impedance converter is composed of two parallel coupled microstrip lines of length λ / 4 cascaded together and connected to an open-circuit microstrip line of length λ / 2; where λ is the center wavelength corresponding to the center frequency of the filter power amplifier.

2. The filtered power amplifier as described in claim 1, characterized in that, The gate DC bias network includes a first bias microstrip line with a length of λ / 2, a stabilizing resistor, and a first bypass filter capacitor. One end of the first bias microstrip line is connected to the gate bias voltage, and the other end is connected to the gate of the power amplifier transistor via the stabilizing resistor. One end of the first bypass filter capacitor is connected to the gate bias voltage input terminal, and the other end is grounded.

3. The filtered power amplifier as described in claim 1, characterized in that, The drain DC bias network includes a second bias microstrip line with a length of λ / 2 and a second bypass filter capacitor. One end of the second bias microstrip line is connected to the drain bias voltage, and the other end is connected to the drain of the power amplifier transistor. One end of the second bypass filter capacitor is connected to the input terminal of the drain bias voltage, and the other end is grounded.

4. The filtered power amplifier as described in claim 1, characterized in that, The input impedance matching network includes a first filter impedance transformer, a first tuned microstrip line, and a stabilizing capacitor. The first filter impedance transformer is composed of a first parallel coupled microstrip line, a second parallel coupled microstrip line, and a first open-circuit microstrip line. The first parallel-coupled microstrip line is provided with a first input port, a first stub connection port and a first cascade port. The first input port is connected to an external signal input port, the first stub connection port is connected to a first open-circuit microstrip line, and the first cascade port is connected to the input terminal of the second parallel-coupled microstrip line. The output terminal of the second parallel-coupled microstrip line is connected in series with the stabilizing capacitor and then connected to the gate of the power amplifier transistor. The first tuning microstrip line is connected to the path between the stabilizing capacitor and the gate of the power amplifier transistor.

5. The filtered power amplifier as described in claim 1, characterized in that, The output impedance matching network includes a second filter impedance transformer, a second tuned microstrip line, and a harmonic suppression open-circuit microstrip line. The second filter impedance transformer is composed of a third parallel-coupled microstrip line, a fourth parallel-coupled microstrip line, and a second open-circuit microstrip line. The input terminal of the third parallel-coupled microstrip line is connected in series with the second tuning microstrip line and then connected to the drain of the power amplifier transistor. The harmonic suppression open-circuit microstrip line is connected in parallel to the common node between the drain and the second tuned microstrip line; The fourth parallel-coupled microstrip line is provided with a second input port, a second stub connection port and a second cascade port. The second input port is connected to the output terminal of the third parallel-coupled microstrip line, the second stub connection port is connected to the second open-circuit microstrip line, and the second cascade port is led out to form a signal output port.

6. The filtered power amplifier as described in claim 5, characterized in that, The length of the harmonic suppression open-circuit microstrip line is λ / 12.

7. The filtered power amplifier as described in claim 1, characterized in that, The input impedance matching network is used to match the standard 50Ω port impedance to the optimal source impedance of the power amplifier transistor gate. The output impedance matching network is used to match the standard 50Ω port impedance to the optimal load impedance of the power amplifier transistor drain.

8. The filtered power amplifier as described in claim 1, characterized in that, The power amplifier transistor used is GaNHEMT CGH40010F.

9. A radio frequency integrated circuit, characterized in that, It integrates a highly selective and structurally simple filtered power amplifier as described in any one of claims 1-8.

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