Comparator circuit with latching function and control method thereof

Abstract

This invention provides a comparator circuit with latching function and its control method. The comparator circuit with latching function uses an initial voltage provided by a pre-comparison module. The initial voltage is dynamically adjusted based on the input comparison voltage to generate a first current variable. This first current variable is converted into a control voltage, and a first comparison result is output based on the control voltage. The first comparison result is compared and positive feedback latched by the latching module to obtain a second comparison result. This comparator circuit with latching function, designed for low-to-medium precision and low-frequency applications, replaces the redundant design and related bias circuits of multi-stage operational amplifier cascades with a pre-comparison module. The common-mode voltage bias is integrated into the structure of the pre-comparison module, simplifying the circuit structure. This comparator circuit does not interfere with the preceding or following circuits, reducing process sensitivity.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and in particular to a comparator circuit with latching function and its control method. Background Technology

[0002] Successive approximation analog-to-digital converters (ADCs) achieve an excellent balance between power consumption, area, speed, and accuracy, making them a highly capable architecture. However, when pursuing higher comparison accuracy and speed, preamplifiers and latches are often used in their design.

[0003] Currently, the first-stage preamplifier circuit amplifies the input comparison voltage and directly inputs it into the latch structure of the subsequent stage. This structure designs the preamplifier as the core of the comparator. In successive approximation analog-to-digital converters (ADCs), two to three cascaded operational amplifiers are required as preamplifier circuits. To ensure that each amplifier stage does not interfere with each other, a buffer is also needed between the two stages. In practical applications, successive approximation ADCs are generally used in low-to-medium precision and low-frequency bands. In these application scenarios, using multi-stage cascaded operational amplifiers as preamplifiers would lead to performance overkill. To ensure the operation of multi-stage operational amplifiers, more bias circuits and common-mode voltage related designs for each stage are also required. Summary of the Invention

[0004] This invention provides a comparator circuit with latching function and its control method to solve the technical problems of complex operational amplifier circuit structure, excessive performance in practical applications, and large demand for auxiliary circuits in the comparator structure of the above-mentioned successive approximation analog-to-digital converter.

[0005] In a first aspect, the present invention provides a comparator circuit with latching function, comprising:

[0006] A pre-comparison module, whose input is connected to a comparison voltage and provides an initial voltage, is used to dynamically adjust the initial voltage based on the comparison voltage to generate a first current variable, and to convert the first current variable into a control voltage to output a first comparison result according to the control voltage; The latching module, connected to the output of the pre-comparison module, compares the first comparison result and performs positive feedback latching to obtain the second comparison result.

[0007] In one embodiment of the present invention, the pre-comparison module includes two branch comparison units. Each branch comparison unit provides the initial voltage. The input terminals of the two branch comparison units cooperate to input the comparison voltage. The initial voltage is dynamically adjusted based on the comparison voltage, and a first current variable is generated based on the adjusted voltage difference. A second current variable is obtained according to the current splitting relationship between the first current variable and the total branch current. The control voltage is determined based on the second current variable. Under the adjustment of the control voltage, the two branch comparison units cooperate to output the first comparison result.

[0008] In one embodiment of the present invention, the branch comparison unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a first switch. The source of the first PMOS transistor is connected to a power supply voltage, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The first terminal of the first switch is connected to the drain of the first NMOS transistor. The second terminal of the switch is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is grounded, the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the fourth PMOS transistor is grounded. The gate of the first NMOS transistor is the input terminal of the branch comparator unit, the source of the fourth PMOS transistor is the output terminal of the branch comparator unit, and the gate of the first PMOS transistor is connected to a first bias voltage.

[0009] In one embodiment of the present invention, the aspect ratio of the first NMOS transistor is at least N times the aspect ratio of the third PMOS transistor, where N is a positive integer and N≥50.

[0010] In one embodiment of the present invention, the latch module includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the fifth PMOS transistor is connected to a power supply voltage, and the source of the fifth PMOS transistor is also connected to the sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor. The source of the ten PMOS transistors is connected to the source of the fifth PMOS transistor, the gate of the fifth PMOS transistor is connected to the gate of the seventh PMOS transistor, the gate of the seventh PMOS transistor is also connected to the drain of the seventh PMOS transistor, the gate of the sixth PMOS transistor is connected to the gate of the eighth PMOS transistor, the gate of the eighth PMOS transistor is also connected to the drain of the eighth PMOS transistor, the drain of the seventh PMOS transistor is connected to the drain of the second NMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the third NMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the source of the third NMOS transistor, the source of the second NMOS transistor is also connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the fifth NMOS transistor is grounded, and the drain of the sixth NMOS transistor is connected to the drain of the tenth PMOS transistor. The gate of the S-channel transistor is connected to the drain of the eighth PMOS transistor, and the source of the sixth NMOS transistor is grounded. The gates of the ninth and tenth PMOS transistors are connected to a second bias voltage, and the gate of the fourth NMOS transistor is connected to a third bias voltage. The gate of the second NMOS transistor is the positive input terminal of the latch module, and the gate of the third NMOS transistor is the negative input terminal of the latch module. The drain of the seventh PMOS transistor is the first output terminal of the latch module, and the drain of the eighth PMOS transistor is the second output terminal of the latch module.

[0011] Secondly, the present invention provides a control method for a comparator circuit with latching function, comprising: Provide initial voltage and comparison voltage; The initial voltage is dynamically adjusted based on the comparison voltage to generate a first current variable; The first current variable is converted into a control voltage, and a first comparison result is determined based on the control voltage; The first comparison result is compared and positive feedback latching is performed to obtain the second comparison result.

[0012] In one embodiment of the present invention, converting the first current variable into a control voltage includes: obtaining the total branch current; determining a second current variable based on the total branch current and the first current variable; and determining the control voltage based on the second current variable.

[0013] The beneficial effects of this invention are as follows: This invention provides a comparator circuit with latching function and its control method. The comparator circuit with latching function provides an initial voltage based on a pre-comparison module. The initial voltage is dynamically adjusted based on the input comparison voltage to generate a first current variable. This first current variable is converted into a control voltage, and a first comparison result is output based on the control voltage. The first comparison result is compared and positive feedback latched by the latching module to obtain a second comparison result. The comparator circuit with latching function provided by this invention, designed for low-to-medium precision and low-frequency applications, replaces the redundant design and related bias circuits of multi-stage operational amplifier cascades with a pre-comparison module. The common-mode voltage bias is integrated into the structure of the pre-comparison module, simplifying the circuit structure. This comparator circuit does not interfere with the preceding or following circuits, reducing process sensitivity. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] In the attached diagram: Figure 1 This is a schematic diagram of a successive approximation analog-to-digital converter in the prior art; Figure 2 This is a block diagram of a comparator circuit with latching function provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the specific structure of the first branch comparison unit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the specific structure of the second branch comparison unit provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the specific structure of the latch module provided in an embodiment of the present invention.

[0016] Figure reference numerals: 210 - pre-comparison module; 220 - latch module; Vin - comparison voltage; Vb - initial voltage; Vc - control voltage; A1 - first comparison result; A2 - second comparison result; I1 - First current variable; I2 is the second current variable. Detailed Implementation

[0017] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0018] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0019] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0020] Successive approximation analog-to-digital converters (ADCs) achieve an excellent balance between power consumption, area, speed, and accuracy, making them a highly capable architecture. However, when pursuing higher comparison accuracy and speed, preamplifiers and latches are often used in their design.

[0021] like Figure 1 As shown, Figure 1As a common successive approximation analog-to-digital converter, when switch SW is closed, the successive approximation analog-to-digital converter is in the sampling state, sampling the input signal, which is stored on the upper plate of the capacitor array (8C, ..., 2C, 1C). When switch SW is open, switches S1, S1N, S2, S2N, ... are connected according to the selection of the successive approximation register logic. At this time, the successive approximation analog-to-digital converter is in the comparison state. The charge stored on the upper plate of the capacitor array during the sampling state is calculated on the upper plate of the capacitor due to the connection of the quantization switch. Since the charge on the capacitor cannot change abruptly, the voltage change on the upper plate of the capacitor will cause the voltage on the lower plate of the corresponding capacitor, i.e., point A, to change in the same way. Similarly, the charge on both sides of capacitor CN cannot change abruptly either, and the voltage at point B will also change in the same way as the voltage at point A. Since there is no DC path for the voltage at point A during the sampling state, the voltage at point A is 0, and the voltage at point B overlaps with the subsequent circuit. Through the design of the subsequent circuit, the voltage at point B is raised to the value at which the subsequent circuit is operating normally. This value will be used as the initial voltage at point B. During the comparison state, the value of point B during the sampling state can be obtained, and the voltage at point B will change with the voltage at point A based on the initial voltage. Through the above process, the voltage at point B and the voltage at point C are then compared by a comparator to obtain the comparison result. This is a complete operation process of a successive approximation analog-to-digital converter circuit.

[0022] Currently, the first-stage preamplifier circuit amplifies the input comparison voltage and directly inputs it into the latch structure of the subsequent stage. This structure designs the preamplifier as the core of the comparator. In successive approximation analog-to-digital converters (ADCs), two to three cascaded operational amplifiers are required as preamplifier circuits. To ensure that each amplifier stage does not interfere with each other, a buffer is also needed between the two stages. In practical applications, successive approximation ADCs are generally used in low-to-medium precision and low-frequency bands. In these application scenarios, using multi-stage cascaded operational amplifiers as preamplifiers would lead to performance overkill. To ensure the operation of multi-stage operational amplifiers, more bias circuits and common-mode voltage related designs for each stage are also required.

[0023] To solve the above problems, such as Figure 2 As shown, the present invention provides a comparator circuit with latching function, comprising: The pre-comparison module 210 has an input terminal connected to a comparison voltage Vin and provides an initial voltage Vb. It is used to dynamically adjust the initial voltage Vb based on the comparison voltage Vin to generate a first current variable. I1, and the first current variable I1 is converted into a control voltage Vc, and a first comparison result A1 is output based on the control voltage Vc; The latch module 220 is connected to the output of the pre-comparison module 210. It compares the first comparison result A1 and performs positive feedback latching to obtain the second comparison result A2.

[0024] In detail, the pre-comparison module 210 includes two branch comparison units, each providing an initial voltage Vb. The input terminals of the two branch comparison units are matched with the input comparison voltage Vin. Based on the comparison voltage Vin, the initial voltage Vb is dynamically adjusted, and a first current variable is generated based on the adjusted voltage difference. I1; based on the first current variable The relationship between I1 and the branch current is used to obtain the second current variable. I2, based on the second current variable I2 determines the control voltage Vc. Under the adjustment of the control voltage Vc, the two branch comparison units cooperate to output the first comparison result A1.

[0025] More specifically, the branch comparator unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a first switch. The source of the first PMOS transistor is connected to the power supply voltage, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The first terminal of the first switch is connected to the drain of the first NMOS transistor. The second terminal of the switch is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is grounded, the gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the third PMOS transistor is grounded, the source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, the gate of the fourth PMOS transistor is connected to the source of the third PMOS transistor, and the drain of the fourth PMOS transistor is grounded. The gate of the first NMOS transistor is the input terminal of the branch comparator unit, the source of the fourth PMOS transistor is the output terminal of the branch comparator unit, and the gate of the first PMOS transistor is connected to the first bias voltage.

[0026] Specifically, such as Figure 3As shown, the first branch comparator unit includes a first PMOS transistor PM11, a second PMOS transistor PM21, a third PMOS transistor PM31, a fourth PMOS transistor PM41, a first NMOS transistor NM11, and a first switch K11. The source of the first PMOS transistor PM11 is connected to the power supply voltage VDD. The source of the first PMOS transistor PM11 is also connected to the source of the second PMOS transistor PM21. The gate of the first PMOS transistor PM11 is connected to the gate of the second PMOS transistor PM21. The drain of the first PMOS transistor PM11 is connected to the drain of the first NMOS transistor NM11. The drain of the first PMOS transistor PM11 is connected to the source of the third PMOS transistor PM31. The first terminal of the first switch K11 is connected to the drain of the first NMOS transistor NM11. The second terminal of the first switch K11 is connected to the gate of the first NMOS transistor NM11, and the source of the first NMOS transistor NM11 is grounded. The gate of the third PMOS transistor PM31 is connected to the drain of the third PMOS transistor PM31, and the drain of the third PMOS transistor PM31 is grounded. The source of the fourth PMOS transistor PM41 is connected to the drain of the second PMOS transistor PM21, and the gate of the fourth PMOS transistor PM41 is connected to the source of the third PMOS transistor PM31, and the drain of the fourth PMOS transistor PM41 is grounded. The gate of the first NMOS transistor NM11 is the input terminal of the first branch comparator unit, and the source of the fourth PMOS transistor PM41 is the output terminal of the first branch comparator unit. The gate of the first PMOS transistor PM11 is connected to the first bias voltage VB11.

[0027] Specifically, such as Figure 4As shown, the second branch comparator unit includes a first PMOS transistor PM12, a second PMOS transistor PM22, a third PMOS transistor PM32, a fourth PMOS transistor PM42, a first NMOS transistor NM12, and a first switch K12. The source of the first PMOS transistor PM12 is connected to the power supply voltage VDD. The source of the first PMOS transistor PM12 is also connected to the source of the second PMOS transistor PM22. The gate of the first PMOS transistor PM12 is connected to the gate of the second PMOS transistor PM22. The drain of the first PMOS transistor PM12 is connected to the drain of the first NMOS transistor NM12. The drain of the first PMOS transistor PM12 is connected to the source of the third PMOS transistor PM32. The first terminal of the first switch K12 is connected to the drain of the first NMOS transistor NM12. The second terminal of the first switch K12 is connected to the gate of the first NMOS transistor NM12, and the source of the first NMOS transistor NM12 is grounded. The gate of the third PMOS transistor PM32 is connected to the drain of the third PMOS transistor PM32, and the drain of the third PMOS transistor PM32 is grounded. The source of the fourth PMOS transistor PM42 is connected to the drain of the second PMOS transistor PM22, and the gate of the fourth PMOS transistor PM42 is connected to the source of the third PMOS transistor PM32, and the drain of the fourth PMOS transistor PM42 is grounded. The gate of the first NMOS transistor NM12 is the input terminal of the second branch comparator unit, and the source of the fourth PMOS transistor PM42 is the output terminal of the second branch comparator unit. The gate of the first PMOS transistor PM12 is connected to the first bias voltage VB12.

[0028] More specifically, when the change in comparison voltage Vin is small, the aspect ratio of the first NMOS transistor (NM11, NM12) is at least N times the aspect ratio of the third PMOS transistor (PM31, PM32), where N is a positive integer and N≥50, thereby amplifying the small voltage change through current.

[0029] More in detail, such as Figure 5As shown, the latch module 220 includes a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, an eighth PMOS transistor PM8, a ninth PMOS transistor PM9, a tenth PMOS transistor PM10, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, and a sixth NMOS transistor NM6. The source of the fifth PMOS transistor PM5 is connected to the power supply voltage VDD. The source of the fifth PMOS transistor PM5 is also connected to the sources of the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, and the tenth PMOS transistor PM10. The source of transistor 10 is connected to the gate of the fifth PMOS transistor PM5, which is connected to the gate of the seventh PMOS transistor PM7. The gate of the seventh PMOS transistor PM7 is also connected to the drain of the seventh PMOS transistor PM7. The gate of the sixth PMOS transistor PM6 is connected to the gate of the eighth PMOS transistor PM8, which is also connected to the drain of the eighth PMOS transistor PM8. The drain of the seventh PMOS transistor PM7 is connected to the drain of the second NMOS transistor NM2. The drain of the eighth PMOS transistor PM8 is connected to the drain of the third NMOS transistor NM3. The drain of the fifth PMOS transistor PM5 is connected to the drain of the third NMOS transistor NM3. The drain of the sixth PMOS transistor PM6 is connected to the drain of the second NMOS transistor NM2. The source of NMOS transistor NM2 is connected to the source of the third NMOS transistor NM3. The source of the second NMOS transistor NM2 is also connected to the drain of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded. The drain of the fifth NMOS transistor NM5 is connected to the drain of the ninth PMOS transistor PM9. The gate of the fifth NMOS transistor NM5 is connected to the drain of the seventh PMOS transistor PM7. The source of the fifth NMOS transistor NM5 is grounded. The drain of the sixth NMOS transistor NM6 is connected to the drain of the tenth PMOS transistor PM10. The gate of the sixth NMOS transistor NM6 is connected to the drain of the eighth PMOS transistor PM8. The source of the sixth NMOS transistor NM6 is grounded. The gate of the ninth PMOS transistor PM9 and the tenth PMOS transistor PM10 are connected to the drain of the tenth PMOS transistor PM10. The gate of the OS transistor PM10 is connected to the second bias voltage VB2, the gate of the fourth NMOS transistor NM4 is connected to the third bias voltage VB3, the gate of the second NMOS transistor NM2 is the positive input terminal of the latch module 220, and the positive input terminal of the latch module 220 is connected to the output terminal of the first branch comparator unit, the gate of the third NMOS transistor NM3 is the negative input terminal of the latch module 220, and the negative input terminal of the latch module 220 is connected to the output terminal of the second branch comparator unit, the drain of the seventh PMOS transistor PM7 is the first output terminal of the latch module 220, and the drain of the eighth PMOS transistor PM8 is the second output terminal of the latch module 220. The two output terminals of the latch module 220 work together to output the second comparison result A2.

[0030] Please refer to Figures 1 to 5As shown, the working principle of the comparator circuit with latching function provided by the present invention is as follows: like Figure 1-5 As shown, the input terminal of the pre-comparison module 210 receives the comparison voltage Vin, that is, the input terminals of the pre-comparison module 210 are respectively connected to... Figure 1 In the successive approximation analog-to-digital converter, points B and C are used to sense changes in the voltage at these two points. The pre-comparison module 210 provides an initial voltage Vb, and performs addition and subtraction operations on the initial voltage Vb based on the input comparison voltage Vin, converting the voltage after the operation into a first current variable. I1, will be the first current variable I1 is converted into a control voltage Vc, and a first comparison result A1 is output according to the control voltage Vc. The first comparison result A1 is compared and positively fed back and latched by the latch module 220 to obtain a second comparison result A2.

[0031] like Figure 3 and Figure 4 As shown, the gate of the first NMOS transistors (NM11, NM12) is connected to the comparison voltage Vin. When the first switch (K11, K12) is closed, the successive approximation analog-to-digital converter is in sampling state. At this time, the current generated by the power supply voltage VDD passes through the first PMOS transistors (PM11, PM12) and the first switch (K11, K12) and is input to the gate of the first NMOS transistors (NM11, NM12), providing an initial voltage Vb to the gate of the first NMOS transistors (NM11, NM12). When the first switch (K11, K12) is open, the comparison voltage Vin is input to the input terminal of the pre-compare module 210. At this time, the gate voltage of the first NMOS transistors (NM11, NM12) will be increased or decreased by the comparison voltage Vin on the initial voltage Vb. The current of the first NMOS transistors (NM11, NM12) changes significantly with the change of the voltage at point B. The gate voltage change of the first NMOS transistor (NM11, NM12) is converted into the first current change of the first NMOS transistor (NM11, NM12). I1, the current flowing through the first PMOS transistor (PM11, PM12) is the total branch current. This total branch current is shunted to the first NMOS transistor (NM11, NM12) and the third PMOS transistor (PM31, PM32). Therefore, based on the total branch current and the first current variable... I1 determines the second current variable flowing through the third PMOS transistors (PM31, PM32). I2, due to the gate being connected to the drain of the third PMOS transistor (PM31, PM32), is based on the second current variable of the third PMOS transistor (PM31, PM32). I2 determines the source voltage variable of the third PMOS transistor (PM31, PM32), which is the gate voltage (control voltage Vc) of the fourth PMOS transistor (PM41, PM42).

[0032] After the comparison voltage Vin is pre-compared by the pre-comparison module 210, when the input comparison voltage Vin is too high, the control voltage Vc will be very low, close to ground. At this time, the fourth PMOS transistors (PM41, PM42) are turned on, and the branch comparison unit outputs a low level. When the input comparison voltage Vin is too low, the control voltage Vc will be very high, close to the power supply voltage VDD. At this time, the fourth PMOS transistors (PM41, PM42) are turned off, and the branch comparison unit outputs a high level. Therefore, it can be seen that the high-order comparison voltage Vin can be obtained in advance by the pre-comparison module 210, which fully ensures the accuracy of high-order quantization.

[0033] The present invention also provides a control method for a comparator circuit with latching function, comprising: Provide the initial voltage Vb and the comparison voltage Vin; The initial voltage Vb is dynamically adjusted based on the comparison voltage Vin to generate the first current variable. I1; The first current variable I1 is converted into control voltage Vc, and the first comparison result A1 is determined based on control voltage Vc; The first comparison result A1 is compared and positive feedback latching is performed to obtain the second comparison result A2.

[0034] In detail, the first current variable The conversion of I1 into control voltage Vc includes: obtaining the total branch current; and adjusting the total branch current and the first current variable. I1 determines the second current variable. I2; based on the second current variable I2 determines the control voltage Vc. Specifically, the current flowing through the first PMOS transistors (PM11, PM12) is the total branch current. This total branch current is shunted to the first NMOS transistors (NM11, NM12) and the third PMOS transistors (PM31, PM32). The control voltage Vc can be determined based on the total branch current and the first current variable. I1 calculates the second current variable flowing through the third PMOS transistors (PM31, PM32). I2, because the gate of the third PMOS transistor (PM31, PM32) is connected to the drain, according to the second current variable of the third PMOS transistor (PM31, PM32) I2 determines the source control voltage Vc of the third PMOS transistor (PM31, PM32).

[0035] This invention provides a comparator circuit with latching function and its control method. The comparator circuit with latching function uses an initial voltage provided by a pre-comparison module. The initial voltage is dynamically adjusted based on the input comparison voltage to generate a first current variable. This first current variable is converted into a control voltage, and a first comparison result is output based on the control voltage. The first comparison result is compared and positive feedback latched by the latching module to obtain a second comparison result. This comparator circuit with latching function, designed for low-to-medium precision and low-frequency applications, replaces the redundant design and related bias circuits of multi-stage operational amplifier cascades with a pre-comparison module. The common-mode voltage bias is integrated into the structure of the pre-comparison module, simplifying the circuit structure. This comparator circuit does not interfere with the preceding or following circuits, reducing process sensitivity.

[0036] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A comparator circuit with latching function, characterized in that, include: A pre-comparison module, whose input is connected to a comparison voltage and provides an initial voltage, is used to dynamically adjust the initial voltage based on the comparison voltage to generate a first current variable, and to convert the first current variable into a control voltage to output a first comparison result according to the control voltage; The latching module, connected to the output of the pre-comparison module, compares the first comparison result and performs positive feedback latching to obtain the second comparison result.

2. The comparator circuit with latching function according to claim 1, characterized in that, The pre-comparison module includes two branch comparison units, each of which provides the initial voltage. The input terminals of the two branch comparison units cooperate to input the comparison voltage, dynamically adjust the initial voltage based on the comparison voltage, and generate the first current variable based on the adjusted voltage difference. Based on the current splitting relationship between the first current variable and the total branch current, a second current variable is obtained. The control voltage is determined based on the second current variable. Under the adjustment of the control voltage, the two branch comparison units cooperate to output the first comparison result.

3. The comparator circuit with latching function according to claim 2, characterized in that, The branch comparison unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a first switch. The source of the first PMOS transistor is connected to the power supply voltage, and the source of the first PMOS transistor is also connected to the source of the second PMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first PMOS transistor is connected to the source of the third PMOS transistor. The first terminal of the first switch is connected to the drain of the first NMOS transistor. The second terminal of the first switch... The gate of the first NMOS transistor is connected to the first NMOS transistor, and the source of the first NMOS transistor is grounded. The gate of the third PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the third PMOS transistor is grounded. The source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the fourth PMOS transistor is connected to the source of the third PMOS transistor. The drain of the fourth PMOS transistor is grounded. The gate of the first NMOS transistor is the input terminal of the branch comparator unit, and the source of the fourth PMOS transistor is the output terminal of the branch comparator unit. The gate of the first PMOS transistor is connected to a first bias voltage.

4. The comparator circuit with latching function according to claim 3, characterized in that, The aspect ratio of the first NMOS transistor is at least N times the aspect ratio of the third PMOS transistor, where N is a positive integer and N≥50.

5. The comparator circuit with latching function according to claim 1, characterized in that, The latching module includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The source of the fifth PMOS transistor is connected to the power supply voltage. The source of the fifth PMOS transistor is also connected to the sources of the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor. The source of the fifth PMOS transistor is connected to the gate of the seventh PMOS transistor, and the gate of the seventh PMOS transistor is also connected to the drain of the seventh PMOS transistor. The gate of the sixth PMOS transistor is connected to the gate of the eighth PMOS transistor, and the gate of the eighth PMOS transistor is also connected to the drain of the eighth PMOS transistor. The drain of the seventh PMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the eighth PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the fifth PMOS transistor is connected to the drain of the third NMOS transistor. The drain of the PMOS transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is connected to the source of the third NMOS transistor, the source of the second NMOS transistor is also connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is grounded, the drain of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor, the gate of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, the source of the fifth NMOS transistor is grounded, the drain of the sixth NMOS transistor is connected to the drain of the tenth PMOS transistor, and the sixth NMOS transistor... The gate of the NMOS transistor is connected to the drain of the eighth PMOS transistor, and the source of the sixth NMOS transistor is grounded. The gates of the ninth and tenth PMOS transistors are connected to a second bias voltage, and the gate of the fourth NMOS transistor is connected to a third bias voltage. The gate of the second NMOS transistor is the positive input terminal of the latch module, and the gate of the third NMOS transistor is the negative input terminal of the latch module. The drain of the seventh PMOS transistor is the first output terminal of the latch module, and the drain of the eighth PMOS transistor is the second output terminal of the latch module.

6. A control method for a comparator circuit with latching function, characterized in that, include: Provide initial voltage and comparison voltage; The initial voltage is dynamically adjusted based on the comparison voltage to generate a first current variable; The first current variable is converted into a control voltage, and a first comparison result is determined based on the control voltage; The first comparison result is compared and positive feedback latching is performed to obtain the second comparison result.

7. The control method for a comparator circuit with latching function according to claim 6, characterized in that, Converting the first current variable into a control voltage includes: Obtain the total branch current; The second current variable is determined based on the total branch current and the first current variable; The control voltage is determined based on the second current variable.

Images