A method of manufacturing a semiconductor device

Abstract

This application discloses a method for fabricating a semiconductor device, relating to the field of semiconductor device technology. The method includes: forming a trench structure with a high aspect ratio on a silicon substrate, and forming an interface oxide layer on the surface of the silicon substrate and the bottom and sidewalls of the trench structure; depositing a crystalline silicon layer within the trench structure; performing a thermal oxidation treatment on the crystalline silicon layer to partially oxidize it to form a silicon oxide layer; etching the silicon oxide layer to expose the crystalline silicon layer; sequentially performing the deposition process, thermal oxidation treatment, and etching treatment on the exposed crystalline silicon layer surface, and repeating the deposition process, thermal oxidation treatment, and etching treatment at least once; depositing a crystalline silicon layer to fill the trench structure; and planarizing the crystalline silicon layer using a chemical mechanical polishing process to obtain a semiconductor device. The semiconductor device with a high aspect ratio trench structure in this application can achieve completely dense filling, and the fabrication process is simple.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a method for fabricating a semiconductor device. Background Technology

[0002] As semiconductor devices evolve towards higher integration and three-dimensionality, high aspect ratio trench structures are widely used in memory devices, power devices, and advanced logic devices, such as deep trench capacitors, trench gate structures, and three-dimensional interconnect structures. However, due to the large aspect ratio of trench structures, uneven coverage, insufficient sidewall growth, and premature sealing at the top of the trench can easily occur when filling them with materials such as crystalline silicon. This results in voids, seams, or inclusion defects within the trench. Current technologies typically employ a one-time deposition of dielectric material followed by direct trench filling, which struggles to balance deposition efficiency and filling quality, especially in trenches with large aspect ratios where these defects are more pronounced.

[0003] The interface quality between the trench sidewalls and bottomwalls has a significant impact on the electrical performance of devices. High interface defect density can easily lead to leakage current and decreased reliability. Current technologies attempt to treat trench structures through thermal oxidation or etching, but these methods are mostly focused on single process steps and lack a systematic design that considers the synergistic effect of multiple depositions and morphology trimming. This makes it difficult to achieve dense and uniform filling of the dielectric material while ensuring the integrity of the high aspect ratio structure.

[0004] Existing semiconductor device fabrication technologies still face challenges in high aspect ratio trench structures, such as poor dielectric material filling quality, difficulty in effectively suppressing interface defects, and insufficient surface flatness. Summary of the Invention

[0005] One objective of this invention is to provide a method for fabricating semiconductor devices, which solves the technical problem that in the prior art, the high aspect ratio trench structure of semiconductor devices is difficult to achieve uniform and dense filling of crystalline silicon while ensuring interface quality and surface flatness, and is prone to voids and defects.

[0006] Another objective of this invention is to further improve the morphological regularity of the silicon layer within the trench structure.

[0007] According to the purpose of this invention, a method for fabricating a semiconductor device is provided, comprising the following steps: A trench structure with a high aspect ratio is formed on a silicon substrate, and an interface oxide layer is formed on the surface of the silicon substrate and the bottom and sidewalls of the trench structure, wherein the aspect ratio of the trench structure is greater than or equal to 5:1. A crystalline silicon layer is deposited within the trench structure, wherein the crystalline silicon layer is made of polycrystalline silicon or amorphous silicon. The crystalline silicon layer is subjected to thermal oxidation treatment to oxidize a portion of the crystalline silicon layer to form a silicon oxide layer; The silicon oxide layer is etched to expose the crystalline silicon layer; The deposition process of the silicon layer, the thermal oxidation process, and the etching process are performed sequentially on the exposed surface of the silicon layer, and the deposition process, the thermal oxidation process, and the etching process are repeated at least once. Deposit the crystalline silicon layer to fill the trench structure; The semiconductor device is prepared by planarizing the crystalline silicon layer using a chemical mechanical polishing process.

[0008] Optionally, in the step of depositing a crystalline silicon layer in the trench structure, the ratio of the thickness of the crystalline silicon layer deposited in a single deposition to the width of the trench structure is any value between 0.2 and 0.5.

[0009] Optionally, the thickness of the silicon oxide layer is any value between 10 Å and 50,000 Å.

[0010] Optionally, the etching solution required for the etching process is a hydrofluoric acid diluted etching solution or a buffered oxide etching solution.

[0011] Optionally, the volume ratio of NH4F to HF in the buffer oxide etching solution is any value between 5:1 and 25:1.

[0012] Optionally, the etching rate of the buffer oxide etching solution is any value between 0.5 nm / s and 5 nm / s.

[0013] Optionally, the interface oxide layer is formed by a low-pressure chemical vapor deposition process or a thermal oxidation process.

[0014] Optionally, the deposition process of the crystalline silicon layer is a low-pressure chemical vapor deposition process or an epitaxial growth process.

[0015] Optionally, the step of forming a trench structure with a high aspect ratio on a silicon substrate includes: A hard mask layer is grown or deposited on the silicon substrate; The hard mask layer is subjected to photolithography and etching to form a preset pattern on the silicon substrate; The trench structure with a high aspect ratio is prepared by etching a silicon substrate using a deep silicon etching process.

[0016] Optionally, the deep silicon etching process is the Bosch process, the low-temperature deep reactive ion etching process, or the inductively coupled plasma deep silicon etching process.

[0017] This invention introduces a cyclic control process of multiple silicon layer deposition, thermal oxidation, and etching processes in a high aspect ratio trench structure, and combines it with the final overall filling and planarization process to achieve precise control over the morphology, interface quality, and density of the silicon structure within the trench structure. This effectively avoids common problems in high aspect ratio trench structures such as filling voids, interface defects, and stress concentration, thereby producing semiconductor devices with high structural integrity, stable electrical performance, and excellent reliability.

[0018] Furthermore, the ratio of the thickness of the silicon layer to the width of the trench structure in a single deposition is any value between 0.2 and 0.5. This ensures that a single silicon deposition will not produce defects such as premature sealing, voids, or gaps in high aspect ratio trenches due to excessively thick deposition layers, nor will it result in low film formation efficiency and excessive cycle counts due to excessively thin deposition layers. Within this ratio range, the silicon layer can achieve relatively uniform coverage on the bottom and sidewalls of the trench, which is beneficial for subsequent thermal oxidation and etching processes to gradually refine the morphology of the silicon layer, further improving the morphological regularity of the silicon layer.

[0019] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0020] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 2 This is a focused ion beam scanning electron microscope image of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention; Figure 4 This is a schematic structural diagram of the trench structure and the interface oxide layer according to an embodiment of the present invention; Figure 5 This is a schematic structural diagram of a single-filled crystalline silicon layer according to an embodiment of the present invention; Figure 6 This is a schematic structural diagram of a silicon oxide layer according to an embodiment of the present invention; Figure 7 This is a focused ion beam scanning electron microscope image of a silicon oxide layer according to an embodiment of the present invention; Figure 8This is a schematic structural diagram of the crystalline silicon layer after etching of the silicon oxide layer according to an embodiment of the present invention; Figure 9 This is a focused ion beam scanning electron microscope image of a crystalline silicon layer after etching of the silicon oxide layer according to an embodiment of the present invention; Figure 10 This is a schematic structural diagram of a trench structure with a fully filled crystalline silicon layer according to an embodiment of the present invention; Figure 11 This is a focused ion beam scanning electron microscope image of a trench structure with a fully filled crystalline silicon layer according to an embodiment of the present invention; Figure 12 This is a schematic structural diagram of a pre-patterned silicon substrate according to an embodiment of the present invention; Figure 13 This is a schematic structural diagram of a trench structure according to an embodiment of the present invention; Figure 14 This is a focused ion beam scanning electron microscope image of the semiconductor device according to Comparative Example 1 of the present invention; Figure 15 yes Figure 14 A magnified view of the area shown at point A in the middle; Figure 16 This is a focused ion beam scanning electron microscope image of the crystalline silicon layer after deposition according to Comparative Example 1 of the present invention.

[0021] Figure label: 100 - Semiconductor device, 10 - Silicon substrate, 11 - Trench structure, 20 - Interface oxide layer, 30 - Crystalline silicon layer, 40 - Silicon oxide layer, 50 - Hard mask layer. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0024] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 2 This is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 3 This is a focused ion beam scanning electron microscope image of a semiconductor device according to an embodiment of the present invention. Figure 4 This is a schematic structural diagram of the trench structure and the interface oxide layer according to an embodiment of the present invention. Figure 5 This is a schematic structural diagram of a single-filled crystalline silicon layer according to an embodiment of the present invention. Figure 6 This is a schematic structural diagram of a silicon oxide layer according to an embodiment of the present invention. Figure 7 This is a focused ion beam scanning electron microscope image of a silicon oxide layer according to an embodiment of the present invention. Figure 8 This is a schematic structural diagram of the silicon layer after etching of the silicon oxide layer according to an embodiment of the present invention. Figure 9 This is a focused ion beam scanning electron microscope image of the silicon layer after etching of the silicon oxide layer according to an embodiment of the present invention. Figure 10 This is a schematic structural diagram of a trench structure with a fully filled crystalline silicon layer according to an embodiment of the present invention. Figure 11 This is a focused ion beam scanning electron microscope image of a trench structure with a fully filled crystalline silicon layer according to an embodiment of the present invention.

[0027] like Figure 1 As shown, the present invention provides a method for fabricating a semiconductor device 100, comprising the following steps: Step S100: A trench structure 11 with a high aspect ratio is formed on the silicon substrate 10, and an interface oxide layer 20 is formed on the surface of the silicon substrate 10 and the bottom and sidewalls of the trench structure 11 (refer to...). Figure 4 The depth-to-width ratio of the trench structure 11 is greater than or equal to 5:1; Step S200: Deposit a crystalline silicon layer 30 within the trench structure 11 (refer to...) Figure 5 The material of the crystalline silicon layer 30 is polycrystalline silicon or amorphous silicon; Step S300: Perform thermal oxidation on the crystalline silicon layer 30 to oxidize a portion of the crystalline silicon layer 30 to form a silicon oxide layer 40 (refer to...) Figure 6 and Figure 7 ); Step S400: Etch the silicon oxide layer 40 to expose the crystalline silicon layer 30 (refer to...) Figure 8 and Figure 9 ); Step S500: Sequentially perform the deposition process, thermal oxidation process and etching process of the silicon layer 30 on the exposed surface of the silicon layer 30, and repeat the deposition process, thermal oxidation process and etching process at least once. Step S600: Deposit a crystalline silicon layer 30 to fill the trench structure 11 (refer to...) Figure 10 and Figure 11 ); Step S700: The silicon layer 30 is planarized using a chemical mechanical polishing process to prepare a semiconductor device 100 (refer to...). Figure 2 and Figure 3 ).

[0028] In this embodiment, the method for fabricating the semiconductor device 100 firstly involves forming a trench structure 11 with a high aspect ratio on a silicon substrate 10, and forming an interface oxide layer 20 on the surface of the silicon substrate 10 and the bottom and sidewalls of the trench structure 11. The aspect ratio of the trench structure 11 is greater than or equal to any value of 5:1. Next, a crystalline silicon layer 30 is deposited in the trench structure 11, and the crystalline silicon layer 30 is subjected to thermal oxidation to oxidize a portion of the crystalline silicon layer 30 to form a silicon oxide layer 40. Then, the silicon oxide layer 40 is etched to expose the crystalline silicon layer 30. Next, the deposition process, thermal oxidation process, and etching process of the crystalline silicon layer 30 are sequentially performed on the surface of the exposed crystalline silicon layer 30, and the deposition process, thermal oxidation process, and etching process are repeated at least once to deposit a final crystalline silicon layer 30 to fill the trench structure 11. Finally, the crystalline silicon layer 30 is planarized using a chemical mechanical polishing process to obtain the semiconductor device 100. Here, the aspect ratio of the trench structure 11 of the silicon substrate 10 can be 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1 or 12:1. The number of cycles for the deposition process, thermal oxidation process and etching process of the crystalline silicon layer 30 can be one or more. The number of cycles is adjusted and optimized according to the aspect ratio and size of the actual structure.

[0029] In this embodiment, by introducing a cyclic control process of multiple silicon layer 30 deposition, thermal oxidation and etching in the high aspect ratio trench structure 11, and cooperating with the final overall filling and planarization process, precise control of the morphology, interface quality and compactness of the silicon structure in the trench structure 11 is achieved. This effectively avoids common problems in the high aspect ratio trench structure 11 such as filling voids, interface defects and stress concentration, thereby preparing a semiconductor device 100 with high structural integrity, stable electrical performance and excellent reliability.

[0030] In steps S100 and S200, by forming a high aspect ratio trench structure 11 with an aspect ratio greater than or equal to 5:1 on the silicon substrate 10, and forming an interface oxide layer 20 on the bottom and sidewalls of the trench structure 11, not only is a good interface passivation basis provided for the subsequent deposition of the crystalline silicon layer 30, reducing the interface state density, but the high aspect ratio trench structure 11 also provides structural conditions for achieving high integration and a large effective working area of ​​the semiconductor device 100. Furthermore, the crystalline silicon layer 30 is subsequently deposited within the trench structure 11, ensuring continuous coverage along the trench walls and bottom, laying the initial framework for subsequent structural adjustments.

[0031] In steps S300 and S400, the surface portion of the deposited silicon layer 30 is transformed into a silicon oxide layer 40 by thermal oxidation treatment. Then, the silicon oxide layer 40 is etched to re-expose the surface of the silicon layer 30, thereby achieving preliminary adjustment of the thickness and surface morphology of the silicon layer 30. This process can effectively eliminate the non-uniform accumulation formed on the sidewalls and bottom of the trench during the initial deposition process, which is beneficial to improving the uniformity and continuity of the silicon layer 30 in the high aspect ratio trench structure 11.

[0032] In step S500, by repeatedly performing the silicon layer 30 deposition process, thermal oxidation treatment, and etching treatment cycle at least once on the exposed silicon layer 30 surface, the silicon layer 30 is grown and trimmed layer by layer inside the trench structure 11, achieving fine control over the silicon layer 30. This multi-cycle process can gradually repair morphological defects on the trench sidewalls and bottom, suppress the generation of voids and seams, and alleviate the stress concentration problem caused by the high aspect ratio trench structure 11, thereby significantly improving the density and overall consistency of the silicon structure inside the trench.

[0033] In steps S600 and S700, after multiple cycles of adjustment, a silicon layer 30 is deposited to completely fill the trench structure 11, forming a continuous and dense silicon filler inside the trench structure 11. Subsequently, a chemical mechanical polishing process is used to planarize the silicon layer 30, so that the device surface obtains good flatness. The combination of multiple adjustment processes ensures that the high aspect ratio trench structure 11 is filled without voids and meets the surface flatness requirements of the subsequent semiconductor device 100 process.

[0034] In this embodiment, the filling morphology is actively controlled through oxidation and etching cycles, which continuously delays and eventually eliminates the top sealing problem that may cause voids, achieving completely dense filling. Furthermore, this embodiment also adopts the LPCVD (Low Pressure Chemical Vapor Deposition) polycrystalline silicon process with a faster deposition rate, combined with mature thermal oxidation technology, which has a significantly higher production efficiency than the ALD (Atomic Layer Deposition) process, making it more suitable for large-scale production.

[0035] In a further embodiment, in the step of depositing a crystalline silicon layer 30 within the trench structure 11, the ratio of the thickness of the crystalline silicon layer 30 deposited in a single deposition to the width of the trench structure 11 is any value between 0.2 and 0.5. That is, the ratio of the thickness of the crystalline silicon layer 30 deposited in a single deposition to the width of the trench structure 11 can be 1 / 5, 1 / 4, 1 / 3, or 1 / 2, or any other value between 1 / 5 and 1 / 2. In this embodiment, by limiting the ratio of the thickness of the silicon layer 30 deposited in a single deposition to the width of the trench structure 11 to within the range of 0.2-0.5, the single silicon deposition will not produce defects such as premature sealing, voids or gaps in the high aspect ratio trench due to excessively thick deposition layer, nor will it lead to low film formation efficiency and excessive cycle count due to excessively thin deposition layer. Within this ratio range, the silicon layer 30 can achieve relatively uniform coverage on the bottom and sidewalls of the trench, which is beneficial for the subsequent thermal oxidation and etching processes to gradually refine the morphology of the silicon layer 30, further improving the morphological regularity of the silicon layer 30.

[0036] In a further embodiment, the thickness of the silicon oxide layer 40 is any value between 10 Å and 50,000 Å, that is, the thickness of the silicon oxide layer 40 can be 10 Å, 100 Å, 1000 Å, 25,000 Å, 30,000 Å, 35,000 Å, 40,000 Å, 45,000 Å, or 50,000 Å, or any other value between 10 Å and 50,000 Å. In this embodiment, by limiting the thickness of the silicon oxide layer 40 to the range of 10 Å to 50,000 Å, the silicon oxide layer 40 formed by thermal oxidation has sufficient thickness to effectively protect and morphology control the underlying crystalline silicon layer 30, while avoiding excessive consumption of crystalline silicon material due to excessive oxidation depth. This achieves precise control over the oxidation depth of the crystalline silicon layer 30 in the high aspect ratio trench structure 11. Within this thickness range, the silicon oxide layer 40 can be uniformly and controllably removed in subsequent etching processes, which is beneficial for repairing the surface roughness and sidewall morphology of the silicon layer 30, reducing interface defects and stress concentration. At the same time, it works in conjunction with the cyclic process of multiple silicon layer 30 deposition, thermal oxidation, and etching processes to gradually improve the density and consistency of the silicon structure inside the trench structure 11.

[0037] In a further embodiment, the etching solution required for the etching process is a hydrofluoric acid diluted etching solution or a buffered oxide etching solution. By using a hydrofluoric acid diluted etching solution or a buffered oxide etching solution to etch the silicon oxide layer 40, the etching process has high selectivity and controllability for the silicon oxide material, effectively removing the silicon oxide layer 40 while avoiding significant damage to the underlying crystalline silicon layer 30. Specifically, the hydrofluoric acid diluted etching solution can achieve rapid and uniform silicon oxide removal, suitable for process scenarios with high etching rate requirements, while the buffered oxide etching solution reduces etching rate fluctuations and improves etching uniformity and repeatability by stabilizing the hydrofluoric acid concentration and pH value in the solution.

[0038] In a further embodiment, the volume ratio of NH4F to HF in the buffer oxide etching solution is any value between 5:1 and 25:1, i.e., the volume ratio of NH4F to HF in the buffer oxide etching solution is 5:1, 10:1, 15:1, 20:1, or 25:1, or any other value between 5:1 and 25:1. In this embodiment, by limiting the volume ratio of NH4F to HF in the buffer oxide etching solution to the range of 5:1 to 25:1, the effective concentration of free HF in the etching system is buffered and regulated, thereby ensuring that the silicon oxide layer 40 can be stably removed while significantly reducing the fluctuation of the etching rate. Furthermore, within this volume ratio range, the etching process has better isotropy and etching uniformity, which is beneficial for achieving synchronous and controllable etching of the bottom and sidewall silicon oxide layers 40 of the high aspect ratio trench structure 11, avoiding over-etching of sidewalls, local residues, or interface damage caused by excessively fast or uneven etching. Furthermore, this buffer ratio works in conjunction with the aforementioned multiple silicon layer 30 deposition process, thermal oxidation treatment, and etching process cycle, making each round of silicon oxide layer 40 removal smoother and more controllable, which helps to gradually refine the morphology of the silicon layer 30, reduce surface roughness, and improve filling density.

[0039] In a further embodiment, the etching rate of the buffer oxide etchant is any value between 0.5 nm / s and 5 nm / s, that is, the etching rate of the buffer oxide etchant can be 0.5 nm / s, 1.0 nm / s, 1.5 nm / s, 2.0 nm / s, 2.5 nm / s, 3.0 nm / s, or 5 nm / s, or any other value between 0.5 nm / s and 5 nm / s. In this embodiment, by limiting the etching rate of the buffer oxide etchant to the range of 0.5 nm / s to 5 nm / s, the removal process of the silicon oxide layer 40 is kept within a finely controllable rate range. This avoids over-etching, sidewall erosion, or interface damage caused by excessively fast etching rates, while also preventing excessively slow etching rates from significantly extending the process time and reducing process efficiency. Within this etching rate range, the etching depth can be precisely controlled by time, which is beneficial for achieving synchronous and uniform removal of the bottom and sidewall silicon oxide layers 40 in the high aspect ratio trench structure 11.

[0040] In a further embodiment, the interface oxide layer 20 is formed by a low-pressure chemical vapor deposition (LPCVD) process or a thermal oxidation process. By configuring the interface oxide layer 20 to be formed by LCVD or thermal oxidation, a dense, continuous, and thickness-controllable interface oxide layer 20 is formed on the surface of the silicon substrate 10 and on the bottom and sidewalls of the high aspect ratio trench structure 11. LCVD is advantageous for achieving good coverage consistency in the complex trench structure 11, while thermal oxidation can form a higher-quality intrinsic oxide layer with fewer interface defects at the silicon-silicon oxide interface. Both processes help improve the interface quality between the crystalline silicon layer 30 and the silicon substrate 10, reduce interface state density and leakage risk, and provide a stable interface foundation for subsequent cyclic processes of crystalline silicon layer 30 deposition, thermal oxidation, and etching. This synergistic effect with the multi-step process enhances the structural reliability and electrical performance stability of the semiconductor device 100.

[0041] In a further embodiment, the deposition process of the crystalline silicon layer 30 is a low-pressure chemical vapor deposition process or an epitaxial growth process.

[0042] Figure 12 This is a schematic structural diagram of a pre-patterned silicon substrate according to an embodiment of the present invention. Figure 13 This is a schematic structural diagram of a trench structure according to an embodiment of the present invention.

[0043] like Figure 12 and Figure 13 As shown, in a further embodiment, step S100 further includes: A hard mask layer 50 is grown or deposited on the silicon substrate 10; The hard mask layer 50 is subjected to photolithography and etching to form a preset pattern on the silicon substrate 10; A trench structure 11 with a high aspect ratio is prepared by etching a silicon substrate 10 using a deep silicon etching process.

[0044] In this embodiment, in step S100, a hard mask layer 50 is first grown or deposited on the silicon substrate 10, and the hard mask layer 50 is photolithographically etched and etched to form a preset pattern. Then, a high aspect ratio trench structure 11 is etched in the silicon substrate 10 using a deep silicon etching process. This allows the planar dimensions and spatial positions of the trench structure 11 to be precisely defined by the photolithographic pattern, thereby significantly improving the dimensional consistency and arrangement accuracy of the trench structure 11. Furthermore, the hard mask layer 50 plays a good role in etching blocking and protection during the deep silicon etching process, which is beneficial for improving the etching selectivity, suppressing mask erosion, and ensuring the verticality and morphological stability of the sidewalls of the trench structure 11.

[0045] In a further embodiment, the deep silicon etching process is the Bosch process, the low-temperature deep reactive ion etching process, or the inductively coupled plasma deep silicon etching process, enabling the silicon substrate 10 to form a high aspect ratio trench structure 11 while maintaining a high etching rate. The Bosch process, through its alternating etching and sidewall passivation process, facilitates achieving a high etching depth and good sidewall uprightness. The low-temperature deep reactive ion etching process, by enhancing the sidewall passivation effect under low-temperature conditions, can further suppress lateral etching and improve sidewall morphology. The inductively coupled plasma deep silicon etching process, on the other hand, can achieve precise control of the etching rate and anisotropy through high-density plasma.

[0046] In this embodiment, the selection of the above etching process is conducive to the stable fabrication of trench structure 11 with an aspect ratio greater than or equal to 5:1 under the preset pattern conditions. It works in conjunction with the subsequent cyclic steps of interface oxide layer 20 formation and multiple silicon layer 30 deposition, thermal oxidation and etching treatment to provide a regular and controllable three-dimensional structural basis for high-quality filling of silicon in trench structure 11, thereby improving the fabrication consistency, structural reliability and electrical performance stability of semiconductor device 100.

[0047] The technical solution of this application will be further described below with reference to specific embodiments.

[0048] Example 1 In the method for fabricating semiconductor device 100, a trench structure 11 with a high aspect ratio is first formed on a silicon substrate 10, and an interface oxide layer 20 is formed on the surface of the silicon substrate 10 and the bottom and sidewalls of the trench structure 11. The aspect ratio of the trench structure 11 is any value greater than or equal to 5:1. Next, a crystalline silicon layer 30 is deposited in the trench structure 11. The crystalline silicon layer 30 is made of polycrystalline silicon, and the crystalline silicon layer 30 is subjected to thermal oxidation treatment to oxidize part of the crystalline silicon layer 30 to form a silicon oxide layer 40. Then, the silicon oxide layer 40 is etched to expose the crystalline silicon layer 30. Next, the deposition process, thermal oxidation treatment and etching treatment of the crystalline silicon layer 30 are sequentially performed on the surface of the exposed crystalline silicon layer 30, and the deposition process, thermal oxidation treatment and etching treatment are repeated at least once to deposit a last crystalline silicon layer 30 to fill the trench structure 11. Finally, the crystalline silicon layer 30 is planarized using a chemical mechanical polishing process to obtain semiconductor device 100.

[0049] Comparative Example 1 The only difference between Comparative Example 1 and Example 1 is that the trench structure 11 is filled with a single-pass crystalline silicon layer 30.

[0050] Figure 14 This is a focused ion beam scanning electron microscope image of a crystalline silicon layer according to Comparative Example 1 of the present invention. Figure 15 yes Figure 14 A magnified view of the area shown at point A in the middle. Figure 16 This is a focused ion beam scanning electron microscope image of the crystalline silicon layer after deposition according to Comparative Example 1 of the present invention.

[0051] The semiconductor devices 100 prepared in Example 1 and Comparative Example 1 were subjected to focused ion beam scanning electron microscopy (FEM) tests, respectively, and the results were as follows: Figure 3 He Ru Figure 14-16 The test results.

[0052] like Figure 3 As shown in the focused ion beam scanning electron microscope image of the semiconductor device 100 in Example 1, the polycrystalline silicon layer 30 is intact and the trench structure 11 is free of pores. Figures 14 to 16 In Comparative Example 1, there are obvious gaps in the trench structure 11 of the semiconductor device 100, indicating that the fabrication method of this application can achieve complete and dense filling of the trench structure with a high aspect ratio, thereby obtaining a semiconductor device 100 with high structural integrity, stable electrical performance and excellent reliability.

[0053] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A trench structure with a high aspect ratio is formed on a silicon substrate, and an interface oxide layer is formed on the surface of the silicon substrate and the bottom and sidewalls of the trench structure, wherein the aspect ratio of the trench structure is greater than or equal to 5:

1. A crystalline silicon layer is deposited within the trench structure, wherein the crystalline silicon layer is made of polycrystalline silicon or amorphous silicon. The crystalline silicon layer is subjected to thermal oxidation treatment to oxidize a portion of the crystalline silicon layer to form a silicon oxide layer; The silicon oxide layer is etched to expose the crystalline silicon layer; The deposition process of the silicon layer, the thermal oxidation process, and the etching process are performed sequentially on the exposed surface of the silicon layer, and the deposition process, the thermal oxidation process, and the etching process are repeated at least once. Deposit the crystalline silicon layer to fill the trench structure; The semiconductor device is prepared by planarizing the crystalline silicon layer using a chemical mechanical polishing process.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, In the step of depositing a crystalline silicon layer in the trench structure, the ratio of the thickness of the crystalline silicon layer deposited in a single deposition to the width of the trench structure is any value between 0.2 and 0.

5.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The thickness of the silicon oxide layer is any value between 10 Å and 50,000 Å.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The etching solution required for the etching process is a hydrofluoric acid diluted etching solution or a buffered oxide etching solution.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The volume ratio of NH4F to HF in the buffer oxide etching solution is any value between 5:1 and 25:

1.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The etching rate of the buffer oxide etching solution is any value between 0.5 nm / s and 5 nm / s.

7. The method for fabricating a semiconductor device according to any one of claims 1-6, characterized in that, The interface oxide layer is formed by low-pressure chemical vapor deposition or thermal oxidation.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The deposition process of the crystalline silicon layer is a low-pressure chemical vapor deposition process or an epitaxial growth process.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The step of forming a trench structure with a high aspect ratio on a silicon substrate includes: A hard mask layer is grown or deposited on the silicon substrate; The hard mask layer is subjected to photolithography and etching to form a preset pattern on the silicon substrate; The trench structure with a high aspect ratio is prepared by etching a silicon substrate using a deep silicon etching process.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The deep silicon etching process is the Bosch process, the low-temperature deep reactive ion etching process, or the inductively coupled plasma deep silicon etching process.

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