Method for improving reliability of metal interconnect layer and method for preparing semiconductor structure
By using carbon dioxide gas and adjusting the radio frequency power, pressure, and flow rate in a step-by-step dry etching process, the problem of damage to low dielectric constant layers was solved, and the reliability of the metal interconnect layer was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING XINLIAN MICROELECTRONICS CO LTD
- Filing Date
- 2026-01-29
- Publication Date
- 2026-06-09
AI Technical Summary
After double damask dry etching, surface damage to the low dielectric constant layer leads to an increase in dielectric constant and an increased chance of leakage current, affecting the reliability of the metal interconnect layer.
Carbon dioxide is used as the etching gas for stepwise dry etching. By adjusting the high-frequency and low-frequency radio frequency power, chamber pressure and etching gas flow rate, the resist removal position is precisely controlled, reducing damage to low dielectric constant layers.
It effectively reduces damage to low dielectric constant layers, lowers their surface hydrophilicity, reduces water vapor adsorption, and improves the reliability of metal wires.
Smart Images
Figure CN122180376A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to a method for improving the reliability of metal interconnect layers and a method for preparing semiconductor structures. Background Technology
[0002] After double damascene dry etching, photoresist ashing is required. Ashing typically utilizes oxygen for dry etching. Low-k materials containing -CH3 groups (low dielectric constant materials) have low dielectric constants. Upon impact with oxygen free radicals (O+-radical), the -CH3 groups are oxidized and reduced. Damage to the surface of ultra-low dielectric constant materials (ULK, Ultra Low-k; in the industry, materials with K values below 2.7 or 2.5 are generally classified as ULK) at vias and trenches makes the low dielectric constant layer 3 hydrophilic, easily adsorbing moisture from the air. This results in an increase in dielectric constant and also increases the chance of leakage current. ULK damage typically refers to the formation of an oxide layer of approximately 30-80 angstroms, i.e., damage layer 6, at the ULK interface after double damascene dry etching (see reference). Figure 3 This oxide layer is susceptible to breakdown due to prolonged voltage.
[0003] Further research revealed that after metallization, i.e., Cu-filling, the water vapor adsorbed in the low-dielectric-constant layer 3 and the metal diffusion barrier layer filling the via 31 can undergo further oxidation, affecting the reliability of the metal lines. One of the biggest challenges of dual damask dry etching is how to reduce damage to the low-dielectric-constant (low-k) material during the ash process in order to improve the reliability of the metal interconnect layer. Summary of the Invention
[0004] In view of all or part of the deficiencies of the prior art described above, the purpose of this invention is to provide a method for improving the reliability of metal interconnect layers and a method for fabricating semiconductor structures, and to propose optimizing dry etching and ashing conditions / resin removal conditions to reduce surface damage of low dielectric constant layers, thereby further improving the reliability of metal lines.
[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution: This invention provides a method for improving the reliability of metal interconnect layers. Based on a photoresist pattern forming vias of the metal interconnect layer in a low-dielectric-constant layer, the photoresist is ashed. A step-by-step dry etching process is performed using carbon dioxide as the etching gas. This step-by-step dry etching includes at least a first etching step and a second etching step performed sequentially. The high-frequency radio frequency power of both the first and second etching steps is maintained at 0W. The low-frequency radio frequency power of the first etching step is greater than that of the second etching step. The chamber pressure of the first etching step is greater than that of the second etching step. The etching gas flow rate of the first etching step is greater than that of the second etching step.
[0006] This invention selects carbon dioxide as the etching gas for photoresist ashing. Compared to oxygen, carbon dioxide causes less damage to low-dielectric-constant layers, such as porous SiCOH materials. Furthermore, by setting the high-frequency RF power to 0W and using only low-frequency RF for dry etching, the bombardment of the low-dielectric-constant material on the via sidewalls can be reduced, thus minimizing damage to the low-dielectric-constant layer. The thickness of the damaged layer can be less than 15 angstroms. The less damage to the low-dielectric-constant layer, the less hydrophilic its surface, making it less likely for moisture in the environment to be adsorbed. This reduces the likelihood of oxidation reactions between moisture and the diffusion barrier layer, which could affect the reliability of the metal line, during the subsequent formation of the diffusion barrier layer and filling of the conductive metal within the via. Conversely, the greater the thickness of the damaged layer on the surface of the low-dielectric-constant layer, the easier it is for moisture in the environment to be adsorbed, resulting in a greater impact on the diffusion barrier layer and lower metal line reliability. Step-by-step etching allows for precise control of the resist removal location and improves the resist removal efficiency at the bottom of the via contour. Simultaneously, by combining variations in RF power, chamber pressure, and etching gas flow rate, damage to the low-dielectric-constant layer is synergistically reduced.
[0007] The step-by-step dry etching process also includes a third etching step performed after the second etching step. The high-frequency radio frequency (RF) power of the third etching step is 0W, the low-frequency RF power of the third etching step is lower than that of the second etching step, the chamber pressure of the third etching step is lower than that of the second etching step, and the etching gas flow rate of the third etching step is lower than that of the second etching step. This three-step etching process allows for more precise control of the resist removal location, further reducing damage to the low-dielectric-constant layer.
[0008] The low-frequency radio frequency power of the first etching step, the second etching step, and the third etching step is less than or equal to 400W; the frequency of the low-frequency radio frequency is 13MHz.
[0009] The low-frequency radio frequency power of the first etching step is 300W±30W, the low-frequency radio frequency power of the second etching step is 250W±30W, and the low-frequency radio frequency power of the third etching step is 200W±30W.
[0010] The chamber pressure for the first etching step is 40 mT, the chamber pressure for the second etching step is 30 mT, and the chamber pressure for the third etching step is 20 mT. By gradually decreasing the chamber pressure according to this gradient, the processing time can be shortened by 10-20 seconds. When the pressure is adjusted to near the optimal point, the processing time is short; further reducing the pressure may prolong the processing time due to a decrease in the removal rate. Balancing chemical reaction and physical bombardment achieves a fast removal rate and short processing time.
[0011] The etching gas flow rate for the first etching step is 350 sccm ± 50 sccm, for the second etching step it is 300 sccm ± 50 sccm, and for the third etching step it is 200 sccm ± 50 sccm. By controlling the etching gas flow rate within a certain range and comprehensively considering the resist removal efficiency and the removal location, appropriate gas, flow rate, and plasma parameters are used to efficiently remove the resist at a precise location, i.e., the target organic layer, while ensuring the safety of the underlying device structure.
[0012] The processing time for the first etching step is t1 seconds, the processing time for the second etching step is t2 seconds, and the processing time for the third etching step is t3 seconds; wherein 80≤t1+t2+t3≤100. The processing time is calculated using the amount of adhesive removed per unit time, that is, first obtain the amount of adhesive removed per second for each step, and then use the same amount of adhesive removed to estimate the appropriate processing time.
[0013] The first etching step takes 40-50 seconds, the second etching step takes 20-30 seconds, and the third etching step takes 20-30 seconds.
[0014] The present invention also provides a method for preparing a semiconductor structure, comprising the following steps: Step S1: Form a metal layer on the substrate, wherein a dielectric barrier layer, a low dielectric constant layer, a capping layer and a photoresist pattern are sequentially formed on the metal layer; Step S2: Using the method described above for improving the reliability of metal interconnect layers, form vias in the low dielectric constant layer and perform photoresist ashing treatment; Step S3: A diffusion barrier layer is formed inside the through hole, and a conductive metal is filled inside the diffusion barrier layer.
[0015] The dielectric barrier layer is a silicon carbide layer, the low dielectric constant layer is a SiCOH material layer, the capping layer is a hard mask layer, the photoresist (photolithography material) is one or more of the following: ODL layer, SHB layer, and PR layer, the diffusion barrier layer is a Ta / TaN layer, and the conductive metal is copper. The ODL layer is the bottom organic layer, the SHB layer is the bottom anti-reflection coating of the intermediate silicon-containing hard mask, and the PR layer is the top photoresist layer. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 These are schematic diagrams of the ashing process in the embodiments and comparative examples; the arrows represent plasma bombardment; Figure 2 This refers to the damaged layer after ashing treatment in Example 1 or Example 3; the arrow represents plasma bombardment. Figure 3 This shows the damaged layer after ashing treatment in Comparative Example 3; the arrows represent plasma bombardment. Figure 4 These are transmission electron microscope images and corresponding elemental line scan analyses from Example 3; Figure 5 This is a transmission electron microscope image and corresponding elemental line scan analysis of Comparative Example 3.
[0018] Reference numerals: 1-Metal layer; 2-Dielectric barrier layer; 3-Low dielectric constant layer; 31-Through hole; 4-Capping layer; 5-Photoresist pattern; 6-Damage layer. Detailed Implementation
[0019] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] It should be noted that, in order to describe the technical solution more specifically, the steps described in the following embodiments do not strictly correspond one-to-one with the steps described in the invention content section.
[0021] Example 1 A method for improving the reliability of metal interconnect layers, see [link to relevant documentation]. Figure 1 and Figure 2 Based on the photoresist pattern 5, vias 31 with metal interconnect layers are formed in the low dielectric constant layer 3 using a double damascene process. In this embodiment, the low dielectric constant layer 3 is a porous SiCOH material layer. Figure 1 In the diagram, the position of the via 31 is for illustrative purposes only and is not limited to etching to the bottom. It can also remain within the low dielectric constant layer 3, i.e., partially etched, depending on the actual process sequence.
[0022] The photoresist undergoes ashing treatment: Carbon dioxide is used as the etching gas for step-by-step dry etching. In this embodiment, the step-by-step dry etching includes a first etching step, a second etching step, and a third etching step performed sequentially. In other embodiments, two or more etching steps may be performed. In this embodiment, ashing mainly refers to the removal of photolithographic materials such as the SHB layer and ODL layer. Figure 1 The photoresist pattern 5 in the diagram is for illustrative purposes only. In other embodiments, it could also involve removing the PR layer, etc. The ODL layer is made of a carbon coating, and the SHB layer is made of a silicon-based anti-reflective coating.
[0023] In this process, the high-frequency radio frequency power of the first etching step, the second etching step, and the third etching step is kept at 0W.
[0024] The low-frequency radio frequency (RF) power of the first etching step is greater than that of the second etching step, and the RF power of the second etching step is greater than that of the third etching step. In this embodiment, the RF power of the first, second, and third etching steps is all less than or equal to 400W. In this embodiment, the frequency of the RF is 13MHz; in other embodiments, it could be 2MHz, etc.
[0025] The chamber pressure in the first etching step is greater than the chamber pressure in the second etching step, and the chamber pressure in the second etching step is greater than the chamber pressure in the third etching step.
[0026] The etching gas flow rate in the first etching step is greater than the etching gas flow rate in the second etching step, and the etching gas flow rate in the second etching step is greater than the etching gas flow rate in the third etching step.
[0027] The processing time for the first etching step is t1 seconds, the processing time for the second etching step is t2 seconds, and the processing time for the third etching step is t3 seconds; wherein, 80≤t1+t2+t3≤100.
[0028] Specifically, the following etching steps are performed sequentially: The first etching step has a chamber pressure of 40mT, a high-frequency radio frequency power of 0W, a low-frequency radio frequency power of 300W±30W, an etching gas flow rate of 350sccm±50sccm, and a processing time of 40 seconds.
[0029] The second step of etching involves a chamber pressure of 30 mT, a high-frequency radio frequency power of 0 W, a low-frequency radio frequency power of 250 W ± 30 W, an etching gas flow rate of 300 sccm ± 50 sccm, and a processing time of 30 seconds.
[0030] The third step is etching. The chamber pressure is 20mT, the high-frequency radio frequency power is 0W, the low-frequency radio frequency power is 200W±30W, the etching gas flow rate is 200sccm±50sccm, and the processing time is 20 seconds.
[0031] In other embodiments, the chamber pressure, low-frequency radio frequency power, etching gas flow rate, and processing time for the first, second, and third etching steps can be adjusted accordingly.
[0032] The chemical composition of damaged layer 6 is SiO2. x Its source is the reaction of oxygen with the low dielectric constant layer 3. In this embodiment, the thickness of the surface damage layer 6 of the low dielectric constant layer 3 is less than 15 angstroms, approximately 12-15 angstroms, and the size of the via 31 has little impact.
[0033] Example 2 A method for improving the reliability of metal interconnect layers, referenced Figure 1 and Figure 2 Based on the photoresist pattern 5, vias 31 with metal interconnect layers are formed in the low dielectric constant layer 3 using a double damascene process. In this embodiment, the low dielectric constant layer 3 is a porous SiCOH material layer.
[0034] The photoresist undergoes ashing treatment: step-by-step dry etching is performed using carbon dioxide as the etching gas. In this embodiment, the step-by-step dry etching includes a first-step etching and a second-step etching performed sequentially. In this embodiment, ashing mainly refers to the removal of photolithographic materials such as the SHB layer and ODL layer; in other embodiments, it may also refer to the removal of the PR layer, etc.
[0035] In this process, the high-frequency radio frequency power of both the first and second etching steps is kept at 0W.
[0036] The low-frequency radio frequency power of the first etching step is greater than that of the second etching step. The chamber pressure of the first etching step is greater than that of the second etching step. The etching gas flow rate of the first etching step is greater than that of the second etching step.
[0037] Specifically, the following etching steps are performed sequentially: The first etching step has a chamber pressure of 40mT, a high-frequency radio frequency power of 0W, a low-frequency radio frequency power of 300W±30W, an etching gas flow rate of 350sccm±50sccm, and a processing time of 50 seconds.
[0038] The second step of etching involves a chamber pressure of 20 mT, a high-frequency radio frequency power of 0 W, a low-frequency radio frequency power of 200 W ± 30 W, an etching gas flow rate of 200 sccm ± 50 sccm, and a processing time of 50 seconds.
[0039] In other embodiments, the chamber pressure, low-frequency radio frequency power, etching gas flow rate, and processing time for the first and second etching steps can be adjusted accordingly. In this embodiment, the thickness of the surface damage layer 6 of the low dielectric constant layer 3 is approximately 25 angstroms.
[0040] Example 3 A method for fabricating a semiconductor structure, referenced Figure 1 and Figure 2 This includes the following steps: Step S1: Form a metal layer 1 on the substrate. In this embodiment, metal layer 1 is a first metal layer. A dielectric barrier layer 2 is formed on the metal layer 1. In this embodiment, dielectric barrier layer 2 is a silicon carbide layer. A low dielectric constant layer 3 is formed on the dielectric barrier layer 2. In this embodiment, low dielectric constant layer 3 is a porous SiCOH material layer. A capping layer 4 is formed on the low dielectric constant layer 3. In this embodiment, capping layer 4 is a hard mask layer. The hard mask layer can be a titanium nitride metal hard mask or a layer stacked with other materials. Photoresist is spin-coated onto capping layer 4 to form a photoresist pattern 5.
[0041] Step S2: After forming vias 31 with metal interconnect layers in the low dielectric constant layer 3 based on the photoresist pattern 5, the photoresist is ashed: step-by-step dry etching is performed using carbon dioxide as the etching gas. In this embodiment, the step-by-step dry etching includes a first etching step, a second etching step, and a third etching step performed sequentially. For specific steps, please refer to Embodiment 1, that is, using a method for improving the reliability of the metal interconnect layer in Embodiment 1 to form vias 31 in the low dielectric constant layer 3 and perform photoresist ashing treatment. In this embodiment, ashing mainly refers to removing photolithographic materials such as the SHB layer and ODL layer. In other embodiments, it can also be the removal of the PR layer, etc.
[0042] Step S3: A diffusion barrier layer is formed within the via 31. In this embodiment, the diffusion barrier layer is a Ta / TaN layer; in other embodiments, it can be other types of diffusion barrier layers. A conductive metal is filled within the diffusion barrier layer; in this embodiment, the conductive metal is copper. The thickness of the surface damage layer 6 of the low dielectric constant layer 3 is less than 15 angstroms, approximately 12-15 angstroms. See [link to documentation]. Figure 4 The thickness of the damaged layer 6 is estimated by using the overlapping region of Si (silicon) and O (oxygen), which is one of the existing methods for detecting the thickness of the damaged layer 6.
[0043] Comparative Example 1 The difference from Example 3 is that the ashing process for the photoresist is as follows: oxygen is used as the etching gas, the chamber pressure is 50 mT, the high-frequency radio frequency power is 500 W, the high-frequency radio frequency frequency is 40 MHz, the low-frequency radio frequency power is 0 W, the etching gas flow rate is 500 sccm, and the processing time is 90 seconds. The thickness of the surface damage layer 6 of the low dielectric constant layer 3 is 30-80 angstroms.
[0044] Comparative Example 2 The difference from Example 3 is that the ashing process for the photoresist is as follows: carbon dioxide is used as the etching gas, the chamber pressure is 50 mT, the high-frequency radio frequency power is 500 W, the high-frequency radio frequency frequency is 40 MHz, the low-frequency radio frequency power is 0 W, the etching gas flow rate is 500 sccm, and the processing time is 90 seconds. The thickness of the surface damage layer 6 of the low dielectric constant layer 3 is greater than 50 angstroms.
[0045] Comparative Example 3 The difference from Example 3 is that the ashing process for the photoresist is as follows: carbon dioxide is used as the etching gas, the chamber pressure is 50 mT, the high-frequency RF power is 0 W, the low-frequency RF power is 500 W, the low-frequency RF frequency is 13 MHz, the etching gas flow rate is 500 sccm, and the processing time is 90 seconds. The thickness of the surface damage layer 6 of the low dielectric constant layer 3 is approximately 40-45 angstroms. See [link to example]. Figure 5 The thickness of the damaged layer 6 is estimated using the overlapping region of Si (silicon) and O (oxygen), which is one of the existing methods for detecting the thickness of the damaged layer 6. With adjustments to the etching gas flow rate and processing time, the thickness of the damaged layer 6 is generally between 30 and 50 angstroms.
[0046] Comparative Example 4 The difference from Example 3 is that the ashing process for the photoresist is as follows: carbon dioxide is used as the etching gas, the chamber pressure is 50 mT, the high-frequency RF power is 0 W, the low-frequency RF power is 300 W, the low-frequency RF frequency is 13 MHz, the etching gas flow rate is 300 sccm, and the processing time is 90 seconds. The thickness of the surface damage layer 6 of the low dielectric constant layer 3 is approximately 30 angstroms.
[0047] As described in the above embodiments, by only enabling low-frequency (13MHz) radio frequency power and reducing the power value (PW) to around 300W or even less, surface damage to the low-dielectric-constant layer can be effectively reduced. This invention further employs a gradual reduction in chamber gas pressure, low-frequency radio frequency power, and carbon dioxide flow rate. Parameter adjustments are based on the equal amount of adhesive removed and the defined removal location in each step. Extensive experimental verification has shown that this synergistically reduces damage to the Low K film layer and further reduces oxidation of the diffusion barrier layer, thereby significantly improving the reliability of the metal interconnect layer.
[0048] The above description of the embodiments is only for the purpose of helping to understand the method and core idea of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A method for improving the reliability of a metal interconnect layer, characterized in that, After forming vias (31) of metal interconnects in a low dielectric constant layer (3) based on the photoresist pattern (5), the photoresist is ashed: carbon dioxide is used as the etching gas for step-by-step dry etching, which includes at least a first step etching and a second step etching performed sequentially. The high-frequency radio frequency power of the first step etching and the second step etching are both kept at 0W. The low-frequency radio frequency power of the first step etching is greater than that of the second step etching. The chamber pressure of the first step etching is greater than that of the second step etching. The etching gas flow rate of the first step etching is greater than that of the second step etching.
2. The method for improving the reliability of a metal interconnect layer according to claim 1, characterized in that, The step-by-step dry etching also includes a third etching step performed after the second etching step. The high-frequency radio frequency power of the third etching step is 0W, the low-frequency radio frequency power of the third etching step is less than the low-frequency radio frequency power of the second etching step, the chamber pressure of the third etching step is less than the chamber pressure of the second etching step, and the etching gas flow rate of the third etching step is less than the etching gas flow rate of the second etching step.
3. The method for improving the reliability of a metal interconnect layer according to claim 2, characterized in that, The low-frequency radio frequency power of the first etching step, the second etching step, and the third etching step is less than or equal to 400W; the frequency of the low-frequency radio frequency is 13MHz.
4. A method for improving the reliability of a metal interconnect layer according to claim 2 or 3, characterized in that, The low-frequency radio frequency power of the first etching step is 300W±30W, the low-frequency radio frequency power of the second etching step is 250W±30W, and the low-frequency radio frequency power of the third etching step is 200W±30W.
5. A method for improving the reliability of a metal interconnect layer according to claim 2, characterized in that, The chamber pressure for the first etching step is 40 mT, the chamber pressure for the second etching step is 30 mT, and the chamber pressure for the third etching step is 20 mT.
6. The method for improving the reliability of a metal interconnect layer according to claim 2, characterized in that, The etching gas flow rate for the first etching step is 350 sccm ± 50 sccm, the etching gas flow rate for the second etching step is 300 sccm ± 50 sccm, and the etching gas flow rate for the third etching step is 200 sccm ± 50 sccm.
7. The method for improving the reliability of a metal interconnect layer according to claim 2, characterized in that, The processing time for the first etching step is t1 seconds, the processing time for the second etching step is t2 seconds, and the processing time for the third etching step is t3 seconds; wherein, 80≤t1+t2+t3≤100.
8. The method for improving the reliability of a metal interconnect layer according to claim 7, characterized in that, The first etching step takes 40-50 seconds, the second etching step takes 20-30 seconds, and the third etching step takes 20-30 seconds.
9. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Step S1: Form a metal layer (1) on the substrate, wherein a dielectric barrier layer (2), a low dielectric constant layer (3), a capping layer (4) and a photoresist pattern (5) are sequentially formed on the metal layer (1). Step S2: Using the method for improving the reliability of the metal interconnect layer according to any one of claims 1-8, a via (31) is formed in the low dielectric constant layer (3) and a photoresist ashing treatment is performed; Step S3: A diffusion barrier layer is formed in the through hole (31), and a conductive metal is filled in the diffusion barrier layer.
10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The dielectric barrier layer (2) is a silicon carbide layer, the low dielectric constant layer (3) is a SiCOH material layer, the cover layer (4) is a hard mask layer, the photoresist is one or more of the ODL layer, SHB layer and PR layer, the diffusion barrier layer is a Ta / TaN layer, and the conductive metal is copper.