A filter and synchronization signal processing method

Abstract

The application discloses a filter and a synchronization signal processing method. The filter comprises a first filter set and a second filter set; input ends of the first filter set and the second filter set are connected to a signal sampling component; output ends of the first filter set and the second filter set are connected to a filter output end; the signal sampling component is used for collecting a double-sampling-point communication signal and transmitting the communication signal to the first filter set and the second filter set; the first filter set is used for receiving a first communication signal and filtering the first communication signal to obtain a first filtered signal; the second filter set is used for receiving a second communication signal and filtering the second communication signal to obtain a second filtered signal; and the filter output end is used for coupling the first filtered signal and the second filtered signal to obtain a final filtered signal. According to the embodiment of the application, the downsampling is realized while the filtering precision is ensured, and the operation amount is reduced.

Description

Technical Field

[0001] This application belongs to the technical field of filters, and particularly relates to a filter and a method for processing synchronous signals. Background Technology

[0002] In 5G application scenarios, the Reduced Capability (RedCap) is responsible for wireless communication between two users. During the communication process, a filter is usually set on the RedCap to reduce interference. However, due to the characteristics of the RedCap, such as dense user distribution and many adjacent interfering cells, the filter has high requirements.

[0003] Currently, traditional Infinite Impulse Response (IIR) filters are commonly used for filtering. Although IIR filters can meet the filtering requirements, they are inherently unstable, difficult to design, and cannot be designed as multi-element structures in downsampling systems, thus failing to accommodate downsampling functionality and incurring high computational demands. Summary of the Invention

[0004] This application provides a filter and a synchronization signal processing method that can achieve downsampling and reduce computational load while ensuring filtering accuracy.

[0005] In a first aspect, embodiments of this application provide a filter, the filter comprising:

[0006] First filter bank and second filter bank;

[0007] The input terminals of the first filter group and the second filter group are both connected to the signal sampling component, and the output terminals of the first filter group and the second filter group are both connected to the filter output terminal;

[0008] The signal sampling component is used to acquire communication signals with double sampling points and transmit the communication signals to the first filter group and the second filter group, wherein the communication signals include a first communication signal with an odd number of sampling points and a second communication signal with an even number of sampling points;

[0009] The first filter bank is used to receive the first communication signal and filter the first communication signal to obtain a first filtered signal;

[0010] The second filter bank is used to receive the second communication signal and filter the second communication signal to obtain a second filtered signal;

[0011] The filter output terminal is used to couple the first filter signal and the second filter signal to obtain the final filter signal.

[0012] Optionally, the first filter bank includes a first delay unit and at least one first filter unit cascaded with the first delay unit. The input terminal of the first delay unit is connected to the signal sampling component, the output terminal of the first delay unit is connected to the input terminal of the first filter unit, and the output terminal of the first filter unit is connected to the filter output terminal.

[0013] The second filter bank includes at least one second filter unit, the input terminal of the second filter unit is connected to the signal sampling component, and the output terminal of the second filter unit is connected to the filter output terminal;

[0014] In the case where the second filter bank includes multiple second filter units, the multiple second filter units are cascaded.

[0015] Optionally, the filters of the first filtering unit and / or the second filtering unit are elliptic IIR filters.

[0016] Optionally, the input-output relationship of the first filtering unit / or the second filtering unit is as follows:

[0017] OUT2 = a i *(IN1-IN2)+IN2

[0018] OUT1 = OUT2 - (IN1 - IN2)

[0019] Wherein, OUT1 is the first filtered signal at the first output terminal, OUT2 is the second filtered signal at the second output terminal, IN1 is the communication signal at the first input terminal, IN2 is the first filtered signal at the first output terminal with delay, and a i represents the filtering coefficient of the i-th first or second filtering unit, where i is a positive integer.

[0020] Optionally, the first delay unit is provided between the second input terminal and the first output terminal, and the relationship between the second input terminal and the first output terminal is as follows:

[0021] IN2(n) = OUT1(nb)

[0022] Wherein, the first filtered signal input to the second input terminal is the first filtered signal after b delays, and n is the sampling point, which is a positive integer.

[0023] Optionally, the filter further includes a second delay unit, the input of which is connected to the filter output.

[0024] The second delay unit is used to delay the output of the final filtered signal.

[0025] Secondly, embodiments of this application provide a synchronization signal processing method, the method comprising:

[0026] Acquire communication signals collected by the signal sampling component;

[0027] The communication signal is filtered using the filter described in the first aspect to obtain the final filtered signal;

[0028] The final filtered signal is subjected to sequence signal extraction to obtain the first communication sequence signal;

[0029] The first communication sequence signal is compensated for parameters to obtain the compensated second communication sequence signal;

[0030] The second communication sequence signal is upsampled using a preset equalization algorithm to obtain the synchronized communication signal.

[0031] Optionally, the parameter compensation includes phase compensation, and the first communication sequence signal includes a primary synchronization sequence signal and a secondary synchronization sequence signal;

[0032] The step of performing parameter compensation on the first communication sequence signal to obtain the compensated second communication sequence signal includes:

[0033] Obtain the phase information of the filter within a preset resource range;

[0034] Based on the phase information, determine the phase compensation information;

[0035] Based on the phase compensation information, phase compensation is performed on the primary synchronization sequence signal and the secondary synchronization sequence signal respectively to obtain the second communication sequence signal.

[0036] Optionally, the parameter compensation includes amplitude compensation;

[0037] The step of performing parameter compensation on the first communication sequence signal to obtain the compensated second communication sequence signal includes:

[0038] Obtain the amplitude information of the filter within a preset resource range;

[0039] If the amplitude information meets the preset compensation conditions, the amplitude compensation information is determined based on the amplitude information and the preset compensation formula.

[0040] The amplitude of the first communication sequence signal is compensated based on the amplitude compensation information to obtain the compensated second communication sequence signal.

[0041] Optionally, the step of upsampling the second communication sequence signal using a preset equalization algorithm to obtain the synchronized communication signal includes:

[0042] The first communication sequence signal is interpolated in the frequency domain to obtain the third communication sequence signal in the frequency domain.

[0043] Based on a preset sequence length, the third communication sequence signal is padded with zeros according to a preset zero-padding direction to obtain a zero-padding fourth communication sequence signal;

[0044] In the time domain, the fourth communication sequence signal is forced to zero in the time domain to obtain the fifth communication sequence signal in the time domain;

[0045] Perform an inverse Fourier transform on the fifth communication sequence signal to obtain the synchronized communication signal in the frequency domain.

[0046] In another aspect, embodiments of this application provide a lightweight terminal, which includes: a processor and a memory storing computer program instructions;

[0047] When the processor executes the computer program instructions, it implements the synchronization signal processing method as described in the first aspect.

[0048] In another aspect, embodiments of this application provide a computer storage medium storing computer program instructions, which, when executed by a processor, implement the synchronization signal processing method as described in the first aspect.

[0049] In another aspect, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform the synchronization signal processing method as described in the first aspect.

[0050] The filter and synchronization signal processing method of this application embodiment can filter the first communication signal with odd sampling points by using a first filter bank during the filtering process of the communication signal sampled by the signal sampling component, and then simultaneously use a second filter bank to filter the second communication signal with even sampling points. In this process, the first filter bank and the second filter bank respectively filter half of the communication signal. Then, by coupling the first filtered signal and the second filtered signal at the filter output terminal, the final filtered signal is obtained. Compared with the existing all-pass filter, the first filter bank and the second filter bank can achieve all-pass filtering of the communication signal by only completing half of the communication signal filtering while ensuring filtering accuracy. This not only reduces the amount of computation, but also improves the filtering efficiency. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a structural block diagram of a filter provided in one embodiment of this application;

[0053] Figure 2 This is a schematic diagram of the structure of a filter provided in one embodiment of this application;

[0054] Figure 3 This is a schematic diagram of the structure of a first filtering unit / second filtering unit provided in one embodiment of this application;

[0055] Figure 4 This is a schematic flowchart of a synchronization signal processing method provided in one embodiment of this application;

[0056] Figure 5 This is a response diagram of phase information provided in one embodiment of this application;

[0057] Figure 6 This is a response diagram of amplitude information provided in one embodiment of this application;

[0058] Figure 7 This is a flowchart illustrating a synchronization signal processing method provided in another embodiment of this application;

[0059] Figure 8 This is a schematic diagram of a frequency-domain interpolated signal provided in one embodiment of this application;

[0060] Figure 9 This is a schematic diagram of a frequency-domain zero-padded signal provided in one embodiment of this application;

[0061] Figure 10 This is a schematic diagram of a time-domain converted signal provided in one embodiment of this application;

[0062] Figure 11 This is a schematic diagram of the signal after time-domain zero-forcing according to an embodiment of this application;

[0063] Figure 12 This is a schematic diagram of the structure of a 7th-order filter provided in one embodiment of this application;

[0064] Figure 13 This is a phase response diagram of a 7th-order filter provided in one embodiment of this application;

[0065] Figure 14 This is the amplitude response diagram of a 7th-order filter provided in one embodiment of this application;

[0066] Figure 15 This is a schematic diagram of the structure of a lightweight terminal provided in another embodiment of this application.

[0067] Explanation of reference numerals in the attached figures:

[0068] 10. First filter bank; 11. First delay unit; 12. First filtering unit; 20. Second filter bank; 21. Second filtering unit; 30. Signal sampling component; 40. Second delay unit; 50. Filter output terminal. Detailed Implementation

[0069] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0070] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0071] To address the problems of existing technologies, this application provides a filter and a synchronization signal processing method. In the process of filtering the communication signal sampled by the signal sampling component, a first filter bank is used to filter the first communication signal with odd-numbered sampling points, and then a second filter bank is simultaneously used to filter the second communication signal with even-numbered sampling points. In this process, the first and second filter banks each filter half of the communication signal. Then, by coupling the first and second filtered signals at the filter output, the final filtered signal is obtained. Compared to existing all-pass filters, the first and second filter banks, while ensuring filtering accuracy, only need to filter half of the communication signal to achieve all-pass filtering, thus reducing computational load and improving filtering efficiency.

[0072] The filter and synchronization signal processing method provided in this application will be described in detail below with reference to the accompanying drawings.

[0073] Reference Figure 1 The filter may include:

[0074] First filter bank 10 and second filter bank 20.

[0075] The input terminals of the first filter group 10 and the second filter group 20 are both connected to the signal sampling component 30, and the output terminals of the first filter group 10 and the second filter group 20 are both connected to the filter output terminal 50.

[0076] In this embodiment, the signal sampling component 30 can be an analog-to-digital converter. During the synchronization signal processing, the analog-to-digital converter needs to perform oversampling, and the sampling rate can be:

[0077] FS=E*SCS*128 (1)

[0078] Where FS is the sampling rate, E is the oversampling ratio, and SCS is the subcarrier spacing; as an example, SCS can be 15KHz or 30KHz.

[0079] In some embodiments, taking the application of a filter to a lightweight terminal as an example, the number of points in the Fourier transform module can be determined to be the number of points used in the Fast Fourier Transform. This number of points determines the frequency resolution and sampling time. In the Fourier transform algorithm, the input signal is decomposed into NFFT (the number of points used in the Fast Fourier Transform) frequency components, and each frequency component corresponds to a specific frequency.

[0080] In some embodiments, the signal sampling component 30 is used to acquire communication signals with double sampling points and transmit communication signals to the first filter group 10 and the second filter group 20, wherein the communication signals include a first communication signal with an odd number of sampling points and a second communication signal with an even number of sampling points.

[0081] The first filter bank 10 is used to receive the first communication signal and filter the first communication signal to obtain the first filtered signal;

[0082] The second filter bank 20 is used to receive the second communication signal and filter the second communication signal to obtain the second filtered signal;

[0083] The filter output terminal 50 is used to couple the first filter signal and the second filter signal to obtain the final filter signal.

[0084] In this embodiment, during the filtering of the communication signal sampled by the signal sampling component 30, the first filter bank 10 is used to filter the first communication signal with odd sampling points, and then the second filter bank 20 is used to filter the second communication signal with even sampling points. In this process, the first filter bank 10 and the second filter bank 20 respectively filter half of the communication signal. Then, the first filtered signal and the second filtered signal are coupled at the filter output terminal 50 to obtain the final filtered signal. Compared with the existing all-pass filter, the first filter bank 10 and the second filter bank 20 can achieve all-pass filtering of the communication signal by only completing half of the communication signal filtering while ensuring the filtering accuracy. This not only reduces the amount of computation but also improves the filtering efficiency.

[0085] Reference Figure 1 and Figure 2 In some embodiments, the first filter bank 10 may include a first delay unit 11 and at least one first filter unit 12 cascaded with the first delay unit 11. The input terminal of the first delay unit 11 is connected to the signal sampling component 30, the output terminal of the first delay unit 11 is connected to the input terminal of the first filter unit 12, and the output terminal of the first filter unit 12 is connected to the filter output terminal 50.

[0086] The second filter bank 20 includes at least one second filter unit 21, the input terminal of the second filter unit 21 is connected to the signal sampling component 30, and the output terminal of the second filter unit 21 is connected to the filter output terminal 50.

[0087] In the case where the second filter bank 20 includes a plurality of second filter units 21, the plurality of second filter units 21 are cascaded.

[0088] In some embodiments, since the first filter bank 10 filters the first communication signal with odd sampling points, after the communication signal enters the filter, the first filter bank 10 starts to filter the first communication signal with odd sampling points. In order to ensure the consistency of the waveform filtered by the first filter bank 10 and the synchronization of the synchronization signal, a first delay unit 11 needs to be set in the first filter bank 10 first, so that the first delay unit 11 performs delay filtering on the first communication signal input to the first filter bank 10, so as to ensure the consistency and synchronization of the communication signal.

[0089] In some embodiments, the first delay unit 11 may be an independent delay output unit or a first filter unit 12 with a filter coefficient of 1.

[0090] It is worth noting that multiple first filter units 12 and multiple second filter units 21 form a digital filter bank with a half-band reciprocal structure. The filter coefficients of the multiple first filter units 12 and multiple second filter units 21 are set in an interleaved manner. For example, the filter coefficient of the first first filter unit 12 of the first filter bank 10 is a3, the filter coefficient of the first second filter unit 21 of the second filter bank 20 is a1, the filter coefficient of the second first filter unit 12 of the first filter bank 10 is a7, and the filter coefficient of the second second filter unit 21 of the second filter bank 20 is a5. The filter coefficients of each first filter unit 12 and each second filter unit 21 are allocated in this interleaved manner.

[0091] In this embodiment, multiple first filter units 12 and multiple second filter units 21 form an N-order filter bank with a half-band reciprocal structure to further reduce the computational load of the filter bank.

[0092] In some embodiments, in order to maintain a narrow transition band and high out-of-band rejection performance during the filtering of communication signals, the filters of the first filtering unit 12 and / or the second filtering unit 21 are elliptic IIR filters.

[0093] As an example, elliptic IIR filters have the following advantages:

[0094] 1. Greater flexibility: IIR filters connect the output to the input through feedback, forming a recursive structure that allows for the implementation of higher-order filters. This structure enables IIR filters to have lower delay and higher frequency selectivity compared to FIR (Finite Impulse Response) filters of the same filter order.

[0095] 2. Lower computational complexity: IIR filters are generally more computationally efficient than FIR filters because they do not require storing large amounts of prior samples; instead, they implement the filtering process through recursive operations. This reduces the demand for computational resources, making IIR filters more efficient when processing large amounts of data.

[0096] 3. Wideband Characteristics: Compared to FIR filters, IIR filters can achieve wider bandpass and bandstop characteristics, thus better adapting to frequency selection requirements. This gives IIR filters a greater advantage in applications requiring wideband processing.

[0097] 4. More complex frequency selection: IIR filters can achieve more complex frequency selection, such as elliptic filters and Chebyshev filters. These filters have better frequency response characteristics in some applications and can meet more stringent filtering requirements.

[0098] Approximating the Ideal Rectangular Filter: Classic IIR filter types, such as the Butterworth filter, Chebyshev Class I and Class II filters, elliptic filters, and Bessel filters, are all designed to approximate the ideal rectangular filter. While it is practically difficult to achieve a perfectly ideal rectangular filter, IIR filters can approximate this ideal state through different design strategies, thereby providing better filtering performance.

[0099] Reference Figure 3 , Figure 3 The structural diagram of the first filter unit 12 or the second filter unit 21 is shown, wherein the input-output relationship of the first filter unit 12 or the second filter unit 21 satisfies the following formulas (2) and (3):

[0100] OUT2 = a i *(IN1-IN2)+IN2 (2)

[0101] OUT1 = OUT2 - (IN1 - IN2) (3)

[0102] Wherein, OUT1 is the first filtered signal at the first output terminal, OUT2 is the second filtered signal at the second output terminal, IN1 is the communication signal at the first input terminal, IN2 is the first filtered signal at the first output terminal with delay, and a i represents the filtering coefficient of the i-th first or second filtering unit, where i is a positive integer.

[0103] In some embodiments, to provide better filtering results, a i Requires: 0 i <0.5.

[0104] ​In other embodiments, in order to ensure the synchronization of the communication signal after filtering, a first delay unit 11 is provided between the second input terminal and the first output terminal, and the relationship between the second input terminal and the first output terminal is given by formula (4):

[0105] IN2(n)=OUT1(nb) (4)

[0106] The first filtered signal input to the second input terminal is the first filtered signal after b delays, where n is the sampling point and is a positive integer.

[0107] As an example, b is 2, meaning that the first filtered signal output from the first output terminal is delayed by 2 units and then filtered again by the second input terminal.

[0108] In some embodiments, for an Nth-order filter, in order to ensure that the filter exhibits a half-band reciprocal structure, the constraint condition for the order N is:

[0109] N = 4 * M - 1, M > 1 (5)

[0110] Where M is a positive integer. In this embodiment, by changing the value of M, the filter can always be a half-band reciprocal filter, thereby reducing the amount of computation.

[0111] In this embodiment, it is necessary to set not only the filter order, but also parameters such as the filter passband cutoff frequency, passband ripple, and out-of-band attenuation. These parameters are all conventional settings and will not be described in detail here.

[0112] It is worth noting that for a half-band reciprocal filter, the filter coefficients a2, a4, ..., aN-1 are all 0, and the effective filter coefficients are a1, a3, ..., aN, for a total of (N-1) / 2.

[0113] In some other embodiments, in order to further ensure the synchronization of communication signals, the filter also includes a second delay unit 40, the input of which is connected to the filter output 50, and the second delay unit 40 is used to delay the output of the final filtered signal.

[0114] In this embodiment, after the first filter bank 10 and the second filter bank 20 filter the communication signal respectively, they are coupled at the filter output terminal 50 to form the final filtered signal. At this time, in order to ensure the synchronization of the final filtered signal, the final filtered signal is input to the second delay unit 40. After the unit delay of the second delay unit 40, the signal is output with a delay.

[0115] In this embodiment, by connecting the first filter bank 10 and the second filter bank 20 in the form of a half-band reciprocal structure, not only can the communication signal be filtered, but the communication signal sampled at double sampling points can also be downsampled, thereby improving the filtering efficiency.

[0116] Reference Figure 4 This application also provides a synchronization signal processing method, which may include steps S401-S405:

[0117] S401, acquire the communication signal collected by the signal sampling component 30;

[0118] S402, the communication signal is filtered using the aforementioned filter to obtain the final filtered signal;

[0119] S403, perform sequence signal extraction on the final filtered signal to obtain the first communication sequence signal;

[0120] S404, Perform parameter compensation on the first communication sequence signal to obtain the compensated second communication sequence signal;

[0121] S405, the second communication sequence signal is upsampled using a preset equalization algorithm to obtain the synchronized communication signal.

[0122] In some embodiments, in S401, the signal sampling component 30 uses double sampling points to achieve oversampling, ensuring the integrity of the communication signal.

[0123] In some embodiments, in S402, when the signal sampling component 30 transmits the acquired communication signal to the filter, a filter with a half-band reciprocal structure is used to filter the communication signal, which can both ensure the filtering effect of the communication signal and achieve downsampling, thereby improving the filtering efficiency.

[0124] In some embodiments, in S403, to ensure efficient synchronization and high performance of the synchronization signal, the final filtered signal is first extracted using the 3GPP protocol to obtain a first communication sequence signal. The first communication sequence signal may include a primary synchronization sequence signal (PSS) and a secondary synchronization sequence signal (SSS). The primary and secondary synchronization sequence signals may satisfy condition formula 6.

[0125] PSS 3GPP (i),SSS 3GPP (i), 1≤i≤127 (6)

[0126] Where i represents a unit of resource.

[0127] In some embodiments, since the filter is an IIR filter, phase distortion and / or amplitude distortion may occur during the synchronization signal processing. Therefore, phase or amplitude compensation is required during the synchronization signal processing.

[0128] In some embodiments, in S404, parameter compensation may include phase compensation and / or amplitude compensation. During the parameter compensation process, the phase information and / or amplitude information of the filter may be acquired in units of resource elements (REs).

[0129] Specifically, S404 may include:

[0130] Obtain the phase information of the filter within the preset resource range;

[0131] Based on the phase information, determine the phase compensation information;

[0132] Phase compensation is performed on the primary synchronization sequence signal and the secondary synchronization sequence signal based on the phase compensation information to obtain the second communication sequence signal.

[0133] In this embodiment, during the phase compensation process, it is first necessary to obtain phase information within a preset resource range on a unit basis, as detailed in the following document. Figure 5 Waveform 1 represents the phase information of the filter.

[0134] Phase filter (i), 1≤i≤127

[0135] After obtaining the phase information of the filter, phase compensation information can be determined based on the phase information, such as... Figure 5 The waveform 2 in the figure shows that the phase compensation information is given by formula (7):

[0136]

[0137] In this embodiment, after obtaining the phase compensation information, phase compensation is performed on the primary synchronization sequence signal and the secondary synchronization sequence signal respectively to obtain the second communication sequence signal, so as to ensure the synchronization of the communication signal.

[0138] In other embodiments, when performing amplitude compensation, S404 may further include:

[0139] Obtain the amplitude information of the filter within the preset resource range;

[0140] If the amplitude information meets the preset compensation conditions, the amplitude compensation information is determined based on the amplitude information and the preset compensation formula.

[0141] The amplitude of the first communication sequence signal is compensated based on the amplitude compensation information to obtain the compensated second communication sequence signal.

[0142] In this embodiment, the amplitude information of the filter within a preset resource range is first obtained. The preset resource range is the same as the preset resource range of the phase information mentioned above, both of which are resource ranges in units of resource units.

[0143] In some embodiments, see Figure 6 First, the amplitude value from 1 to a-1 can be indexed through the resource unit. If the in-band flatness of the preset resource range from 1 to a-1 is within the preset range, amplitude compensation is not required. If the in-band flatness is not within the preset range, amplitude compensation is required.

[0144] in, Figure 6 Waveform 3 in the image represents the filter amplitude information, and waveform 4 represents the amplitude compensation information.

[0145] Specifically, the preset compensation condition is formula (8):

[0146]

[0147] Among them, Amp ThresDB The preset range for in-band flatness.

[0148] When amplitude compensation is required, the amplitude compensation information can be determined based on the following formula (9):

[0149]

[0150] Among them, Amp pre-dist (i) represents amplitude compensation information, Amp filter (i) represents amplitude information.

[0151] Then, the primary synchronization sequence signal and the secondary synchronization sequence signal are compensated based on the amplitude compensation information using the following formulas (10) and (11):

[0152]

[0153] Reference Figure 7 In some embodiments, S405 may specifically include:

[0154] S4051, perform frequency domain interpolation on the first communication sequence signal to obtain the third communication sequence signal in the frequency domain;

[0155] S4052, Based on the preset sequence length, the third communication sequence signal is padded with zeros according to the preset zero-padding direction to obtain the zero-padding fourth communication sequence signal;

[0156] S4053, in the time domain, the fourth communication sequence signal is forced to zero in the time domain to obtain the fifth communication sequence signal in the time domain;

[0157] S4054 performs an inverse Fourier transform on the fifth communication sequence signal to obtain the synchronized communication signal in the frequency domain.

[0158] In this embodiment, in order to eliminate the interference between symbols on the primary synchronization sequence signal and the secondary synchronization sequence signal, it is also necessary to upsample the second communication sequence signal to obtain the second communication sequence signal of NFFT length.

[0159] Specifically, in S4051, the primary synchronization sequence signal and the secondary synchronization sequence signal are first converted in the frequency domain, and then frequency interpolation is performed on the primary synchronization sequence signal and the secondary synchronization sequence signal in the frequency domain. The primary synchronization sequence signal is interpolated in the frequency domain according to the following formula (12), and the secondary synchronization sequence signal is interpolated in the frequency domain according to the following formula (13):

[0160]

[0161] Where E is the oversampling factor, and K represents the position of the effective value corresponding to the main synchronization sequence signal or the auxiliary synchronization sequence signal, which determines how many zeros need to be inserted between the two sequence signals.

[0162] As an example, you can refer to Figure 8 , Figure 8 An interpolation result is shown, where F represents the corresponding valid value.

[0163] In some embodiments, in S4052, the third communication sequence signal needs to be zero-padded, that is, zero-padded in both the negative frequency direction and the positive frequency direction with a length of [missing information]. and So that the length of the fourth communication sequence signal after zero padding is equal to the NFFT length.

[0164] As an example, refer to Figure 9 , Figure 9 To pad the result with zeros.

[0165] In some embodiments, after zero-padding, the fourth communication sequence signal is time-domain transformed to obtain the fifth communication sequence signal in the time domain, i.e.:

[0166]

[0167]

[0168] Here, IFFT represents the inverse Fourier transform.

[0169] As an example, refer to Figure 10 , Figure 10 A schematic diagram of the primary synchronization sequence signal and the secondary synchronization sequence signal is shown.

[0170] In some embodiments, in S4054, the invalid parts of PSS(ext-t1)(i) and SSS(ext-t1)(i) in the time domain are forced to zero to obtain time-domain length finite sequences PSS(ext-t2)(i) and SSS(ext-t2)(i), with zero-forcing lengths of (NFFT-128*E) / 2 and (NFFT-126*E) / 2 in the negative frequency direction and the positive frequency direction, respectively.

[0171] As an example, see Figure 11 , Figure 11 The primary and secondary synchronization sequence signals after zero-forcing are shown.

[0172] In this embodiment, after zero-forcing in the time domain, the fifth communication sequence signal is subjected to inverse Fourier transform to obtain the synchronized communication signal in the frequency domain.

[0173] As a specific example Figure 12 A block diagram of a 7th-order filter is shown in this example. Figure 13 The phase information under this filter is shown. Figure 14 The amplitude information of the 7th order filter is shown. It can be seen that both the phase information and the amplitude information need to be compensated. The specific compensation method can be referred to the above method, and will not be elaborated here.

[0174] Figure 15 A schematic diagram of the hardware structure of the lightweight terminal provided in an embodiment of this application is shown.

[0175] An electronic device may include a processor 1501 and a memory 1502 storing computer program instructions.

[0176] Specifically, the processor 1501 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0177] Memory 1502 may include mass storage for data or instructions. For example, and not limitingly, memory 1502 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. In one instance, memory 1402 may include removable or non-removable (or fixed) media, or memory 1402 may be non-volatile solid-state memory. Memory 1502 may be internal or external to the integrated gateway disaster recovery device.

[0178] In one instance, memory 1502 may be read-only memory (ROM). In one instance, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.

[0179] Memory 1502 may include read-only memory (ROM), random access memory (RAM), disk storage media device, optical storage media device, flash memory device, electrical, optical, or other physical / tangible memory storage device. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the synchronous signal processing method according to the first aspect of this disclosure.

[0180] Processor 1501 reads and executes computer program instructions stored in memory 1502 to achieve... Figure 4 A synchronization signal processing method is shown in the embodiment.

[0181] In one example, the electronic device may also include a communication interface 1503 and a bus 1504. For example, Figure 15 As shown, the processor 1501, memory 1502, and communication interface 1503 are connected through bus 1504 and complete communication with each other.

[0182] The communication interface 1503 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0183] Bus 1504 includes hardware, software, or both, that couples components of an electronic device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 1504 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, this application contemplates any suitable bus or interconnect.

[0184] The electronic device can execute the synchronization signal processing method in the embodiments of this application, thereby achieving the combination Figures 1-14 The method for processing synchronous signals is described.

[0185] Furthermore, in conjunction with the synchronization signal processing methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the synchronization signal processing methods in the above embodiments.

[0186] In an optional embodiment, in conjunction with the synchronization signal processing method in the above embodiments, this application embodiment can provide a computer program product to implement it. The instructions in the computer program product are executed by the processor of the electronic device, enabling the electronic device to implement any of the synchronization signal processing methods in the above embodiments.

[0187] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0188] The functional blocks shown in the above block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0189] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0190] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0191] The above are merely specific embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A filter, characterized in that, include: First filter bank and second filter bank; The input terminals of the first filter group and the second filter group are both connected to the signal sampling component, and the output terminals of the first filter group and the second filter group are both connected to the filter output terminal; The signal sampling component is used to acquire communication signals with double sampling points and transmit the communication signals to the first filter group and the second filter group, wherein the communication signals include a first communication signal with an odd number of sampling points and a second communication signal with an even number of sampling points; The first filter bank is used to receive the first communication signal and filter the first communication signal to obtain a first filtered signal; The second filter bank is used to receive the second communication signal and filter the second communication signal to obtain a second filtered signal; The filter output terminal is used to couple the first filter signal and the second filter signal to obtain the final filter signal.

2. The filter according to claim 1, characterized in that, The first filter bank includes a first delay unit and at least one first filter unit cascaded with the first delay unit. The input terminal of the first delay unit is connected to the signal sampling component, the output terminal of the first delay unit is connected to the input terminal of the first filter unit, and the output terminal of the first filter unit is connected to the filter output terminal. The second filter bank includes at least one second filter unit, the input terminal of the second filter unit is connected to the signal sampling component, and the output terminal of the second filter unit is connected to the filter output terminal; In the case where the second filter bank includes multiple second filter units, the multiple second filter units are cascaded.

3. The filter according to claim 2, characterized in that, The filters of the first filtering unit and / or the second filtering unit are elliptic IIR filters.

4. The filter according to claim 3, characterized in that, The input-output relationship of the first filtering unit and / or the second filtering unit: OUT2=a i *(IN1-IN2)+IN2 OUT1 = OUT2 - (IN1 - IN2) Wherein, OUT1 is the first filtered signal at the first output terminal, OUT2 is the second filtered signal at the second output terminal, IN1 is the communication signal at the first input terminal, IN2 is the first filtered signal at the first output terminal with delay, and a i represents the filtering coefficient of the i-th first or second filtering unit, where i is a positive integer.

5. The filter according to claim 4, characterized in that, The first delay unit is provided between the second input terminal and the first output terminal, and the relationship between the second input terminal and the first output terminal is as follows: IN2(n) = OUT1(nb) Wherein, the first filtered signal input to the second input terminal is the first filtered signal after b delays, and n is the sampling point, which is a positive integer.

6. The filter according to claim 2, characterized in that, The filter further includes a second delay unit, the input of which is connected to the filter output. The second delay unit is used to delay the output of the final filtered signal.

7. A synchronization signal processing method, characterized in that, include: Acquire communication signals collected by the signal sampling component; The communication signal is filtered using the filter described in any one of claims 1-6 to obtain the final filtered signal; The final filtered signal is subjected to sequence signal extraction to obtain the first communication sequence signal; The first communication sequence signal is compensated for parameters to obtain the compensated second communication sequence signal; The second communication sequence signal is upsampled using a preset equalization algorithm to obtain the synchronized communication signal.

8. The method according to claim 7, characterized in that, The parameter compensation includes phase compensation, and the first communication sequence signal includes a primary synchronization sequence signal and a secondary synchronization sequence signal; The step of performing parameter compensation on the first communication sequence signal to obtain the compensated second communication sequence signal includes: Obtain the phase information of the filter within a preset resource range; Based on the phase information, determine the phase compensation information; Based on the phase compensation information, phase compensation is performed on the primary synchronization sequence signal and the secondary synchronization sequence signal respectively to obtain the second communication sequence signal.

9. The method according to claim 7 or 8, characterized in that, The parameter compensation includes amplitude compensation; The step of performing parameter compensation on the first communication sequence signal to obtain the compensated second communication sequence signal includes: Obtain the amplitude information of the filter within a preset resource range; If the amplitude information meets the preset compensation conditions, the amplitude compensation information is determined based on the amplitude information and the preset compensation formula. The amplitude of the first communication sequence signal is compensated based on the amplitude compensation information to obtain the compensated second communication sequence signal.

10. The method according to claim 7, characterized in that, The step of upsampling the second communication sequence signal using a preset equalization algorithm to obtain the synchronized communication signal includes: The first communication sequence signal is interpolated in the frequency domain to obtain the third communication sequence signal in the frequency domain. Based on a preset sequence length, the third communication sequence signal is padded with zeros according to a preset zero-padding direction to obtain a zero-padding fourth communication sequence signal; In the time domain, the fourth communication sequence signal is forced to zero in the time domain to obtain the fifth communication sequence signal in the time domain; Perform an inverse Fourier transform on the fifth communication sequence signal to obtain the synchronized communication signal in the frequency domain.

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