A power device self-current-sharing control system and method

Abstract

The application discloses a power device self-current-sharing control system, which is used for controlling at least two parallel power devices in a parallel system and specifically comprises the following parts: a multi-channel feedback module, which is used for acquiring differential signals representing current imbalance states among the power devices in real time; a control unit, which is used for receiving the differential signals output by the multi-channel feedback module and generating a first group of control signals for controlling the turn-on or turn-off of the power devices and a second group of control signals for controlling the gate voltages of the power devices; at least one active gate drive module, which is connected between the control unit and the gates of the power devices, is used for receiving the first group of control signals and the second group of control signals; and based on the feedback of at least two gate voltages, the active gate drive module outputs dynamically adjustable differential drive signals to the power devices in a closed loop, thereby effectively realizing the self-current-sharing control of the power devices in the parallel system.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor applications, specifically to a self-current sharing control system and method for power devices in parallel systems, and is particularly applicable to high-current, high-power-density converters, power modules, and motor drives that require high reliability. Background Technology

[0002] In modern power electronic systems, with the increasing demands for power density, efficiency, and reliability in fields such as distributed generation, electric vehicles, energy storage systems, and electric aircraft, high-frequency, high-efficiency power devices have become core components. To meet the application requirements of high current and high power, operating multiple power devices in parallel is a common technical solution to expand system capacity.

[0003] However, the parallel application of power devices faces a series of severe challenges under high-frequency switching conditions. First, due to manufacturing tolerances, packaging differences, and asymmetrical circuit layout, the parasitic parameters of each parallel device and its branches inevitably exhibit dispersion. This dispersion is amplified dramatically during high-speed switching transients, leading to significant differences in the switching speed, timing, and trajectory of each device, and consequently causing severe dynamic current imbalance. This imbalance not only causes local device overcurrent and overheating, accelerating their aging or even failure and reducing the overall system reliability, but also leads to problems such as excessive electromagnetic interference noise.

[0004] To alleviate the current sharing problem in parallel circuits, traditional methods mainly fall into two categories: The first is passive suppression methods, such as adding buffer circuits or passively reducing imbalance by precisely matching device parameters and optimizing symmetrical layouts. These methods often come at the cost of sacrificing system efficiency, increasing size and cost, and have limited effect on improving dynamic current sharing. The second approach involves optimizing the drive circuit. While traditional fixed-parameter gate drives are simple and reliable, their switching characteristics are preset and unchangeable, making them unable to cope with dynamic current imbalance caused by load, temperature changes, and device parameter variations. Furthermore, they cannot achieve an adaptive balance between suppressing voltage overshoot oscillations and optimizing switching losses / electromagnetic interference.

[0005] Against this backdrop, active gate drive (AGD) technology has emerged as a cutting-edge approach to resolving the aforementioned contradictions. AGD technology actively shapes the switching trajectory by dynamically adjusting the gate signal of the drive circuit during the switching process of power devices, such as changing the drive resistance, current, or voltage, and controlling the charging and discharging rate of the gate capacitor. Currently, AGD structures mainly include variable resistance type, variable current type, current injection / extraction type, and variable drive voltage type. Compared with traditional fixed drives, AGD has the potential to dynamically adjust the switching rate, delay, and trajectory, providing the possibility for achieving dynamic current sharing of parallel devices while optimizing switching losses and EMI performance.

[0006] Despite this, existing AGD technology still has significant shortcomings in practical applications. The core problem lies in the lack of a precise and rapid adaptive feedback adjustment mechanism. Most AGD solutions employ open-loop or fixed-mode control strategies, with adjustment parameters typically preset or calibrated based on a few operating points. However, under complex real-world conditions, the electrical characteristics of power devices, such as drain-source voltage, drain current, and junction temperature, dynamically change with load, temperature, and device aging. Simultaneously, the effects of unbalanced parasitic inductance and magnetic component interference are not static. Existing technologies cannot accurately sense and track these critical state variables in real time. Consequently, the drive circuit cannot make precise and timely closed-loop adjustments based on the actual imbalance of the channel current in parallel devices, resulting in difficulty in guaranteeing current sharing performance over a wide range of operating conditions and insufficient system robustness. Summary of the Invention

[0007] To address the problem that existing active gate drives cannot achieve accurate dynamic current sharing of parallel devices under a wide range of operating conditions, this invention aims to construct a closed-loop control system based on real-time feedback and adaptive decision-making of multiple state variables. This system uses the instantaneous differential current signals and gate voltage signals of each power device as the main feedback variables to dynamically generate and independently apply gate drive signals with optimal switching trajectories to each device, thereby achieving a fundamental shift from open-loop preset to closed-loop adaptive control.

[0008] Specifically, the present invention provides a power device self-current sharing control system, which is used to control at least two power devices connected in parallel in a parallel system. Specifically, it includes a multi-channel feedback module for acquiring differential signals characterizing the current imbalance state between each power device in real time; and a control unit for receiving the differential signals output by the multi-channel feedback module and generating a first set of control signals for controlling the power devices to turn on or off and a second set of control signals for controlling the gate voltage of the power devices.

[0009] At least one active gate drive module is connected between the control unit and the gate of each power device, for receiving the first set of control signals and the second set of control signals, and for outputting dynamically adjustable differentiated drive signals to each power device in a closed loop based on feedback from at least two gate voltages.

[0010] To reduce system cost while ensuring effective current sharing, the self-current sharing control system can employ a hybrid drive architecture. In a parallel system, one or more power devices can be selectively driven by a dynamically adjustable drive signal output from the active gate drive module, while the remaining power devices are driven using conventional fixed-parameter gate drives. By adjusting the switching trajectories of the active power devices, their current can track the current reference formed by the passive power devices, thereby achieving overall current sharing for the system. This approach is particularly suitable for applications where device parameter dispersion is low but low-cost current sharing improvement is required.

[0011] Furthermore, the aforementioned multi-channel feedback module includes a feedback circuit, which includes a differential amplifier module, a current mirror circuit, a filter circuit, and an AD sampling module. The input terminal of the differential amplifier module is connected to at least two sampled voltage signals, and its output is processed sequentially by the current mirror circuit, the filter circuit, and the AD sampling module to output a digital current monitoring signal.

[0012] Furthermore, the aforementioned active gate drive module includes an isolation drive module and a gate resistor switching circuit connected in sequence; wherein, the isolation drive module is used to receive a first set of control signals and a second set of control signals output by the control unit, and to perform isolation amplification; the gate resistor switching circuit is constructed as a controllable impedance network, which includes multiple parallel impedance branches, each impedance branch including at least one auxiliary switching transistor and at least two gate resistors.

[0013] The network is configured to receive a first set of isolated and amplified control signals and a second set of control signals, and to determine at least one currently valid branch among multiple parallel impedance branches based on the first set of control signals.

[0014] According to the second set of control signals, the conduction state of the auxiliary switch in the current effective branch is adjusted, and the equivalent output impedance of the network is dynamically adjusted, thereby adjusting the drive voltage waveform trajectory output to the gate of the power device to achieve current sharing.

[0015] Furthermore, the aforementioned auxiliary switch can be an NMOS transistor or a PMOS transistor. For controlling the power device turn-on process: when the auxiliary switch is an NMOS transistor, the direction of its gate drive current is such that it flows from the high-side current supply side of the isolation drive module to the drain of the auxiliary switch, and then from the source of the NMOS to the gate of the power switch. When the auxiliary switch is a PMOS transistor, the direction of its gate drive current is such that it flows from the high-side current supply side of the drive circuit to the source of the auxiliary switch, and then from the drain of the PMOS to the gate of the power switch.

[0016] Regarding the power device turn-off process: when the auxiliary switch is an NMOS transistor, the direction of its gate drive current is such that it flows from the gate of the power switch to the drain of the auxiliary switch, and then from the source of the NMOS transistor into the low-side current ground terminal of the drive circuit; when the auxiliary switch is a PMOS transistor, the direction of its gate drive current is such that it flows from the gate of the power switch to the source of the auxiliary switch, and then from the drain of the PMOS transistor into the low-side current ground terminal of the drive circuit.

[0017] Furthermore, the aforementioned multiple parallel impedance branches include at least one turn-on control branch and one turn-off control branch; the turn-on control branch is configured to be selected during the turn-on process of the power device; the turn-off control branch is configured to be selected during the turn-off process of the power device.

[0018] Furthermore, in each impedance branch, the aforementioned at least two gate resistors include a first gate resistor and a second gate resistor; one end of the first gate resistor is connected to the drain of the auxiliary switch at a common node, the common node being configured to receive sink current from the high-side current supply side of the isolation drive module and to receive the first set of control signals to control its potential; the gate of the auxiliary switch is used to receive the second set of control signals to control its switching process and switching time, thereby realizing the selection of the branch and the adjustment of the gate voltage of the power switch; the other end of the first gate resistor is connected to one end of the second gate resistor as the output of the corresponding impedance branch, and the outputs of all impedance branches are connected together to form the output of the gate resistor switching circuit and connected to the gate of the power device; the other end of the second gate resistor is connected to the source of the auxiliary switch.

[0019] The first gate resistor value is greater than or equal to twice the second gate resistor value.

[0020] The topology of the gate resistor switching circuit is scalable, and its scalability is reflected in two dimensions:

[0021] The first dimension is the vertical cascading of the drive stage: by connecting an auxiliary switching transistor in series in front of the gate resistor, the number of drive control stages is increased;

[0022] The second dimension is the lateral multiplication of drive branches: by connecting drive branches with the same parallel structure, the driving capability or configuration options can be increased;

[0023] Furthermore, each of the aforementioned controllable impedance branches includes several switch-resistor units, each of which consists of the source of an auxiliary switch transistor connected in series with one end of a gate resistor. These switch-resistor units are connected in parallel as follows: the drains of all auxiliary switch transistors are connected to a common node, and the other ends of all gate resistors are connected to the drive signal output terminal of the branch and to the gate of the power device. The common node is configured to receive sink current from the high-side current supply side of the isolation drive module and to receive the first set of control signals to control its potential. Each auxiliary switch transistor's gate constitutes an independent control terminal for receiving the second set of control signals. In this structure, the resistance values ​​of all gate resistors are close to or the same.

[0024] Furthermore, the aforementioned isolation drive module includes a main drive signal generation unit, the output of which is connected to the common drain node of all auxiliary switching transistors in the controllable impedance branch, for providing a switching command signal for the power switching device; and multiple sets of auxiliary drive units, each set corresponding to an auxiliary switching transistor, which are respectively connected to the gate of the corresponding auxiliary switching transistor, for providing independent gate control signals to select or turn off the corresponding auxiliary switching transistor.

[0025] The internal structure of the isolation drive module in this invention is not limited, and its purpose is to achieve isolation and amplification of the output signal of the control unit.

[0026] Based on the same inventive concept, this invention also discloses a power device self-current sharing control method. This method is implemented based on the aforementioned system and is equally applied to the turn-on and turn-off control processes of the power device, and includes the following steps:

[0027] Step S1: Real-time acquisition of the gate voltage signals of two parallel power devices; calculation of the voltage difference based on the gate voltage signals; and conversion of the voltage difference into a dynamic deviation current value I characterizing the current imbalance. diff And calculate their respective instantaneous current change rates dI1 / dt and dI2 / dt;

[0028] Step S2: Set the deviation current limit value I threshold Based on the preset current change rate threshold and the dynamic deviation current value and instantaneous current change rate obtained in step S1, mode decision-making and execution are performed:

[0029] First decision: If Execution mode A;

[0030] Second decision: After executing mode A, if dI1 / dt or dI2 / dt is greater than the preset current change rate threshold, then execute mode B;

[0031] Third decision: If If dI1 / dt or dI2 / dt is less than or equal to the preset current change rate threshold, then mode C is executed;

[0032] Modes A, B, and C correspond to different gate drive adjustment strategies. By adjusting the auxiliary switching transistor, the gate resistance of the power device is changed, thereby controlling its switching speed to achieve current balance.

[0033] Step S3: After executing any of the above modes, |I diff |Deviation threshold ΔI from the preset minimum current threshold min When comparing, if Once the current equalization is complete, the system enters a steady state. Then return and repeat mode C until... , where ΔI min It is a positive real number.

[0034] Furthermore, during the activation control process, the mode is executed as follows:

[0035] In mode A, the power device with a large current value is designated as the device to be suppressed, and the power device with a small current value is designated as the device to be assisted. The suppression time period T4 and the auxiliary time period T5 are calculated by sampling the dynamic gate voltage and intrinsic parameters of the power devices. During time period T4, a control signal is output to turn off the auxiliary switch transistor connected to the device to be suppressed. During time period T5, a control signal is output to turn on the auxiliary switch transistor connected to the branch of the device to be assisted.

[0036] In mode B, the power device with a large current value is selected as the device to be suppressed. The suppression time period T4 is calculated by sampling the dynamic gate voltage and intrinsic parameters of the power device. During the time period T4, the control signal for the auxiliary switch transistor to turn off the link with the device to be suppressed is output.

[0037] In mode C, power devices with high current values ​​are selected as devices for waveform optimization. For these devices, the time of Miller plateau T2 is determined by sampling the dynamic gate voltage and detecting its changes. Adjustment periods T1 and T3 are calculated based on the collected dynamic gate voltage and the intrinsic parameters of the power device. During time period T1, a control signal is output to increase the gate drive circuit impedance of the device, suppressing the rise of the gate voltage before the Miller plateau. During time period T2, a control signal is output to decrease the gate drive circuit impedance of the device, providing auxiliary adjustment of the gate voltage during the Miller plateau. During time period T3, a control signal is output to decrease the gate drive circuit impedance of the device, providing auxiliary adjustment of the gate voltage after the Miller plateau.

[0038] During a shutdown control process, modes A, B, and C are triggered based on the same decision logic, and their adjustment actions are configured to be symmetrical with the turn-on control process in order to achieve current balance or optimize the shutdown trajectory at the turn-off moment.

[0039] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0040] 1) This invention achieves an optimal balance between traditional open-loop drive and fully digital closed-loop drive by real-time acquisition of the differential current signal of the power device and applying the state feedback of the previous switching cycle to the real-time control of the current cycle. This scheme significantly reduces the transmission delay and computational complexity of the system, enabling dynamic adjustment to closely follow the switching frequency, and achieving a unity of simplicity and accuracy.

[0041] 2) By employing a direct ADC sampling scheme for the input differential current signal, combined with an adjustable gate resistor network for the auxiliary switching transistor, the system constructs a high-bandwidth, low-delay signal reception and transmission path. After the controller detects the current imbalance through the feedback circuit, it can quickly convert it into a drive signal for fine-tuning the gate voltage of the power device, thereby controlling the switching trajectory of the power device and consequently controlling the channel current variation.

[0042] 3) Based on the above hardware and software co-design, it is not a single-point improvement, but a comprehensive optimization at the system level: effectively improving the dynamic and static current sharing effect of parallel devices and improving system reliability; significantly reducing voltage and current overshoot and oscillation during switching; and providing effective control means to achieve a better trade-off between switching losses and electromagnetic interference. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of the power device self-current sharing control system in the parallel system of the present invention;

[0044] Figure 2 This is a circuit diagram of the power device self-current sharing control system in Example 1;

[0045] Figure 3 This is a schematic diagram of the gate resistance switching circuit in the active gate drive module circuit of Embodiment 2;

[0046] Figure 4 This is a schematic diagram of the gate resistance switching circuit in the active gate drive module circuit of Embodiment 3;

[0047] Figure 5 This is a schematic diagram of the connection between the power device and the gate resistor switching circuit in Example 4;

[0048] Figure 6 This is a schematic diagram of the feedback circuit in this invention;

[0049] Figure 7 This is a schematic diagram of the differential amplifier module circuit in the feedback circuit of this invention;

[0050] Figure 8 This is a flowchart of the power device self-current sharing control method in the parallel system of the present invention;

[0051] Figure 9 This is the timing diagram of the gate resistor adaptive switching based on current comparison in the control method of the present invention;

[0052] in, Figure 9 (a) is a timing diagram showing the differentiated switching of gate resistance in mode A and mode B;

[0053] Figure 9 (b) is the timing diagram of the differentiated switching of the gate resistance in mode A;

[0054] Figure 9 (c) is the timing diagram of the differential switching of gate resistance under mode B and mode C;

[0055] Figure 9 (d) is the timing diagram of the gate resistor switching from a parallel resistance value to a single resistance value in Mode C; Figure 9 (e) is a timing diagram showing the gate resistor switching twice between a single resistance value and a parallel resistance value in Mode C. Figure 9 (f) is the timing diagram of the gate resistor switching from a single resistance value to a parallel resistance value in Mode C;

[0056] Figure 10 This is a diagram showing the current sharing effect of the parallel power devices of this invention after being adjusted by different control modes. Detailed Implementation

[0057] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0058] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0059] like Figure 1 As shown, the present invention discloses a self-current sharing control system for power devices. This system can be applied to the current sharing control of at least two power devices in a parallel system. In the following embodiments, two power switching transistors Q1 and Q2 are used as examples.

[0060] The system includes a multi-channel feedback module 002, which is used to acquire differential signals that characterize the current imbalance state between power devices in real time; the acquired differential signals are processed by a sampling filter and then sent to the control unit; the control unit FPGA is used to receive the differential signals output by the multi-channel feedback module and generate a first set of control signals for controlling the power devices to turn on or off and a second set of control signals for controlling the gate voltage of the power devices.

[0061] At least one active gate drive module 001 is connected between the control unit FPGA and the gates of each power device. It is used to receive the first set of control signals and the second set of control signals, and to obtain feedback of at least two gate voltages based on the sampling and filtering module set between the multi-channel feedback module and the FPGA. It then outputs a dynamically adjustable differentiated drive signal to each power device in a closed loop.

[0062] Example 1

[0063] like Figure 2 As shown, the active gate drive module 001 includes an isolation drive module 02 and a gate resistance switching circuit 01 connected in sequence. The isolation drive module 02 includes a first set of control signals B0, B1, B2, B3 and a second set of control signals A0, A1, A2, A3 output by the FPGA, and implements voltage isolation and current signal amplification functions. The gate resistance switching circuit is constructed as a controllable impedance network, which includes four parallel impedance branches for controlling the power switches Q1 and Q2 to turn on and off. This network is configured to receive the isolated and amplified first and second set of control signals, and determine at least one currently valid branch among the four parallel impedance branches based on the first set of control signals.

[0064] According to the second set of control signals, the conduction state of the auxiliary switch in the currently effective branch is adjusted, and the equivalent output impedance of the network is dynamically adjusted, thereby adjusting the drive voltage waveform trajectory output to the gate of the power device to achieve current sharing; the four parallel impedance branches include two turn-on control branches and two turn-off control branches; the turn-on control branches are configured to be selected during the turn-on process of the power device; the turn-off control branches are configured to be selected during the turn-off process of the power device.

[0065] The system adopts an architecture in which an FPGA and a dedicated PWM controller work together. The FPGA is configured with PWM1, PWM2, PWM3 and PWM4 controllers through a four-wire digital interface. The latter then generates two sets of PWM signals A0-A3 and B0-B3, for a total of eight signals, which are output through its output ports OUTPUT1-OUTPUT4.

[0066] The isolation drive module includes a first DC-DC isolated power supply module 410 and a second DC-DC isolated power supply module 450; four isolation modules for controlling power switching transistor Q1: a first isolation module 411, a second isolation module 421, a third isolation module 431, and a fourth isolation module 441; four isolation modules for controlling power switching transistor Q2: a fifth isolation module 451, a sixth isolation module 461, a seventh isolation module 471, and an eighth isolation module 481; and corresponding four output amplifier modules for controlling power switching transistor Q1: a first amplifier module 412, a second amplifier module 422, a third amplifier module 432, and a fourth amplifier module 442; and four output amplifier modules for controlling power switching transistor Q2: a fifth amplifier module 452, a sixth amplifier module 462, a seventh amplifier module 472, and an eighth amplifier module 482.

[0067] The first amplification module 412 and the second amplification module 422 are respectively connected to the first isolation module 411 and the second isolation module 421; the third amplification module 432 and the fourth amplification module 442 are respectively connected to the third isolation module 431 and the fourth isolation module 441. The first isolation module 411 and the second isolation module 421 are respectively connected to A0 and B0 output from OUTPUT1; the third isolation module 431 and the fourth isolation module 441 are respectively connected to A1 and B1 output from OUTPUT2, and are connected together with the first DC-DC isolated power supply module 410.

[0068] The fifth amplification module 452 and the sixth amplification module 462 are respectively connected to the fifth isolation module 451 and the sixth isolation module 461; the seventh amplification module 472 and the eighth amplification module 482 are respectively connected to the seventh isolation module 471 and the eighth isolation module 481. The fifth isolation module 451 and the sixth isolation module 461 are respectively connected to A2 and B2 of the OUTPUT3 output; the seventh isolation module 471 and the eighth isolation module 481 are respectively connected to A3 and B3 of the OUTPUT4 output, and are connected together with the second DC-DC isolated power supply module 450.

[0069] The impedance branch controlling the turn-on of power switch Q1 includes the first auxiliary switch S0 and the first turn-on gate resistor R. g_on_1 Second gate resistance R g_on_2； The impedance branch controlling the turn-off of power switch Q1 includes the second auxiliary switch S1 and the first gate-off resistor R. g_off_1 Second gate shut-off resistor R g_off_2 ； The impedance branch controlling the turn-on of power switch Q2 includes the third auxiliary switch S2 and the third turn-on gate resistor R. g_on_3 and the fourth gate resistor R g_on_4； The impedance branch controlling the turn-off of power switch Q2 includes the fourth auxiliary switch S3, the third gate resistor, and the gate resistor R. g_off_3and the fourth gate shut-off resistor R g_off_4 ；

[0070] The gate control terminal of the first auxiliary switch S0 is connected to the first amplification module 412; the drain is connected to the first gate-on resistor R. g_on_1 One end is connected to and connected to the second amplification module 422, and the first turn-on gate resistor R g_on_1 The other end is connected to the second gate resistor R g_on_2 One end is connected as the output terminal of the first impedance branch; the second turn-on gate resistor R g_on_2 The other end is connected to the source of the first auxiliary switch S0;

[0071] The gate control terminal of the second auxiliary switch S1 is connected to the third amplification module 432; the drain is connected to the first gate shut-off resistor R. g_off_1 One end is connected to the fourth amplification module 442, and the first shut-off gate resistor R g_off_1 The other end is connected to the second gate shut-off resistor R g_off_2 One end is connected as the output terminal of the second impedance branch; the second gate shut-off resistor R g_off_2 The other end is connected to the source of the second auxiliary switch S1;

[0072] The gate control terminal of the third auxiliary switch S2 is connected to the fifth amplification module 452; the drain is connected to the fourth gate-on resistor R. g_on_4 One end is connected to the sixth amplification module 462, and the fourth turn-on gate resistor R g_on_4 The other end is connected to the third gate resistor R g_on_3 One end is connected as the output terminal of the third impedance branch; the third turn-on gate resistor R g_on_3 The other end is connected to the source of the third auxiliary switch S2;

[0073] The gate control terminal of the fourth auxiliary switch S3 is connected to the seventh amplifier module 472; the drain is connected to the fourth gate shut-off resistor R. g_off_4 One end is connected to the eighth amplifier module 482, and the fourth gate shut-off resistor R. g_off_4 The other end is connected to the third gate shut-off resistor R g_off_3 One end is connected as the output terminal of the fourth impedance branch; the third gate shut-off resistor R g_off_3 The other end is connected to the source of the fourth auxiliary switch S3;

[0074] The output terminals of the first impedance branch and the second impedance branch are connected to the gate of the power switch Q1; the output terminals of the third impedance branch and the fourth impedance branch are connected to the gate of the power switch Q2.

[0075] Figure 2The auxiliary switch shown is a PMOS transistor. In practical applications, either an NMOS transistor or a PMOS transistor can be used as the auxiliary switch. For controlling the power device turn-on process: when the auxiliary switch is an NMOS transistor, the direction of its gate drive current is such that it flows from the high-side current supply side of the isolation drive module to the drain of the auxiliary switch, and then from the source of the NMOS transistor to the gate of the power switch. When the auxiliary switch is a PMOS transistor, the direction of its gate drive current is such that it flows from the high-side current supply side of the drive circuit to the source of the auxiliary switch, and then from the drain of the PMOS transistor to the gate of the power switch.

[0076] Regarding the power device turn-off process: when the auxiliary switch is an NMOS transistor, the direction of its gate drive current is such that it flows from the gate of the power switch to the drain of the auxiliary switch, and then from the source of the NMOS transistor into the low-side current ground terminal of the drive circuit; when the auxiliary switch is a PMOS transistor, the direction of its gate drive current is such that it flows from the gate of the power switch to the source of the auxiliary switch, and then from the drain of the PMOS transistor into the low-side current ground terminal of the drive circuit.

[0077] In this invention, the topology of the gate resistor switching circuit is scalable, and its scalability is reflected in two dimensions:

[0078] The first dimension is the vertical cascading of the drive stage: by connecting an auxiliary switching transistor in series in front of the gate resistor, the number of drive control stages is increased;

[0079] The second dimension is the lateral multiplication of drive branches: by connecting drive branches with the same parallel structure, the driving capability or configuration options can be increased;

[0080] Furthermore, different circuit structures of the gate resistor switching circuit are described in detail through Examples 2 and 3.

[0081] Example 2

[0082] like Figure 3 As shown, in the gate resistance switching circuit 01, while keeping the structure of a single impedance branch unchanged, the current sharing effect can be optimized by increasing the number of impedance branches. The number of auxiliary switching transistors can be any number of S0-S0. m Where m is an even number, for power switch Q1, the number of auxiliary switching units used to control the gate voltage turn-on and gate voltage turn-off processes is m / 2; for power switch Q2, the number of auxiliary switching units used to control the gate voltage turn-on and gate voltage turn-off processes is also m / 2; for a single impedance branch, R g2 ≥2R g1 The control unit and isolation drive module here should output the first set of control signals and the second set of control signals corresponding to the number of impedance branches.

[0083] Example 3

[0084] like Figure 4 As shown, the gate resistor switching circuit 01 maintains four impedance branches. The internal structure of each impedance branch is adjusted to optimize current sharing. The source of an auxiliary switch is connected in series with one end of a gate resistor to form a switch-resistor unit. For each impedance branch, at least one parallel switch-resistor unit can be added. For example... Figure 4 In the example of a turn-on control branch, the source of an auxiliary switch is connected to the first turn-on gate resistor R. g_on_1 One end is connected; the first gate resistor R g_on_1 The other end is connected to the second gate resistor R g_on_2 One end is connected as the output terminal of this branch; the source of the other auxiliary switch is connected to the second gate-on resistor R. g_on_2 The other end is connected; the drains of the two auxiliary switching transistors are connected and receive the first set of control signals; the gates of the two auxiliary switching transistors respectively receive different second set of control signals; the first gate-on resistor R here g_on_1 Second gate resistance R g_on_2 The resistance values ​​are close to or the same;

[0085] Furthermore, it should be noted that the gate resistance switching circuit of the present invention is not limited to the above-described invention. Figure 2 , Figure 3 and Figure 4 The specific embodiments shown are as follows. Any obvious modifications, equivalent substitutions, or structural variations made by those skilled in the art based on their understanding of the core concept of this invention to achieve the same or similar functions should be considered to fall within the protection scope of the claims of this invention.

[0086] To reduce system cost while ensuring effective current sharing, the self-current sharing control system can employ a hybrid drive architecture. In the parallel system, a dynamically adjustable drive signal output from the active gate drive module can be selectively applied to one or more power devices.

[0087] Example 4

[0088] like Figure 5 As shown, the above-described control structure is used only for power switch Q2, while Q1 uses a conventional fixed-parameter gate drive. The number of auxiliary switch units used to control the gate voltage turn-on and gate voltage turn-off processes can be increased or decreased as needed. In this connection configuration, R in the figure... g2 The resistance should be greater than or equal to 2R. g1 Furthermore, all NMOS auxiliary switches can be equivalently replaced by PMOS, provided that the gate current flow direction is correct.

[0089] In addition, the multi-channel feedback module of the present invention includes a feedback circuit, such as Figure 6 As shown, the feedback circuit includes a differential amplifier module 021, a current mirror circuit 022, a filter circuit 023, and an AD sampling module 024. The input terminal of the differential amplifier module 021 is connected to at least two sampling voltage signals, and its output is processed sequentially by the current mirror circuit 022, the filter circuit 023, and the AD sampling module 024 to output a digital current monitoring signal.

[0090] like Figure 7 As shown, the differential amplifier module 021 includes a balancing resistor 210, a first differential input resistor 211, a second differential input resistor 212, a differential feedback resistor 213, a first resistor 214, a capacitor 215, a compensation capacitor 216, an NMOS transistor 217, a source resistor 218, and an operational amplifier 21. The balancing resistor 210, the first differential input resistor 211, and the second differential input resistor 212 are used to control the offset current, reduce the offset voltage, and achieve impedance matching between the preceding and following stages. The first resistor 214 and the capacitor 215 form an RC frequency selection circuit at the non-inverting input terminal to achieve low-pass filtering and prevent interference from high-frequency common-mode spurious signals. The differential feedback resistor 213 and the compensation capacitor 216 form an operational amplifier feedback compensation network to stabilize the common-mode potential, compensate for phase lag, and limit bandwidth. The NMOS transistor 217 is used to output the signal V from the operational amplifier 21. out The amplification is achieved by connecting the source of the transistor to the source resistor 218, which stabilizes the bias voltage. The drain of the NMOS transistor 217 is connected to the input of the next stage differential current mirror.

[0091] like Figure 6 As shown, the IN+ and IN- inputs of operational amplifier 21 are connected to the two source outputs of the parallel power device, respectively, and the OUT terminal of operational amplifier 21 is connected to the input terminal of the next stage. The current mirror circuit 022 consists of a second resistor 220, a third resistor 230, and two PMOS transistors 221 and 222 with identical parameters and symmetrical connections.

[0092] The filter circuit 023 consists of a third differential input resistor 231, a fourth differential input resistor 237, an output feedback resistor 234, an input capacitor 232, a feedback capacitor 233, a filter capacitor 236, a differential operational amplifier 235, and an input reference voltage V. ref Together they constitute.

[0093] In this configuration, the gates of the first PMOS transistor 221 and the second PMOS transistor 222 are connected to the OUT terminal of the operational amplifier 21. The drains of the first PMOS transistor 221 and the second PMOS transistor 222 are connected together. The source of the first PMOS transistor 221 is connected to one end of the second resistor 220, and the other end of the second resistor 220 is grounded. The source of the second PMOS transistor 222 is connected to one end of the third resistor 230 and the differential input resistor 231, and the other end of the third resistor 230 is grounded. The other end of the third differential input resistor 231 is connected to one end of the input capacitor 232 and the feedback capacitor 233; the other end of the input capacitor 232 is connected to the IN- input terminal of the differential operational amplifier 235 and one end of the output feedback resistor 234; the other end of the feedback capacitor 233 is connected to the other end of the output feedback resistor 234, the output terminal of the differential operational amplifier 235, and the input terminal of the next-stage ADC 238; the IN+ input terminal of the differential operational amplifier 235 is connected to the input reference voltage V. ref One end of the fourth differential input resistor 237 and the filter capacitor 236 are connected, the other end of the fourth differential input resistor 237 is connected to ground, the other end of the filter capacitor 236 is connected to the output of the differential operational amplifier 235, and finally the output of the ADC238 outputs the FPGA input parameter V. diff .

[0094] Based on the above system and circuit structure, this invention also discloses a power device self-current sharing control method. This method is used to control at least two parallel power devices in a parallel system. The method is equally applied to the turn-on and turn-off control processes of the power devices. The following embodiment uses the turn-on control process of two power switches as an example. Figure 8 As shown, to initialize the ADC and FPGA, first determine the upper limit V of the power supply level of the gate drive signals for the rated currents I, Q1, and Q2 according to the design requirements. DD and lower limit V EE Then, by reading the datasheet of the power switch transistor, Q is given. g1 Q g2 C iss g fs Assign values, and assign values ​​to I and V according to the experimental design goals. ref Assign a value to T. Simultaneously set the deviation current limit I. threshold and ΔI min With real-time V diff V G1 and V G2 The signal is input to the FPGA through the feedback circuit, and the preliminary parameter V is calculated. g_T1 V g_T2 I g_on1 I g_on2Then, T1, T2, T3, T4, T5, as well as dI1 / dt, dI2 / dt, and dI / dT1 are further calculated for subsequent calculations corresponding to the lookup table.

[0095] The following describes in detail the mode judgment and switching methods for feedback values ​​in FPGA. The system uses V... diff The values ​​of V are used to determine the magnitudes of I1 and I2. diff If I > 0, then I2 > I1. When the FPGA initially detects |I diff |>I threshold At that time, based on the lookup table of the corresponding time and current relationship, the FPGA outputs Mode A for T1 and T2. Further, if |I... diff | threshold When dI1 / dt or dI2 / dt > 110%dI / dT1, the FPGA output executes Mode B for Q2 / Q1; when dI1 / dt or dI2 / dt > 110%dI / dT1, the FPGA output executes Mode C for T2 / T1. In all three modes, it is necessary to finally determine |I diff Is it less than ΔI? min If the judgment result is yes, then the flow sharing is completed; if the judgment result is no, then the previous execution operation regarding Mode C is returned.

[0096] The specific process is as follows: The current difference V between the two power switching transistors... diff Sample and according to the reference voltage V ref V diff Converted to dynamic deviation current value I diff Simultaneously, the gate voltage signal V of the two parallel switching transistors... G1 (t) and V G2 (t) Perform ADC signal acquisition, without considering the delay of the control and drive circuits. Two V channels G (t) can be calculated using formulas (1) and (2):

[0097] (1)

[0098] (2)

[0099] If the first auxiliary switch S0 is open in the initial state, then τ1=C iss ×R g_on1 The gate voltage sampling module includes, but is not limited to, using resistor voltage dividers to acquire gate voltage signal values ​​that satisfy the ADC voltage input range. Update dynamic deviation current value I. diff Set the maximum update step size t d_max ​=100ns, the conversion time is calculated in the FPGA according to the minimum unit time step setting formula, Δt=t-5ns. The signal sampling formula is set as follows: where n is the sampling rate of the ADC, Vref is the internal reference voltage of the ADC, formulas (3) and (4) are Vg_Q1(t) and Vg_Q2(t) are the gate voltages of the two power switches Q1 and Q2 that have been collected, and formulas (5) and (6) are Vdiff acquisition conversion and Idiff calculation:

[0100] (3)

[0101] (4)

[0102] (5)

[0103] (6)

[0104] Set the deviation current limit value Isthreshold = 10%I, and the deviation current judgment minimum value ΔImin = 2%I. Pre-calculate the initial parameter values ​​in the FPGA, specifically including the effective values ​​of the gate voltages sampled by the parallel power switches Q1 and Q2. and As shown in equations (7) and (8), T is the time it takes for the overall gate signal to rise from the threshold to the point where the driving voltage stabilizes. After the third auxiliary switch S2 is closed, the gate current I of the power switch Q2... g_on_Q2_1 Before the third auxiliary transistor S2 is closed, the gate current I of the power switch Q2 is... g_on_Q2_2 As shown in equations (9) and (10); after the first auxiliary switch S0 is closed, the gate current I of the power switch Q1 is... g_on_Q1_1 Before the first auxiliary switch S0 is closed, the gate current I of the power switch Q1 is... g_on_Q1_2 As shown in equations (11) and (12); where V CC Provides the high-side power supply level for the output of the driver chip.

[0105] (7)

[0106] (8)

[0107] (9)

[0108] (10)

[0109] (11)

[0110] (12)

[0111] When V g_Q1 and V g_Q2 After reaching the threshold voltage, the channel currents I1 and I2 of the two parallel devices begin to rise. At this time, dI / dt can be controlled by the input capacitance C of the power device. iss and transconductance g fs Calculate according to formulas (13) and (14). Further, by controlling I... g_on_Q2_1 and I g_on_Q1_1 This directly affects the rise time of the channel current. By controlling the auxiliary transistor switch to switch the gate resistance using the FPGA and driving this stage with a high gate current, channel turn-on can be accelerated and switching losses reduced.

[0112] (13)

[0113] (14)

[0114] The three modes are divided according to the start time of Q1 and Q2, such as Figure 9 As shown, specifically:

[0115] like Figure 9 (a) indicates that when I2>I1, the gate resistor of power transistor Q2 switches to R in Mode A and Mode B. g_on_1 And continue for the T4 time span;

[0116] like Figure 9 (b) indicates that when I2>I1, the gate resistor of power transistor Q1 switches to R in Mode A. g_on_1 / / R g_on_2 And it continues for a time span of T5;

[0117] like Figure 9 (c) indicates that in Mode B and Mode C, the gate resistance of the power transistor with relatively small current remains unchanged;

[0118] like Figure 9 (d) indicates that when I2>I1, the gate resistance of power transistor Q2 in Mode C is changed by R. g_on_1 / / R g_on_2 Switch to R g_on_1 And continue for the T1 time span;

[0119] like Figure 9 (e) indicates that when I2>I1, the gate resistance of power transistor Q2 in Mode C is changed by R. g_on_1 Switch to R g_on_1 / / R g_on_2 And continue for the T2 time span, then switch to R. g_on1 ;

[0120] Figure 9 (f) indicates that when I2>I1, the gate resistance of power transistor Q2 in Mode C is changed by R. g_on_1 Switch to R g_on_1 / / R g_on_2 And it continues for a time span of T3; the following is a description of the three modes: Mode A: When the FPGA detects |I diff |>I threshold If at this time I diff If the signal is positive, the FPGA outputs signal A2 low, controlling the third auxiliary transistor S2 to turn off within time T4; simultaneously, it outputs signal A0 high, controlling the first auxiliary transistor S0 to turn on within time T5. Meanwhile, the drive signals B0 and B2 for power switches Q1 and Q2 maintain their original control methods. This increases the gate resistance of power switch Q2, reducing the gate drive current and suppressing the excessively rapid increase in Q2's channel current; it also accelerates the current increase through power switch Q1, gradually achieving a current-sharing effect.

[0121] Mode B: When the FPGA detects |I diff |>I threshold When, and dI1 / dt or dI2 / dt > 110%dI / dT1, if at this time I diff If positive, the FPGA outputs only the A2 signal as low, controlling the auxiliary transistor S2 to turn off within the T4 time range; at the same time, the drive signals B0 and B2 of the power switches Q1 and Q2 maintain the original signal control mode, and further achieve the current sharing effect.

[0122] Mode C: When the FPGA detects |I diff | threshold When, and dI1 / dt or dI2 / dt < 110%dI / dT1, if at this time I diff If the value is positive, the FPGA outputs a low signal A2 during time period T1, controlling the auxiliary transistor S2 to turn off within time period T1; then, during time periods T2 and T3, it outputs a high signal A2, controlling the auxiliary transistor S2 to turn on within time periods T2 and T3. Simultaneously, the drive signals B0 and B2 for the power switches Q1 and Q2 maintain their original signal control methods, ultimately achieving current sharing.

[0123] Furthermore, the operating time of each mode needs to be determined in the FPGA by relating the feedback values ​​to the functional relationships established through the model. A lookup table approach is used to first determine the time scale corresponding to the switching of the auxiliary switching transistor in each mode.

[0124] Specifically, for Mode C, T1 is calculated as shown in formula (15), where Q g1 ​The value of Q needs to be obtained from the gate charge curve of the power device under test. Simply find the gate voltage at which the vertical axis reaches the Miller plateau to calibrate Q. g1 Furthermore, T2 is obtained in units of time Δt by calculating the difference ΔV in the gate voltage sampled by the ADC before and after Δt. If until t... d_max If the value is still 0, then record the corresponding time value of the unchanged gate voltage as T2. Further, calculate T3 as shown in formulas (16) and (17), where formula (16) is Q. g1 With Q g2 Quantitative calculation relationship, Q g2 Q represents the amount of gate charge at the moment when the corresponding device reaches its maximum drive gate voltage. g1 With Q g2 All of these can be obtained directly from the datasheet of the corresponding power device model.

[0125] In Mode B, the gate resistor of Q2 is switched to R. g_on_1 Then T4 is calculated as shown in formula (18). For Mode A, since the gate resistance of Q1 is switched to R... g_on_1 / / R g_on_2 Then T5 is calculated as shown in formula (19). The calculated result is then stored in the FPGA, and the corresponding switching time value can be quickly found based on the feedback current value when in use.

[0126] In this invention, the time output by the FPGA based on the voltage feedback values ​​during the Q1 and Q2 turn-on phases is denoted as T. m (m=1, 2, 3, 4, 5), where T1 is the gate voltage V in Mode C. GS The rise time required is controlled before the Miller platform, and T2 is the gate voltage V in ModeC mode. GS The required duration on the Miller platform, T3 is the gate voltage V in Mode C. GS The rise time is controlled after the Miller plateau. T4 is the rise time of the entire gate voltage of Q2 in Mode B, and T5 is the rise time of the entire gate voltage of Q1 in Mode A.

[0127] (15)

[0128] (16)

[0129] (17)

[0130] (18)

[0131] (19)

[0132] Overall, the voltage difference signal V output by the FPGA through the feedback circuit... diff After employing a pre-defined current-sharing control calculation method, the data control flow for A0, A1, A2, A3, and B0, B1, B2, B3 is obtained. This data then controls the auxiliary switches to adjust their gate resistances and the gate waveform trajectories of the parallel devices. If these values ​​exceed preset values, the FPGA controls the auxiliary switches S0-S3 to perform logic inversion. The output potentials A0-A3 and B0-B3 during this process are determined based on the delay and current difference of the parallel devices. Finally, the switching times of each switching mode are updated, generating the drive signal for the next switching cycle. This process is repeated until current sharing is complete. This method is simple in design, requiring only the judgment of the difference signal, without excessive time complexity, and can quickly respond to changes in channel current.

[0133] It should be noted here that if adopted Figure 5 When only one power switch is controlled, Mode A cannot be triggered; only Mode B or Mode C can be used for current sharing.

[0134] In a turn-off control process, the triggering of Modes A, B, and C follows the same decision logic as the aforementioned turn-on control process. However, their specific adjustment actions, such as the switching strategy and timing of the gate resistor, are configured to be symmetrical to the turn-on process actions but adapted to the target, i.e., performing opposite or complementary adjustments to achieve current balance at the turn-off moment or optimize the turn-off trajectory. Based on the detailed disclosure of the above-described turn-on control process, those skilled in the art can directly understand or deduce the corresponding turn-off control process through adaptive adjustments.

[0135] To further demonstrate the current sharing effect of the parallel power devices of the present invention, such as Figure 10 As shown, when I2 > I1, the FPGA first controls the power transistor Q2 to enter Mode A state and adjusts V by outputting a pair of control signals A2 and B2 from PWM3. GS A2 turns on before the gate voltage rises to the threshold voltage and then remains off until the gate voltage reaches its maximum. Similarly, A3 remains off during the turn-off process. Simultaneously, in Mode A, the FPGA outputs a pair of control signals A0 and B0 to PWM1, keeping A0 constant at 1 and B0 unchanged, thus controlling power transistor Q1 and adjusting V. GSThis achieves the goal of decreasing I2 and increasing I1. Further, the FPGA controls power transistor Q2 to enter Mode B, with the same control signal method as Mode A, while maintaining the same control method for Q1. Then, the FPGA controls power transistor Q2 to enter Mode C, where A2 first switches to 0 for T1, then switches to 1 for T2, and maintains this state for T3; the turn-off process is similar. Through the above signal control process, I1 and I2 are ultimately balanced.

[0136] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications without departing from the spirit and scope of the invention.

Claims

1. A power device self-current sharing control system, the system being used to control at least two power devices connected in parallel in a parallel system, characterized in that, Specifically, it includes a multi-channel feedback module for acquiring differential signals characterizing the current imbalance state between power devices in real time; and a control unit for receiving the differential signals output by the multi-channel feedback module and generating a first set of control signals for controlling the power devices to turn on or off and a second set of control signals for controlling the gate voltage of the power devices. At least one active gate drive module is connected between the control unit and the gate of each power device, for receiving the first set of control signals and the second set of control signals, and for outputting dynamically adjustable differentiated drive signals to each power device in a closed loop based on feedback from at least two gate voltages.

2. The power device self-current sharing control system according to claim 1, characterized in that, The multi-channel feedback module includes a feedback circuit, which includes a differential amplifier module, a current mirror circuit, a filter circuit, and an AD sampling module. The input of the differential amplifier module is connected to at least two sampled voltage signals, and its output is sequentially passed through the current mirror circuit and the filter circuit to receive analog voltage signals. The AD sampling module then converts the analog signals into discrete current monitoring signals.

3. The power device self-current sharing control system according to claim 1, characterized in that, The active gate drive module includes an isolation drive module and a gate resistor switching circuit connected in sequence; wherein, the isolation drive module is used to receive a first set of control signals and a second set of control signals output by the control unit, and realizes the functions of voltage isolation and drive current amplification; the gate resistor switching circuit is constructed as a controllable impedance network, which includes multiple parallel impedance branches, each impedance branch including at least one auxiliary switching transistor and at least two gate resistors. The network is configured to receive a first set of isolated and amplified control signals and a second set of control signals, and to determine at least one currently valid branch among multiple parallel impedance branches based on the first set of control signals. According to the second set of control signals, the conduction state of the auxiliary switch in the current effective branch is adjusted, and the equivalent output impedance of the network is dynamically adjusted, thereby adjusting the drive voltage waveform trajectory output to the gate of the power device to achieve current sharing.

4. The power device self-current sharing control system according to claim 3, characterized in that, The plurality of parallel impedance branches include at least one turn-on control branch and one turn-off control branch; the turn-on control branch is configured to be selected during the turn-on process of the power device; The shutdown control branch is configured to be activated during the shutdown process of the power device.

5. The power device self-current sharing control system according to claim 3, characterized in that, In each impedance branch, the at least two gate resistors include a first gate resistor and a second gate resistor; one end of the first gate resistor is connected to the drain of the auxiliary switch at a common node, the common node being configured to receive sink current from the high-side current supply side of the isolation drive module and to receive the first set of control signals to control its potential. The gate of the auxiliary switch is used to receive the second set of control signals to control its switching process and switching time; The other end of the first gate resistor is connected to one end of the second gate resistor to serve as the output of the corresponding impedance branch. The output ends of all impedance branches are connected together to form the output end of the gate resistor switching circuit and are connected to the gate of the power device. The other end of the second gate resistor is connected to the source of the auxiliary switch.

6. The power device self-current sharing control system according to claim 5, characterized in that, The first gate resistor value is greater than or equal to twice the second gate resistor value.

7. The power device self-current sharing control system according to claim 3, characterized in that, Each of the controllable impedance branches includes several switch-resistor units, each of which consists of the source of an auxiliary switch transistor connected in series with one end of a gate resistor. The several switch-resistor units are connected in parallel as follows: the drains of all auxiliary switches are connected to a common node, and the other ends of all gate resistors are connected to the drive signal output terminal of the branch and connected to the gate of the power device. The common node is configured to receive sink current from the high-side current supply side of the isolation drive module and to receive the first set of control signals to control its potential. The gate of each auxiliary switch transistor constitutes an independent control terminal for receiving the second set of control signals respectively.

8. The power device self-current sharing control system according to claim 3, characterized in that, The isolation drive module includes a main drive signal generation unit, whose output terminal is connected to the common drain node of all auxiliary switching transistors in the controllable impedance branch, for providing a switching command signal for the power switching device; each of the multiple auxiliary drive units corresponds to an auxiliary switching transistor and is connected to the gate of the corresponding auxiliary switching transistor, for providing an independent gate control signal to select or turn off the corresponding auxiliary switching transistor.

9. A self-current sharing control method for power devices, characterized in that, This method is implemented based on the system described in any one of claims 1-8. The method is equally applied to the turn-on and turn-off control processes of power devices, and includes the following steps: Step S1: Real-time acquisition of the gate voltage signals of the two parallel power devices, and calculation of their voltages based on the gate voltage signals. The voltage difference is then converted into a dynamic deviation current value characterizing the current imbalance. And calculate their respective instantaneous current change rates dI1 / dt and dI2 / dt; Step S2: Set the deviation current limit value I threshold And a preset current change rate threshold, and based on the results obtained in step S1 Dynamic deviation current value and instantaneous rate of change of current are used for mode decision-making and execution: First decision: If Execution mode A; Second decision: After executing mode A, if dI1 / dt or dI2 / dt is greater than the preset current change rate threshold, then execute mode A. Formula B; Third decision: If If dI1 / dt or dI2 / dt is less than or equal to the preset current change rate threshold, then the mode is executed. Formula C; Modes A, B, and C correspond to different gate drive adjustment strategies. By adjusting the auxiliary switching transistor, the gate resistance of the power device is changed, thereby controlling its switching speed to achieve current balance. Step S3: After executing any of the above modes, Compare with the preset minimum current deviation threshold ΔImin, if Once the current equalization is complete, the system enters a steady state. Then return and repeat mode C until... .

10. The power device self-current sharing control method according to claim 9, characterized in that, During the activation control process, the mode is executed as follows: In mode A, the power device with a large current value is designated as the device to be suppressed, and the power device with a small current value is designated as the device to be assisted. The suppression time period T4 and the auxiliary time period T5 are calculated by sampling the dynamic gate voltage and intrinsic parameters of the power devices. During time period T4, a control signal is output to turn off the auxiliary switch transistor connected to the device to be suppressed. During time period T5, a control signal is output to turn on the auxiliary switch transistor connected to the branch of the device to be assisted. In mode B, the power device with a large current value is selected as the device to be suppressed. The suppression time period T4 is calculated by sampling the dynamic gate voltage and intrinsic parameters of the power device. During the time period T4, the control signal for the auxiliary switch transistor to turn off the link with the device to be suppressed is output. In mode C, power devices with high current values ​​are selected as devices for waveform optimization. For these devices, the time of Miller plateau T2 is determined by sampling the dynamic gate voltage and detecting its changes. Adjustment periods T1 and T3 are calculated based on the collected dynamic gate voltage and the intrinsic parameters of the power device. During time period T1, a control signal is output to increase the gate drive circuit impedance of the device, suppressing the rise of the gate voltage before the Miller plateau. During time period T2, a control signal is output to decrease the gate drive circuit impedance of the device, providing auxiliary adjustment to the gate voltage during the Miller plateau. During time period T3, a control signal is output to decrease the gate drive circuit impedance of the device, providing auxiliary adjustment to the rise of the gate voltage after the Miller plateau. During a shutdown control process, modes A, B, and C are triggered based on the same decision logic, and their adjustment actions are configured to be symmetrical with the turn-on control process in order to achieve current balance or optimize the shutdown trajectory at the turn-off moment.

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