Spread spectrum phase-locked loop control circuit and control method thereof, and processor chip

Abstract

The application provides a spread spectrum phase-locked loop control circuit and a control method thereof and a processor chip, and relates to the technical field of electronic circuits.The spread spectrum phase-locked loop control circuit comprises a spread spectrum modulation sub-module, a reference clock delay sub-module and a feedback sub-module; the spread spectrum modulation sub-module is connected with the feedback sub-module and the reference clock delay sub-module; the spread spectrum modulation sub-module generates a first adjustment signal, a second adjustment signal and a frequency division control signal based on a frequency division ratio signal; the feedback sub-module generates a modulated feedback clock based on the first adjustment signal, the frequency division control signal and a feedback clock; the reference clock delay sub-module generates a modulated reference clock based on the second adjustment signal and a reference clock; the second adjustment signal is calculated according to the difference between the clock periods of the modulated feedback clock and the reference clock; and the edges of the modulated feedback clock and the modulated reference clock are aligned. The spread spectrum phase-locked loop control circuit helps to reduce phase noise during spread spectrum and improve the frequency accuracy of the spread spectrum clock.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a spread spectrum phase-locked loop control circuit and its control method, and a processor chip. Background Technology

[0002] With the continuous development of integrated circuits towards higher frequencies and higher speeds, high-speed transmission signals have become the main source of electromagnetic interference in electronic circuits. This electromagnetic interference can have a significant negative impact on the performance and stability of the system.

[0003] Currently, the frequency of high-speed transmission signals can be modulated using spread spectrum technology, causing the frequency of the high-speed transmission signal to fluctuate within the frequency range corresponding to fractional division, thereby dispersing the originally concentrated interference energy. The key step in this process is generating the required fractional division signal. The fractional division circuit for generating this signal typically employs a method of rapidly dividing the signal to be divided into adjacent integer division signals, ensuring that the divided signal achieves the desired fractional division effect over a period of time.

[0004] However, using the above fractional frequency divider circuit inevitably generates phase noise, and it is difficult to suppress phase noise well while achieving high frequency and high resolution.

[0005] This application aims to provide a novel spread-frequency phase-locked loop control circuit to solve the aforementioned problems existing in related technologies. Summary of the Invention

[0006] This application aims to provide a spread spectrum phase-locked loop control circuit and its control method, as well as a processor chip. Through a unique structural design, it suppresses phase noise during spread spectrum operation and improves the stability and frequency accuracy of the spread spectrum clock.

[0007] The embodiments of this application adopt the following technical solutions: In a first aspect, embodiments of this application provide a spread spectrum phase-locked loop control circuit, including a spread spectrum function module and a phase-locked loop module. The spread spectrum function module includes a spread spectrum modulation submodule and a reference clock delay submodule, and the phase-locked loop module includes a feedback submodule. The spread spectrum modulation submodule is electrically connected to the feedback submodule and the reference clock delay submodule, respectively. The spread spectrum modulation submodule is configured to generate a first adjustment signal, a second adjustment signal, and a frequency division control signal based on the frequency division ratio signal; The feedback submodule is configured to modulate the feedback clock according to the first adjustment signal and the frequency division control signal to generate a modulated feedback clock; The reference clock delay submodule is configured to modulate the reference clock according to the second adjustment signal to generate a modulated reference clock; The second adjustment signal is calculated based on the difference between the clock period of the modulation feedback clock and the clock period of the reference clock; the edges of the modulation feedback clock and the modulation reference clock are aligned.

[0008] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum modulation submodule includes a first modulation unit and a second modulation unit; the feedback submodule includes a frequency division unit and a frequency division clock delay unit; The first modulation unit is electrically connected to the frequency division unit; the second modulation unit is electrically connected to the frequency division clock delay unit; the frequency division unit is electrically connected to the frequency division clock delay unit. The first modulation unit is configured to generate the frequency division control signal and the first compensation control signal based on the frequency division ratio signal; the frequency division unit is configured to generate a frequency division clock based on the frequency division control signal and the feedback clock; The second modulation unit is configured to generate the first adjustment signal and the second compensation control signal based on the frequency division ratio signal; the frequency division clock delay unit is configured to generate the modulation feedback clock based on the first adjustment signal and the frequency division clock.

[0009] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum modulation submodule further includes a third modulation unit; the reference clock delay submodule includes an bias calculation unit and a delay compensation unit; The bias calculation unit is electrically connected to the delay compensation unit, the first modulation unit, the second modulation unit, and the third modulation unit, respectively. The third modulation unit is configured to generate the second adjustment signal based on the frequency division ratio signal; The bias calculation unit is configured to calculate a bias signal based on a preset bias value, the first compensation control signal, the second compensation control signal, and the second adjustment signal. The delay compensation unit is configured to generate the modulation reference clock based on the bias signal and the reference clock.

[0010] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum function module further includes a spread spectrum configuration submodule, which includes a spread spectrum direction control unit, a spread spectrum size control unit, a spread spectrum signal conversion unit, and a clock control unit; The spread spectrum size control unit is electrically connected to the spread spectrum direction control unit and the spread spectrum signal conversion unit, respectively; the clock control unit is electrically connected to the spread spectrum direction control unit and the spread spectrum size control unit, respectively. The clock control unit is configured to provide a spread spectrum modulation clock to the spread spectrum direction control unit and the spread spectrum size control unit; The spread spectrum direction control unit is configured to periodically switch the sign of the spread spectrum step size signal at the clock frequency of the spread spectrum modulation clock, based on the spread spectrum mode signal and the spread spectrum number signal, to obtain a first spread spectrum signal; The spread spectrum size control unit is configured to periodically accumulate the first spread spectrum signal at the clock frequency of the spread spectrum modulation clock to obtain the second spread spectrum signal; The spread spectrum signal conversion unit is configured to convert the second spread spectrum signal into a portion of the frequency division ratio signal.

[0011] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum direction control unit includes a first spread spectrum direction, a second spread spectrum direction, and a third spread spectrum direction; The first spreading direction involves setting the initial sign of the spreading step signal to negative, and then changing the sign of the spreading step signal to the opposite value every first time interval. The second spreading direction involves setting the initial sign of the spreading step signal to positive, and then changing the sign of the spreading step signal to the opposite value every first time interval. The third spreading direction involves setting the initial sign of the spreading step signal to positive, and then changing the sign of the spreading step signal to the opposite value every second time interval. The first time is twice the second time.

[0012] In some of the spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum configuration submodule further includes an enable control terminal; The enable control terminal is electrically connected to the clock control unit and the spread spectrum signal conversion unit, respectively. The enable control terminal is configured to receive an enable signal to control the clock control unit and the spread spectrum signal conversion unit to start working. When the enable signal is at the first level, the spread spectrum phase-locked loop control circuit is in a fixed frequency division mode, and the spread spectrum configuration submodule outputs the first set of the frequency division ratio signals; When the enable signal is at the second level, the spread spectrum phase-locked loop control circuit is in the spread spectrum working mode, and the spread spectrum configuration submodule outputs the second set of the frequency division ratio signals; The frequency division ratio signal in the second group can change over time.

[0013] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum direction control unit includes a sign conversion subunit and a two's complement generation subunit; The symbol conversion subunit and the two's complement generation subunit are electrically connected; The symbol conversion subunit is configured to determine the symbol of the spread spectrum step size signal based on the spread spectrum mode signal, the spread spectrum number signal, and the number of edges of the spread spectrum modulation clock; The complement generation subunit is configured to convert the spread spectrum step size signal into the first spread spectrum signal.

[0014] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum direction control unit further includes a first adder, a register, and a comparator; The registers are electrically connected to the first adder and the comparator, respectively. The comparator is electrically connected to the symbol conversion subunit; The first adder is configured to accumulate the number of spread spectrum modulation clock edges to obtain a first accumulated count value; The register is configured to store the first accumulated count value; The comparator is configured to compare the first accumulated count value with the spread spectrum number signal and output a comparison result signal; Wherein, when the first accumulated count value is equal to the spread spectrum number signal or half of the spread spectrum number signal, the comparison result signal is at the first level; When the comparison result signal is at the first level, the first accumulated count value stored in the register is cleared to zero, and the sign conversion subunit inverts the sign of the spread spectrum step size signal when it receives the comparison result signal as the first level.

[0015] In some spread spectrum phase-locked loop control circuits provided in this application, the spread spectrum magnitude control unit includes a second adder and a trigger; The second adder is electrically connected to both the flip-flop and the two's complement generation subunit. The second adder is configured to accumulate the first spread spectrum signal to obtain a second accumulated signal; The trigger is configured to periodically output the second accumulated signal at the frequency of the spread spectrum modulation clock to obtain the second spread spectrum signal.

[0016] In some spread spectrum phase-locked loop control circuits provided in this application, the clock control unit includes a switch and a clock buffer subunit; The switch is electrically connected to the clock buffer subunit; the clock buffer subunit is electrically connected to the trigger in the spread spectrum size control unit and the register in the spread spectrum direction control unit, respectively; The switch is configured to turn on or off the transmission path of the spread spectrum modulation clock according to an enable signal; the enable signal is the enable signal output by the enable control terminal in the spread spectrum configuration submodule. The clock buffer subunit is configured to adjust the time when the spread spectrum modulation clock arrives at the flip-flop and the register, and to shape the spread spectrum modulation clock.

[0017] In some spread spectrum phase-locked loop control circuits provided in this application, the phase-locked loop module further includes a frequency synthesis submodule; The frequency synthesis submodule is electrically connected to the feedback submodule and the reference clock delay submodule, respectively. The frequency synthesis submodule is configured to synthesize a spread spectrum clock based on the modulation feedback clock and the modulation reference clock.

[0018] In some spread spectrum phase-locked loop control circuits provided in this application, the frequency synthesis submodule includes a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator; The frequency and phase detector is electrically connected to the charge pump, the charge pump is electrically connected to the loop filter, the loop filter is electrically connected to the voltage-controlled oscillator, and the voltage-controlled oscillator is electrically connected to the frequency division unit in the feedback submodule. The frequency division clock delay unit in the feedback submodule is electrically connected to the frequency and phase detector. The delay compensation unit in the reference clock delay submodule is electrically connected to the frequency and phase detector.

[0019] Secondly, embodiments of this application provide a processor chip including a spread spectrum phase-locked loop control circuit as described in any one of the first aspects.

[0020] Thirdly, embodiments of this application provide a control method applied to control the spread spectrum phase-locked loop control circuit described in any one of the first aspects, the control method comprising: Acquire the frequency division ratio signal, reference clock, and feedback clock; A first adjustment signal, a second adjustment signal, and a frequency division control signal are generated based on the frequency division ratio signal; The feedback clock is modulated according to the first adjustment signal and the frequency division control signal to generate a modulated feedback clock; The reference clock is modulated according to the second adjustment signal to generate a modulated reference clock; The second adjustment signal is calculated based on the difference between the clock period of the modulation feedback clock and the clock period of the reference clock; the edges of the modulation feedback clock and the modulation reference clock are aligned.

[0021] Beneficial effects In this application, by setting up a spread spectrum modulation submodule to generate a first adjustment signal, a second adjustment signal, and a frequency division control signal based on the frequency division ratio signal, and a feedback submodule to perform frequency division and phase modulation on the feedback clock based on the first adjustment signal and the frequency division control signal, and a reference clock delay submodule to perform phase modulation on the reference clock based on the second adjustment signal, the magnitudes of the first adjustment signal and the second adjustment signal are precisely matched. This can compensate for the phase noise when the feedback clock is divided by a fraction without increasing the phase modulation accuracy of the feedback submodule. This allows the phase difference between the modulation feedback clock and the modulation reference clock to approach zero even in high-frequency, high-resolution operating modes of the phase-locked loop module. This effectively reduces the phase deviation between the modulation feedback clock and the modulation reference clock caused by the phase noise generated by the feedback submodule when dividing the feedback clock by a fraction, and further reduces the period jitter and phase drift of the spread spectrum clock caused by phase noise (the spread spectrum clock is the clock synthesized and output by the phase-locked loop from the modulation feedback clock and the modulation reference clock). This significantly improves the stability and frequency accuracy of the spread spectrum clock across the entire operating frequency band. This solution not only achieves energy dispersion of the spread spectrum clock and reduces electromagnetic interference peaks, but also solves the problem that traditional spread spectrum technology cannot simultaneously achieve high-frequency, high-resolution operation and phase noise suppression, ultimately effectively improving the signal integrity and timing stability of the processor chip during high-frequency, high-speed operation. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the circuit structure of a first spread spectrum phase-locked loop control circuit provided for embodiments of this application; Figure 2 A schematic diagram of the circuit structure of a second spread spectrum phase-locked loop control circuit provided for embodiments of this application; Figure 3 A schematic diagram of the circuit structure of a third spread spectrum phase-locked loop control circuit provided for embodiments of this application; Figure 4 A schematic diagram of the circuit structure of a fourth spread spectrum phase-locked loop control circuit provided for embodiments of this application; Figure 5 A schematic diagram of the circuit structure of the fifth spread spectrum phase-locked loop control circuit provided for embodiments of this application; Figure 6A schematic diagram of the circuit structure of a processor chip provided for an embodiment of this application; Figure 7 A flowchart of a control method for a spread spectrum phase-locked loop control circuit provided in an embodiment of this application. Detailed Implementation

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] In the embodiments of this application, the terms "first", "second", "third", "fourth" are used to distinguish the same or similar items with essentially the same function and effect, only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0025] In the embodiments of this application, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0026] In the description of this specification, the terms "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0027] In the embodiments of this application, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly defined.

[0028] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include certain tolerances. Taking into account the measurement and the tolerances associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0030] In this specification, "electrical connection" and "coupling" include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the reception of electrical signals between the connected constituent elements.

[0031] As processor chips continue to evolve towards higher frequencies and higher speeds, electromagnetic interference (EMI) can cause signal transmission distortion, timing logic errors, and lead to communication anomalies between functional modules within the processor chip, as well as a significant increase in data transmission error rates. High-speed signals, due to their high frequency and fast transmission rate, have become a major source of EMI in electronic circuits. Spread spectrum technology, as the mainstream method for suppressing EMI in high-speed signals, is widely used in various processor chips such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), and MCUs (Microcontroller Units). Its core principle is to modulate the frequency of high-speed signals, causing the frequency of the high-speed signals to fluctuate within the frequency range corresponding to fractional frequency division. This disperses the EMI energy concentrated in fixed-frequency signals, significantly reducing the peak value of EMI and achieving a highly efficient EMI suppression effect.

[0032] Fractional frequency division is the core of spread spectrum technology. Currently, the industry generally achieves fractional frequency division by combining phase-locked loops (PLLs) with frequency dividers. Existing frequency dividers typically use a method of quickly switching the clock to be divided to adjacent integer divisions, so that the divided clock achieves the required fractional frequency division effect within a certain statistical time. There is a certain phase difference between the divided clock and the reference clock. The PLL can output the corresponding clock frequency based on this phase difference and continuously calibrate the output clock frequency through a feedback loop to reduce the phase difference between the divided clock and the reference clock, attempting to stabilize the output clock and lock the output clock frequency.

[0033] However, there is always a phase difference, i.e., phase noise, between the frequency divided clock generated by the above fractional division method and the reference clock. This phase noise causes the frequency of the phase-locked loop output clock to deviate from the preset frequency. Moreover, in high-frequency and high-resolution working scenarios, the impact of phase noise on the frequency of the synthesized clock signal will be further aggravated, which seriously restricts the development of processor chips towards high speed, high frequency and high precision.

[0034] Based on this, embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 1 As shown, the spread spectrum phase-locked loop control circuit includes a spread spectrum function module and a phase-locked loop module. The spread spectrum function module includes a spread spectrum modulation submodule 1100 and a reference clock delay submodule 1200, and the phase-locked loop module includes a feedback submodule 2100. The spread spectrum modulation submodule 1100 is electrically connected to the feedback submodule 2100 and the reference clock delay submodule 1200, respectively. The spread spectrum modulation submodule 1100 is configured to generate a first adjustment signal adj1, a second adjustment signal adj2, and a frequency division control signal div_ctrl based on the frequency division ratio signal. The feedback submodule 2100 is configured to generate a first adjustment signal adj1, a second adjustment signal adj2, and a frequency division control signal div_ctrl based on the first adjustment signal adj1. The feedback clock fb_clk is modulated by the frequency divider control signal div_ctrl to generate the modulated feedback clock fb_mod; the reference clock delay submodule 1200 is configured to modulate the reference clock ref_clk according to the second adjustment signal adj2 to generate the modulated reference clock ref_mod; wherein, the second adjustment signal adj2 is calculated based on the difference between the clock period of the modulated feedback clock fb_mod and the clock period of the reference clock ref_clk; the edge alignment of the modulated feedback clock fb_mod and the modulated reference clock ref_mod is set.

[0035] For example, such as Figure 1 As shown, the phase-locked loop module also includes a frequency synthesis submodule 2200; the frequency synthesis submodule 2200 is electrically connected to the feedback submodule 2100 and the reference clock delay submodule 1200 respectively; the frequency synthesis submodule 2200 is configured to synthesize a spread spectrum clock ssc_clk based on the modulation feedback clock fb_mod and the modulation reference clock ref_mod.

[0036] A phase-locked loop (PLL) is a feedback control circuit whose core function is to adjust the output spread spectrum clock frequency (ssc_clk) to an integer or fractional multiple of the input reference clock frequency (ref_clk).

[0037] The reference clock ref_clk is a reference clock signal provided by an external stable signal source such as a crystal oscillator. It sets the frequency and phase reference standard for the entire spread spectrum phase-locked loop control circuit. The spread spectrum clock ssc_clk is the final output clock signal of the phase-locked loop module, which is a spread spectrum modulated clock signal.

[0038] The feedback clock fb_clk refers to the original input signal of the spread spectrum clock ssc_clk, which is directly input to the feedback submodule 2100 from the output of the phase-locked loop. In the circuit structure, the spread spectrum clock ssc_clk and the feedback clock fb_clk have the same frequency, which are essentially different transmission path forms of the same clock signal.

[0039] The frequency division control signal div_ctrl is used to control the frequency division ratio when the feedback submodule 2100 converts the feedback clock fb_clk into the modulation feedback clock fb_mod.

[0040] The frequency division control signal div_ctrl is used to control the frequency division ratio between the feedback clock fb_clk and the modulation feedback clock fb_mod, thereby indirectly controlling the frequency division ratio between the reference clock ref_clk and the spread spectrum clock ssc_clk.

[0041] The modulation feedback clock fb_mod is the clock output after the feedback clock fb_clk is divided and phase-adjusted by the feedback submodule 2100.

[0042] The modulated reference clock ref_mod is the clock output after the reference clock ref_clk has undergone phase adjustment by the reference clock delay submodule 1200.

[0043] The first adjustment signal adj1 is used to adjust the phase offset when generating the modulation feedback clock fb_mod, and the second adjustment signal adj2 is used to adjust the phase offset when generating the modulation reference clock ref_mod. By properly designing the first adjustment signal adj1 and the second adjustment signal adj2, the edges of the modulation feedback clock fb_mod and the modulation reference clock ref_mod can be precisely aligned.

[0044] The frequency synthesis subunit continuously monitors the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod. When a phase difference is detected, the frequency synthesis subunit changes the frequency of the spread spectrum clock ssc_clk according to the magnitude of the phase difference. This spread spectrum clock ssc_clk is also the feedback clock fb_clk. The feedback clock fb_clk is divided and phase-modulated by the feedback submodule 2100 to form the modulation feedback clock fb_mod. The frequency synthesis subunit then compares the modulation feedback clock fb_mod with the modulation reference clock ref_mod. The phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod is adjusted, and the frequency of the spread spectrum clock ssc_clk is adjusted. The above process will continue to loop, and each loop will reduce the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod until the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod is zero. Only when the division ratio between the reference clock ref_clk and the spread spectrum clock ssc_clk is the same as the division ratio of the feedback submodule 2100 can the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod truly converge to zero, thereby achieving high-precision frequency locking. In the initial stage of the spread spectrum phase-locked loop control circuit, the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod is relatively large. At this time, the frequency synthesis subunit can generate a large frequency adjustment signal based on this phase difference, driving the frequency of the spread spectrum clock ssc_clk to rapidly approach the target frequency. As the frequency of the spread spectrum clock ssc_clk gradually approaches the target frequency, the phase difference between the modulation feedback clock fb_mod generated by the feedback clock fb_clk after frequency division and phase modulation and the modulation reference clock ref_mod also gradually decreases. The frequency adjustment signal generated by the frequency synthesis subunit also decreases accordingly. Finally, the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod becomes zero, and the spread spectrum phase-locked loop control circuit enters the locked state. At this time, the frequency of the spread spectrum clock ssc_clk stabilizes at the target value.

[0045] In the feedback submodule 2100, when dividing the feedback clock fb_clk by a fractional value, the feedback clock fb_clk is divided to an integer value greater than the fractional value in the first time period and to an integer value less than the fractional value in the second time period. This results in the average division ratio of the divided clock div_clk after the feedback clock fb_clk is equal to the fractional division ratio in the first and second time periods. However, although this division method can make the average division ratio of the divided clock div_clk equal to the fractional division ratio, there is always a deviation between the clock period of the divided clock div_clk and the clock period of the reference clock ref_clk. This deviation is called phase noise. This phase noise will cause a certain deviation between the clock frequency of the spread spectrum clock ssc_clk and the preset clock frequency. Especially in high-frequency application scenarios, this phase noise will significantly reduce the accuracy and stability of the spread spectrum clock ssc_clk.

[0046] The frequency-divided clock div_clk is the clock obtained by dividing the feedback clock fb_clk by the frequency division unit 2110 according to the frequency division control signal div_ctrl.

[0047] Integer division means that the output clock frequency is an integer multiple of the input clock frequency. For example, the output clock frequency is twice the input clock frequency, ten times the input clock frequency, one hundred times the input clock frequency, etc.

[0048] Fractional division refers to the output clock frequency being a non-integer multiple of the input clock frequency. For example, the output clock frequency is 1.5 times the input clock frequency, or the output clock frequency is 80+1 / 64 times the input clock frequency.

[0049] The following example illustrates how phase noise is generated, using a reference clock ref_clk with a clock period of 15ns, a spread spectrum clock ssc_clk with a clock period of 10ns, a feedback clock fb_clk with a clock period of 10ns, and a division ratio of 1.5: The feedback submodule 2100 implements a 1.5 frequency division. This requires using two clock cycles as a statistical time interval. The first feedback clock, fb_clk, is divided by 1, resulting in a clock period of 10ns × 1 = 10ns. The second feedback clock, fb_clk, is divided by 2, resulting in a clock period of 10ns × 2 = 20ns. Within these two clock cycles, the average clock period of the divided clock div_clk is (10ns + 20ns) / 2 = 15ns, achieving an equivalent fractional frequency division. However, if this divided clock div_clk and the reference clock ref are directly... When _clk is input to the phase-locked loop (PLL), the clock period of the first divided clock div_clk (10ns) is different from that of the first reference clock ref_clk (15ns). Similarly, the clock period of the second divided clock div_clk (20ns) is also different from that of the second reference clock ref_clk (15ns). Consequently, the phase of the reference clock ref_clk and the phase of the divided clock div_clk cannot be the same. The phase difference between the reference clock ref_clk and the divided clock div_clk is the phase noise. In this case, the PLL cannot achieve a stable locked state, and the frequency of the spread spectrum clock ssc_clk cannot be stabilized to the preset value.

[0050] To suppress this phase noise, the feedback submodule 2100 needs to compensate for the clock period of the divided clock div_clk so that the clock period of the divided clock div_clk tends to the clock period of the reference clock ref_clk. However, the feedback submodule 2100 has limited ability to adjust the phase of the divided clock div_clk. To achieve high-precision phase adjustment, a more complex circuit structure or a larger chip area is required, and additional phase noise may even be introduced. Therefore, the period of the modulation feedback clock fb_mod generated after the feedback clock fb_clk is divided and phase-modulated by the feedback submodule 2100 may still deviate from the period of the reference clock ref_clk. This deviation will cause the edges of the modulation feedback clock fb_mod and the reference clock ref_clk to not be completely aligned, thus affecting the stability of the spread spectrum clock ssc_clk. To address this, the phase of the reference clock ref_clk needs to be compensated by the reference clock delay submodule 1200 to generate the modulation reference clock ref_mod, so that the edges of the modulation feedback clock fb_mod and the modulation reference clock ref_mod are aligned. This eliminates the phase deviation caused by the insufficient phase adjustment capability of the feedback submodule 2100, and ultimately significantly improves the frequency stability of the spread spectrum clock ssc_clk.

[0051] The following example illustrates how the reference clock ref_clk delay submodule and the feedback submodule 2100 cooperate to eliminate the phase deviation between the reference clock ref_clk and the divided clock div_clk, using a clock period of 15ns for the reference clock ref_clk, a clock period of 10ns for the spread spectrum clock ssc_clk, a clock period of 10ns for the feedback clock fb_clk, a frequency division ratio of 1.5, and a modulation accuracy of 6ns for the feedback submodule 2100: As mentioned earlier, regarding the first divided clock div_clk and the first reference clock ref_clk: the clock period of the first divided clock div_clk (10ns) and the clock period of the first reference clock ref_clk (15ns) are different. The feedback submodule 2100 can adjust the clock period of the first divided clock div_clk by 6ns, that is, the clock period of the first divided clock div_clk can be adjusted to 10ns + 6ns = 16ns. At this time, the adjusted divided clock div_clk, i.e., the clock period of the modulation feedback clock fb_mod, is 16ns. The clock period of ns is different from that of the reference clock ref_clk (15ns). The clock period of the first reference clock ref_clk needs to be adjusted from 15ns to 16ns through the reference clock ref_clk delay submodule. That is, the clock period of the modulation reference clock ref_mod is 16ns. The clock periods of the modulation reference clock ref_mod and the modulation feedback clock fb_mod are both 16ns, and there is no phase difference. The phase-locked loop will not modulate the clock frequency of the spread spectrum clock ssc_clk, and the clock period of the spread spectrum clock ssc_clk can be maintained stably at 15ns.

[0052] The modulation accuracy of the feedback submodule 2100 refers to the minimum adjustment step size that the feedback submodule 2100 can achieve.

[0053] For example, the edge alignment of the modulation feedback clock fb_mod and the modulation reference clock ref_mod can be the alignment of the rising edge of the modulation feedback clock fb_mod and the rising edge of the modulation reference clock ref_mod.

[0054] In the embodiments of this application, a spread spectrum modulation submodule 1100, a reference clock delay submodule 1200, and a feedback submodule 2100 are provided. The spread spectrum modulation submodule 1100 is configured to generate a first adjustment signal adj1, a second adjustment signal adj2, and a frequency division control signal div_ctrl based on the frequency division ratio signal. The feedback submodule 2100 is configured to modulate the feedback clock fb_clk based on the first adjustment signal adj1 and the frequency division control signal div_ctrl to generate a modulated feedback clock fb_mod. The reference clock delay submodule 1200 is configured to modulate the reference clock ref_clk based on the second adjustment signal adj2 to generate a modulated reference clock ref_mod. The edges of the modulated feedback clock fb_mod and the modulated reference clock ref_mod are aligned.

[0055] The above setup has the following advantages over related technologies: Firstly, the feedback clock fb_clk is divided and phase-modulated using the first adjustment signal adj1 and the frequency division control signal div_ctrl to generate the modulated feedback clock fb_mod. The reference clock ref_clk is phase-modulated using the second adjustment signal adj2 to generate the modulated reference clock ref_mod. By precisely matching the magnitudes of the first adjustment signal adj1 and the second adjustment signal adj2, the phase noise during fractional division of the feedback clock fb_clk can be compensated without increasing the phase modulation accuracy of the feedback submodule 2100. This ensures that even in high-frequency, high-resolution operating modes, the phase difference between the modulated feedback clock fb_mod and the modulated reference clock ref_mod can approach zero. This effectively reduces the phase difference between the modulated feedback clock fb_mod and the modulated reference clock ref_mod caused by the phase noise generated when the feedback submodule 2100 divides the feedback clock fb_clk by a fraction. Consequently, the period jitter and phase drift of the spread spectrum clock ssc_clk caused by the phase difference are reduced, significantly improving the stability of the spread spectrum clock ssc_clk. This solution not only achieves spectrum energy dispersion and reduces electromagnetic interference peaks in the spread spectrum clock ssc_clk, but also solves the problem that traditional spread spectrum technology cannot simultaneously achieve high-frequency, high-resolution operation and phase noise suppression, ultimately effectively improving the signal integrity and timing stability of the processor chip during high-frequency, high-speed operation.

[0056] Secondly, the feedback clock fb_clk is actively phase-modulated by the feedback submodule 2100 to generate the modulated feedback clock fb_mod, and the reference clock delay submodule 1200 is actively phase-modulated by the reference clock ref_clk to generate the modulated reference clock ref_mod. This puts the phase-locked loop (PLL) module in an unlocked initial state (such as when the circuit is first powered on or during output frequency switching). The modulated feedback clock fb_mod and the modulated reference clock ref_mod form an initial phase difference that is much larger than that of a traditional fractional-division PLL. This significantly improves the PLL module's response speed and correction efficiency to the frequency deviation between the reference clock ref_clk and the feedback clock fb_clk. It can adjust the frequency of the spread spectrum clock ssc_clk to the target value more quickly, thereby significantly shortening the time from startup to stable locking of the PLL module. This allows the spread spectrum PLL control circuit to quickly enter a stable working state, further expanding the application scenarios of the circuit.

[0057] Thirdly, in traditional fractional-number frequency-division phase-locked loops (PLLs), to suppress phase noise caused by fractional spurious emissions, larger capacitance values ​​must be used for filtering. These large capacitance values ​​occupy a significant portion of the layout area, severely hindering the miniaturization and high integration of PLL circuits. This application addresses this by setting up a feedback submodule 2100 and a reference clock delay submodule 1200, enabling precise edge alignment between the modulation feedback clock fb_mod and the modulation reference clock ref_mod. This design directly cancels out the phase noise caused by fractional spurious emissions during fractional-number frequency division at its source, eliminating the need for larger capacitance values ​​to suppress fractional spurious emissions. This greatly reduces the layout area occupied by the PLL module on the chip, thereby significantly reducing the overall area of ​​the spread-spectrum PLL control circuit. This not only contributes to the high integration and miniaturization of the circuit but also effectively reduces chip manufacturing costs, significantly improving the circuit's adaptability and application potential in various miniaturized processor chips and portable device chips.

[0058] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, combined with Figure 2 and Figure 3As shown, the spread spectrum modulation submodule 1100 includes a first modulation unit 1110 and a second modulation unit 1120; the feedback submodule 2100 includes a frequency division unit 2110 and a frequency division clock delay unit 2120; the first modulation unit 1110 is electrically connected to the frequency division unit 2110; the second modulation unit 1120 is electrically connected to the frequency division clock delay unit 2120; the frequency division unit 2110 is electrically connected to the frequency division clock delay unit 2120; the first modulation unit 1110 is configured to generate a frequency division control signal di based on the frequency division ratio signal. v_ctrl and the first compensation control signal comp1; the frequency division unit 2110 is configured to generate a frequency division clock div_clk based on the frequency division control signal div_ctrl and the feedback clock fb_clk; the second modulation unit 1120 is configured to generate a first adjustment signal adj1 and a second compensation control signal comp2 based on the frequency division ratio signal; the frequency division clock delay unit 2120 is configured to generate a modulation feedback clock fb_mod based on the first adjustment signal adj1 and the frequency division clock div_clk.

[0059] For example, the frequency division ratio signal includes a fractional frequency division ratio signal u(n), an integer frequency division ratio signal M, and a first phase control code a(n); the first phase control code a(n) is used to characterize the phase offset between the frequency division clock div_clk and the modulation feedback clock fb_mod; The first modulation unit 1110 can generate a frequency division control signal div_ctrl based on the fractional frequency division ratio signal u(n) and the integer frequency division ratio signal M; the second modulation unit 1120 can generate a first adjustment signal adj1 based on the first phase control code a(n).

[0060] For example, both the first modulation unit 1110 and the second modulation unit 1120 can be SDM (Sigma-Delta Modulator). The SDM may include an adder, an integrator, a comparator, and a digital-to-analog converter; the integrator is electrically connected to the adder and the comparator respectively, and the digital-to-analog converter is electrically connected to the adder and the comparator respectively; For example, the frequency divider unit 2110 may employ an MMD (Multi-Mode Divider).

[0061] Frequency divider unit 2110 supports integer frequency division, but cannot directly perform fractional frequency division. Under the control of the frequency division control signal div_ctrl, the frequency division clock div_clk generated by frequency divider unit 2110 can quickly switch between adjacent integer frequency division ratios, thereby achieving an equivalent fractional frequency division effect within a statistical time period.

[0062] The following example illustrates the specific processing method of fractional frequency division by the frequency divider unit 2110, using a feedback clock fb_clk period of 1ns and a division ratio of 1.5: Using two clock cycles as a statistical period, the frequency divider unit 2110 controls the first clock cycle of the frequency divider clock div_clk to be 1ns, and the second clock cycle of the frequency divider clock div_clk to be 2ns. Then, within these two clock cycles, the average period of the frequency divider clock div_clk is (1ns+2ns) / 2=1.5ns, which is equivalent to achieving a 1.5 frequency divider.

[0063] For example, the frequency division clock delay unit 2120 may employ a PI (Phase Interpolator).

[0064] For example, the frequency division clock delay unit 2120 can also be a DTC (Digital to Time Converter).

[0065] When there is a phase difference between the frequency divider clock div_clk and the reference clock ref_clk, the frequency divider clock delay unit 2120 can adjust the period of the frequency divider clock div_clk with a certain modulation accuracy according to the first adjustment signal adj1, so that the period of the frequency divider clock div_clk tends to the period of the reference clock ref_clk.

[0066] The following example illustrates how the frequency divider clock delay unit 2120 adjusts the frequency divider clock div_clk period: the clock period is 64ns, the modulation accuracy of the frequency divider clock delay unit 2120 is 4ns, and the first phase control code a(n) is 4. When the frequency division clock delay unit 2120 controls the frequency division clock div_clk period to increase: After the frequency divider clock delay unit 2120 performs the first adjustment on the frequency divider clock div_clk, the clock period of the frequency divider clock div_clk can be adjusted to 64ns + 4ns = 68ns, that is, the clock period of the modulation feedback clock fb_mod is 68ns. After the frequency divider clock delay unit 2120 performs the second adjustment on the frequency divider clock div_clk, the clock period of the frequency divider clock div_clk can be adjusted to 68ns + 4ns = 72ns, that is, the clock period of the modulation feedback clock fb_mod is 72ns.

[0067] When the frequency division clock delay unit 2120 controls the frequency division clock div_clk period to decrease: After the frequency divider clock delay unit 2120 performs the first adjustment on the frequency divider clock div_clk, the clock period of the frequency divider clock div_clk can be adjusted to 64ns-4ns=60ns, that is, the clock period of the modulation feedback clock fb_mod is 60ns. After the frequency divider clock delay unit 2120 performs the second adjustment on the frequency divider clock div_clk, the clock period of the frequency divider clock div_clk can be adjusted to 60ns-4ns=56ns, that is, the clock period of the modulation feedback clock fb_mod is 56ns.

[0068] When the fractional division ratio signal u(n) is not 0, at least some of the clock edges of the modulation feedback clock fb_mod have a phase deviation from the clock edges of the division clock div_clk; at least some of the clock edges of the modulation feedback clock fb_mod have a phase deviation from the clock edges of the reference clock ref_clk.

[0069] For example, the clock edge can be a rising edge.

[0070] Wherein, at least some clock edges of the modulation feedback clock fb_mod have a phase deviation from the clock edges of the frequency divider clock div_clk, which may include, but is not limited to, the following cases: The first scenario: All rising edges of the modulation feedback clock fb_mod are misaligned with the rising edges of the frequency divider clock div_clk.

[0071] The second scenario is that part of the rising edge of the modulation feedback clock fb_mod is misaligned with part of the rising edge of the frequency divider clock div_clk, while another part of the rising edge of the modulation feedback clock fb_mod is aligned with another part of the rising edge of the frequency divider clock div_clk.

[0072] At least some clock edges of the modulation feedback clock fb_mod have a phase deviation from the clock edges of the reference clock ref_clk, which may include, but is not limited to, the following cases: The first scenario: All rising edges of the modulation feedback clock fb_mod are misaligned with the rising edges of the reference clock ref_clk.

[0073] The second scenario is that part of the rising edge of the modulation feedback clock fb_mod is misaligned with part of the rising edge of the reference clock ref_clk, while another part of the rising edge of the modulation feedback clock fb_mod is aligned with another part of the rising edge of the reference clock ref_clk.

[0074] In the embodiments of this application, a first modulation unit 1110, a second modulation unit 1120, a frequency division unit 2110, and a frequency division clock delay unit 2120 are provided. The first modulation unit 1110 is electrically connected to the frequency division unit 2110; the second modulation unit 1120 is electrically connected to the frequency division clock delay unit 2120; the frequency division unit 2110 is electrically connected to the frequency division clock delay unit 2120; the first modulation unit 1110 is configured to generate a frequency division control signal div_ctrl and a first compensation control signal comp1 according to the frequency division ratio signal; the frequency division unit 2110 is configured to generate a frequency division clock div_clk according to the frequency division control signal div_ctrl and the feedback clock fb_clk; the second modulation unit 1120 is configured to generate a first adjustment signal adj1 and a second compensation control signal comp2 according to the frequency division ratio signal; the frequency division clock delay unit 2120 is configured to generate a modulation feedback clock fb_mod according to the first adjustment signal adj1 and the frequency division clock div_clk.

[0075] With the above settings, the feedback clock fb_clk is divided into a frequency-divided clock div_clk by the frequency divider unit 2110. The frequency divider clock delay unit 2120 modulates the period of the frequency divider clock div_clk to generate the modulated feedback clock fb_mod, so that the clock period of the modulated feedback clock fb_mod tends to the reference clock ref_clk, which significantly reduces the phase difference between the reference clock ref_clk and the frequency divider clock div_clk. This means that the subsequent phase compensation of the reference clock ref_clk does not need to deal with the wide dynamic range and large phase compensation requirements, which can improve the phase compensation accuracy and response speed, and improve the operating speed of the spread spectrum control circuit.

[0076] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 3 As shown, the spread spectrum modulation submodule 1100 further includes a third modulation unit 1130; the reference clock delay submodule 1200 includes an bias calculation unit 1210 and a delay compensation unit 1220; the bias calculation unit 1210 is electrically connected to the delay compensation unit 1220, the first modulation unit 1110, the second modulation unit 1120 and the third modulation unit 1130 respectively; the third modulation unit 1130 is configured to generate a second adjustment signal adj2 according to the frequency division ratio signal; the bias calculation unit 1210 is configured to calculate the bias signal according to the preset bias value TRIM, the first compensation control signal comp1, the second compensation control signal comp2 and the second adjustment signal adj2; the delay compensation unit 1220 is configured to generate a modulation reference clock ref_mod according to the bias signal and the reference clock ref_clk.

[0077] For example, the frequency division ratio signal may also include a second phase control code b(n), which is used to characterize the phase offset between the reference clock ref_clk and the modulation reference clock ref_mod.

[0078] The third modulation unit 1130 can generate a second adjustment signal adj2 according to the second phase control code b(n).

[0079] The preset bias value TRIM can specifically calibrate phase deviations caused by hardware factors such as process deviations and trace delays. The first compensation control signal comp1 can adaptively shield the adjustment function of the delay compensation unit 1220 according to the division ratio when the frequency division unit 2110 is actually working, so as to achieve accurate adaptation between the frequency division ratio change and the bias signal, and ensure that the edges of the modulation feedback clock fb_mod and the modulation reference clock ref_mod are always aligned when the frequency division unit 2110 is working under different frequency division ratios.

[0080] The second compensation control signal comp2 is used to accurately calibrate the bias signal according to the interpolation rule of the second modulation unit 1120, and to make adaptive adjustments to the bias signal at the critical node of the period counting of the second modulation unit 1120, so as to ensure that the modulation reference clock ref_mod and the modulation feedback clock fb_mod remain synchronized during the phase modulation process.

[0081] For example, the bit width of the fractional frequency division ratio signal u(n), the first phase control code a(n), and the second phase control code b(n) can all be 6 bits; Wherein, the fractional frequency ratio signal u(n) is divided by 2 n This refers to the fractional division when dividing the reference clock ref_clk, where n is the bit width of the fractional division ratio signal u(n). For example, when the division ratio is 80 + 1 / 64, the fractional division is 1 / 64, and the fractional division ratio signal u(n) is 1.

[0082] The interpolable phase of the frequency division clock delay unit 2120 is 2. m At this time, the first phase control code a(n)[5-m:0] is configured to be zero, the first phase control code a(n)[5:5-m+1] = the second spread spectrum signal ssc_depth[5:5-m+1] + 1, the first phase control code b(n)[5:5-m+1] is configured to be zero, and the first phase control code b(n)[5-m:0] is configured to be the inverse code of the second spread spectrum signal ssc_depth[5-m:0] plus 1, where m is a positive integer.

[0083] The following example illustrates the collaborative operation of the first modulation unit 1110, the second modulation unit 1120, the third modulation unit 1130, the frequency division unit 2110, the frequency division clock delay unit 2120, the bias calculation unit 1210, and the delay compensation unit 1220, using a reference clock ref_clk clock period of 64×80+1ns, a frequency division ratio of 80+1 / 64, an interpolable phase number of the frequency division clock delay unit 2120, and a feedback clock fb_clk clock period of 64. The interpolable phase of the frequency divider clock delay unit 2120 is 16, i.e., m=4. At this time, the second spread spectrum signal ssc_depth[5:0] is 6'b000001, the first phase control code a(n)[5:0] is configured as 6'b000100, and the first phase control code b(n)[5:0] is configured as 6'b000011.

[0084] In this case, the fractional division ratio signal u(n) takes the value of 1, and the integer division ratio signal M takes the value of 80. The first modulation unit 1110 can generate a division control signal div_ctrl based on the fractional division ratio signal u(n) and the integer division ratio signal M. The division unit 2110 divides the feedback clock fb_clk according to the division control signal div_ctrl to generate a division signal. Among the 64 clock cycles of the division clock div_clk, 63 clock cycles are generated by dividing the feedback clock fb_clk by 80, and 1 clock cycle is generated by dividing the feedback clock fb_clk by 81.

[0085] When the frequency division ratio is 80, the clock period of the frequency division clock div_clk is 64×80ns, which is 1ns less than the clock period of the reference clock ref_clk (64×80+1ns). At this time, the second modulation unit 1120 can generate a first adjustment signal adj1 and a second compensation control signal comp2 according to the first phase control code a(n). The second modulation unit 1120 can extend the clock period of the frequency division clock div_clk by 64 / 16ns according to the first adjustment signal adj1 to generate the modulation feedback clock fb_mod. The clock period of the modulation feedback clock fb_mod is 64×80+4ns.

[0086] However, at this time, the clock period of the reference clock ref_clk is 64×80+1ns. The difference between the clock period of the reference clock ref_clk and the clock period of the modulation feedback clock fb_mod (64×80+4ns) is 3ns. The third modulation unit 1130 can generate the second adjustment signal adj2 according to the second phase control code b(n). The bias calculation unit 1210 can calculate the bias signal according to the second adjustment signal adj2. At this time, the bias signal is 3ns. The delay compensation unit 1220 can extend the clock period of the reference clock ref_clk by 3ns through the bias signal to generate the modulation reference clock ref_mod. The clock period of the modulation reference clock ref_mod is 64×80+4ns, which is the same as the clock period of the modulation feedback clock fb_mod (64×80+4ns). This can further realize the edge alignment of the modulation reference clock ref_mod and the modulation feedback clock fb_mod.

[0087] After the frequency division clock delay unit 2120 completes the modulation of the 15th frequency division clock div_clk, when modulating the clock period of the 16th frequency division clock div_clk, the phase delay value of the frequency division clock delay unit 2120 will become 0. At this time, the clock period of the 16 modulation feedback clocks fb_mod is (64×80+4)×16-4×16ns. If the clock period of the modulation reference clock ref_mod is not modulated, the clock period of the 16 modulation reference clocks ref_mod will still be (64×80+1)×16+3×16ns. The clock period of the 16th modulation feedback clock fb_mod is 64ns longer than that of the 16th modulation feedback clock fb_mod. At this time, the second modulation unit 1120 generates a second compensation control signal comp2. The bias calculation unit 1210 reduces the bias signal by 64ns according to the second compensation control signal comp2. The delay compensation unit 1220 controls the clock period of the modulation reference clock ref_mod to be reduced by 64ns accordingly, so that the clock period of the 16th modulation feedback clock fb_mod is the same as the clock period of the 16th modulation reference clock ref_mod. This further enables the edge alignment of the modulation reference clock ref_mod and the modulation feedback clock fb_mod.

[0088] After the clock delay unit 2120 completes the clock cycle modulation of the 63rd clock division div_clk, when modulating the clock cycle of the 64th clock division div_clk, the 64th clock division div_clk is obtained by dividing the feedback clock fb_clk by 81. The clock cycle of the 64th clock division div_clk is 64×81. The phase delay value of the clock delay unit 2120 becomes 0. At this time, from the 49th modulation feedback clock fb_mod to the 64th modulation feedback clock f The clock period of b_mod is (64×80+4)×15+64×81-4×15ns. The clock periods of the 49th modulation reference clock ref_mod to the 64th modulation reference clock ref_mod are (64×80+1)×16+3×16ns. The clock periods of the 16 modulation feedback clocks fb_mod are the same as the clock periods of the 16 modulation reference clocks ref_mod. Edge alignment can still be achieved between the modulation feedback clock fb_mod and the modulation reference clock ref_mod.

[0089] After completing the modulation of the 64th frequency division clock div_clk, the first modulation unit 1110 generates the first compensation control signal comp1. After receiving the first compensation control signal comp1, the bias calculation unit 1210 sets the bias signal to 0, and the phase delay value of the frequency division clock delay unit 2120 is also set to 0. The states of the modulation feedback clock fb_mod and the modulation reference clock ref_mod are the same as the initial states, and it is ready to proceed with the next round of modulation.

[0090] For example, the delay compensation unit 1220 can be a DTC (Digital to Time Converter).

[0091] For example, the delay compensation unit 1220 can be a PI (Phase Interpolator).

[0092] In the embodiments of this application, a third modulation unit 1130, an offset calculation unit 1210, and a delay compensation unit 1220 are provided. The offset calculation unit 1210 is electrically connected to the delay compensation unit 1220, the first modulation unit 1110, the second modulation unit 1120, and the third modulation unit 1130, respectively. The third modulation unit 1130 is configured to generate a second adjustment signal adj2 based on the frequency division ratio signal. The offset calculation unit 1210 is configured to calculate an offset signal based on a preset offset value TRIM, a first compensation control signal comp1, a second compensation control signal comp2, and a second adjustment signal adj2. The delay compensation unit 1220 is configured to generate a modulation reference clock ref_mod based on the offset signal and a reference clock ref_clk. By setting the third modulation unit 1130 to generate a second adjustment signal adj2 based on the frequency division ratio signal, and the bias calculation unit 1210 combining the preset bias value TRIM, the first compensation control signal comp1, the second compensation control signal comp2, and the second adjustment signal adj2 to calculate the bias signal, the delay compensation unit 1220 modulates the reference clock ref_clk according to the bias signal to generate a modulation reference clock ref_mod. This allows for the use of the third modulation unit 1130 and the bias calculation unit 1210 to compensate for insufficient modulation capability of the frequency division clock delay unit 2120 on the frequency division clock div_clk. The delay compensation unit 1220 modulates the reference clock ref_clk and generates a modulation reference clock ref_mod to compensate for the phase difference between the modulation feedback clock fb_mod and the reference clock ref_clk. This allows the edges of the modulation feedback clock fb_mod and the modulation reference clock ref_mod to be aligned without increasing the design complexity and chip area of ​​the frequency divider clock delay unit 2120. This effectively suppresses the period jitter and phase drift caused by the insufficient modulation capability of the delay compensation unit 1220, and makes the spread spectrum clock ssc_clk highly stable throughout the entire spread spectrum period.

[0093] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, wherein the spread spectrum function module further includes a spread spectrum configuration submodule 1300, such as... Figure 4 As shown, the spread spectrum configuration submodule 1300 includes a spread spectrum direction control unit 1310, a spread spectrum size control unit 1320, a spread spectrum signal conversion unit 1330, and a clock control unit 1340; the spread spectrum size control unit 1320 is electrically connected to the spread spectrum direction control unit 1310 and the spread spectrum signal conversion unit 1330 respectively; the clock control unit 1340 is electrically connected to the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320 respectively; the clock control unit 1340 is configured to provide a spread spectrum modulation clock ssc_mod_clk to the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320; the spread spectrum direction control unit 1310 is configured to provide a spread spectrum modulation clock ssc_mod_clk to the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320; the spread spectrum direction control unit 1310 is configured to provide a spread spectrum modulation clock ssc_mod_clk to the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320 respectively. The spread spectrum mode signal ssc_mode and the spread spectrum number signal ssc_num are configured to periodically switch the sign of the spread spectrum step size signal ssc_step at the clock frequency of the spread spectrum modulation clock ssc_mod_clk to obtain the first spread spectrum signal ssc_dir; the spread spectrum size control unit 1320 is configured to periodically accumulate the first spread spectrum signal ssc_dir at the clock frequency of the spread spectrum modulation clock ssc_mod_clk to obtain the second spread spectrum signal ssc_depth; the spread spectrum signal conversion unit 1330 is configured to convert the second spread spectrum signal ssc_depth into a portion of the division ratio signal.

[0094] The spread spectrum modulation clock ssc_mod_clk is the core synchronization clock signal of the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320, which determines the symbol switching of the spread spectrum step size signal ssc_step and the frequency of accumulation of the first spread spectrum signal ssc_dir.

[0095] The spread spectrum mode signal ssc_mode is used to determine the initial symbol and symbol switching period of the spread spectrum step signal ssc_step.

[0096] The spread spectrum count signal ssc_num is used in conjunction with the edge-accumulated count value of the spread spectrum modulation clock ssc_mod_clk to trigger the sign switching of the spread spectrum step size signal ssc_step.

[0097] The spread spectrum step size signal ssc_step is used to determine the spread spectrum direction and the amplitude of the frequency modulation of the spread spectrum clock ssc_clk for each spread spectrum clock cycle.

[0098] The first spread spectrum signal ssc_dir is the output signal after the spread spectrum step size signal ssc_step has undergone sign switching and two's complement conversion.

[0099] The second spread spectrum signal ssc_depth is the output signal after periodically accumulating the first spread spectrum signal ssc_dir at the frequency of the spread spectrum modulation clock ssc_mod_clk.

[0100] When the spread spectrum direction control unit 1310 detects the rising edge of the spread spectrum modulation clock ssc_mod_clk, it inputs the spread spectrum mode signal ssc_mode and the spread spectrum count signal ssc_num into the spread spectrum phase-locked loop control circuit. When the spread spectrum size control unit 1320 detects the rising edge of the spread spectrum modulation clock ssc_mod_clk, it outputs the second spread spectrum signal ssc_depth. At the same time, the output second spread spectrum signal ssc_depth is used as the input of the spread spectrum size control unit 1320 and added to the first spread spectrum signal ssc_dir. When the spread spectrum size control unit 1320 detects the rising edge of the spread spectrum modulation clock ssc_mod_clk again, it outputs the accumulated second spread spectrum signal ssc_depth.

[0101] The spread spectrum signal conversion unit 1330 is configured to convert the second spread spectrum signal ssc_depth into a fractional division ratio signal u(n), a first phase control code a(n), and a second phase control code b(n).

[0102] For example, the integer division ratio signal M can be provided by an external circuit.

[0103] In the embodiments of this application, by setting a spread spectrum direction control unit 1310, a spread spectrum size control unit 1320, a spread spectrum signal conversion unit 1330, and a clock control unit 1340, the spread spectrum direction control unit 1310 can periodically switch the sign of the spread spectrum step size signal ssc_step to obtain a first spread spectrum signal ssc_dir; the spread spectrum size control unit 1320 can periodically accumulate the first spread spectrum signal ssc_dir to obtain a second spread spectrum signal ssc_depth; the spread spectrum signal conversion unit 1330 can convert the second spread spectrum signal ssc_depth into a portion of the division ratio signal, and can periodically adjust the spread spectrum direction and size when spreading the reference clock ref_clk, so that the frequency of the spread spectrum clock ssc_clk can change smoothly within a certain range, improve the dispersion effect of electromagnetic interference energy, effectively reduce the peak value of electromagnetic interference of high-frequency signals, and expand the application range of the processor chip in high-frequency and high-speed scenarios.

[0104] An embodiment of this application provides a spread spectrum phase-locked loop control circuit. The spread spectrum direction control unit 1310 includes a first spread spectrum direction, a second spread spectrum direction, and a third spread spectrum direction. The first spread spectrum direction sets the initial sign of the spread spectrum step signal ssc_step to negative, and then changes the sign of the spread spectrum step signal ssc_step to the opposite value every first time interval. The second spread spectrum direction sets the initial sign of the spread spectrum step signal ssc_step to positive, and then changes the sign of the spread spectrum step signal ssc_step to the opposite value every first time interval. The third spread spectrum direction sets the initial sign of the spread spectrum step signal ssc_step to positive, and then changes the sign of the spread spectrum step signal ssc_step to the opposite value every second time interval. The first time interval is twice the second time interval.

[0105] When the spread spectrum mode signal ssc_mode is 0, the spread spectrum direction is the first spread spectrum direction, the initial spread spectrum step signal ssc_step is negative, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk increases. When the value of register 1314 in the spread spectrum direction control unit 1310 is equal to the spread spectrum number signal ssc_num, the sign of the spread spectrum step signal ssc_step is changed to positive, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk decreases.

[0106] When the spread spectrum mode signal ssc_mode is 1, the spread spectrum direction is the second spread spectrum direction, the initial spread spectrum step signal ssc_step is positive, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk decreases; when the value of register 1314 in the spread spectrum direction control unit 1310 is equal to the spread spectrum number signal ssc_num, the sign of the spread spectrum step signal ssc_step is changed to negative, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk increases.

[0107] When the spread spectrum mode signal ssc_mode is 2, the spread spectrum direction is the third spread spectrum direction, the initial spread spectrum step signal ssc_step is positive, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk decreases; when the value of register 1314 in the spread spectrum direction control unit 1310 is equal to half of the spread spectrum number signal ssc_num, the sign of the spread spectrum step signal ssc_step is changed to negative, and the frequency of the spread spectrum clock ssc_clk relative to the reference clock ref_clk increases.

[0108] In the embodiments of this application, by setting a first spreading direction, a second spreading direction, and a third spreading direction, the reference clock ref_clk can generate a spreading clock ssc_clk according to different initial spreading directions and different spreading direction variation frequencies. This allows for flexible configuration of the spreading clock ssc_clk according to different application scenarios, enhancing the adaptability of the spreading phase-locked loop control circuit in different working scenarios. While improving the electromagnetic interference suppression effect, it also takes into account the overall flexibility of the spreading phase-locked loop control circuit.

[0109] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 4 As shown, the spread spectrum configuration submodule 1300 also includes an enable control terminal EN; the enable control terminal EN is electrically connected to the clock control unit 1340 and the spread spectrum signal conversion unit 1330 respectively; the enable control terminal EN is configured to receive an enable signal clk_en to control the clock control unit 1340 and the spread spectrum signal conversion unit 1330 to start working; when the enable signal clk_en is at the first level, the spread spectrum phase-locked loop control circuit is in the fixed frequency division working mode, and the spread spectrum configuration submodule 1300 outputs the first group frequency ratio signal; when the enable signal clk_en is at the second level, the spread spectrum phase-locked loop control circuit is in the spread spectrum working mode, and the spread spectrum configuration submodule 1300 outputs the second group frequency ratio signal; wherein, the second group frequency ratio signal can change with time.

[0110] When the enable signal clk_en is at the first level, the clock control unit 1340 cannot provide the spread spectrum modulation clock ssc_mod_clk to the spread spectrum direction control unit 1310 and the spread spectrum size control unit 1320. The first spread spectrum signal ssc_dir and the second spread spectrum signal ssc_depth remain unchanged. The fractional division ratio signal u(n), the first phase control code a(n), and the second phase control code b(n) obtained by the spread spectrum signal conversion unit 1330 based on the second spread spectrum signal ssc_depth cannot change with time. Correspondingly, the frequency division control... If the signals div_ctrl, first compensation control signal comp1, first adjustment signal adj1, second compensation control signal comp2, and second adjustment signal adj2 all remain unchanged over time, the division ratio of the feedback clock fb_clk will not change, the frequency of the divided clock div_clk will not change, and the reference clock ref_clk and the divided clock div_clk cannot be modulated. In this case, the spread spectrum phase-locked loop control circuit can divide the reference clock ref_clk according to a fixed division ratio to generate a spread spectrum clock ssc_clk with a fixed frequency. If the fixed division ratio is a fractional division, there will be a phase deviation between the modulated feedback clock fb_mod and the modulated reference clock ref_mod, and the frequency of the spread spectrum clock ssc_clk will deviate from the preset frequency.

[0111] When the enable signal clk_en is at the second level, the division ratio signal will change once every clock cycle of the spread spectrum modulation clock ssc_mod_clk, and the frequency of the spread spectrum clock ssc_clk will change accordingly.

[0112] For example, the first level can be a low level and the second level can be a high level.

[0113] In the embodiments of this application, when the enable signal clk_en is at the first level, the frequency of the spread spectrum clock ssc_clk remains constant and does not modulate the clock periods of the divider clock div_clk and the reference clock ref_clk. At this time, the spread spectrum phase-locked loop control circuit can be applied to scenarios where there is no need to modulate the divider clock div_clk and the reference clock ref_clk, such as integer frequency division scenarios; or the spread spectrum phase-locked loop control circuit can be applied to scenarios where the phase noise between the divider clock div_clk and the reference clock ref_clk is not sensitive, such as low frequency division scenarios. Setting the enable signal clk_en to the first level can significantly reduce the dynamic power consumption of the spread spectrum phase-locked loop control circuit and simplify the control logic.

[0114] When the enable signal clk_en is at the second level, the clock period of the spread spectrum clock ssc_clk changes periodically with the frequency of the spread spectrum modulation clock ssc_mod_clk. This allows the clock frequency of the spread spectrum clock ssc_clk to fluctuate within a certain range, dispersing electromagnetic interference energy, reducing the peak value of electromagnetic interference, and improving the stability of signal transmission of the processor chip in high-frequency and high-speed scenarios.

[0115] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 5 As shown, the spread spectrum direction control unit 1310 includes a symbol conversion subunit 1311 and a two's complement generation subunit 1312; the symbol conversion subunit 1311 and the two's complement generation subunit 1312 are electrically connected; the symbol conversion subunit 1311 is configured to determine the symbol of the spread spectrum step size signal ssc_step based on the spread spectrum mode signal ssc_mode, the spread spectrum number signal ssc_num, and the number of edges of the spread spectrum modulation clock ssc_mod_clk; the two's complement generation subunit 1312 is configured to convert the spread spectrum step size signal ssc_step into a first spread spectrum signal ssc_dir.

[0116] For example, such as Figure 5 As shown, the spread spectrum direction control unit 1310 further includes a first adder 1313, a register 1314, and a comparator 1315; the register 1314 is electrically connected to the first adder 1313 and the comparator 1315 respectively; the comparator 1315 is electrically connected to the symbol conversion subunit 1311; the first adder 1313 is configured to accumulate the number of edges of the spread spectrum modulation clock ssc_mod_clk to obtain a first accumulated count value; the register 1314 is configured to store the first accumulated count value; the comparator 1315 is configured to... The first accumulated count value is compared with the spread spectrum number signal ssc_num, and the comparison result signal is output. When the first accumulated count value is equal to the spread spectrum number signal ssc_num or half of the spread spectrum number signal ssc_num, the comparison result signal is at the first level. When the comparison result signal is at the first level, the first accumulated count value stored in register 1314 is cleared to zero, and the sign conversion subunit 1311 inverts the sign of the spread spectrum step size signal ssc_step when it receives the comparison result signal as the first level.

[0117] When the spread spectrum direction control unit 1310 detects the rising edge of the spread spectrum modulation clock ssc_mod_clk, the first adder 1313 increments the current value of register 1314 by 1 to obtain the first accumulated count value, and writes the first accumulated count value into register 1314. The comparator 1315 compares the first accumulated count value with the spread spectrum count signal ssc_num in real time.

[0118] When the spread spectrum mode signal ssc_mode is 0 or 1, the comparison result signal is at the first level when the first accumulated count value is equal to the spread spectrum number signal ssc_num. When the spread spectrum mode signal ssc_mode is 2, the comparison result signal is at the first level when the first accumulated count value is equal to half of the spread spectrum number signal ssc_num.

[0119] When the comparison result signal is at the first level, the value of register 1314 is cleared to zero, and the sign conversion subunit 1311 changes the sign of the spread spectrum step signal ssc_step to the opposite value. When the sign of the spread spectrum step signal ssc_step is positive, the first spread spectrum signal ssc_dir generated by the two's complement generation subunit 1312 is the same as the spread spectrum step signal ssc_step; when the sign of the spread spectrum step signal ssc_step is negative, the two's complement generation subunit 1312 inverts each bit of the spread spectrum step signal ssc_step and then adds 1 to obtain the first spread spectrum signal ssc_dir.

[0120] When the comparison result signal is at the second level, the value of register 1314 continues to accumulate the number of rising edges of the spread spectrum modulation clock ssc_mod_clk to obtain the first accumulated count value. The comparison result signal becomes the first level signal when the first accumulated count value is equal to the spread spectrum count signal ssc_num or half of the spread spectrum count signal ssc_num.

[0121] For example, the first level signal can be a high level signal, and the second level signal can be a low level signal.

[0122] In the embodiments of this application, by setting the spread spectrum direction control unit 1310 to include a symbol conversion subunit 1311, a two's complement generation subunit 1312, a first adder 1313, a register 1314, and a comparator 1315, the first spread spectrum signal ssc_dir can flexibly adjust its symbol according to the spread spectrum number signal ssc_num and the spread spectrum mode signal ssc_mode, thereby further controlling the spread spectrum direction. This enables fine control and periodic switching of the spread spectrum direction, significantly improving the flexibility and controllability of the spread spectrum phase-locked loop control circuit, and providing a stable and efficient modulation basis for electromagnetic interference suppression in high-frequency and high-speed scenarios.

[0123] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 5As shown, the spread spectrum size control unit 1320 includes a second adder 1321 and a flip-flop 1322; the second adder 1321 is electrically connected to the flip-flop 1322 and the two's complement generation subunit 1312 respectively; the second adder 1321 is configured to accumulate the first spread spectrum signal ssc_dir to obtain a second accumulated signal; the flip-flop 1322 is configured to periodically output the second accumulated signal at the frequency of the spread spectrum modulation clock ssc_mod_clk to obtain the second spread spectrum signal ssc_depth.

[0124] When the flip-flop 1322 detects the first rising edge of the spread spectrum modulation clock ssc_mod_clk, the flip-flop 1322 outputs the second spread spectrum signal ssc_depth for the first time. At this time, the first spread spectrum signal ssc_dir and the second spread spectrum signal ssc_depth are the same. Subsequently, the second adder 1321 adds the second spread spectrum signal ssc_depth to the first spread spectrum signal ssc_dir to obtain the second accumulated signal, and uses the second accumulated signal as the input of the flip-flop 1322. When the flip-flop 1322 detects the second rising edge of the spread spectrum modulation clock ssc_mod_clk, the second spread spectrum signal ssc_depth output by the flip-flop 1322 is the same as the second accumulated signal. After that, the second adder 1321 continues to add the second spread spectrum signal ssc_depth output by the flip-flop 1322 to the first spread spectrum signal ssc_dir to obtain the second accumulated signal after two accumulations, and uses the second accumulated signal after two accumulations as the input of the flip-flop 1322. When the flip-flop 1322 detects the third rising edge of the spread spectrum modulation clock ssc_mod_clk, the second spread spectrum signal ssc_depth output by the flip-flop 1322 for the third time is the same as the second accumulated signal of the second accumulation. The subsequent steps repeat the above process, which will not be described in detail here.

[0125] In the embodiments of this application, by setting the spread spectrum size control unit 1320 to include a second adder 1321 and a trigger 1322, the second spread spectrum signal ssc_depth can be periodically changed with the rising edge of the spread spectrum modulation clock ssc_mod_clk as the trigger reference, thereby periodically controlling the clock frequency of the spread spectrum clock ssc_clk. This allows the clock frequency of the spread spectrum clock ssc_clk to be precisely adjusted according to the spread spectrum step size signal ssc_step, making the frequency change curve of the spread spectrum clock ssc_clk smooth and controllable. This provides a stable and predictable numerical basis for the spread spectrum operation of the spread spectrum phase-locked loop control circuit, and provides a reliable low-jitter clock generation scheme for the low electromagnetic interference design of high-performance processor chips in high-frequency and high-speed operating modes.

[0126] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 5 As shown, the clock control unit 1340 includes a switch 1341 and a clock buffer subunit 1342; the switch 1341 is electrically connected to the clock buffer subunit 1342; the clock buffer subunit 1342 is electrically connected to the trigger 1322 in the spread spectrum size control unit 1320 and the register 1314 in the spread spectrum direction control unit 1310, respectively; the switch 1341 is configured to turn on or off the transmission path of the spread spectrum modulation clock ssc_mod_clk according to the enable signal clk_en; the enable signal clk_en is the enable signal clk_en output by the enable control terminal EN in the spread spectrum configuration submodule 1300; the clock buffer subunit 1342 is configured to adjust the time when the spread spectrum modulation clock ssc_mod_clk arrives at the trigger 1322 and the register 1314, and to shape the spread spectrum modulation clock ssc_mod_clk.

[0127] In the embodiments of this application, by setting the switch 1341 and the clock buffer subunit 1342 in the clock control unit 1340, the enable signal clk_en can precisely control the conduction and cutoff of the transmission path of the spread spectrum modulation clock ssc_mod_clk through the switch 1341, realizing the precise switching between the fixed frequency division and spread spectrum operating modes of the spread spectrum phase-locked loop control circuit. The clock buffer subunit 1342 can precisely adjust the time when the spread spectrum modulation clock ssc_mod_clk arrives at the trigger 1322 of the spread spectrum size control unit 1320 and the register 1314 of the spread spectrum direction control unit 1310, ensuring that the working timing of the two units is strictly synchronized, avoiding timing misalignment during spread spectrum direction switching and spread spectrum size accumulation, ensuring the overall collaborative working efficiency of the spread spectrum configuration submodule 1300, and also shaping the spread spectrum modulation clock ssc_mod_clk to improve the quality of the clock signal, reduce signal distortion and jitter, ensure the stability of the spread spectrum modulation clock ssc_mod_clk, and ultimately improve the working stability of the overall spread spectrum phase-locked loop control circuit.

[0128] Embodiments of this application provide a spread spectrum phase-locked loop control circuit, such as... Figure 2 or Figure 3As shown, the frequency synthesis submodule 2200 includes a frequency and phase detector 2210, a charge pump 2220, a loop filter 2230, and a voltage-controlled oscillator 2240. The frequency and phase detector 2210 is electrically connected to the charge pump 2220, the charge pump 2220 is electrically connected to the loop filter 2230, the loop filter 2230 is electrically connected to the voltage-controlled oscillator 2240, and the voltage-controlled oscillator 2240 is electrically connected to the frequency division unit 2110 in the feedback submodule 2100. The frequency division clock delay unit 2120 in the feedback submodule 2100 is electrically connected to the frequency and phase detector 2210. The delay compensation unit 1220 in the reference clock delay submodule 1200 is electrically connected to the frequency and phase detector 2210.

[0129] The frequency and phase detector 2210 is configured to detect the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod, and output the corresponding phase detection control signal according to the detection result; The charge pump 2220 is configured to perform charge and discharge operations based on a phase detection control signal, converting the phase detection control signal into a phase detection current; The loop filter 2230 is configured to perform low-pass filtering on the phase detection current, filter out high-frequency noise in the phase detection current, and output a stable voltage control signal. The voltage-controlled oscillator 2240 is configured to adjust its own oscillation frequency according to the amplitude change of the voltage control signal to generate a spread spectrum clock ssc_clk.

[0130] In the embodiments of this application, by setting up a frequency and phase detector 2210, a charge pump 2220, a loop filter 2230 and a voltage-controlled oscillator 2240, the phase difference between the modulation feedback clock fb_mod and the modulation reference clock ref_mod can be accurately detected, high-frequency noise of the signal can be filtered out, and the frequency of the spread spectrum clock ssc_clk can be dynamically and accurately adjusted according to the processed signal. This is a key guarantee for achieving low electromagnetic interference and high signal integrity.

[0131] Embodiments of this application provide a processor chip, such as Figure 6 As shown, it can achieve the same technical effect as the spread spectrum phase-locked loop control circuit in the previous embodiment. To avoid repetition, it will not be described again here.

[0132] For example, the processor chip can be any one of a central processing unit, graphics processing unit, digital signal processor, field-programmable gate array, application-specific integrated circuit, system-on-a-chip, microcontroller, or microprocessor, or it can be a computing device, mobile terminal, communication device, Internet of Things device, vehicle device, wearable device, or server that includes any of the above processor chips.

[0133] Embodiments of this application provide a control method for a spread spectrum phase-locked loop control circuit, such as... Figure 7As shown, the control method includes: S1. Obtain the frequency division ratio signal, reference clock ref_clk, and feedback clock fb_clk; S2. Generate a first adjustment signal adj1, a second adjustment signal adj2, and a frequency division control signal div_ctrl based on the frequency division ratio signal; S3. Modulate the feedback clock fb_clk according to the first adjustment signal adj1 and the frequency division control signal div_ctrl to generate the modulated feedback clock fb_mod; S4. Modulate the reference clock ref_clk according to the second adjustment signal adj2 to generate the modulated reference clock ref_mod; The second adjustment signal adj2 is calculated based on the difference between the clock period of the modulation feedback clock fb_mod and the clock period of the reference clock ref_clk; the edge alignment of the modulation feedback clock fb_mod and the modulation reference clock ref_mod is set.

[0134] In the embodiments of this application, a first adjustment signal adj1, a second adjustment signal adj2, and a frequency division control signal div_ctrl are generated based on the frequency division ratio signal. The feedback clock fb_clk is modulated according to the first adjustment signal adj1 and the frequency division control signal div_ctrl to generate a modulated feedback clock fb_mod. The reference clock ref_clk is modulated according to the second adjustment signal adj2 to generate a modulated reference clock ref_mod. The second adjustment signal adj2 is calculated based on the difference between the clock period of the modulated feedback clock fb_mod and the clock period of the reference clock ref_clk. The edge alignment setting of the modulated feedback clock fb_mod and the modulated reference clock ref_mod can effectively reduce the phase difference between the modulated feedback clock fb_mod and the modulated reference clock ref_mod, thereby reducing the period jitter and phase drift of the spread spectrum clock ssc_clk caused by the phase difference, and significantly improving the stability of the spread spectrum clock ssc_clk. While achieving spectrum energy dispersion and reducing electromagnetic interference peaks of the spread spectrum clock ssc_clk, it can also take into account the stability and frequency accuracy of the spread spectrum clock ssc_clk, ultimately effectively improving the signal integrity and timing stability of the processor chip during operation.

[0135] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A spread-spectrum phase-locked loop control circuit, characterized in that, It includes a spread spectrum function module and a phase-locked loop module. The spread spectrum function module includes a spread spectrum modulation submodule and a reference clock delay submodule. The phase-locked loop module includes a feedback submodule. The spread spectrum modulation submodule is electrically connected to the feedback submodule and the reference clock delay submodule, respectively. The spread spectrum modulation submodule is configured to generate a first adjustment signal, a second adjustment signal, and a frequency division control signal based on the frequency division ratio signal; The feedback submodule is configured to modulate the feedback clock according to the first adjustment signal and the frequency division control signal to generate a modulated feedback clock; The reference clock delay submodule is configured to modulate the reference clock according to the second adjustment signal to generate a modulated reference clock; The second adjustment signal is calculated based on the difference between the clock period of the modulation feedback clock and the clock period of the reference clock. The edges of the modulation feedback clock and the modulation reference clock are aligned.

2. The spread spectrum phase-locked loop control circuit according to claim 1, characterized in that, The spread spectrum modulation submodule includes a first modulation unit and a second modulation unit; the feedback submodule includes a frequency division unit and a frequency division clock delay unit. The first modulation unit is electrically connected to the frequency division unit; the second modulation unit is electrically connected to the frequency division clock delay unit; the frequency division unit is electrically connected to the frequency division clock delay unit. The first modulation unit is configured to generate the frequency division control signal and the first compensation control signal based on the frequency division ratio signal; the frequency division unit is configured to generate a frequency division clock based on the frequency division control signal and the feedback clock; The second modulation unit is configured to generate the first adjustment signal and the second compensation control signal based on the frequency division ratio signal; The frequency division clock delay unit is configured to generate the modulation feedback clock based on the first adjustment signal and the frequency division clock.

3. The spread spectrum phase-locked loop control circuit according to claim 2, characterized in that, The spread spectrum modulation submodule further includes a third modulation unit; the reference clock delay submodule includes an offset calculation unit and a delay compensation unit. The bias calculation unit is electrically connected to the delay compensation unit, the first modulation unit, the second modulation unit, and the third modulation unit, respectively. The third modulation unit is configured to generate the second adjustment signal based on the frequency division ratio signal; The bias calculation unit is configured to calculate a bias signal based on a preset bias value, the first compensation control signal, the second compensation control signal, and the second adjustment signal. The delay compensation unit is configured to generate the modulation reference clock based on the bias signal and the reference clock.

4. The spread spectrum phase-locked loop control circuit according to claim 1, characterized in that, The spread spectrum function module also includes a spread spectrum configuration submodule, which includes a spread spectrum direction control unit, a spread spectrum size control unit, a spread spectrum signal conversion unit, and a clock control unit; The spread spectrum size control unit is electrically connected to the spread spectrum direction control unit and the spread spectrum signal conversion unit, respectively; the clock control unit is electrically connected to the spread spectrum direction control unit and the spread spectrum size control unit, respectively. The clock control unit is configured to provide a spread spectrum modulation clock to the spread spectrum direction control unit and the spread spectrum size control unit; The spread spectrum direction control unit is configured to periodically switch the sign of the spread spectrum step size signal at the clock frequency of the spread spectrum modulation clock, based on the spread spectrum mode signal and the spread spectrum number signal, to obtain a first spread spectrum signal; The spread spectrum size control unit is configured to periodically accumulate the first spread spectrum signal at the clock frequency of the spread spectrum modulation clock to obtain the second spread spectrum signal; The spread spectrum signal conversion unit is configured to convert the second spread spectrum signal into a portion of the frequency division ratio signal.

5. The spread spectrum phase-locked loop control circuit according to claim 4, characterized in that, The spread spectrum direction control unit includes a first spread spectrum direction, a second spread spectrum direction, and a third spread spectrum direction; The first spreading direction involves setting the initial sign of the spreading step signal to negative, and then changing the sign of the spreading step signal to the opposite value every first time interval. The second spreading direction involves setting the initial sign of the spreading step signal to positive, and then changing the sign of the spreading step signal to the opposite value every first time interval. The third spreading direction involves setting the initial sign of the spreading step signal to positive, and then changing the sign of the spreading step signal to the opposite value every second time interval. The first time is twice the second time.

6. The spread spectrum phase-locked loop control circuit according to claim 4, characterized in that, The spread spectrum configuration submodule also includes an enable control terminal; The enable control terminal is electrically connected to the clock control unit and the spread spectrum signal conversion unit, respectively. The enable control terminal is configured to receive an enable signal to control the clock control unit and the spread spectrum signal conversion unit to start working. When the enable signal is at the first level, the spread spectrum phase-locked loop control circuit is in a fixed frequency division mode, and the spread spectrum configuration submodule outputs the first set of the frequency division ratio signals; When the enable signal is at the second level, the spread spectrum phase-locked loop control circuit is in the spread spectrum working mode, and the spread spectrum configuration submodule outputs the second set of the frequency division ratio signals; The frequency division ratio signal in the second group can change over time.

7. The spread spectrum phase-locked loop control circuit according to claim 4, characterized in that, The spread spectrum direction control unit includes a symbol conversion subunit and a two's complement generation subunit; The symbol conversion subunit and the two's complement generation subunit are electrically connected; The symbol conversion subunit is configured to determine the symbol of the spread spectrum step size signal based on the spread spectrum mode signal, the spread spectrum number signal, and the number of edges of the spread spectrum modulation clock; The complement generation subunit is configured to convert the spread spectrum step size signal into the first spread spectrum signal.

8. The spread spectrum phase-locked loop control circuit according to claim 7, characterized in that, The spread spectrum direction control unit also includes a first adder, a register, and a comparator; The registers are electrically connected to the first adder and the comparator, respectively. The comparator is electrically connected to the symbol conversion subunit; The first adder is configured to accumulate the number of spread spectrum modulation clock edges to obtain a first accumulated count value; The register is configured to store the first accumulated count value; The comparator is configured to compare the first accumulated count value with the spread spectrum number signal and output a comparison result signal; Wherein, when the first accumulated count value is equal to the spread spectrum number signal or half of the spread spectrum number signal, the comparison result signal is at the first level; When the comparison result signal is at the first level, the first accumulated count value stored in the register is cleared to zero, and the sign conversion subunit inverts the sign of the spread spectrum step size signal when it receives the comparison result signal as the first level.

9. The spread spectrum phase-locked loop control circuit according to claim 7, characterized in that, The spread spectrum size control unit includes a second adder and a trigger; The second adder is electrically connected to both the flip-flop and the two's complement generation subunit. The second adder is configured to accumulate the first spread spectrum signal to obtain a second accumulated signal; The trigger is configured to periodically output the second accumulated signal at the frequency of the spread spectrum modulation clock to obtain the second spread spectrum signal.

10. The spread spectrum phase-locked loop control circuit according to claim 4, characterized in that, The clock control unit includes a switch and a clock buffer subunit; The switch is electrically connected to the clock buffer subunit; the clock buffer subunit is electrically connected to the trigger in the spread spectrum size control unit and the register in the spread spectrum direction control unit, respectively; The switch is configured to turn on or off the transmission path of the spread spectrum modulation clock according to an enable signal; the enable signal is the enable signal output by the enable control terminal in the spread spectrum configuration submodule. The clock buffer subunit is configured to adjust the time when the spread spectrum modulation clock arrives at the flip-flop and the register, and to shape the spread spectrum modulation clock.

11. The spread spectrum phase-locked loop control circuit according to claim 1, characterized in that, The phase-locked loop module also includes a frequency synthesis submodule; The frequency synthesis submodule is electrically connected to the feedback submodule and the reference clock delay submodule, respectively. The frequency synthesis submodule is configured to synthesize a spread spectrum clock based on the modulation feedback clock and the modulation reference clock.

12. The spread spectrum phase-locked loop control circuit according to claim 11, characterized in that, The frequency synthesis submodule includes a frequency and phase detector, a charge pump, a loop filter, and a voltage-controlled oscillator. The frequency and phase detector is electrically connected to the charge pump, the charge pump is electrically connected to the loop filter, the loop filter is electrically connected to the voltage-controlled oscillator, and the voltage-controlled oscillator is electrically connected to the frequency division unit in the feedback submodule. The frequency division clock delay unit in the feedback submodule is electrically connected to the frequency and phase detector. The delay compensation unit in the reference clock delay submodule is electrically connected to the frequency and phase detector.

13. A processor chip, characterized in that, Includes the spread spectrum phase-locked loop control circuit as described in any one of claims 1 to 12.

14. A control method for a spread spectrum phase-locked loop control circuit, characterized in that, The control method includes: Acquire the frequency division ratio signal, reference clock, and feedback clock; A first adjustment signal, a second adjustment signal, and a frequency division control signal are generated based on the frequency division ratio signal; The feedback clock is modulated according to the first adjustment signal and the frequency division control signal to generate a modulated feedback clock; The reference clock is modulated according to the second adjustment signal to generate a modulated reference clock; The second adjustment signal is calculated based on the difference between the clock period of the modulation feedback clock and the clock period of the reference clock; the edges of the modulation feedback clock and the modulation reference clock are aligned.

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