FCCSP packaging structure, manufacturing method thereof and electronic device

Abstract

The application discloses a FCCSP packaging structure and a manufacturing method thereof and electronic equipment, and belongs to the technical field of semiconductors, and comprises a substrate, a flip chip arranged on the surface of the substrate, a heat-conducting layer arranged on the surface of the flip chip, a heat sink bonded with the heat-conducting layer, and a plastic sealing layer covering the sidewall of the flip chip, the sidewall of the heat-conducting layer and the sidewall of the heat sink, wherein at least part of the heat sink is exposed to the plastic sealing layer. Compared with the prior art, the application combines the heat sink and the flip chip through the heat-conducting layer first, then performs overall plastic sealing and exposes the heat sink, thereby omitting the difficult step of etching and cutting the thick heat sink, so that the process is simplified and the overall profile height of the package is controlled under the premise that the heat sink has sufficient thickness to improve the heat dissipation efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an FCCSP package structure, its fabrication method, and an electronic device thereof. Background Technology

[0002] Flip Chip Chip Scale Package (FCCSP) is an advanced packaging technology that directly interconnects the active surface of a chip to the substrate via bumps. It offers advantages such as high density and high performance, and is widely used in fields such as controller chips with stringent size and performance requirements. To improve heat dissipation, existing technologies involve mounting heat sinks onto the already encapsulated package structure and exposing part of the heat sink through etching. However, etching processes struggle to handle thicker heat sinks, resulting in limited heat dissipation enhancement. Summary of the Invention

[0003] The purpose of this invention is to provide an FCCSP packaging structure, its manufacturing method, and an electronic device, which can improve the heat dissipation performance of the chip.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides an FCCSP package structure, comprising: a substrate; a flip chip disposed on the surface of the substrate; a thermally conductive layer disposed on the surface of the flip chip; a heat sink bonded to the thermally conductive layer; and a molding compound layer covering the sidewalls of the flip chip, the sidewalls of the thermally conductive layer, and the sidewalls of the heat sink; wherein at least a portion of the heat sink is exposed in the molding compound layer.

[0005] According to one embodiment of the present invention, a filler layer is further included, wherein the flip chip is flip-bonded to one side surface of the substrate by a plurality of solder joints, and the filler layer fills the space between the flip chip and the substrate and covers the plurality of solder joints.

[0006] According to one embodiment of the present invention, the thermally conductive layer is a thermally conductive thin film or a thermally conductive interface material layer.

[0007] According to one embodiment of the present invention, the thermally conductive interface material layer is a thermally conductive adhesive layer or a thermally conductive paste layer.

[0008] According to one embodiment of the present invention, the molding compound is made of an organic resin material.

[0009] According to one embodiment of the present invention, the top surface of the heat sink is exposed outside the molding compound.

[0010] According to one embodiment of the present invention, the top surface of the heat sink is flush with the top surface of the molding compound.

[0011] According to one embodiment of the present invention, the substrate further includes solder balls disposed on the surface of the substrate.

[0012] Secondly, the present invention also provides a method for manufacturing an FCCSP package structure, the method being applied to the manufacturing of the FCCSP package structure of the above embodiments, comprising: providing the substrate; mounting the flip chip on one side of the substrate; mounting the heat sink on the surface of the flip chip facing away from the substrate, wherein the heat sink is bonded to the surface of the flip chip through the thermally conductive layer; and forming a molding compound layer on the sidewall of the flip chip, the sidewall of the thermally conductive layer, and the sidewall of the heat sink through a thin-film assisted molding process.

[0013] Thirdly, the present invention also provides an electronic device, including the FCCSP package structure of the above embodiments, or the FCCSP package structure obtained by the manufacturing method of the FCCSP package structure of the above embodiments.

[0014] The beneficial effects of the present invention include at least the following: The FCCSP packaging structure of this invention features a heat sink connected to a flip chip via a thermally conductive layer. A molding compound covers the flip chip and the sidewalls of the heat sink, exposing a portion of the heat sink. This structure allows the heat sink to directly conduct heat generated during chip operation and efficiently dissipate it to the external environment through the exposed portion.

[0015] This invention eliminates the difficult step of etching and cutting thick heat sinks by first bonding the heat sink and flip chip through a thermally conductive layer, and then performing overall molding and exposing the heat sink. This process helps to simplify the process and control the overall profile height of the package while ensuring that the heat sink has sufficient thickness to improve heat dissipation efficiency. At the same time, the molding layer's coverage of the flip chip and the sidewalls of the heat sink enhances the overall integrity and reliability of the structure. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the FCCSP packaging structure of the present invention; Figure 2 This is a flowchart illustrating the manufacturing process of the FCCSP package structure of the present invention. Figure 3 This is a flowchart of the method for manufacturing the FCCSP package structure of the present invention.

[0018] Explanation of main labels: 1. Substrate; 2. Flip chip; 3. Thermal conductive layer; 4. Heat sink; 5. Molding layer; 6. Filler layer; 7. Solder ball. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Furthermore, the following descriptions of various embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments that can be implemented in this application. Directional terms used in this application, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying illustrations. Therefore, the directional terms used are for better and clearer explanation and understanding of this application, and are not intended to indicate or imply that the referred device or element must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed," "connected," "linked," and "set on" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two or three, and "multiple sets" means at least two sets, such as two or three sets, unless otherwise explicitly specified.

[0023] Please refer to Figure 1 This application provides an FCCSP packaging structure, including: a substrate 1 (i.e., Figure 1 "Substrate" in the text); flip chip 2 (i.e. Figure 1The “Silicon die” in the text is disposed on the surface of the substrate 1; the thermally conductive layer 3 (i.e. Figure 1 The “Film / TIM” in the figure is disposed on the surface of the flip chip 2; the heat sink 4 (i.e. Figure 1 The “lid” in the text is bonded to the thermally conductive layer 3; the molding layer 5 (i.e. Figure 1 The "mold compound" in this embodiment covers the sidewalls of the flip chip 2, the sidewalls of the thermally conductive layer 3, and the sidewalls of the heat sink 4; wherein at least a portion of the heat sink 4 is exposed outside the molding compound 5. The heat sink 4 is bonded to the back of the flip chip 2 via the thermally conductive layer 3, forming an efficient heat conduction path from the chip to the heat sink 4. Heat generated from the flip chip 2 is rapidly transferred to the heat sink 4 via the thermally conductive layer 3, and then dissipated directly to the external environment from the portion of the heat sink 4 exposed outside the molding compound 5. Simultaneously, the molding compound 5 covers the flip chip 2, the thermally conductive layer 3, and the sidewalls of the heat sink 4, providing mechanical and environmental protection for the internal structure. This embodiment, by first bonding the heat sink 4 to the flip chip 2 via the thermally conductive layer 3, and then performing overall molding and exposing the heat sink 4, eliminates the difficult step of etching and cutting the thick heat sink 4, thereby simplifying the process and controlling the overall profile height of the package while ensuring that the heat sink 4 has sufficient thickness to improve heat dissipation efficiency. Meanwhile, the molding layer 5, which covers the sidewalls of the flip chip 2 and the heat sink 4, enhances the overall integrity and reliability of the structure.

[0024] Optionally, the molding compound 5 is made of an organic resin material. The portion of the heat sink 4 exposed outside the molding compound 5 can be its top surface, or its top surface and part of its side surface. The substrate 1 can be an organic substrate, a ceramic substrate, or a silicon interposer with a redistribution layer. The electrical connection between the flip chip 2 and the substrate 1 is achieved through solder bumps, copper pillar bumps, or microbumps.

[0025] In some embodiments, the FCCSP package structure further includes a filler layer 6 (i.e. Figure 1The term "Underfill" refers to the process where the flip chip 2 is flip-bonded to one side of the substrate 1 via multiple solder joints. The filler layer 6 fills the space between the flip chip 2 and the substrate 1, covering the solder joints. When the flip chip 2 is flip-bonded to the substrate 1 via the multiple solder joints, the filler layer 6 flows into and fills the gap between the flip chip 2 and the substrate 1, covering these solder joints. After curing, the filler layer 6 can share the mechanical stress on the solder joints and prevent moisture, contaminants, and other substances from corroding the solder joints. In some embodiments, the solder joints of the flip chip 2 are small in size and are prone to failure due to stress concentration under temperature cycling or mechanical shock. This embodiment, by providing the filler layer 6 to cover the multiple solder joints, can effectively buffer and disperse stress, reducing the risk of solder joint fatigue cracking. This, in turn, improves the long-term reliability and service life of the packaging structure.

[0026] Specifically, the filler layer 6 is a capillary underfill adhesive or a non-flowing underfill adhesive, and its material is usually epoxy resin. The filler layer 6 completely fills the gap between the flip chip 2 and the substrate 1, and covers all solder joints.

[0027] In some embodiments, the thermally conductive layer 3 is a thermally conductive thin film or a thermally conductive interface material layer. The thermally conductive layer 3 serves as the interface material between the heat sink 4 and the flip chip 2. Its physical form can be a pre-formed solid thermally conductive thin film or a thermally conductive interface material layer formed after coating. The thermally conductive thin film facilitates pre-processing and mounting, while the thermally conductive interface material layer can better fill microscopically uneven surfaces, reducing contact thermal resistance. In some embodiments, when mounting the heat sink 4, if the heat sink 4 is in direct contact with the chip surface, a large number of tiny air gaps will exist due to surface roughness, severely hindering heat conduction. This embodiment, by setting the thermally conductive layer 3, whether it is a thermally conductive thin film or a thermally conductive interface material layer, can effectively fill the air gaps between the interfaces, establishing a continuous low-thermal-resistance thermal path. This helps to further optimize the heat conduction efficiency from the chip to the heat sink 4.

[0028] Optionally, the thermally conductive film is a pre-formed graphene film, a polyimide-based thermally conductive film, or a metal foil thermally conductive tape with adhesive on one or both sides. The thermally conductive interface material layer is a coated phase change thermally conductive material, silicone grease, or a gel-like thermally conductive material.

[0029] In some embodiments, the thermally conductive interface material layer is a thermally conductive adhesive layer or a thermally conductive paste layer. When the thermally conductive layer 3 is a thermally conductive interface material layer, its specific components may be a thermally conductive adhesive with adhesive function or a thermally conductive paste with a high thermal conductivity.

[0030] Specifically, the thermally conductive adhesive layer is a silicone thermally conductive adhesive, epoxy thermally conductive adhesive, or acrylate thermally conductive adhesive. It is fluid before curing and is applied by dispensing or printing. After curing, it forms a solid adhesive layer. The thermally conductive paste layer is a silicone oil-based thermally conductive paste, hydrocarbon oil-based thermally conductive paste, or synthetic oil-based thermally conductive paste. Its main components are a mixture of thermally conductive filler and carrier oil. It usually does not have strong adhesion and needs to be fixed by mechanical pressing between the heat sink 4 and the chip or by the surrounding structure.

[0031] In some embodiments, the heat sink 4 is made of copper or a copper alloy. Copper has extremely high thermal conductivity, enabling it to rapidly diffuse heat from the area in contact with the thermally conductive layer 3 to the entire heat sink 4, and then efficiently dissipate it through its exposed surface. In some embodiments, the choice of material for the heat sink 4 directly affects its heat dissipation capability. If a metal with low thermal conductivity is used, even with good contact with the chip, heat will accumulate in the contact area and cannot be effectively dissipated. This embodiment, by limiting the material of the heat sink 4 to high thermal conductivity copper or a copper alloy, ensures that heat is rapidly and evenly distributed within the heat sink 4, fully utilizing its exposed surface area for heat dissipation. This helps to further improve the overall heat dissipation performance of the package.

[0032] Optionally, the copper alloy is a copper-tungsten alloy, a copper-molybdenum alloy, or a copper alloy doped with small amounts of other elements to improve mechanical properties. The heat sink 4 can be formed by stamping, etching, or machining, and its surface can be plated with nickel, silver, or gold to improve corrosion resistance or weldability.

[0033] In some embodiments, the top surface of the heat sink 4 is exposed to the molding compound 5. The top surface of the heat sink 4 is not covered by the molding compound 5 and is directly exposed. This allows the heat sink 4 to have the largest effective heat dissipation area, and heat can be dissipated directly from the top surface into the air through convection and radiation. This embodiment increases the surface area of ​​the heat sink 4 in contact with the air by exposing the top surface of the heat sink 4 to the molding compound 5. This enables more efficient dissipation of heat generated by the chip, helping to meet the heat dissipation requirements of higher power consumption chips.

[0034] Specifically, the molding compound 5 completely covers the sides of the heat sink 4, but the entire top surface of the heat sink 4 remains exposed and uncovered by any molding compound. This can be achieved by using a mold and a film to precisely define the flow range of the molding compound in a film-assisted molding process.

[0035] In some embodiments, the top surface of the heat sink 4 is flush with the top surface of the molding compound 5. The top surface of the heat sink 4 and the top surface of the molding compound 5 are on the same plane, forming a flat upper surface for the package. This structure is typically achieved in thin-film assisted molding processes by pressing the top surface of the heat sink 4 together with a mold while simultaneously molding the molding compound 5. In some embodiments, the flatness of the upper surface of the package structure affects subsequent stacking or heat sink installation. If the heat sink 4 protrudes from the molding compound 5, it hinders flat mounting; if it is recessed, it can accumulate dust or affect heat sink contact. This embodiment, by making the top surface of the heat sink 4 flush with the top surface of the molding compound 5, results in a neat overall package structure and a flat surface. This not only facilitates subsequent assembly operations but also provides convenient conditions for directly attaching a larger area heat sink or cold plate to the top surface of the heat sink 4, thereby contributing to better heat dissipation.

[0036] Optionally, by controlling the pressing depth of the mold in the thin-film assisted molding process, the top surface of the mold cavity can be made to contact and apply pressure to the top surface of the heat sink 4, thereby ensuring that the top surface of the heat sink 4 and the top surface of the finally formed plastic seal 5 are coplanar while forming the plastic seal 5. Alternatively, the plastic seal 5 can be formed first so that it is slightly higher than the heat sink 4, and then the plastic seal 5 can be ground to be flush with the top surface of the heat sink 4 through a grinding process.

[0037] In some embodiments, the FCCSP package structure further includes solder balls 7 (i.e. Figure 1 The solder balls 7 (referred to as "balls") are disposed on the surface of the substrate 1. These solder balls 7 serve as input / output pins for the package, used to solder the package structure to a circuit board. The chip needs to interact with external circuits via electrical connections for signal and power communication. This embodiment provides a standardized and reliable electrical interconnection method by using the solder balls 7. This allows the enhanced heat dissipation FCCSP package to be easily integrated into the circuit systems of various electronic devices, thereby expanding its application range.

[0038] Specifically, the solder ball 7 is a tin-silver-copper alloy solder ball, a tin-bismuth alloy solder ball, or a pure tin solder ball. The solder ball 7 is disposed on the pads on the lower surface of the substrate 1 through a ball-mounting process, and can form a strong electrical and mechanical connection with the substrate 1 through reflow soldering. Alternatively, the electrical connection terminals on the lower surface of the substrate 1 can also be planar grid array pins or ball grid array solder balls.

[0039] Please refer to Figure 2 and Figure 3 This embodiment also provides a method for manufacturing an FCCSP package structure. The method is applied to manufacturing the FCCSP package structure described in the above embodiment and includes: S1. Provide the substrate 1; S2. The flip chip 2 is attached to one side of the substrate 1; S3. The heat sink 4 is attached to the surface of the flip chip 2 facing away from the substrate 1, wherein the heat sink 4 is attached to the surface of the flip chip 2 through the thermally conductive layer 3. S4. A molding layer 5 is formed on the sidewall of the flip chip 2, the sidewall of the thermal conductive layer 3, and the sidewall of the heat sink 4 using a thin film-assisted molding process. S5. Solder balls 7 are formed on the pads on the lower surface of substrate 1 by a ball-planting process.

[0040] This fabrication method first mounts a flip chip 2 onto a substrate 1, then mounts a heat sink 4 onto the back of the flip chip 2 through a thermally conductive layer 3, and finally forms a molding compound 5 using a thin-film assisted molding process. In the thin-film assisted molding process, the thin film presses against the top surface of the heat sink 4 to prevent molding compound from overflowing onto it. Simultaneously, the mold cavity defines the shape of the molding compound 5, ensuring it covers the chip, the thermally conductive layer 3, and the sidewalls of the heat sink 4. This embodiment avoids complex etching steps by first mounting the heat sink 4 and then using a thin-film assisted molding process to complete the sidewall molding in one step, improving the heat dissipation performance of the flip chip 2, controlling the overall package thickness, and adapting to applications requiring ultra-thin packaging with enhanced heat dissipation performance.

[0041] Specifically, the steps for mounting the flip chip 2 on one side of the substrate 1 include the following: The first step involves thinning and dicing the wafer after bump fabrication to obtain individual flip chips 2. Simultaneously, the substrate 1 is cleaned and pre-treated. A thin, uniform layer of flux is applied to the bonding areas of the substrate 1 using methods such as printing, spraying, or dipping. The main function of the flux is to remove oxides from the metal surface during subsequent reflow, promote solder wetting and flow, and ensure the formation of good solder joints.

[0042] The second step involves using a high-precision pick-and-place machine to pick up a single flip chip 2 from the wafer frame or carrier using a vacuum nozzle. A machine vision system simultaneously identifies the bump array on the flip chip 2 and the corresponding pad pattern on the substrate 1, performing sub-micron level precision alignment. After alignment, the pick-and-place machine places the flip chip 2 face down (i.e., circuit side facing the substrate 1) onto the designated position on the substrate 1, which has been coated with flux. At this point, the bumps and pads make initial contact and are temporarily adhered and fixed by the flux.

[0043] The third step involves transferring the substrate 1, with the flip chip 2 placed on it, to a reflow oven for heating under a controlled temperature profile. During heating, the flux first activates and cleans the surfaces of the bumps (usually tin-based solder) and the substrate 1 pads (usually plated with gold or nickel). When the temperature rises above the solder melting point, the solder in the bumps melts and, under the influence of liquid surface tension and flux, wets and covers the substrate 1 pads, forming an intermetallic compound (such as Cu6Sn5). After passing through a cooling zone, the molten solder solidifies, forming a strong, electrically and thermally conductive solder joint between each bump and pad, thus completing the electrical interconnection and mechanical fixation between the flip chip 2 and the substrate 1.

[0044] In the fourth step, after reflow soldering, the flip chip 2 and the substrate 1 are connected only by discrete solder joints, leaving gaps. To improve reliability, underfilling is necessary. Using precision dispensing equipment, liquid epoxy resin underfill is injected along one or both edges of the chip. Under capillary action, the adhesive automatically flows to the bottom of the chip, filling all the gaps between solder joints and the entire gap between the chip and the substrate 1. After filling, the underfill is cured by heating, forming a robust filler layer 6. This filler layer 6 effectively distributes the thermal and mechanical stresses on the solder joints, preventing them from cracking due to fatigue, while also protecting them from environmental factors such as moisture and ion contamination.

[0045] Specifically, the heat sink 4 is mounted on the surface of the flip chip 2 facing away from the substrate 1, and the specific steps for the heat sink 4 to be attached to the surface of the flip chip 2 through the thermally conductive layer 3 are as follows: The first step, before mounting, is to clean the back side (silicon substrate surface) of the flip chip 2 and the bonding surface of the heat sink 4 to remove dust, oxides, or organic contaminants, ensuring good interface contact for the subsequent thermal conductive layer 3. The back side of the chip is usually silicon, while the bonding surface of the heat sink 4 needs to be surface activated or coated with a protective layer (such as nickel plating) depending on the material (e.g., copper) to improve adhesion and prevent oxidation.

[0046] The second step is the application of the heat-conducting layer 3. Depending on the type of heat-conducting layer 3 selected, there are two main application methods: Method 1: Pre-formed thermally conductive film attachment. If the thermally conductive layer 3 is a solid thermally conductive film (such as a thermally conductive graphite film with pressure-sensitive adhesive, a polyimide-based thermally conductive film, or a metal foil thermally conductive tape), it is first precisely pre-cut according to the size of the flip chip 2, and then one side is attached to the bonding surface of the heat sink 4 using a film attachment device, or directly attached to the back of the chip.

[0047] Method 2: Liquid thermal interface material coating. If thermal conductive layer 3 is thermal adhesive or thermal paste, a precision dispensing machine or printing equipment (such as screen printing) is used to apply a specific amount of material in a specific pattern (such as an "X", multiple dots, or an array) to the central area on the back of the chip. The coating amount needs to be precisely controlled to ensure that the interface gaps are filled after lamination without excessive adhesive overflow.

[0048] The third step involves using high-precision mounting equipment to pick up the pre-applied thermal conductive film or the heat sink 4 to be mounted. Using a machine vision system, the heat sink 4 is precisely aligned with the flip chip 2 below in the XY direction and angle, ensuring that the heat sink 4 completely covers the heat-generating area of ​​the chip and leaves sufficient space around it for subsequent molding compound filling. After alignment, the equipment moves the heat sink 4 downwards, pressing it against the back of the chip coated with the thermal conductive layer 3 (or with a pre-applied thermal conductive film) at a set pressure and for a certain time. This pressure causes the thermal conductive layer 3 material (especially liquid TIM) to flow fully, filling all air gaps caused by microscopic unevenness between the chip back and the bonding surface of the heat sink 4.

[0049] The fourth step, if using thermally conductive adhesive, requires heat curing after lamination. The components are placed in an oven or heated online, and cured according to the material's required temperature profile, causing the adhesive layer to transform from a liquid or viscous state to a solid state, forming a solid layer with sufficient adhesive strength and thermal conductivity. If using thermal paste or pre-cured thermally conductive film, the lamination step itself completes the main mechanical fixation, establishing the heat transfer path. Thermal paste fills gaps using its paste-like properties, while pre-cured films rely on their own adhesiveness for fixation.

[0050] Specifically, the steps for forming the molding compound 5 on the sidewalls of the flip chip 2, the thermal conductive layer 3, and the heat sink 4 using a thin-film assisted molding process are as follows: The first step involves loading the substrate 1 assembly (i.e., the semi-finished product), which has already undergone flip chip 2 bonding, underfill, and heat sink 4 mounting, onto the carrier or frame of the thin-film assisted molding equipment. Simultaneously, the equipment loads a roll of specialized auxiliary film. This film is typically a high-temperature resistant polymer film with specific surface properties (such as low viscosity), and its size is larger than the product array.

[0051] The second step involves mold closing and film pressing. The mold consists of an upper mold and a lower mold. The lower mold has a cavity to accommodate the substrate 1 assembly and define the shape of the molding compound 5. The upper mold first pulls the auxiliary film from the roll and tensions it flat on the top of the mold. Then, the upper mold carries the film downwards to close with the lower mold. During the mold closing process, the film is precisely pressed against the top surface of the heat sink 4 and the frame or carrier surrounding the substrate 1 assembly, forming a physical sealing barrier. The tension of the film ensures close contact with the top surface of the heat sink 4, while the adhesion is controlled to a level that allows for easy separation after mold opening.

[0052] The third step involves closing the mold and sealing the film. Molten epoxy molding compound (EMC) is then injected through the injection port into the sealed space formed by the mold cavity and the film. Since the top surface of the heat sink 4 is completely covered and sealed by the film, the molten EMC cannot flow onto the top surface of the heat sink 4. The EMC can only flow below the film, within the other spaces defined by the mold cavity. Therefore, the EMC fills and coats the sidewalls of the flip chip 2, the thermally conductive layer 3, and the heat sink 4, while also filling other voids on the substrate 1. Subsequently, it is heated and cured at a set temperature and time, causing the EMC to transform from a liquid to a solid state, forming a robust molding layer 5.

[0053] Fourth, after curing, the upper mold is lifted. Since the film only adheres slightly, it will peel off smoothly from the surface of the cured molding layer 5 and the top surface of the heat sink 4, and be rolled up or removed. At this time, the top surface of the heat sink 4 remains completely clean and exposed, while the molding layer 5 is precisely formed at the preset side wall position, and its top surface height is precisely controlled by the depth of the mold cavity.

[0054] The fifth step is to remove the sealed components and proceed with standard procedures such as ball placement, cutting, and testing.

[0055] Through the above-mentioned thin-film assisted molding process steps, a molding layer 5 is formed on the sidewalls of the flip chip 2, the thermal conductive layer 3 and the heat sink 4, while ensuring that the top surface of the heat sink 4 is absolutely exposed, providing a large effective area for heat dissipation. By controlling the mold cavity depth and film pressing force, the top surface of the final molded plastic seal 5 can be made to be flush with the top surface of the heat sink 4, forming a flat upper surface of the package without the need for subsequent grinding. This reduces the complexity of the existing process of first encapsulating the entire surface and then etching to create windows, and also reduces the limitations on the thickness of the heat sink.

[0056] Specifically, the steps for forming the solder balls 7 on the pads on the lower surface of the substrate 1 using the ball-planting process are as follows: The first step is to clean the exposed pads (usually copper pads with a nickel / gold or organic solder resist coating) on ​​the lower surface of substrate 1 to remove oxide layers, dust or contaminants left over from previous processes, and to ensure that the pad surface has good solderability.

[0057] The second step involves applying a thin, even layer of flux to the pad area. This is typically done via screen printing or stencil printing, using a stencil with openings that match the pad array pattern to precisely print the paste flux onto each pad. The flux serves two purposes: it cleans the surfaces of the pads and solder balls 7 during subsequent reflow, promoting soldering; simultaneously, its adhesiveness temporarily holds the placed solder balls 7 in place before reflow, preventing them from shifting.

[0058] The third step is planting the bulbs, which includes two methods: Stencil Ball Placement Method: A precision metal or polymer stencil, similar to a flux printing stencil but with an aperture diameter slightly smaller than that of the solder ball 7, is used. This stencil is precisely aligned with the pads on the substrate 1. A large number of solder balls 7 are poured onto the stencil, and a scraper is used to roll the solder balls 7 into each stencil aperture, thus pre-positioning one solder ball 7 in the aperture above each pad. After removing the stencil, the solder balls 7 are temporarily fixed in the center of each pad by the adhesive properties of the flux below.

[0059] Solder Ball Placement Machine Method: This method utilizes high-precision automated solder ball placement equipment. The equipment identifies the pad positions using a vision system, then picks up solder balls 7 one by one from the feeder using a nozzle or tweezers and precisely places them into the center of each flux-coated pad. This method offers greater flexibility and is suitable for products with diverse product types, small batch sizes, or smaller solder ball pitches.

[0060] The fourth step involves transferring the substrate 1 assembly with the solder balls 7 already placed to a reflow oven for heating according to the set temperature profile. During heating, the flux is first activated, cleaning the surfaces of the pads and solder balls 7. When the temperature rises above the melting point of the solder ball 7 alloy (e.g., approximately 217°C-227°C for SnAgCu lead-free solder), the solder balls 7 melt. In the molten state, the liquid solder, under the action of surface tension, wets and covers the underlying pads, forming a crescent shape. A metallurgical reaction occurs at the interface between the solder and the pad metal (e.g., copper), forming a thin, strong intermetallic compound (e.g., Cu6Sn5). Subsequently, after passing through the cooling zone, the solder solidifies, firmly connecting the solder balls 7 to the pads of substrate 1, forming an electrically and mechanically integrated interconnect.

[0061] Fifth, after reflow soldering, use a cleaning agent to remove residual flux to ensure the cleanliness of the bottom of the package. Finally, use optical or X-ray inspection to confirm the diameter, height, coplanarity, and presence of defects such as bridging or missing balls in the solder ball 7.

[0062] This embodiment also provides an electronic device, including the FCCSP package structure of the above embodiments, or the FCCSP package structure obtained by the manufacturing method of the FCCSP package structure of the above embodiments. The electronic device integrates the FCCSP package structure of the above embodiments, or the FCCSP package structure produced using the above manufacturing method. This package structure, as the core processor, controller, or power device in the device, ensures stable operation of the chip under high load due to its enhanced heat dissipation capability. Electronic devices, especially mobile or portable devices, have strict limitations on the power consumption and heat dissipation of internal components. The insufficient heat dissipation capability of traditional FCCSP packages has become a bottleneck for improving device performance. This embodiment, by adopting this novel enhanced heat dissipation package structure for FCCSP, enables the device to accommodate chips with higher performance and higher power consumption, or to maintain the low-temperature operation of the chip in a more compact space. This helps to improve the overall performance, reliability, and design flexibility of the electronic device.

[0063] Specifically, the electronic device is a solid-state drive, smartphone, tablet computer, laptop computer, server, or network communication device. The FCCSP package structure serves as a main controller, storage controller, power management chip, or RF front-end module within this electronic device.

[0064] The above description is only a part of the embodiments of this application and does not limit the scope of protection of this application. Any equivalent device or equivalent process transformation made based on the content of this application specification and drawings, or directly or indirectly used in other related technical fields, are similarly included in the patent protection scope of this application.

Claims

1. An FCCSP packaging structure, characterized in that, include: substrate(1); A flip chip (2) is disposed on the surface of the substrate (1); A thermally conductive layer (3) is disposed on the surface of the flip chip (2); The heat sink (4) is bonded to the heat-conducting layer (3); A molding layer (5) covers the sidewalls of the flip chip (2), the sidewalls of the thermal conductive layer (3), and the sidewalls of the heat sink (4); At least a portion of the heat sink (4) is exposed outside the molding layer (5).

2. The FCCSP packaging structure according to claim 1, characterized in that, It also includes a filler layer (6), wherein the flip chip (2) is flip-bonded to one side surface of the substrate (1) by multiple solder joints, and the filler layer (6) fills the space between the flip chip (2) and the substrate (1) and covers the multiple solder joints.

3. The FCCSP packaging structure according to claim 1, characterized in that, The thermally conductive layer (3) is a thermally conductive thin film or a thermally conductive interface material layer.

4. The FCCSP packaging structure according to claim 3, characterized in that, The thermally conductive interface material layer is a thermally conductive adhesive layer or a thermally conductive paste layer.

5. The FCCSP packaging structure according to claim 1, characterized in that, The molding layer (5) is made of organic resin.

6. The FCCSP packaging structure according to claim 1, characterized in that, The top surface of the heat sink (4) is exposed on the plastic sealant (5).

7. The FCCSP packaging structure according to claim 6, characterized in that, The top surface of the heat sink (4) is flush with the top surface of the plastic sealant (5).

8. The FCCSP packaging structure according to claim 1, characterized in that, It also includes solder balls (7) disposed on the surface of the substrate (1).

9. A method for fabricating an FCCSP package structure, characterized in that, The manufacturing method is applied to the manufacturing of the FCCSP package structure according to any one of claims 1 to 8, comprising: Provide the substrate (1); The flip chip (2) is mounted on one side of the substrate (1); The heat sink (4) is attached to the surface of the flip chip (2) facing away from the substrate (1), wherein the heat sink (4) is attached to the surface of the flip chip (2) through the thermal conductive layer (3); A molding layer (5) is formed on the sidewall of the flip chip (2), the sidewall of the thermal conductive layer (3), and the sidewall of the heat sink (4) using a thin film-assisted molding process.

10. An electronic device, characterized in that, Includes the FCCSP package structure according to any one of claims 1 to 8, or the FCCSP package structure obtained by the manufacturing method of the FCCSP package structure according to claim 9.

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