IC package electrical failure analysis sample, preparation method and test method

Abstract

This application provides an IC package electrical failure analysis sample, preparation method, and testing method. The method includes sequentially wrapping a first material layer and a second material layer on the outside of the IC package to form an inlay; grinding the inlay from the back of the IC package until the back of the bare die and the packaging wires within the molding compound are exposed; removing the remaining first and second material layers on the outside of the IC package; and electrically connecting the packaging wires within the molding compound through multiple conductive pads, wherein each conductive pad connects several packaging wires of the same electrical property. This application does not damage the pads on the bare die, thereby helping to ensure the accuracy of subsequent electrical failure analysis results.

Description

Technical Field

[0001] This application relates to the field of semiconductor testing technology, and in particular to an IC package electrical failure analysis sample, preparation method and testing method. Background Technology

[0002] In the field of semiconductor packaging and testing, electrical failure analysis (EFA) of IC (integrated circuit) packaging is a crucial step in ensuring product quality and reliability.

[0003] IC packages typically consist of a bare die and an outer molding compound. The molding compound contains bonding wires that are electrically connected to the pads on the bare die. During electrical failure analysis, the presence of the molding compound can affect test results. Therefore, related technologies often use fuming nitric acid to remove the molding compound, leaving only the bare die. The bare die is then transferred to a circuit board, and the pads on the bare die are electrically connected to the pads on the circuit board via secondary bonding wire bonding to facilitate electrical failure analysis.

[0004] However, when using related technologies to remove the molding compound with fuming nitric acid, the pads on the bare core may be damaged, which may affect the success rate of secondary wire bonding and make the final analysis results inaccurate. Summary of the Invention

[0005] In order to overcome the above-mentioned defects in related technologies, the purpose of this application is to provide an IC package electrical failure analysis sample, preparation method and testing method. This application will not damage the pads on the bare die, thereby helping to ensure the accuracy of subsequent electrical failure analysis results.

[0006] On one hand, this application provides a method for preparing an IC package electrical failure analysis sample, wherein the IC package includes a bare die and a molding compound disposed on the outside of the bare die, and the molding compound has a package bonding wire electrically connected to the pads on the bare die, the method comprising:

[0007] A first material layer and a second material layer are sequentially wrapped around the outside of the IC package to form an inlay;

[0008] The inlay is ground from the back of the IC package until the back of the bare die and the package wire bonding within the molding layer are exposed;

[0009] Remove the remaining first and second material layers from the outside of the IC package;

[0010] The encapsulation wires within the molding layer are electrically connected via multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity.

[0011] In one possible implementation, the step of sequentially wrapping a first material layer and a second material layer on the outside of the IC package to form an inlay includes:

[0012] The IC package is placed inside a container;

[0013] A liquid first material is poured into the container, and after solidification, a layer of the first material is formed on the outside of the IC package;

[0014] A liquid second material is poured into the container, and after solidification, a second material layer is formed on the outside of the first material layer.

[0015] In one possible implementation, the first material layer includes a hot melt adhesive layer, which includes any one of a paraffin layer, a rosin layer, a terpene resin layer, an oligomer resin layer, a low molecular weight polyisobutylene layer, and a microcrystalline wax layer; the second material layer includes a cold-applied adhesive layer, which includes any one of an epoxy molding compound-based cold-applied adhesive layer, a phenoxy resin-modified cold-applied adhesive layer, and a phenolic resin-based cold-applied adhesive layer.

[0016] In one possible implementation, the melting temperature of the first material is 60-120°C, and the curing temperature of the first material is less than or equal to 40°C.

[0017] The curing temperature of the second material is less than or equal to 60°C.

[0018] In one possible implementation, grinding the inlay from the back of the IC package until the back of the bare die and the package wire bonding within the molding compound includes:

[0019] The inlay is fixed to the grinding equipment with the back side of the IC package facing upwards;

[0020] Grind the inlay with 400-500 grit sandpaper until the crystal back of the bare core is visible;

[0021] Continue polishing with 1200-1500 grit sandpaper until the back of the bare die is fully exposed and the packaging wires are visible or partially exposed.

[0022] Continue sanding with 2400-2500 grit sandpaper until the encapsulation wires are fully exposed.

[0023] In one possible implementation, removing the remaining first and second material layers outside the IC package includes:

[0024] The polished insert is placed in an acetone or ethanol solution to remove the remaining first material layer and separate the IC package from the second material layer.

[0025] In one possible implementation, electrically connecting the encapsulation wires within the molding compound layer via multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity, includes:

[0026] Liquid conductive material is coated onto several encapsulation wires of the same electrical polarity in the molding layer;

[0027] Heating solidifies the liquid conductive material to form a plurality of conductive pads on the surface of the encapsulation layer.

[0028] In one possible implementation, the conductive material includes any one of silver, copper, gold, aluminum, nickel, and tin;

[0029] And / or, the heating temperature for solidifying the liquid conductive material is 180-220°C.

[0030] On the other hand, this application provides an IC package electrical failure analysis sample, which is prepared using any of the methods described above.

[0031] Furthermore, this application provides a testing method for IC package electrical failure analysis samples, used to test the IC package electrical failure analysis samples as described above, the method comprising:

[0032] The IC package electrical failure analysis sample was placed on the testing machine.

[0033] Insert the probes of the machine into the corresponding conductive pads for testing.

[0034] This application provides an IC package electrical failure analysis sample, preparation method, and testing method. The method includes sequentially wrapping a first material layer and a second material layer on the outside of the IC package to form an inlay; grinding the inlay from the back of the IC package until the back of the bare die and the encapsulation wires within the molding compound are exposed; removing the remaining first and second material layers on the outside of the IC package; and electrically connecting the encapsulation wires within the molding compound through multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical property. This application facilitates placing the IC package on a grinding device for subsequent grinding by sequentially wrapping the first and second material layers on the outside of the IC package to form an inlay; by exposing the back of the bare die and the encapsulation wires within the molding compound through grinding, it eliminates the need to use fuming nitric acid to remove the molding compound, thus avoiding damage to the pads on the bare die; and by electrically connecting the encapsulation wires within the molding compound through multiple conductive pads, it eliminates the need for secondary wire bonding, thereby reducing the difficulty of preparation. This application does not damage the pads on the bare die, thus helping to ensure the accuracy of subsequent electrical failure analysis results. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A flowchart illustrating a method for preparing an IC package electrical failure analysis sample according to an embodiment of this application;

[0037] Figures 2-6 for Figure 1 The structural diagrams corresponding to each step in the process;

[0038] Figure 7 A simplified structural diagram of an IC package electrical failure analysis sample provided in an embodiment of this application;

[0039] Figure 8 A flowchart illustrating a test method for analyzing the electrical failure of an IC package sample according to an embodiment of this application.

[0040] Figure label:

[0041] 100 - IC package; 110 - Bare die; 111 - Solder pad; 120 - Molding layer; 121 - Wire bonding for package;

[0042] 200 - First material layer;

[0043] 300 - Second material layer;

[0044] 400-Conductive disk. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments.

[0046] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] As described in the background section, the presence of the molding compound layer in related technologies can affect test results during electrical failure analysis. For example, when using a high-precision thermal imaging device to capture hotspot signals, the molding compound layer can lead to poor resolution, making it difficult to clearly see the location of the pads where the hotspot signals are located. Therefore, related technologies typically use fuming nitric acid to remove the molding compound layer, leaving only the bare die. The bare die is then transferred to the circuit board, and the pads on the bare die are electrically connected to the pads on the circuit board via secondary wire bonding to facilitate electrical failure analysis. However, removing the molding compound layer with fuming nitric acid may damage the pads on the bare die, affecting the success rate of secondary wire bonding and resulting in inaccurate final analysis results.

[0048] In view of this, the embodiments of this application aim to provide an IC package electrical failure analysis sample, preparation method, and testing method. By sequentially wrapping a first material layer and a second material layer on the outside of the IC package to form an inlay, it is easier to place the IC package on a polishing device for subsequent polishing. By polishing to expose the back of the bare die and the packaging wire bonding within the molding compound, it is not necessary to use fuming nitric acid to remove the molding compound, thus avoiding damage to the pads on the bare die. Multiple conductive pads are electrically connected to the packaging wire bonding within the molding compound, thus eliminating the need for secondary wire bonding and reducing the difficulty of preparation. This application does not damage the pads on the bare die, thereby helping to ensure the accuracy of subsequent electrical failure analysis results.

[0049] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can gain a more detailed understanding of the contents of this application.

[0050] Please refer to Figure 1 This embodiment provides a method for preparing an IC package electrical failure analysis sample. The IC package includes a bare die and a molding compound layer disposed outside the bare die. The molding compound layer contains package bonding wires electrically connected to pads on the bare die. The method includes:

[0051] Step S110: Wrap a first material layer and a second material layer on the outside of the IC package in sequence to form an inlay.

[0052] For example, please refer to Figure 2 The IC package 100 is surrounded by a first material layer 200, and the first material layer 200 is surrounded by a second material layer 300, which together constitute an inlay. The purpose of surrounding the first material layer 200 and the second material layer 300 is to increase the volume of the IC package 100, thereby facilitating subsequent polishing of the IC package 100. The first material layer 200 and the second material layer 300 can be made of materials with different chemical properties to facilitate subsequent removal.

[0053] Step S120: Grind the inlay from the back of the IC package until the back of the bare die and the package wire bonding inside the molding layer are exposed.

[0054] For example, when grinding the inlay from the back of the IC package, a portion of the second material layer, the first material layer, and a portion of the molding compound are removed sequentially. The final structure is shown in [reference needed]. Figure 3 The back of the bare die 110 of IC package 100 and the packaging wire 121 inside the molding layer 120 are directly exposed. The front and sides of the bare die 110 of IC package 100 still have the first material layer 200 and the second material layer 300.

[0055] Step S130: Remove the remaining first and second material layers on the outside of the IC package.

[0056] For example, the first and second material layers can be removed using chemical agents to obtain the polished IC package 100. Please refer to [reference needed] for its final structure. Figure 4 and Figure 5 ,in, Figure 4 This is a side view of the IC package after grinding. Figure 5 This is a bottom view of the IC package after grinding. At this point, the back of the bare die 110 of the IC package 100 and the package bonding wires 121 within the molding compound 120 are directly exposed. The package bonding wires 121 are electrically connected to the pads 111 on the front of the bare die 110, thereby leading out the corresponding pad information to the package bonding wires 121. The package bonding wires 121 and pads 111 can be connected one-to-one, or multiple pads 111 can be connected to a single package bonding wire 121; the specific configuration can be adjusted as needed.

[0057] Step S140: Connect the encapsulation wires within the molding layer through multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity.

[0058] For example, the conductive pad in this embodiment can be made of a conductive metal or alloy material. The structure corresponding to this step is as follows: Figure 6 As shown, the encapsulation wires 121 of the molding compound 120 are covered by the conductive pad 400. The conductive pad 400 can electrically connect several encapsulation wires of the same electrical polarity together, thereby increasing the area of ​​the conductive pad 400 to facilitate subsequent electrical failure analysis and testing.

[0059] As described above, this embodiment forms an inlay by sequentially wrapping a first material layer and a second material layer around the outside of the IC package, facilitating the placement of the IC package on a polishing device for subsequent polishing. Polishing exposes the die back and the packaging wires within the molding compound, eliminating the need for fuming nitric acid to remove the molding compound and avoiding damage to the pads on the die. Multiple conductive pads electrically connect the packaging wires within the molding compound, eliminating the need for secondary wire bonding and reducing manufacturing complexity. This embodiment does not damage the pads on the die, thus ensuring the accuracy of subsequent electrical failure analysis results.

[0060] Since it does not damage the pads on the bare core, this application can solve the risk of failure in small sample preparation, and has a significant success rate even in the case of a unique product, ensuring that the product is not damaged.

[0061] In one possible implementation, the method of sequentially wrapping a first material layer and a second material layer around the outside of the IC package to form an inlay includes:

[0062] The IC package is placed inside the container.

[0063] For example, the shape of the container can be set according to the needs of subsequent grinding processes. For instance, the inner cavity of the container can be generally prismatic, cylindrical, etc., so as to facilitate subsequent clamping of the inlay.

[0064] A liquid first material is poured into a container, and after solidification, a first material layer is formed on the outside of the IC package.

[0065] A liquid second material is poured into the container, and after solidification, a second material layer is formed on the outside of the first material layer.

[0066] The first material layer includes a hot melt adhesive layer, which can quickly form a dense and adherent base layer to protect the IC package. In this embodiment, the hot melt adhesive layer includes any one of a paraffin wax layer, a rosin layer, a terpene resin layer, an oligomeric resin layer, a low molecular weight polyisobutylene layer, and a microcrystalline wax layer. This embodiment preferably uses a paraffin wax layer.

[0067] The second material layer includes a cold-applied adhesive layer, which provides high-strength sealing and protection, facilitating clamping during subsequent grinding. The cold-applied adhesive layer can be any one of epoxy molding compound-based cold-applied adhesive layers, phenoxy resin-modified cold-applied adhesive layers, or phenolic resin-based cold-applied adhesive layers. In this embodiment, an epoxy molding compound-based cold-applied adhesive layer is preferred.

[0068] In this embodiment, a first material layer and a second material layer are sequentially wrapped around the outside of the IC package to form an inlay, which facilitates the placement of the IC package on a polishing device for subsequent polishing.

[0069] Furthermore, in this embodiment, the melting temperature of the first material can be 60-120℃, and the solidification temperature of the first material can be less than or equal to 40℃. Specifically, during preparation, the first material can be heated to the melting temperature range to make it liquid, and then poured into a container to cover the IC package. After natural cooling at room temperature, the first material solidifies and forms a first material layer on the outside of the IC package.

[0070] The curing temperature of the second material is less than or equal to 60℃. Specifically, the second material is a thermosetting material, which is initially in a liquid state and can be cured by a chemical reaction caused by heating. After curing, it will not melt but will only undergo thermal decomposition and carbonization. In the preparation process, the liquid second material can be poured into a container to coat the first material layer, and then cured by heating to produce a chemical reaction, forming a second material layer on the outside of the first material layer.

[0071] In one possible implementation, the grinding of the inlay from the back of the IC package until the back of the bare die and the package wire bonding within the molding compound includes:

[0072] The inlay is fixed to the polishing equipment, for example by clamping, so that the back of the IC package faces up, which facilitates polishing.

[0073] Grind the inlay with 400-500 grit sandpaper until the back of the bare core is visible. This step uses 400-500 grit sandpaper with high friction to quickly remove part of the second material layer and part of the first material layer, thereby improving grinding efficiency.

[0074] Continue sanding with 1200-1500 grit sandpaper until the back of the bare die is fully exposed, and the encapsulation wires are visible or partially exposed. This step uses 1200-1500 grit sandpaper with moderate friction, which can uniformly thin part of the second material layer and part of the first material layer, thereby exposing the complete back of the die area and approaching the height of the encapsulation wires.

[0075] Continue polishing with 2400-2500 grit sandpaper until the package bonding wires are fully exposed. Using 2400-2500 grit sandpaper with low friction in this step avoids damaging the back of the bare die and the package bonding wires, ensuring the smooth progress of subsequent testing.

[0076] This embodiment exposes the back of the bare die and the packaging wire bonding within the molding compound by grinding, thus eliminating the need to use fuming nitric acid to remove the molding compound and avoiding damage to the pads on the bare die.

[0077] In one possible implementation, removing the remaining first and second material layers outside the IC package in this embodiment includes:

[0078] The polished insert is placed in an acetone or ethanol solution to remove the remaining first material layer and separate the IC package from the second material layer.

[0079] It is understandable that since the first material layer uses any one of the hot melt adhesive layers mentioned above, such as paraffin layer, rosin layer, terpene resin layer, oligomer resin layer, low molecular weight polyisobutylene layer, and microcrystalline wax layer, it is soluble in acetone solution or ethanol solution. After the first material layer is removed, the outer second material layer naturally separates from the inner IC package, thereby obtaining the polished IC package.

[0080] In one possible implementation, the encapsulation wires within the molding compound are electrically connected via multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity, including:

[0081] Liquid conductive material is coated onto several encapsulation wires of the same electrical polarity in the molding layer.

[0082] The conductive material can be any one of silver, copper, gold, aluminum, nickel, or tin, or a conductive alloy material can also be used.

[0083] Heating solidifies the liquid conductive material to form multiple conductive pads on the surface of the encapsulation layer.

[0084] The heating temperature for solidifying the liquid conductive material is 180-220℃.

[0085] In this embodiment, multiple conductive pads are used to electrically connect the encapsulation wires within the molding layer, thus eliminating the need for secondary wire bonding and reducing the difficulty of manufacturing.

[0086] This embodiment also provides an IC package electrical failure analysis sample, which is prepared using the above method.

[0087] Specifically, such as Figure 7 As shown, the IC package includes a bare die 110 and an outer molding layer 120. The back side of the bare die 110 is directly exposed. The package bonding wires 121 inside the molding layer 120 are covered by a conductive pad 400. The conductive pad 400 can electrically connect several package bonding wires of the same electrical polarity together, thereby increasing the area of ​​the conductive pad 400 to facilitate subsequent electrical failure analysis and testing.

[0088] This embodiment will not damage the pads 111 on the bare core 110, which helps to ensure the accuracy of subsequent electrical failure analysis results.

[0089] Please refer to Figure 8 This embodiment also provides a testing method for IC package electrical failure analysis samples, used to test the aforementioned IC package electrical failure analysis samples, the method comprising:

[0090] Step S210: Place the IC package electrical failure analysis sample onto a testing machine. The testing machine may include any machine used for electrical failure analysis, such as a high-precision thermal imaging (thermal) machine, an ultra-low emission microscopy (EMMI) machine, or a beam-induced resistance change (OBIRCH) machine.

[0091] Step S220: Insert the probes of the machine into the corresponding conductive disks for testing.

[0092] For example, the probes of the instrument can be directly inserted into the conductive pad. Since the conductive pad is connected to the solder pads on the bare core through the package wire bonding, the probes can also be electrically connected to the solder pads on the bare core through the conductive pad, thereby enabling electrical failure analysis and testing.

[0093] The testing method for IC package electrical failure analysis samples in this embodiment does not damage the pads on the bare die, thus helping to ensure the accuracy of the results.

[0094] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0095] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0096] It should be noted that in the description of this application, the terms "first" and "second" are used only for convenience in describing different components and should not be construed as indicating or implying a sequential relationship, relative importance, or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features.

[0097] The embodiments or implementation methods in this application are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0098] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for preparing an IC package electrical failure analysis sample, wherein the IC package includes a bare die and a molding compound disposed on the outside of the bare die, and the molding compound has a bonding wire electrically connected to the pads on the bare die, characterized in that, include: A first material layer and a second material layer are sequentially wrapped around the outside of the IC package to form an inlay; The inlay is ground from the back of the IC package until the back of the bare die and the package wire bonding within the molding layer are exposed; Remove the remaining first and second material layers from the outside of the IC package; The encapsulation wires within the molding layer are electrically connected via multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity.

2. The method according to claim 1, characterized in that, The process of sequentially wrapping a first material layer and a second material layer on the outside of the IC package to form an inlay includes: The IC package is placed inside a container; A liquid first material is poured into the container, and after solidification, a layer of the first material is formed on the outside of the IC package; A liquid second material is poured into the container, and after solidification, a second material layer is formed on the outside of the first material layer.

3. The method according to claim 2, characterized in that, The first material layer includes a hot melt adhesive layer, which includes any one of a paraffin layer, a rosin layer, a terpene resin layer, an oligomer resin layer, a low molecular weight polyisobutylene layer, and a microcrystalline wax layer; the second material layer includes a cold-applied adhesive layer, which includes any one of an epoxy molding compound-based cold-applied adhesive layer, a phenoxy resin-modified cold-applied adhesive layer, and a phenolic resin-based cold-applied adhesive layer.

4. The method according to claim 3, characterized in that, The melting temperature of the first material is 60-120℃, and the curing temperature of the first material is less than or equal to 40℃; The curing temperature of the second material is less than or equal to 60°C.

5. The method according to claim 1, characterized in that, The grinding of the inlay from the back of the IC package until the back of the bare die and the package wire bonding within the molding compound are included: The inlay is fixed to the grinding equipment with the back side of the IC package facing upwards; Grind the inlay with 400-500 grit sandpaper until the crystal back of the bare core is visible; Continue polishing with 1200-1500 grit sandpaper until the back of the bare die is fully exposed and the packaging wires are visible or partially exposed. Continue sanding with 2400-2500 grit sandpaper until the encapsulation wires are fully exposed.

6. The method according to claim 3, characterized in that, The removal of the remaining first and second material layers on the outside of the IC package includes: The polished insert is placed in an acetone or ethanol solution to remove the remaining first material layer and separate the IC package from the second material layer.

7. The method according to claim 1, characterized in that, The step of electrically connecting the encapsulation wires within the molding layer via multiple conductive pads, wherein each conductive pad connects several encapsulation wires of the same electrical polarity, includes: Liquid conductive material is coated onto several encapsulation wires of the same electrical polarity in the molding layer; Heating solidifies the liquid conductive material to form a plurality of conductive pads on the surface of the encapsulation layer.

8. The method according to claim 7, characterized in that, The conductive material includes any one of silver, copper, gold, aluminum, nickel, and tin; And / or, the heating temperature for solidifying the liquid conductive material is 180-220°C.

9. An IC package electrical failure analysis sample, characterized in that, It is prepared by the method described in any one of claims 1-8.

10. A test method for analyzing the electrical failure of IC packaged samples, characterized in that, The method for testing IC package electrical failure analysis samples as described in claim 9 includes: The IC package electrical failure analysis sample was placed on the testing machine. Insert the probes of the machine into the corresponding conductive pads for testing.

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