Display panel and display device

Abstract

This application discloses a display panel and a display device, belonging to the field of display technology. The display panel includes: a substrate; scan lines extending along a first direction and spaced apart on the substrate; data lines extending along a second direction and spaced apart on the substrate, the scan lines and data lines intersecting on different layers to form sub-pixel areas; common electrode traces extending along the second direction and spaced apart on the substrate in the first direction; the projections of the common electrode traces and data lines on the substrate at least partially overlap; and bridging traces configured to bridge two adjacent common electrode traces in the second direction; the display device includes the above-described display panel. This application reduces the lateral space occupied by the common electrode traces in the pixel aperture area, improves the pixel aperture ratio and light transmittance, increases display brightness, reduces device operating power consumption, and can improve display uniformity and reduce vertical bright and dark stripes.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel with a higher aperture ratio, and a display device having the display panel. Background Technology

[0002] The common electrode traces on the display panel are usually non-transparent metal lines. In existing designs, in order to reduce the manufacturing process, the common electrode traces are usually arranged on the same layer and adjacent to the data lines. This wiring method causes the common electrode traces and adjacent data lines to occupy a large horizontal space in the pixel aperture area, which greatly limits the light-transmitting area of ​​the pixel aperture area, reduces the pixel aperture ratio and light transmittance, resulting in insufficient brightness and increased power consumption of the display panel.

[0003] Furthermore, to ensure the light-transmitting area of ​​the pixel aperture region, existing designs typically place common electrode traces only on one or both sides of the pixel unit. Common electrode traces are generally not placed between sub-pixel areas within the pixel unit. This results in significant differences in the width of the black matrix (BM) of the display panel at different vertical positions; the width is relatively larger in areas with common electrode traces, and relatively narrower between sub-pixel areas without common electrode traces. When the display panel is in operation, the width difference of the black matrix translates into uneven light intensity distribution in the vertical direction, forming visible alternating bright and dark stripes, resulting in vertical mura (mura), which negatively impacts the user experience.

[0004] In view of this, there is an urgent need to improve existing technologies to solve the aforementioned technical problems. Summary of the Invention

[0005] This application provides a display panel and a display device, wherein the common electrode trace of the display panel is configured to at least partially overlap with the data line, and the common electrode trace is connected in the second direction by bridging the trace, which significantly reduces the occupation of the common electrode trace in the lateral space of the pixel opening area, thereby at least partially solving the above-mentioned technical problems.

[0006] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising: Substrate; Scan lines extend along a first direction and are spaced apart on the substrate in a second direction; Data lines extend along the second direction and are spaced apart on the substrate in the first direction. The scan lines intersect with the data lines on different layers to form an array of sub-pixel regions. A common electrode trace extends along the second direction and is spaced apart on the substrate in the first direction; in the thickness direction of the display panel, the common electrode trace at least partially overlaps with the projection of the data line onto the substrate; and, A bridging trace is configured to bridge two adjacent common electrode traces in the second direction.

[0007] Optionally, the common electrode trace and the scan line are located in the same metal layer; Optionally, the bridging trace and the data line are located on the same metal layer.

[0008] Optionally, the display panel further includes: A pixel unit is arrayed on the substrate, and the pixel unit includes at least three sub-pixel regions, each of which is provided with a pixel electrode. The common electrode trace is located between two adjacent pixel units.

[0009] Optionally, the sub-pixel region in the pixel unit includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged in the first direction; In the first direction, the common electrode trace is located on one side of the first sub-pixel region of the pixel unit and on the opposite side of the third sub-pixel region; In the second direction, a bridging trace is provided between two adjacent pixel units.

[0010] Optionally, the pixel unit further includes a common electrode electrically connected to the common electrode trace, wherein the projection of the common electrode on the substrate is at least partially located within the projections of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region on the substrate; In the second direction, the common electrode is partially recessed at the corner of the third sub-pixel area to form an avoidance gap, and the avoidance gap between two adjacent common electrodes defines an avoidance area. The projection of the bridging trace onto the substrate is located within the projection of the avoidance area onto the substrate.

[0011] Optionally, the common electrode trace includes: The main body extends along the second direction, and the main body at least partially overlaps with the data line; A connecting portion is provided at both ends of the main body, and the connecting portion extends into the avoidance area; In the second direction, the bridging trace and the projection of the connection portion on the substrate have an overlapping area; Within the overlapping area, the bridging trace is electrically connected to the corresponding connection portion through bridging holes.

[0012] Optionally, the common electrode includes multiple parallel branch electrodes and a peripheral electrode connected to the branch electrodes from the end, with a light-transmitting gap between adjacent branch electrodes. The projection of the light-transmitting gap onto the substrate is located within the projections of the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area onto the substrate.

[0013] Optionally, a transistor region is formed at the intersection of the scan line and the data line; The transistor region located on one side of the pixel unit at least partially overlaps with the avoidance region.

[0014] According to a second aspect of this application, a display device is provided, the display device comprising the display panel described in any one of the preceding claims.

[0015] In the display panel provided in this application embodiment, by using the above technical solution, the common electrode traces and data lines are set to at least partially overlap in projection on the substrate, which significantly reduces the occupation of the horizontal space of the pixel aperture area by the common electrode traces, thereby improving the pixel aperture ratio and light transmittance. This is beneficial to improving the display brightness of the display panel, reducing the power consumption of the device, and improving display uniformity and reducing vertical bright and dark stripes.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a partial structural diagram of a display panel disclosed in the prior art; Figure 2 This is a schematic diagram of a partial structure of the black matrix in a common display panel in existing technology; Figure 3 This is a partial structural schematic diagram of the display panel provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of a partial structure of the black matrix of a display panel provided in an exemplary embodiment of this disclosure; Figure 5 This is a partial structural diagram of the display panel after the first metal layer has been fabricated, provided in an exemplary embodiment of this disclosure; Figure 6 This is a partial structural diagram of the display panel after the second metal layer has been fabricated, provided in an exemplary embodiment of this disclosure; Figure 7 yes Figure 3 A partial structural diagram of the display panel after concealing features such as the black matrix, common electrode traces, bridging traces, pixel electrodes, and thin-film transistors; Figure 8 yes Figure 3 A partial structural diagram of the display panel after features such as the black matrix and common electrode have been hidden. Figure 9 yes Figure 3 A schematic diagram of the cross-sectional structure at point AA.

[0020] Explanation of reference numerals in the attached figures: 10 - Display panel; 101 - Pixel unit; 102 - Black matrix; X - First direction; Y - Second direction; Z - Thickness direction; 1-Substrate; 2-First metal layer; 21-Scan line; 22-Common electrode trace; 221-Main body; 222-Connection portion; 3-Gate insulating layer; 31-Via; 4-Second metal layer; 40-Bridging hole; 41-Data line; 42-Bridging trace; 43-First trace; 44-Second trace; 45-Third trace; 5-Sub-pixel region; 51-First sub-pixel region; 52-Second sub-pixel region; 53-Third sub-pixel region; 6-Pixel electrode; 61-First pixel electrode; 62-Second pixel electrode; 63-Third pixel electrode; 7-Avoidance area; 8-Overlapping area; 9-Transistor area; 91-First transistor area; 92-Second transistor area; 93-Third transistor area; 11-Thin film transistor; 111-First thin film transistor; 112-Second thin film transistor; 113-Third thin film transistor; 12-Common electrode; 121-Branch electrode; 122-Peripheral electrode; 123-Light transmission gap; Avoidance notch 124. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] The common electrode traces 22 on the display panel 10 are typically opaque metal traces. (See also...) Figure 1 In existing designs, to reduce manufacturing processes, common electrode traces 22 and data lines 41 are typically arranged on the same layer and close to each other. To prevent short circuits between common electrode traces 22 and data lines 41, a sufficiently large gap must be reserved between them. However, for a display panel 10 with a fixed size, the area of ​​the light-transmitting area reserved in the pixel aperture is relatively fixed. Existing designs result in the common electrode traces 22 and data lines 41, which are arranged at intervals, occupying a large horizontal space in the pixel aperture area. The maximum aperture ratio of the pixels can only reach 62.87%. The low aperture ratio and light transmittance lead to insufficient brightness and increased power consumption of the display panel 10.

[0023] Additionally, please see Figure 1 and Figure 2 To ensure the light-transmitting area of ​​the pixel opening region, in existing designs, the common electrode trace 22 is generally only set on one or both sides of the pixel unit 101. Common electrode traces 22 are generally not set between the sub-pixel areas 5 within the pixel unit 101. This results in significant differences in the width of the black matrix 102 (BM) of the display panel 10 at different vertical positions. For example, the width M1 of the black matrix 102 located above the data line 41 between the sub-pixel areas 5 within the pixel unit 101 is generally 3.5–4.5 μm, while the width M2 of the black matrix 102 located above the adjacent common electrode trace 22 and data line 41 between pixel units 101 is generally 12–15 μm. The difference between M1 and M2 is significant. When the display panel 10 is in operation, the width difference of the black matrix 102 in the vertical direction will be converted into uneven light intensity distribution in the vertical direction, forming visible alternating bright and dark stripes, resulting in the problem of vertical bright and dark stripes (full name: Vertical Mura, abbreviation: mura), which affects the user experience.

[0024] In view of this, please refer to Figures 3 to 4 According to a first aspect of this application, a display panel 10 with a higher aperture ratio is proposed, the display panel 10 including a substrate 1 (such as...). Figure 9As shown in the diagram, the display panel 10 includes scan lines 21, data lines 41, common electrode traces 22, and bridging traces 42. The substrate 1 can be a rigid substrate 1 such as glass, or a flexible substrate 1 such as polyimide (PI). This application does not specifically limit the type of substrate 10. In this embodiment, the display panel 10 is described using a rectangular structure as an example. In the planar direction, the shape of the display panel 10 is the same as the shape of the substrate 1.

[0025] Specifically, the scan line 21, also known as the gate line, is a plurality of scan lines 21. The scan lines 21 extend along a first direction X, and are spaced apart on the substrate 1 along a second direction Y. The first direction X is the overall extension direction of the scan lines 21, and the second direction Y is the arrangement direction of the multiple scan lines 21. The second direction Y differs from the first direction X. In this embodiment, the first direction X is described using the length direction of the display panel 10 as an example, and the second direction Y is described using the width direction of the display panel 10 as an example. The first direction X can also be defined as the row direction, and the second direction Y can also be defined as the column direction. Understandably, the first direction X is the overall extension direction of the scan lines 21, but it is not required that the scan lines 21 always extend in a straight line along the first direction X, i.e., the row direction. In specific implementations, the scan lines 21 can also exhibit approximate bends, such as zigzag lines or wavy lines, to ensure that their overall extension direction follows the first direction X. The scan lines 21 are mainly used to transmit scan signals to select and drive the pixel units 101 of the display panel 10 row by row or column by column.

[0026] Specifically, data lines 41, also known as data lines, are arranged in multiples. Each data line 41 extends along the second direction Y, and the multiple data lines 41 are spaced apart on the substrate 1 along the first direction X. The second direction Y is the overall extension direction of the data lines 41, and the first direction X is the arrangement direction in which the multiple data lines 41 are spaced apart. It is understandable that while the second direction Y is the overall extension direction of the data lines 41, it does not require that the data lines 41 always extend in a straight line along the second direction Y, i.e., the column direction. In practice, the data lines 41 can also exhibit approximate bends, wavy lines, or other curves, as long as their overall extension direction remains along the second direction Y. The data lines 41 are mainly used to transmit high-frequency data signals to control the grayscale of the pixel unit 101.

[0027] Specifically, in the thickness direction Z of the display panel 10, the data line 41 is located on the side of the scan line 21 away from the substrate 1; in other words, the data line 41 is located on the upper layer of the scan line 21. The scan line 21 and the data line 41 intersect at different layers and form an array of sub-pixel areas 5 (e.g., ...). Figure 6 As shown in the figure, each subpixel area 5 corresponds to a subpixel of the display panel 10.

[0028] Specifically, the common electrode trace 22 can also be called a COM trace. Multiple common electrode traces 22 are provided, extending along the second direction Y. These multiple common electrode traces 22 are spaced apart on the substrate 1 in the first direction X, i.e., the row direction. It can be understood that the second direction Y is the overall extending direction of the display panel 10. It is not required that the common electrode traces 22 always extend in a straight line along the second direction Y, i.e., the column direction. In specific implementations, the common electrode traces 22 can also exhibit approximate bends, wavy lines, or other curves, as long as their overall extending direction remains along the second direction Y.

[0029] The common electrode trace 22 is a conductive line in the display panel 10 used to transmit the common voltage (Vcom) and connect the common electrode 12, i.e., COM. Its core function is to ensure the potential uniformity of the common electrode 12 and form a stable electric field with the pixel electrode 6 to drive the liquid crystal or control light emission. It can directly affect the display uniformity, crosstalk suppression, and transmittance of the display panel 10. In the thickness direction Z of the display panel 10, the common electrode trace 22 can be disposed below the data line 41, that is, closer to the substrate 1 than the data line 41. The width of the common electrode trace 22 in the first direction X can be set to be the same as the width of the data line 41 in the first direction X, or it can be set to be different from the width of the data line 41 in the first direction X. This application does not make a specific limitation in this regard.

[0030] Specifically, please refer to Figure 6 In the thickness direction Z of the display panel 10, the projection of the common electrode trace 22 and the data line 41 on the substrate 1 at least partially overlaps, such that a portion of the common electrode trace 22 overlaps with the data line 41 in the vertical direction. This overlapping arrangement can be achieved through precise photolithography alignment and deposition processes. For example, the common electrode trace 22 can be located above or below the data line 41 and is insulated by an interlayer dielectric.

[0031] A bridging trace 42 is disposed on the substrate 1. The bridging trace 42 is configured to bridge two adjacent common electrode traces 22 in the second direction Y, i.e., the column direction, thereby achieving a COM that runs vertically through the entire surface. This releases the openings occupied by the common electrode traces 22 and their surrounding space, and ensures the signal consistency of all connected common electrode traces 22 in the column direction. In specific implementations, the bridging trace 42 can be patterned in an independent metal layer, i.e., the bridging trace 42 is on a different layer from any of the common electrode traces 22, scan lines 21, and data lines 41; or, the bridging trace 42 can be patterned in the same metal layer as the data lines 41, but it is necessary to ensure that the bridging trace 42 can effectively connect two adjacent common electrode traces 22 in the second direction Y.

[0032] For example, when the common electrode trace 22 is located in the metal layer below the data line 41 (e.g., the common electrode trace 22 and the scan line 21 are located in the same metal layer, or the common electrode trace 22 is located in the metal layer between the scan line 21 and the data line 41, or the common electrode trace 22 is located in the metal layer below the scan line 21), the bridging trace 42 can be disposed in the same layer as the data line 41 or in the metal layer above the data line 41, ensuring that the bridging trace 42 can effectively connect the two adjacent common electrode traces 22 in the second direction Y.

[0033] Through the above technical solution, in the display panel 10 provided in this application embodiment, the common electrode trace 22 is configured to at least partially overlap with the data line 41, and the connection of the common electrode trace 22 in the longitudinal direction, i.e. the second direction Y, is realized through the bridging trace 42. Compared with the existing design in which the common electrode trace 22 and the data line 41 are arranged close to each other, this application significantly reduces the lateral space occupied by the common electrode trace 22 in the pixel opening area, and can increase the light transmission space of at least one common electrode trace 22 width in the pixel opening area, significantly improving the lateral light transmission area of ​​each sub-pixel area 5 in the pixel unit 101. The pixel aperture ratio of the display panel 10 is increased from 62.87% in the existing design to 64.62%, and the light transmittance Tr can be increased by 5%, thereby improving the display brightness of the display panel 10, reducing the operating power consumption of the display panel 10, and achieving the effect of energy saving and emission reduction.

[0034] In addition, such as Figure 4 As shown in the embodiment of this application, the display panel 10 has the common electrode trace 22 configured to at least partially overlap with the data line 41, so that the width M4 of the black matrix 102 corresponding to the area is closer to the width M3 of the black matrix 102 corresponding to the data line 41 between the sub-pixel areas 5. Compared with the existing design, the width difference of the black matrix 102 at different positions in the vertical direction can be reduced to less than 50%, which improves the width uniformity of the black matrix 102 at different positions in the vertical direction, avoids the vertical mura problem that occurs when the display panel 10 is in working state, and improves the risk of vertical lines.

[0035] In some embodiments, please refer to Figure 5 and Figure 9 In the display panel 10 provided in this application, the common electrode trace 22 and the scan line 21 can be located in the same metal layer.

[0036] Specifically, the display panel 10 includes a first metal layer 2 located on the substrate 1 and a second metal layer 4 located on the first metal layer 2 (e.g., ...). Figure 9 As shown in the diagram), the first metal layer 2 and the second metal layer 4 are separated by a gate insulating layer 3 (as shown in the diagram). Figure 9(As shown in the diagram) insulation isolation is achieved. The common electrode trace 22 and scan line 21 are located in the first metal layer 2, and the data line 41 is located in the second metal layer 4. The bridging trace 42 can be on the same layer as the data line 41 or on a different layer; this application does not specifically limit this, as long as the bridging trace 42 can effectively connect two adjacent common electrode traces 22 in the second direction Y. The common electrode trace 22 is perpendicular to two adjacent scan lines 21 and is insulated from the scan lines 21 to prevent the common electrode trace 22 from crossing the scan lines 21 within the first metal layer 2. In the second direction Y, i.e., the column direction, two adjacent common electrode traces 22 are connected across scan lines 21 via the bridging trace 42.

[0037] In the manufacturing process of the display panel 10, a first metal layer 2 can be deposited on the substrate 1. The first metal layer 2 is the common carrier for the common electrode traces 22 and the scan lines 21. It can be a single metal layer formed by depositing a single material such as gold (Au), copper (Cu), molybdenum (Mo), or titanium (Ti), or it can be a stacked metal structure formed by depositing multiple materials such as molybdenum (Mo), aluminum (Al), and molybdenum (Mo) in sequence. The materials and layer structures of the first metal layer 2 and the second metal layer 4 can be the same or different, and this application does not make specific limitations in this regard. Then, photoresist is coated on the formed first metal layer 2, and the first metal layer 2 is exposed, developed, and etched through a first mask containing the common electrode trace pattern and the scan line pattern, so that the common electrode traces 22 and the scan lines 21 can be formed in the same patterning process. At this time, the overall structure of the first metal layer 2 is as follows: Figure 5 As shown in the figure. Then, a gate insulating layer 3 is deposited on the patterned first metal layer 2, so that the gate insulating layer 3 can completely cover the common electrode trace 22 and the scan line 21. Then, a second metal layer 4 is deposited on the formed gate insulating layer 3, and the gate insulating layer 3 is used to achieve insulation isolation between the common electrode trace 22, the scan line 21 and the second metal layer 4.

[0038] like Figure 1 As shown in the prior art, the common electrode trace 22 and the data line 41 are generally placed in the same metal layer. The common electrode trace 22 and the data line 41 are arranged close to each other and a certain distance needs to be reserved. This design not only causes the closely arranged common electrode trace 22 and data line 41 to occupy a large horizontal space in the pixel aperture area, reducing the pixel aperture ratio, but also causes the data line 41 and the common electrode trace 22 to easily generate a capacitive coupling effect due to the common electrode trace 22 and the data line 41 being in the same layer and arranged close to each other. This can cause signal distortion of the data line 41 or potential fluctuation of the common electrode 12, affecting the stability of signal transmission and reducing the display effect.

[0039] In view of this, the display panel 10 provided in this application, through the above-mentioned technical solution, adjusts the common electrode trace 22 to be located on the same metal layer as the scan line 21. The arrangement of the common electrode trace 22 can be realized using the first metal layer 2 where the scan line 21 is located, without occupying the pixel aperture area and the metal layer space where the data line 41 is located, effectively improving the pixel aperture ratio. At the same time, the common electrode trace 22 and the scan line 21 can complete the patterning process simultaneously, simplifying the process steps and reducing production costs. In addition, this application adjusts the common electrode trace 22 to be located on the same metal layer as the scan line 21, while the scan line 21 and the data line 41 are located on different metal layers and are insulated from each other by interlayer dielectrics such as the gate insulating layer 3. That is, the common electrode trace 22 and the data line 41 are also on different layers and insulated. This significantly reduces the risk of signal crosstalk between the common electrode trace 22 and the data line 41, ensures the stability of signal transmission, and thus improves the display effect of the display panel 10.

[0040] In some embodiments, please refer to Figure 6 and Figure 9 In the display panel 10 provided in this application, the bridging trace 42 and the data line 41 are located on the same metal layer.

[0041] Specifically, the bridging trace 42 and the data line 41 are located in the second metal layer 4. The bridging trace 42 is parallel to the adjacent data line 41 and is insulated from the data line 41 to prevent the bridging trace 42 and the data line 41 from crossing within the second metal layer 4. Since the common electrode trace 22 is interrupted by the scan line 21 in the second direction Y, i.e., the column direction, in order to achieve a vertical COM that runs through the entire surface, this application uses the bridging trace 42, which is on the same layer as the data line 41, to connect two adjacent common electrode traces 22 in the column direction across layers.

[0042] In the manufacturing process of the display panel 10, vias 31 are first etched on the gate insulating layer 3, so that the vias 31 can expose the end of the lower common electrode trace 22 that is blocked by the scan line 21. Then, a second metal layer 4 is deposited on the gate insulating layer 3 where the vias 31 are formed. During the deposition of the second metal layer 4, some conductive metal material is deposited on the inner wall of the vias 31 and the end of the common electrode trace 22 to form a conductive bridging hole 40, thereby realizing the cross-layer connection between the common electrode trace 22 and the second metal layer 4 through the bridging hole 40.

[0043] The second metal layer 4 serves as the common carrier for the bridging lines 42 and the data lines 41. It can be a single-layer metal layer formed by depositing a single material such as gold (Au), copper (Cu), molybdenum (Mo), or titanium (Ti), or it can be a stacked metal structure formed by depositing multiple materials such as molybdenum (Mo), aluminum (Al), and molybdenum (Mo) sequentially. The materials and layer structures of the second metal layer 4 and the first metal layer 2 can be the same or different, and this application does not impose specific limitations on this. Subsequently, photoresist is coated on the formed second metal layer 4, and then the second metal layer 4 is exposed, developed, and etched through a second mask containing the bridging line pattern and the data line pattern, so that the bridging lines 42 and the data lines 41 can be formed in the same patterning process, and the two adjacent common electrode lines 22 in the second direction Y can be bridged through the formed bridging lines 42, so as to achieve continuous conduction of the common electrode lines 22 in the column direction.

[0044] Through the above technical solution, the display panel 10 provided in this application places the bridging trace 42 and the data line 41 on the same metal layer. The second metal layer 4 where the data line 41 is located can be used to arrange the bridging trace 42, so that the bridging trace 42 and the data line 41 can complete the patterning process simultaneously. Compared with the design of placing the bridging trace 42 in other metal layers, there is no need to add an additional metal layer or photolithography process, which simplifies the process steps, reduces the production cost, and helps to reduce the stress risk and photolithography alignment difficulty caused by film layer stacking, which is conducive to improving the production yield. In addition, the bridging trace 42 bridges the two adjacent common electrode traces 22 in the second direction Y across the scan line 21. This design allows the bridging trace 42 to be arranged only at the four corners of the opening area of ​​the pixel unit 101, avoiding the bridging trace 42 occupying the core light-transmitting area within the pixel opening area, and ensuring the improvement effect of the pixel aperture ratio of the technical solution of this application.

[0045] In some embodiments, please refer to Figure 3 and Figure 6 The display panel 10 provided in this application also includes pixel units 101 (such as...). Figure 3 As shown in the figure), the pixel unit 101 array is disposed on the substrate 1, and the pixel unit 101 includes at least three sub-pixel regions 5 (as shown in the figure). Figure 6 As shown in the diagram, a pixel electrode 6 is disposed within the sub-pixel area 5. The common electrode trace 22 is disposed between two adjacent pixel units 101.

[0046] Pixel unit 101 is the basic display unit of display panel 10, typically composed of at least three sub-pixel areas 5. Pixel electrodes 6 are disposed within each sub-pixel area 5, constituting one sub-pixel in pixel unit 101. For example, according to the difference in emitted color, the sub-pixels include a first sub-pixel emitting red light, a second sub-pixel emitting green light, and a third sub-pixel emitting blue light. The first, second, and third sub-pixels can constitute one pixel unit 101 of display panel 10. There are various arrangements of sub-pixels on display panel 10. In this embodiment, a standard RGB arrangement is used as an example, where each pixel unit 101 includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially in the first direction X. All pixel units 101 are arranged in an array along the first direction X and the second direction Y. Understandably, in some other embodiments, the sub-pixels may also include a fourth sub-pixel emitting white light. The first, second, third, and fourth sub-pixels together constitute one pixel unit 101 to achieve a more refined display effect.

[0047] The common electrode trace 22 is disposed between two adjacent pixel units 101. Specifically, the common electrode trace 22 is disposed below the data line 41 between two adjacent pixel units 101 in the first direction X.

[0048] The display panel 10 provided in this application embodiment, through the above technical solution, places the common electrode trace 22 on one side of the pixel unit 101, which will not occupy too much of the light-transmitting space of the pixel aperture area, and ensures that the pixel aperture ratio meets the design requirements.

[0049] In some embodiments, please refer to Figure 6 The display panel 10 provided in this application includes a first sub-pixel region 51, a second sub-pixel region 52, and a third sub-pixel region 53 arranged in a first direction X. The first sub-pixel region 51 can correspond to a first sub-pixel that emits red light, the second sub-pixel region 52 can correspond to a second sub-pixel that emits green light, and the third sub-pixel region 53 can correspond to a third sub-pixel that emits blue light, so as to realize the color display of the pixel unit 101.

[0050] In the first direction X, i.e., the direction of travel, the common electrode trace 22 is located on one side of the first sub-pixel area 51 of the pixel unit 101 and on the opposite side of the third sub-pixel area 53.

[0051] In the second direction Y, i.e. column direction, a bridging trace 42 is provided between two adjacent pixel units 101.

[0052] Specifically, in the row direction, the third sub-pixel area 53 of the previous pixel unit 101 is adjacent to the first sub-pixel area 51 of the next pixel unit 101. The common electrode trace 22 is located below the data line 41 between the third sub-pixel area 53 and the first sub-pixel area 51 of the two adjacent pixel units 101, so as to avoid the common electrode trace 22 occupying the light-transmitting space inside the sub-pixel area 5 and reduce the impact on the pixel aperture ratio.

[0053] In the column direction, adjacent pixel units 101 are roughly aligned, that is, the first sub-pixel area 51 of the previous pixel unit 101 is adjacent to the first sub-pixel area 51 of the next pixel unit 101, the second sub-pixel area 52 of the previous pixel unit 101 is adjacent to the second sub-pixel area 52 of the next pixel unit 101, and the third sub-pixel area 53 of the previous pixel unit 101 is adjacent to the third sub-pixel area 53 of the next pixel unit 101.

[0054] The display panel 10 provided in this application, through the above-described technical solution, sets the common electrode trace 22 in the first direction X between the third sub-pixel area 53 and the first sub-pixel area 51 of two adjacent pixel units 101. By utilizing the boundary between pixel units 101, the consistency of the common electrode trace 22 in the vertical direction is ensured, effectively avoiding bright and dark stripes caused by the width difference of the black matrix 102 at different positions in the vertical direction. It also avoids setting the common electrode trace 22 between adjacent sub-pixel areas 5 inside the pixel unit 101 (e.g., between the first sub-pixel area 51 and the second sub-pixel area 52, and between the second sub-pixel area 52 and the third sub-pixel area 53), reducing the number of common electrode traces 22 in the pixel unit 101, minimizing the occupation of the lateral light transmission space of the pixel opening area by the common electrode trace 22, and ensuring the pixel aperture ratio. Meanwhile, in the second direction Y, bridging traces 42 are positioned between two adjacent pixel units 101, so that the bridging traces 42 are distributed at one corner of the pixel unit 101. This minimizes the occupancy of the bridging traces 42 on the lateral light transmission space of the pixel aperture area, ensuring the pixel aperture ratio and balancing the overall wiring density, further improving the vertical bright and dark stripe phenomenon caused by uneven wiring. In addition, the placement of the bridging traces 42 also ensures that it can cross the scan line 21 of the common electrode trace 22 in the second direction Y, ensuring that the bridging traces 42 can bridge two adjacent common electrode traces 22 across layers in the second direction Y, ensuring the consistency of the common potential.

[0055] Please see Figure 3 and Figure 7In some embodiments, the display panel 10 provided in this application further includes a common electrode 12 electrically connected to the common electrode trace 22 in its pixel unit 101. The projection of the common electrode 12 on the substrate 1 is at least partially located within the projections of the first sub-pixel area 51, the second sub-pixel area 52, and the third sub-pixel area 53 on the substrate 1, that is, the common electrode 12 covers at least three sub-pixel areas 5 of the pixel unit 101.

[0056] Specifically, the display panel 10 is provided with a full-surface common electrode 12 or an independent common electrode 12 corresponding to each pixel unit 101. In this embodiment, the common electrode 12 is described as an independent common electrode 12 corresponding to each pixel unit 101. Each common electrode 12 is electrically connected to the common electrode trace 22 on the left or right side of the pixel unit 101. In the second direction Y, i.e., the column direction, all common electrode traces 22 are connected by bridging traces 42, and all common electrode traces 22 in the same column are connected to all common electrodes 12 in the same column to achieve a COM that runs vertically through the entire surface.

[0057] Pixel electrode 6 receives a grayscale voltage signal from data line 41, and common electrode 12 receives a reference potential signal from common electrode trace 22, creating a potential difference electric field between pixel electrode 6 and common electrode 12. This electric field is then used to control the deflection direction of liquid crystal molecules sandwiched between the two electrodes or the brightness of the light-emitting material, thereby achieving image display. Pixel electrode 6 can be made of a transparent conductive material (such as indium tin oxide (ITO) or indium zinc oxide (IZO)) to ensure the light transmittance of sub-pixel area 5. The material of common electrode 12 can be the same as that of pixel electrode 6, i.e., both can be made of transparent material; the material of common electrode 12 can also be the same as that of the first metal layer 2 or the second metal layer 4, i.e., it can be made of non-transparent material; or the material of common electrode 12 can be different from that of pixel electrode 6 and the first metal layer 2 or the second metal layer 4, as long as it meets the actual usage requirements of common electrode 12. This application does not impose specific limitations in this regard.

[0058] The display panel 10 provided in this application embodiment, through the above technical solution, uses bridging traces 42 to connect the common electrode traces 22 and common electrodes 12 that are separated by scan lines 21 in the vertical direction, thereby realizing a common electrode network that runs through the entire surface in the vertical direction, ensuring the uniform distribution of common potential and the integrity of signals, and ensuring the display effect of the display panel 10.

[0059] Furthermore, in the second direction Y, i.e., the column direction, the common electrode 12 is located at the corner of the third sub-pixel area 53 (e.g., Figure 7The right corner of the common electrode 12 shown in the diagram is partially recessed to form a clearance notch 124, which can be U-shaped, C-shaped, or a simple rectangular cut. The clearance notch 124 between two adjacent common electrodes 12 in the longitudinal direction defines a clearance region 7. The projection of the bridging trace 42 on the substrate 1 is located within the projection of the clearance region 7 on the substrate 1.

[0060] The avoidance area 7 is a specific area defined by the avoidance gap 124 between two adjacent common electrodes 12 in the second direction Y. This avoidance area 7 aims to provide wiring space for the bridging trace 42 without affecting the display effect, reducing the occupancy of the bridging trace 42 and the common electrode trace 22 on the arrangement space and light-transmitting space of the common electrode 12 and pixel electrode 6 within the third sub-pixel area 53, thus ensuring the effective light-transmitting area of ​​the third sub-pixel area 53. Furthermore, the avoidance area 7 is located at the corner of the third sub-pixel area 53 adjacent to the first sub-pixel area 51 of the next pixel unit 101. These locations are typically areas within the pixel unit 101 with low sensitivity to display effects, or non-core light-transmitting areas. Placing the avoidance area 7 here minimizes the impact on the pixel aperture ratio. This can be achieved by placing the geometric center or main part of the avoidance area 7 at the left or right corner of the pixel unit 101 in the layout design.

[0061] The bridging trace 42 is used to electrically connect two adjacent common electrode traces 22 in the second direction Y, to achieve a COM that runs longitudinally across the entire surface. The projection of the bridging trace 42 onto the substrate 1 lies within the projection of the avoidance region 7 onto the substrate 1, meaning that the physical position of the bridging trace 42 in the direction perpendicular to the substrate 1, i.e., the thickness direction Z, is completely within the plane defined by the avoidance region 7. This can be achieved through precise layout design, controlling the width and length of the bridging trace 42 within the boundary of the avoidance region 7 and ensuring that its routing path is completely within the range of the avoidance region 7; or, through multilayer routing technology, arranging the bridging trace 42 in the layer corresponding to the avoidance region 7 and ensuring that it is aligned with the avoidance region 7 on the plane.

[0062] Through the above technical solution, the display panel 10 provided in this application sets the avoidance area 7 at the corner of the third sub-pixel area 53. These areas usually have a relatively small impact on the pixel aperture ratio, light transmittance, and the function realization of the pixel electrode 6, providing space for the arrangement of the bridging line 42. This minimizes the space occupied by the bridging line 42 on the arrangement of the common electrode 12 and the pixel electrode 6, ensures the total light-transmitting area of ​​the pixel unit 101, ensures that the pixel aperture ratio meets the design requirements, maintains the light transmittance performance and display uniformity of the display panel 10, and improves the user experience.

[0063] In some embodiments, please refer to Figure 7 In the display panel 10 provided in this application, the common electrode 12 is a comb-shaped electrode, which includes multiple parallel branch electrodes 121 arranged in a comb-like shape, and peripheral electrodes 122 connected to the branch electrodes 121 from the ends. A light-transmitting gap 123 is left between adjacent branch electrodes 121. The extension direction of the branch electrodes 121 may be the same as the first direction X, or the same as the second direction Y, or different from the first direction X and the second direction Y. This application does not specifically limit this. In the embodiments of this application, the branch electrodes 121 are described by extending along the second direction Y as an example.

[0064] The projection of the light-transmitting gaps 123 onto the substrate 1 lies within the projections of the first sub-pixel region 51, the second sub-pixel region 52, and the third sub-pixel region 53 onto the substrate 1. This ensures that the common electrode 12, made of a non-transparent material, has a sufficient number of light-transmitting gaps 123 in the portions corresponding to each sub-pixel region. Understandably, the more light-transmitting gaps 123 the common electrode 12 has in each sub-pixel region, and the wider the light-transmitting gaps 123 are, the larger the total light-transmitting area allowed for direct backlight penetration of the common electrode 12, and the higher the light transmittance Tr of the pixel opening region.

[0065] The display panel 10 provided in this application reduces the lateral light-transmitting space occupied by the common electrode trace 22 in the pixel opening area by overlapping the data line 41, thus providing clearance for the lateral expansion of the common electrode 12 within the pixel unit 101. Based on this, without increasing the width of the branch electrodes 121 and the light-transmitting gaps 123, the lateral expansion of the common electrode 12 can be achieved by increasing the number of branch electrodes 121, and the number of light-transmitting gaps 123 in the common electrode 12 can be increased, thereby improving the light transmission efficiency per unit area of ​​the pixel unit 101. Alternatively, without increasing the number of branch electrodes 121 and the light-transmitting gaps 123, the lateral expansion of the common electrode 12 can also be achieved by reducing the width of the branch electrodes 121 and increasing the width of the light-transmitting gaps 123, thereby increasing the total light-transmitting area of ​​the light-transmitting gaps 123 in the common electrode 12, and thus improving the light transmission efficiency per unit area of ​​the pixel unit 101.

[0066] In some embodiments, please refer to Figure 8The display panel 10 provided in this application includes a pixel electrode 6 in a pixel unit 101 comprising a first pixel electrode 61 located in a first sub-pixel region 51, a second pixel electrode 62 located in a second sub-pixel region 52, and a third pixel electrode 63 located in a third sub-pixel region 53. The projections of the first pixel electrode 61, the second pixel electrode 62, and the third pixel electrode 63 onto the substrate 1 at least partially overlap with the projection of the common electrode 12 onto the substrate 1. This ensures that the pixel electrode 6 within the pixel unit 101 has a sufficiently large overlap area with the common electrode 12 corresponding to each sub-pixel region, thereby guaranteeing that the pixel electrode 6 and the common electrode 12 form a stable electric field to drive liquid crystal or control light emission.

[0067] Specifically, the shape of the corner of the third pixel electrode 63 near the common electrode trace 22 can be configured to match the shape of the corner of the common electrode 12 in that region. That is, the projection of the corner of the third pixel electrode 63 near the common electrode trace 22 onto the substrate 1 completely overlaps with the projection of the corner of the common electrode 12 within the third sub-pixel region 53 onto the substrate 1, to prevent the corner portion of the third pixel electrode 63 from encroaching into the avoidance area 7 and to prevent the third pixel electrode 63 from affecting the normal connection between the bridging trace 42 and the common electrode trace 22. It is understood that in some other embodiments, the shape of the corner of the third pixel electrode 63 near the common electrode trace 22 can also be configured to be recessed compared to the corner of the common electrode 12 within the third sub-pixel region 53. In some embodiments, please refer to... Figure 5 and Figure 6 In the display panel 10 provided in this application, the common electrode trace 22 includes a main body 221 and a connecting portion 222. The main body 221 is the main conductive portion of the common electrode trace 22. The main body 221 extends along the second direction Y, and at least partially overlaps with the data line 41. This overlapping arrangement aims to make full use of the existing wiring space on the display panel 10 and minimize the occupancy of the lateral light transmission space of the pixel aperture area by the common electrode trace 22, which helps to maintain a high pixel aperture ratio and light transmittance. The main body 221 can be made of a metal material with good conductivity, such as molybdenum-aluminum alloy, copper, or titanium, and can be formed by standard photolithography, etching, and deposition processes. In the second direction Y, the length of the main body 221 is less than the distance between two adjacent scan lines 21 to prevent the two ends of the main body 221 from contacting the scan lines 21; in the first direction X, the width of the main body 221 may be the same as the width of the data line 41 or may not be the same as the width of the data line 41. This application does not make a specific limitation on this. In the embodiments of this application, the width of the main body 221 is described as being slightly larger than the width of the data line 41.

[0068] The connecting portion 222 is an extension of the common electrode trace 22. The connecting portion 222 is located at both ends of the main body 221 along its length and extends into the clearance area 7. The function of the connecting portion 222 is to provide electrical connection points for the bridging trace 42. Extending the connecting portion 222 into the clearance area 7 improves space utilization. The connecting portion 222 can extend perpendicularly to the main body 221 into the clearance area 7, or it can extend obliquely into the clearance area 7. This application does not specifically limit this; in this embodiment, the connecting portion 222 extending perpendicularly to the main body 221 into the clearance area 7 is used as an example for explanation.

[0069] In the second direction Y, i.e., the column direction, the projections of the bridging trace 42 and the connection portion 222 onto the substrate 1 have an overlapping region 8 (e.g., ...). Figure 6 (As shown in the diagram). Within the overlapping area 8, the bridging trace 42 passes through the bridging hole 40 (as shown in the diagram). Figure 9 (As shown in the figure) is electrically connected to the corresponding connecting part 222.

[0070] The overlapping region 8 refers to the area on the projection plane of the substrate 1 where the connection portions 222 between the bridging trace 42 and the two adjacent common electrode traces 22 overlap. This region is crucial for achieving a reliable electrical connection between the bridging trace 42 and the connection portion 222. By precisely designing the layout of each trace, a sufficiently large overlap area is ensured between the bridging trace 42 and the connection portion 222 between the two adjacent common electrode traces 22, providing a physical basis for cross-layer bridging of the common electrode traces 22. As described above, the bridging via 40 is formed by filling the via 31 penetrating the gate insulating layer 3 with the conductive metal material of the second metal layer 4. Located within the overlapping region 8, it enables cross-layer connection between the connection portion 222 and the bridging trace 42 in the thickness direction Z, thereby electrically connecting the two adjacent common electrode traces 22 in the second direction Y through the bridging trace 42. This vertical connection method effectively saves planar wiring space and provides a stable and reliable electrical path.

[0071] Furthermore, the corner structure design of the common electrode 12 located in the third sub-pixel area 53, and the corner structure design of the third pixel electrode 63 near the common electrode trace 22, are closely integrated with the layout of the bridging trace 42 and the connecting part 222, so that the two adjacent pixel units 101 form an almost interlocking structure, making full use of the space of the pixel unit 101 and minimizing the occupation of the light-transmitting space in the pixel opening area, ensuring that the pixel aperture ratio and light transmittance meet the design requirements, and at the same time realizing effective bridging between adjacent common electrode traces 22 in the vertical direction.

[0072] Viewed from the plane of the display panel 10, the overlapping wiring arrangement of the common electrode trace 22 and the data line 41 provides space for the lateral expansion of the pixel opening area. In specific implementations, the expanded space can be evenly distributed to each sub-pixel area 5 of the pixel unit 101, so that the opening width of each sub-pixel area 5 in the first direction X remains consistent, that is, the spacing between the data lines 41 remains consistent. Based on this, the number of branch electrodes 121 corresponding to the common electrode 12 in each sub-pixel area can also be the same. In some other embodiments, because the overlapping wiring arrangement of the common electrode trace 22 and the data line 41 provides space for the lateral expansion of the pixel opening area, the expanded space can also be allocated only to the third sub-pixel area 53 within the pixel unit 101, so that the opening width of the third sub-pixel area 53 within the pixel unit 101 in the first direction X is greater than the opening width of the first sub-pixel area 51 and the second sub-pixel area 52 in the first direction X. The increased lateral space in the third sub-pixel region 53 provides additional space for the arrangement of branch electrodes 121 for the common electrode 12, thereby increasing the number of light-transmitting gaps 123 of the common electrode 12 in the third sub-pixel region 53 and improving the light transmittance.

[0073] Through the above technical solution, in the display panel 10 provided by this application, the common electrode trace 22 is disposed between two adjacent pixel units 101 in the first direction X, specifically disposed between the third sub-pixel area 53 of the previous pixel unit 101 and the first sub-pixel area 51 of the next pixel unit 101, while the avoidance area 7 is only disposed on the side of the third sub-pixel area 53. This requires that the connection portion 222 of all the common electrode traces 22 extend toward the avoidance area 7 at the corner of the third sub-pixel area 53 of the previous pixel unit 101. This design creates a nested structure between two adjacent pixel units 101 in the first direction X. Specifically, the connection portion 222 of the common electrode trace 22 between the two pixel units 101 extends into the avoidance area 7 at the corner of the third sub-pixel area 53 of the preceding pixel unit 101 in an almost embedded manner. This further optimizes the structure of the common electrode trace 22 and its connection with the bridging trace 42, reducing the occupation of the light-transmitting space in the pixel aperture area. This is crucial for maintaining a high pixel aperture ratio and light transmittance, and helps to improve the brightness of the display panel 10 and reduce power consumption.

[0074] In some embodiments, please refer to Figure 7In the display panel 10 provided in this application, a transistor region 9 is formed at the intersection of the scan line 21 and the data line 41. The transistor region 9 located on one side of the pixel unit 101 at least partially overlaps with the clearance region 7 of the adjacent pixel unit 101. A thin-film transistor 11 (TFT) is disposed within the transistor region 9. The TFT is the core driving element of the pixel unit 101, used to control the charging and discharging of each pixel electrode 6. The scan line 21 horizontally penetrates the transistor region 9 of its row and is electrically connected to the gate of all TFTs 11 in its row; the data line 41 vertically penetrates the transistor region 9 of its column and is electrically connected to the source of all TFTs 11 in its column, ensuring that each sub-pixel can be independently addressed and controlled.

[0075] For example, please refer to Figures 6 to 8 When each pixel unit 101 includes three sub-pixel regions 5, in the first direction X, as shown... Figure 7 As shown, transistor region 9 includes a first transistor region 91, a second transistor region 92, and a third transistor region 93. The first transistor region 91 is located at the left or right corner of pixel unit 101, and the first transistor region 91 at least partially overlaps with the avoidance region 7 of adjacent pixel unit 101. Figure 6 and Figure 8 As shown, a first thin-film transistor 111 is disposed in the first transistor region 91, a second thin-film transistor 112 is disposed in the second transistor region 92, and a third thin-film transistor 113 is disposed in the third transistor region 93. The drain of the first thin-film transistor 111, located below the pixel unit 101, is connected across layers to the first pixel electrode 61 in the pixel unit 101 via a first trace 43; the drain of the second thin-film transistor 112, located below the pixel unit 101, is connected across layers to the second pixel electrode 62 in the pixel unit 101 via a second trace 44; and the drain of the third thin-film transistor 113, located below the pixel unit 101, is connected across layers to the third pixel electrode 63 in the pixel unit 101 via a third trace 45. In specific implementations, the first trace 43, the second trace 44, and the third trace 45 can be configured to reside in the same metal layer as the data line 41 and the bridging trace 42.

[0076] Through the above technical solution, in the display panel 10 provided by this application, in the first direction X, i.e., the row direction, the first transistor region 91 located on one side of the pixel unit 101 at least partially overlaps with the adjacent clearance region 7, so that the adjacent pixel units 101 form a mating structure. Specifically, a portion of the first thin film transistor 111 in the subsequent pixel unit 101 extends into the clearance region 7 at the corner of the third sub-pixel region 53 of the preceding pixel unit 101 in an approximately embedded manner, and is located between the connection portions 222 of two adjacent common electrode traces 22 in the second direction Y, so that the first transistor region 91 can reuse part of the space of the clearance region 7 of the preceding pixel unit 101, further improving the space utilization rate of the pixel opening area, optimizing the internal layout of the pixel unit 101, and making the overall structure more compact. In addition, since the first transistor region 91 at least partially overlaps with the adjacent avoidance region 7, the width of the non-transparent region between pixel units 101 in the first direction X is reduced to a certain extent, which helps to maintain the consistency of the width of the black matrix 102, avoids the occurrence of vertical bright and dark stripes, improves display uniformity, and thus improves the user experience.

[0077] Specifically, the display panel 10 provided in this application includes an array substrate and a counter substrate disposed opposite each other. In one specific embodiment, the display panel 10 can be a liquid crystal display (LCD) panel. The array substrate can be a glass substrate 1, on which scan lines 21, data lines 41, thin-film transistors 11, pixel electrodes 6, common electrode traces 22, bridging traces 42, etc., are sequentially fabricated. The scan lines 21 and data lines 41 can be formed by stacking and patterning multiple layers of metal such as molybdenum / aluminum / molybdenum (Mo / Al / Mo). The common electrode traces 22 can be located in the same metal layer as the scan lines 21 (e.g., the first metal layer 2), while the bridging traces 42 can be located in the same metal layer as the data lines 41 (e.g., the second metal layer 4). The pixel electrodes 6 can be made of transparent conductive oxide materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The counter substrate can also be a glass substrate, on which a color filter layer (including red, green, and blue filters) is fabricated and precisely aligned with the sub-pixel areas 5 on the display panel 10. A black matrix 102 can also be provided on the opposing substrate to shield non-transparent areas, such as thin-film transistors 11, scan lines 21, data lines 41, and common electrode traces 22. Furthermore, transparent or opaque common electrodes 12 can typically be provided on the opposing substrate, which, together with the pixel electrodes 6 on the array substrate, form a liquid crystal capacitor. The array substrate and the opposing substrate are precisely aligned and encapsulated using a peripheral sealing frame, and liquid crystal material is injected between them. Finally, a polarizer is attached to the outer surface of the display panel 10 to complete the construction of the entire display panel 10.

[0078] Through the above technical solution, the display panel provided by this application effectively solves the problems of low pixel aperture ratio and light transmittance, insufficient brightness of the display panel, and vertical bright and dark stripes caused by improper wiring method of common electrode line 22, thereby improving the image quality of the display panel and the user's visual experience.

[0079] According to a second aspect of this application, a display device is provided, which includes the display panel described in any of the above embodiments. The display device provided by this application has all the beneficial effects of the above-described display panel, which will not be repeated here.

[0080] For example, the display devices provided in the embodiments of this application include, but are not limited to: portable display devices such as tablet computers and laptops, mobile phones, vehicle displays, televisions, commercial advertising displays, and display devices in professional fields such as military and medical fields.

[0081] In the description of this application, the terms "first," "second," "third," and "fourth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," "third," or "fourth" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0084] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, include: Substrate; Scan lines extend along a first direction and are spaced apart on the substrate in a second direction; Data lines extend along the second direction and are spaced apart on the substrate in the first direction. The scan lines intersect with the data lines on different layers to form an array of sub-pixel regions. A common electrode trace extends along the second direction and is spaced apart on the substrate in the first direction; in the thickness direction of the display panel, the common electrode trace and the projection of the data line on the substrate at least partially overlap. as well as, A bridging trace is configured to bridge two adjacent common electrode traces in the second direction.

2. The display panel according to claim 1, characterized in that, The common electrode trace and the scan line are located in the same metal layer.

3. The display panel according to claim 1 or 2, characterized in that, The bridging trace and the data line are located on the same metal layer.

4. The display panel according to claim 1, characterized in that, Also includes: A pixel unit is arrayed on the substrate, and the pixel unit includes at least three sub-pixel regions, each of which is provided with a pixel electrode. The common electrode trace is located between two adjacent pixel units.

5. The display panel according to claim 4, characterized in that, The sub-pixel region in the pixel unit includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region arranged in the first direction; In the first direction, the common electrode trace is located on one side of the first sub-pixel region of the pixel unit and on the opposite side of the third sub-pixel region; In the second direction, a bridging trace is provided between two adjacent pixel units.

6. The display panel according to claim 5, characterized in that, The pixel unit further includes a common electrode electrically connected to the common electrode trace, and the projection of the common electrode on the substrate is at least partially located within the projections of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region on the substrate; In the second direction, the common electrode is partially recessed at the corner of the third sub-pixel area to form an avoidance gap, and the avoidance gap between two adjacent common electrodes defines an avoidance area. The projection of the bridging trace onto the substrate is located within the projection of the avoidance area onto the substrate.

7. The display panel according to claim 6, characterized in that, The common electrode trace includes: The main body extends along the second direction, and the main body at least partially overlaps with the data line; A connecting portion is provided at both ends of the main body, and the connecting portion extends into the avoidance area; In the second direction, the bridging trace and the projection of the connection portion on the substrate have an overlapping area; Within the overlapping area, the bridging trace is electrically connected to the corresponding connection portion through bridging holes.

8. The display panel according to claim 6, characterized in that, The common electrode includes multiple parallel branch electrodes and a peripheral electrode connected to the branch electrodes from the end, with a light-transmitting gap between adjacent branch electrodes. The projection of the light-transmitting gap onto the substrate is located within the projections of the first sub-pixel area, the second sub-pixel area, and the third sub-pixel area onto the substrate.

9. The display panel according to claim 6, characterized in that, A transistor region is formed at the intersection of the scan line and the data line; The transistor region located on one side of the pixel unit at least partially overlaps with the avoidance region.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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