Intelligent cockpit-based dual-system power management method and system, and electronic device

Abstract

This application discloses a dual-system power management method, system, and electronic device based on a smart cockpit, relating to the field of vehicle control. The method includes the following steps: deploying a first power management module in an MCU, a second power management module in a first operating system, and a third power management module in a second operating system; each of the first, second, and third power management modules constructs an independent state machine, and each state machine achieves cross-module and cross-system state coordination through message synchronization; based on the state machine coordination, the entire power management process of the smart cockpit—including power-on startup, hibernation to memory mode, and power-off and wake-up—is completed; wherein, in the hibernation to memory mode, the core system components are powered off while the storage unit maintains a self-refresh state; and in the deep hibernation mode, the core control chip and peripherals are completely powered off, and the MCU monitors the wake-up source status with low power consumption.

Description

Technical Field

[0001] This invention relates to the field of vehicle control, and in particular to a dual-system power management method based on a smart cockpit, a dual-system power management system based on a smart cockpit, electronic devices, and storage media. Background Technology

[0002] Currently, intelligentization has become the core development trend of electric vehicles. The continuous improvement of vehicle intelligence has greatly optimized user convenience. However, the number of in-vehicle interconnection peripherals is increasing, and different peripherals have different power-on timing requirements. How to achieve efficient power management of multiple devices has become a key technical aspect of the intelligent development of electric vehicles.

[0003] Currently, mainstream automotive smart cockpit hardware is based on Qualcomm's series of system-on-a-chip (SoC, such as 8155 and 8295) and microcontroller chip (MCU) as the core architecture: the SoC is responsible for running the vehicle operating system, and the MCU is equipped with an AUTOSAR standard embedded system. The two are interconnected and interact through SPI, UART communication bus and GPIO interface.

[0004] In-vehicle cockpit systems generally adopt a dual-system deployment scheme of QNX and Android: QNX, with its high real-time performance and high security, undertakes the operation of key functions such as instrument panel and HUD; while the Android system focuses on the entertainment domain, carrying user interaction applications such as navigation and multimedia.

[0005] The power management module needs to coordinate multiple units such as QNX, Android, MCU and various vehicle peripherals. How to achieve orderly scheduling of each module and stably and efficiently complete power control operations such as sleep, wake-up and power-on / off is a core technical challenge that urgently needs to be solved in the current intelligent development of electric vehicles. Summary of the Invention

[0006] In view of this, the purpose of the present invention is to provide a dual-system power management method based on a smart cockpit, a dual-system power management system based on a smart cockpit, electronic devices and storage media, aiming to achieve stable and efficient power state transitions by setting different state machines on the QNX, Android and MCU sides based on the power management method of state machines.

[0007] This invention provides the following solution:

[0008] According to one aspect of this application, a dual-system power management method based on a smart cockpit is provided, comprising the following steps:

[0009] Deploy the first power management module in the MCU, the second power management module in the first operating system, and the third power management module in the second operating system;

[0010] The first, second, and third power management modules each construct an independent state machine, and the state machines achieve cross-module and cross-system state coordination through message synchronization;

[0011] Based on the state machine collaboration, the entire power management process of the intelligent cockpit is completed, including power-on startup, hibernation and wake-up from sleep mode to memory mode, and power-off and wake-up from deep sleep mode.

[0012] The hibernation to memory mode is a mode in which the core system components are powered off, but the storage unit keeps refreshing to achieve fast recovery;

[0013] Deep sleep mode is a mode in which the core control chip and peripherals are completely powered down, and the MCU monitors the wake-up source with low power consumption.

[0014] Furthermore, the state machine of the first power management module includes a running state, a power-down preparation state, a deep sleep preparation state, a sleep-to-memory preparation state, and a corresponding power-down execution state. The state transition satisfies one of the following conditions:

[0015] When a power-off signal is detected, there is no network wake-up source, and the core control chip has not entered sleep mode, the system transitions from the running state to the power-down preparation state.

[0016] When a power-on signal is detected and the core control chip has not entered hibernation, the system transitions from the power-down preparation state, the deep hibernation-related state, or the hibernation-to-memory-related state to the running state.

[0017] When a power-off signal is detected, there is no network wake-up source, the system is set to deep sleep mode, and a deep sleep feedback is received from the first operating system or a preset timeout condition is met, the system transitions from the power-down preparation state to the deep sleep preparation state.

[0018] When a power-off signal is detected, there is no network wake-up source, the system is set to hibernate to memory mode, and the preset timeout conditions are met, the system transitions from the power-off preparation state to the hibernate to memory preparation state.

[0019] Based on the hibernation state feedback or preset timeout conditions of the core control chip, the system transitions from the deep hibernation preparation state or hibernation to the memory preparation state to the corresponding power-down execution state, and performs the power-down operation of the peripheral device or the core control chip.

[0020] Furthermore, the state machine of the second power management module includes a running state, a power-down preparation state, a deep sleep state, and a sleep-to-memory state. The state transitions satisfy one of the following conditions:

[0021] Upon receiving the power-down preparation signal from the MCU, the system transitions from the running state to the power-down preparation state.

[0022] Upon successful startup and receipt of the running status signal from the MCU, the system transitions from the power-down preparation state to the running state.

[0023] Upon receiving a deep sleep signal from the MCU, the system transitions from the power-down preparation state to the deep sleep state and triggers the first operating system to power down.

[0024] Upon receiving the sleep-to-memory signal from the MCU, the system transitions from the power-down preparation state to the sleep-to-memory state and triggers the first operating system to enter sleep mode.

[0025] When the MCU sends a running status signal, the system transitions from deep sleep state or sleep state to memory state and then to running state.

[0026] Furthermore, the state machine of the third power management module includes a startup state, a running state, a power-down preparation state, a sleep state, and a power-off state. The state transitions satisfy one of the following conditions:

[0027] When the second operating system finishes booting up and receives the running signal from the first operating system, or when the first operating system is powered on again and triggered, it transitions from the boot state to the running state.

[0028] Upon receiving the power-down preparation signal from the first operating system, the system transitions from the running state to the power-down preparation state.

[0029] Upon receiving the running signal from the first operating system, the system transitions from the power-down preparation state to the running state.

[0030] Upon receiving a deep sleep signal from the first operating system, the system transitions from the power-down preparation state to the power-off state and shuts down the peripheral power supply in sequence.

[0031] Upon receiving the hibernation to memory signal from the first operating system, the system transitions from the power-down preparation state to the hibernation state, saving the runtime state to support rapid recovery.

[0032] When the first operating system is powered on again, it transitions from the shutdown or hibernation state to the startup state.

[0033] Furthermore, the power-on startup process includes:

[0034] After detecting the power-on signal, the MCU enters the running state, powers on the core control chip and peripherals according to the preset timing, and continuously sends running status signals to the first operating system.

[0035] After the first operating system starts up, it receives the running status signal, enters the running state, and triggers the second operating system to start. It continuously sends the running status signal to the second operating system and monitors the startup status of the second operating system.

[0036] After the second operating system starts up, it receives the running status signal, enters the running state, powers on the associated peripherals according to the preset timing sequence, and sends a startup completion signal.

[0037] The entire system has entered a stable operating state and the power-on process has been completed.

[0038] Furthermore, the process of switching from sleep to memory mode includes:

[0039] After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system.

[0040] After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system.

[0041] After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare for hibernation.

[0042] After the preset timeout condition is met, the MCU enters sleep mode to memory preparation mode and sends the corresponding mode signal to the first operating system.

[0043] After receiving the signal, the first operating system enters sleep mode in memory and sends a mode signal to the second operating system. After the second operating system enters sleep mode, the first operating system enters sleep mode and feeds back to the MCU.

[0044] After receiving the sleep feedback, the MCU monitors the sleep state of the core control chip, cuts off the power to the peripherals or forces them to power down according to the preset timing sequence, and completes the sleep process.

[0045] Furthermore, the deep sleep mode process includes:

[0046] After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system.

[0047] After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system.

[0048] After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare to shut down.

[0049] After the preset timeout conditions are met, the MCU enters a deep sleep preparation state and sends the corresponding mode signal to the first operating system.

[0050] After receiving the signal, the first operating system enters a deep sleep state and sends a mode signal to the second operating system. After the second operating system enters the power-off state, it powers down and sends feedback to the MCU.

[0051] After receiving the power-down feedback, the MCU cuts off the power supply to the core control chip and peripherals according to the preset timing, enters the low-power monitoring state, and completes the deep sleep process.

[0052] According to two aspects of this application, a dual-system power management device based on a smart cockpit is provided, comprising:

[0053] Hardware layer, power management core layer, and power status detection unit;

[0054] The hardware layer includes: main control chip, MCU microcontroller, and peripheral units.

[0055] The main control chip and the MCU microcontroller are connected through a communication bus. The MCU is connected to the peripheral unit through the communication bus. The main control chip is equipped with a first operating system and a second operating system. The two operating systems run independently.

[0056] The power management core layer consists of a first power management module deployed on the MCU, a second power management module deployed on the first operating system, and a third power management module deployed on the second operating system. Each module contains an independent state machine and achieves state synchronization through message interaction.

[0057] Power status detection unit: used to detect vehicle power start and stop signals, and realize power-on trigger and power-off trigger;

[0058] The system supports stable operation and state switching in power-on startup, hibernation to memory mode, and deep hibernation mode through the coordinated state machines of each power management module.

[0059] According to three aspects of this application, an electronic device is provided, comprising: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0060] The memory stores a computer program that, when executed by a processor, causes the processor to perform steps of a dual-system power management method based on a smart cockpit.

[0061] According to four aspects of this application, a computer-readable storage medium is provided that stores a computer program executable by an electronic device, which, when run on the electronic device, causes the electronic device to perform the steps of a dual-system power management method based on a smart cockpit.

[0062] Compared with the prior art, the present invention has the following advantages:

[0063] This application uses a SoC to support the dual operation of QNX and Android systems, while the MCU is dedicated to interfacing with the SoC and managing the power supply of peripherals and peripherals. This separates the core system's computing power from the power control of peripherals and peripherals, ensuring the computing performance of the vehicle system while achieving independent and precise power control of peripherals, reducing the load on a single chip and improving the stability of hardware operation. Attached Figure Description

[0064] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0065] Figure 1 This is a flowchart of a dual-system power management method based on a smart cockpit provided by one or more embodiments of the present invention.

[0066] Figure 2 This is a framework diagram of a dual-system power management system based on an intelligent cockpit provided by one or more embodiments of the present invention.

[0067] Figure 3 This is a hardware connection block diagram of a dual-system power management system based on a smart cockpit, provided by one or more embodiments of the present invention.

[0068] Figure 4 This is a logical block diagram of a hardware connection block diagram of a dual-system power management system based on an intelligent cockpit provided by one or more embodiments of the present invention.

[0069] Figure 5 This is a power module architecture diagram of a dual-system power management system based on a smart cockpit, provided by a specific embodiment of the present invention.

[0070] Figure 6 This is a schematic diagram of the mcu_pm state machine provided in a specific embodiment of the present invention.

[0071] Figure 7 This is a schematic diagram of the qnx_pm state machine provided in a specific embodiment of the present invention.

[0072] Figure 8 This is a schematic diagram of the Android_pm state machine provided in a specific embodiment of the present invention.

[0073] Figure 9This is a block diagram of an electronic device structure according to one or more embodiments of the present invention, which provides a dual-system power management method based on a smart cockpit. Detailed Implementation

[0074] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, and “multiple” generally includes at least two unless the context clearly indicates otherwise.

[0076] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0077] It should be understood that although the terms first, second, third, etc., may be used in the embodiments of this application, these descriptions should not be limited to these terms. These terms are only used to distinguish the descriptions. For example, first may also be referred to as second without departing from the scope of the embodiments of this application, and similarly, second may also be referred to as first.

[0078] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0079] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0080] It should be noted that any symbols and / or numbers present in the specification that are not marked in the accompanying drawings are not reference numerals.

[0081] Figure 1 This is a flowchart of a dual-system power management method based on a smart cockpit provided by one or more embodiments of the present invention.

[0082] like Figure 1 As shown, it includes the following steps:

[0083] Step S1: Deploy the first power management module in the MCU, deploy the second power management module in the first operating system, and deploy the third power management module in the second operating system.

[0084] Specifically, the state machine of the first power management module includes a running state, a power-down preparation state, a deep sleep preparation state, a sleep-to-memory preparation state, and a corresponding power-down execution state. The state transitions satisfy one of the following conditions:

[0085] When a power-off signal is detected, there is no network wake-up source, and the core control chip has not entered sleep mode, the system transitions from the running state to the power-down preparation state.

[0086] When a power-on signal is detected and the core control chip has not entered hibernation, the system transitions from the power-down preparation state, the deep hibernation-related state, or the hibernation-to-memory-related state to the running state.

[0087] When a power-off signal is detected, there is no network wake-up source, the system is set to deep sleep mode, and a deep sleep feedback is received from the first operating system or a preset timeout condition is met, the system transitions from the power-down preparation state to the deep sleep preparation state.

[0088] When a power-off signal is detected, there is no network wake-up source, the system is set to hibernate to memory mode, and the preset timeout conditions are met, the system transitions from the power-off preparation state to the hibernate to memory preparation state.

[0089] Based on the hibernation state feedback or preset timeout conditions of the core control chip, the system transitions from the deep hibernation preparation state or hibernation to the memory preparation state to the corresponding power-down execution state, and performs the power-down operation of the peripheral device or the core control chip.

[0090] The state machine of the second power management module includes a running state, a power-down preparation state, a deep sleep state, and a sleep-to-memory state. The state transitions satisfy one of the following conditions:

[0091] Upon receiving the power-down preparation signal from the MCU, the system transitions from the running state to the power-down preparation state.

[0092] Upon successful startup and receipt of the running status signal from the MCU, the system transitions from the power-down preparation state to the running state.

[0093] Upon receiving a deep sleep signal from the MCU, the system transitions from the power-down preparation state to the deep sleep state and triggers the first operating system to power down.

[0094] Upon receiving the sleep-to-memory signal from the MCU, the system transitions from the power-down preparation state to the sleep-to-memory state and triggers the first operating system to enter sleep mode.

[0095] When the MCU sends a running status signal, the system transitions from deep sleep state or sleep state to memory state and then to running state.

[0096] The state machine of the third power management module includes a startup state, a running state, a power-down preparation state, a hibernation state, and a power-off state. The state transitions satisfy one of the following conditions:

[0097] When the second operating system finishes booting up and receives the running signal from the first operating system, or when the first operating system is powered on again and triggered, it transitions from the boot state to the running state.

[0098] Upon receiving the power-down preparation signal from the first operating system, the system transitions from the running state to the power-down preparation state.

[0099] Upon receiving the running signal from the first operating system, the system transitions from the power-down preparation state to the running state.

[0100] Upon receiving a deep sleep signal from the first operating system, the system transitions from the power-down preparation state to the power-off state and shuts down the peripheral power supply in sequence.

[0101] Upon receiving the hibernation to memory signal from the first operating system, the system transitions from the power-down preparation state to the hibernation state, saving the runtime state to support rapid recovery.

[0102] When the first operating system is powered on again, it transitions from the shutdown or hibernation state to the startup state.

[0103] Step S2: The first, second, and third power management modules each construct an independent state machine, and each state machine achieves cross-module and cross-system state coordination through message synchronization;

[0104] Step S3: Based on the state machine collaboration, complete the entire power management process of the intelligent cockpit, including power-on startup, hibernation and wake-up from sleep mode to memory mode, and power-off and wake-up from deep sleep mode.

[0105] The hibernation to memory mode is a mode in which the core system components are powered off, but the storage unit keeps refreshing to achieve fast recovery;

[0106] Deep sleep mode is a mode in which the core control chip and peripherals are completely powered down, and the MCU monitors the wake-up source with low power consumption.

[0107] Specifically, the power-on startup process includes:

[0108] After detecting the power-on signal, the MCU enters the running state, powers on the core control chip and peripherals according to the preset timing, and continuously sends running status signals to the first operating system.

[0109] After the first operating system starts up, it receives the running status signal, enters the running state, and triggers the second operating system to start. It continuously sends the running status signal to the second operating system and monitors the startup status of the second operating system.

[0110] After the second operating system starts up, it receives the running status signal, enters the running state, powers on the associated peripherals according to the preset timing sequence, and sends a startup completion signal.

[0111] The entire system has entered a stable operating state and the power-on process has been completed.

[0112] The process of switching from sleep to memory mode includes:

[0113] After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system.

[0114] After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system.

[0115] After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare for hibernation.

[0116] After the preset timeout condition is met, the MCU enters sleep mode to memory preparation mode and sends the corresponding mode signal to the first operating system.

[0117] After receiving the signal, the first operating system enters sleep mode in memory and sends a mode signal to the second operating system. After the second operating system enters sleep mode, the first operating system enters sleep mode and feeds back to the MCU.

[0118] After receiving the sleep feedback, the MCU monitors the sleep state of the core control chip, cuts off the power to the peripherals or forces them to power down according to the preset timing sequence, and completes the sleep process.

[0119] The deep sleep mode process includes:

[0120] After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system.

[0121] After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system.

[0122] After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare to shut down.

[0123] After the preset timeout condition is met, the MCU enters a deep sleep preparation state and sends the corresponding mode signal to the first operating system.

[0124] After receiving the signal, the first operating system enters a deep sleep state and sends a mode signal to the second operating system. After the second operating system enters the power-off state, it powers down and sends feedback to the MCU.

[0125] After receiving the power-down feedback, the MCU cuts off the power supply to the core control chip and peripherals according to the preset timing, enters the low-power monitoring state, and completes the deep sleep process.

[0126] Specifically, an independent power management module and state machine are deployed in layers using an MCU and dual operating systems. Cross-module and cross-system collaboration is achieved through message synchronization, reducing module coupling and improving the reliability, robustness and maintainability of the system power management.

[0127] Each power management module has clearly defined state machine transition conditions to avoid state confusion and timing conflicts, ensuring the stability and accuracy of power state switching.

[0128] It supports both hibernation to memory mode and deep hibernation mode, balancing fast wake-up experience with ultra-low power consumption requirements, and adapting to the needs of various smart cockpit usage scenarios.

[0129] The power-on and power-off processes employ an MCU-controlled, step-by-step timing mechanism to avoid voltage surges, data loss, and peripheral malfunctions, thereby extending hardware lifespan and improving system stability.

[0130] Collaborative management and control can be achieved through message synchronization, eliminating the need for additional dedicated hardware modifications, reducing design costs, and improving the versatility and portability of the method.

[0131] By combining timeout conditions and status feedback mechanisms, the fault tolerance capability in abnormal scenarios is enhanced, avoiding problems such as system freezes, inability to hibernate, or power failure.

[0132] Figure 2 This is a framework diagram of a dual-system power management system based on an intelligent cockpit provided by one or more embodiments of the present invention.

[0133] like Figure 2 As shown, it includes:

[0134] Hardware layer, power management core layer, and power status detection unit;

[0135] The hardware layer includes: main control chip, MCU microcontroller, and peripheral units.

[0136] The main control chip and the MCU microcontroller are connected through a communication bus. The MCU is connected to the peripheral unit through the communication bus. The main control chip is equipped with a first operating system and a second operating system. The two operating systems run independently.

[0137] The power management core layer consists of a first power management module deployed on the MCU, a second power management module deployed on the first operating system, and a third power management module deployed on the second operating system. Each module contains an independent state machine and achieves state synchronization through message interaction.

[0138] Power status detection unit: used to detect vehicle power start and stop signals, and realize power-on trigger and power-off trigger;

[0139] The system supports stable operation and state switching in power-on startup, hibernation to memory mode, and deep hibernation mode through the coordinated state machines of each power management module.

[0140] Figure 3 This is a hardware connection block diagram of a dual-system power management system based on a smart cockpit, provided by one or more embodiments of the present invention.

[0141] like Figure 3 As shown, it includes:

[0142] The cockpit power control hardware is implemented using a SoC+MCU approach. The vehicle infotainment software runs on the SoC, which uses a Qualcomm 8155 or 8295 chip and employs a dual-system architecture of QNX and Android. The QNX system is responsible for steering wheel control, instrument cluster, etc., while the Android system is responsible for Wi-Fi, Bluetooth, USB, camera, microphone, etc. The MCU connects the SoC and related components and manages their power supply.

[0143] The cockpit domain typically provides two power modes: DEEPSLEEP and STR. DEEPSLEEP refers to a low-power state where all peripherals and the SoC are powered down, but the MCU remains powered on, monitoring wake-up sources such as the IG Line. STR refers to a Qualcomm chip-provided Suspend to RAM mode where all CPU cores, peripherals, and IP cores are powered down, and the internal bus clock is reduced to the lowest frequency for minimal power consumption. DDR enters self-refresh mode, and the system quickly recovers from STR to normal state by monitoring interrupt responses. This invention designs state machines for the QNX, Android, and MCU modules based on Qualcomm chips 8155 and 8295. The state machines synchronize their states via messages to complete the power management of the vehicle system, i.e., entering DEEPSLEEP or STR.

[0144] Figure 4 This is a logical block diagram of a hardware connection block diagram of a dual-system power management system based on an intelligent cockpit provided by one or more embodiments of the present invention.

[0145] like Figure 4 As shown, it includes:

[0146] The cockpit domain power management module includes two sub-modules: SoC and MCU. The SoC module runs QNX and Android systems, while the MCU connects to the device via a communication bus (such as CAN bus). The SoC and MCU are connected via communication buses such as SPI.

[0147] The QNX system includes modules such as MCU_service, qnx_pm, service layer, and applications. MCU_service processes signals transmitted between the MCU and VHAL module and forwards them to the service layer and qnx_pm module, and receives signals from the service layer and qnx_pm module and forwards them to the MCU and VHAL module. The qnx_pm module handles the power management of the QNX system. The service layer provides service interfaces for the application layer. The application modules refer to user-related applications such as instruments and control systems.

[0148] The Android system includes modules such as VHA, android_pm, service layer, and application. VHA processes signals transmitted between the MCU and MCU_service module and forwards them to the service layer and android_pm module. It also receives signals from the service layer and android_pm module and forwards them to the MCU and MCU_service module.

[0149] android_pm is the power management module of the Android system; the service layer provides service interfaces for the application layer; the application module refers to applications that interact with the user, such as maps, music, etc.

[0150] The MCU module runs data transmission and mcu_pm modules, among others. The data transmission module interacts with other devices, I / O, SoC, mcu_pm, and other modules. The mcu_pm module is the power management module on the MCU side.

[0151] Figure 5 This is a power module architecture diagram of a dual-system power management system based on a smart cockpit, provided by a specific embodiment of the present invention.

[0152] like Figure 5 As shown, it includes:

[0153] mcu_pm module

[0154] 1. Detect the vehicle power status, such as IG Line and DoIP Active Line. IG Line is powered on when it is high and powered off when it is low. DoIP Active Line is powered on when it is high and powered off when it is low.

[0155] 2. Interact with the qnx_pm module, send the current vehicle power status to qnx_pm, and determine the current action based on the status feedback from qnx_pm.

[0156] When the power-down conditions are met, the device notifies the other device to power down in the agreed sequence and puts the MCU into a low-power state, only monitoring trigger sources such as the IG line.

[0157] Figure 6 This is a schematic diagram of the mcu_pm state machine provided in a specific embodiment of the present invention.

[0158] like Figure 6 As shown, the switching conditions are represented by numbers 1, 2, 3, 4, 5, 6, and 7. PMIC_IO is controlled by Qualcomm and goes high when entering sleep mode (Suspend to RAM mode); all others are low. Details are as follows:

[0159] 1. When the power signal is IG OFF, there is no network wake-up source, and PMIC_IO is low, the system switches from the ON state to the SHUTDOWN_PREPARE state.

[0160] 2. When the power signal changes from IG OFF to IG ON and PMIC_IO is low, the system switches back from the SHUTDOWN_PREPARE state to the ON state.

[0161] 3. When the power signal is IG OFF, there is no network wake-up source, the power mode is DEEPSLEEP, PMIC_IO is low, and either QNX enters DEEPSLEEP or reaches a 180s timeout condition, the system switches from SHUTDOWN_PREPARE state to DEEPSLEEP state.

[0162] 4. When the power signal changes from IG OFF to IG ON and PMIC_IO is low, the system switches back from the DEEPSLEEP state to the ON state.

[0163] 5. When the power signal is IG OFF, there is no network wake-up source, the power mode is STR, PMIC_IO is low, and this condition lasts for 60 seconds, the system switches from the SHUTDOWN_PREPARE state to the STR state.

[0164] 6. When the power signal is IG OFF, there is no network wake-up source, the power mode is STR, and PMIC_IO goes high, the system switches from the STR state to the STR_POST state.

[0165] 7. When the power signal is IG OFF, there is no network wake-up source, the power mode is STR, PMIC_IO is low, and a 300s timeout is reached, the system switches from the STR state to the DEEPSLEEP_POST state.

[0166] 8. When the power signal is IG OFF, there is no network wake-up source, the power mode is DEEPSLEEP, PMIC_IO is low, and a 150s timeout is reached, the system switches from the DEEPSLEEP state to the DEEPSLEEP_POST state.

[0167] Actions performed in each state:

[0168] ON state;

[0169] Send an ON command to QNX;

[0170] The power signal is continuously polled. If the IG signal is detected to change from ON to OFF, the system automatically enters the SHUTDOWN_PREPARE state.

[0171] SHUTDOWN_PREPARE status;

[0172] Send the SHUTDOWN_PREPARE command to QNX;

[0173] If the second transition condition is met, then switch back to the ON state;

[0174] Then, according to the flow conditions in Articles 3 and 5, it enters the DEEPSLEEP or STR state respectively.

[0175] DEEPSLEEP status

[0176] Send the DEEPSLEEP command to QNX;

[0177] If the second transition condition is met, then switch back to the ON state;

[0178] If condition 7 is met, the process will enter the DEEPSLEEP_POST state.

[0179] STR state;

[0180] Send the DEEPSLEEP command to QNX;

[0181] If condition 4 is met, then switch back to the ON state;

[0182] If condition 6 is met, then the process enters the STR_POST state.

[0183] If condition 7 is met, the process will enter the DEEPSLEEP_POST state.

[0184] STR_POST status;

[0185] The MCU cuts off the power to the peripherals according to the power-down sequence, and the system enters sleep mode.

[0186] If condition 4 is met, then switch back to the ON state.

[0187] DEEPSLEEP_POST status;

[0188] The MCU cuts off the power to the SoC and peripherals according to the power-down sequence, and the system enters sleep mode;

[0189] If condition 4 is met, then switch back to the ON state.

[0190] Figure 7 This is a schematic diagram of the qnx_pm state machine provided in a specific embodiment of the present invention.

[0191] like Figure 7 As shown, the qnx_pm module

[0192] 1. Interact with the mcu_pm and android_pm modules to determine the next state based on the current state of the MCU, Android, and QNX.

[0193] 2. Monitor the virtual machine status and take appropriate actions based on the current status (such as restarting or shutting down).

[0194] The circulation conditions are represented by serial numbers 1, 2, 3, 4, 5, and 6, as detailed below:

[0195] 1. When the system receives the SHUTDOWN_PREPARE command sent by the MCU, it switches from the ON state to the SHUTDOWN_PREPARE state;

[0196] 2. When the system is in the SHUTDOWN_PREPARE state and has started successfully, and receives the ON state command sent by the MCU, it switches from the SHUTDOWN_PREPARE state to the ON state;

[0197] 3. When the system is in the SHUTDOWN_PREPARE state, if it receives a DEEPSLEEP instruction from the MCU, it switches to the DEEPSLEEP state;

[0198] 4. When the system is in the SHUTDOWN_PREPARE state, if it receives the STR command from the MCU, it switches to the STR state;

[0199] 5. When the system is in STR state, if it receives an ON command from the MCU, it switches to ON state;

[0200] 6. When the system is in the DEEPSLEEP state, if it receives an ON command from the MCU, it switches to the ON state.

[0201] The system will execute corresponding preset actions in different operating states and switch states according to relevant conditions. The specific actions are described below:

[0202] When the system is in the ON state, it mainly performs three actions: first, it receives the status command sent by the MCU; second, it sends the ON status signal to the Android terminal; and third, it switches to the SHUTDOWN_PREPARE state according to preset condition 1.

[0203] When the system is in the SHUTDOWN_PREPARE state, it performs the following actions: First, it receives the status command sent by the MCU; second, it sends the SHUTDOWN_PREPARE status signal to the Android terminal and monitors the sleep state of the Android terminal in real time; finally, according to preset conditions 2, 3, and 4, it switches to the ON state, DEEPSLEEP state, and STR state respectively.

[0204] When the system is in the DEEPSLEEP state, the following actions are taken: First, receive the status command sent by the MCU; second, when preset condition 6 is met, switch to the ON state; third, if the Android terminal is detected to be performing a power-off operation, call the power_down method to complete the power-down of the QNX system.

[0205] When the system is in the STR state, the specific actions include: first, receiving the status command sent by the MCU; second, switching to the ON state when the preset condition 6 is met; and third, if the Android terminal is detected to be successfully hibernating, calling the suspend method to put the system into the Suspend to ram (suspend to memory) mode.

[0206] Figure 8 This is a schematic diagram of the Android_pm state machine provided in a specific embodiment of the present invention.

[0207] like Figure 8 As shown, it includes:

[0208] Manage and monitor the power status of modules such as Wi-Fi and Bluetooth, and perform corresponding actions (such as turning off, turning on, restarting, etc.) according to different statuses.

[0209] It interacts with the qnx_pm module to determine the power status of modules such as Wi-Fi and Bluetooth based on the current state.

[0210] The system will execute corresponding preset actions in different operating states and switch states according to relevant conditions. The specific actions are described below:

[0211] 1. Flow Sequence Number 1: The flow state is BOOTING (startup state) → ON (running state). The flow condition is (Android starts successfully && receives the ON signal sent by QNX) || either condition 6 or 7 is met. During this flow, a startup timeout threshold is set. If Android startup times out or fails to complete, or fails to respond to the ON signal from QNX within the timeout period, the system will trigger a feedback mechanism to re-trigger the BOOTING state or enter the exception handling process to avoid startup freezing. At the same time, after Android starts, it will send a startup success signal to QNX. After QNX confirms the feedback, it completes the collaboration to ensure flow synchronization and prevents accidental entry into the ON state.

[0212] 2. Flow Sequence Number 2: Flow state is ON (running state) → SHUTDOWN_PREPARE (power-down preparation state). The flow condition is receiving the SHUTDOWN_PREPARE signal sent by QNX. After receiving the signal, the Android system enters the power-down preparation process and simultaneously sends feedback to QNX that it has entered the SHUTDOWN_PREPARE state. If subsequent instructions (DEEPSLEEP, STR, ON) from QNX are not received within the preset timeout period, the system will trigger the timeout protection mechanism, maintain the SHUTDOWN_PREPARE state, and continuously send status query signals to QNX to avoid accidental flow to other states or power-down lag.

[0213] 3. Flow Sequence Number 3: The flow state is SHUTDOWN_PREPARE (power-down preparation state) → ON (running state), and the flow condition is receiving the ON signal sent by QNX. After receiving the signal, the Android system immediately starts the running state recovery process and reports the recovery progress to QNX; if the recovery process times out or fails to successfully report the recovery completion signal, QNX will resend the ON signal to trigger a secondary recovery, avoiding the system from getting stuck in an intermediate state and freezing.

[0214] 4. Transition Sequence Number 4: The transition state is SHUTDOWN_PREPARE (power-down preparation state) → OFF (power-off state). The transition condition is receiving the DEEPSLEEP signal sent by QNX. After receiving the signal, the Android system executes the power-off process, shuts down associated peripherals and saves critical data, while simultaneously sending feedback on the power-off progress to QNX. If the power-off process times out or no power-off completion signal is received, QNX will trigger a forced power-off command to ensure the system successfully enters the OFF state and avoids the problem of being unable to power down.

[0215] 5. Transition Sequence Number 5: The transition state is SHUTDOWN_PREPARE (power-down preparation state) → SUSPEND (sleep state), and the transition condition is receiving the STR (sleep to memory) signal sent by QNX. After receiving the signal, the Android system saves its running state, enters sleep mode, and sends a sleep completion signal back to QNX. If the sleep process times out or fails to send a sleep status signal, the system will automatically restart the sleep process or trigger the timeout fault tolerance mechanism to maintain the SHUTDOWN_PREPARE state and wait for QNX to issue a new instruction, thus avoiding sleep failure or system freeze.

[0216] 6. Flow Sequence Number 6: Flow state is OFF (power off) → BOOTING (boot up). The flow condition is that QNX re-powers on Android (controlled by the system). During the power-on process, the Android system feeds back the power-on status to QNX in real time. If the power-on timeout does not enter the BOOTING state, QNX will trigger a second power-on or enter the anomaly troubleshooting process to avoid problems such as failure to wake up or power-on freeze. At the same time, a power-on feedback timeout threshold is set to ensure that QNX obtains the Android power-on status in a timely manner, enabling cross-system collaboration.

[0217] 7. Transition Sequence Number 7: The transition state is SUSPEND (sleep state) → BOOTING (boot state), and the transition condition is that QNX re-powers on the Android system (controlled by the system). After the Android system is powered on, it quickly restores the previously saved running state and simultaneously sends wake-up progress feedback to QNX. If the wake-up process times out or no wake-up completion signal is sent, QNX will trigger a forced wake-up command to avoid the problem of the system failing to wake up and remaining in the sleep state, thus ensuring the stability of the wake-up process.

[0218] The system state is switched through transition conditions 1 to 7:

[0219] When transition condition 1 is met (Android starts and receives an ON signal from QNX, or either condition 6 or 7 is met), BOOTING → ON;

[0220] When transition condition 2 is met (QNX sends SHUTDOWN_PREPARE), ON → SHUTDOWN_PREPARE;

[0221] When transition condition 3 (receive QNX and send ON) is met, SHUTDOWN_PREPARE → ON;

[0222] When flow condition 4 (receiving QNX and sending DEEPSLEEP) is met, SHUTDOWN_PREPARE → OFF;

[0223] When transition condition 5 (receiving QNX and sending STR) is met, SHUTDOWN_PREPARE → SUSPEND;

[0224] When transition condition 6 is met (QNX repowers Android, controlled by the system), OFF → BOOTING;

[0225] When transition condition 7 is met (QNX re-powers Android, controlled by the system), SUSPEND → BOOTING.

[0226] Figure 9 This is a block diagram of an electronic device structure according to one or more embodiments of the present invention, which provides a dual-system power management method based on a smart cockpit.

[0227] like Figure 9 As shown, this application provides an electronic device, including: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0228] The memory stores a computer program that, when executed by the processor, causes the processor to perform steps of a dual-system power management method based on a smart cockpit.

[0229] This application also provides a computer-readable storage medium storing a computer program executable by an electronic device, which, when run on the electronic device, causes the electronic device to perform steps of a dual-system power management method based on a smart cockpit.

[0230] For the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0231] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0232] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-system power management method based on a smart cockpit, characterized in that, The intelligent cockpit is based on a hardware architecture built around a main control chip and a microcontroller, and is equipped with a dual system consisting of a first operating system and a second operating system. The method includes: Deploy the first power management module in the MCU, the second power management module in the first operating system, and the third power management module in the second operating system; The first, second, and third power management modules each construct an independent state machine, and the state machines achieve cross-module and cross-system state coordination through message synchronization; Based on the state machine collaboration, the entire power management process of the intelligent cockpit is completed, including power-on startup, hibernation and wake-up from sleep mode to memory mode, and power-off and wake-up from deep sleep mode. The hibernation to memory mode involves power loss of the core system components while the storage unit remains in a self-refreshing state. The deep sleep mode is characterized by the complete power-down of the core control chip and peripherals, with the MCU monitoring the wake-up source status at low power.

2. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, include: The state machine of the first power management module includes a running state, a power-down preparation state, a deep sleep preparation state, a sleep-to-memory preparation state, and a corresponding power-down execution state. The state transition satisfies one of the following conditions: When a power-off signal is detected, there is no network wake-up source, and the core control chip has not entered sleep mode, the system transitions from the running state to the power-down preparation state. When a power-on signal is detected and the core control chip has not entered hibernation, the system transitions from the power-down preparation state, the deep hibernation-related state, or the hibernation-to-memory-related state to the running state. When a power-off signal is detected, there is no network wake-up source, the system is set to deep sleep mode, and a deep sleep feedback is received from the first operating system or a preset timeout condition is met, the system transitions from the power-down preparation state to the deep sleep preparation state. When a power-off signal is detected, there is no network wake-up source, the system is set to hibernate to memory mode, and the preset timeout conditions are met, the system transitions from the power-off preparation state to the hibernate to memory preparation state. Based on the hibernation state feedback or preset timeout conditions of the core control chip, the system transitions from the deep hibernation preparation state or hibernation to the memory preparation state to the corresponding power-down execution state, and performs the power-down operation of the peripheral device or the core control chip.

3. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, include: The state machine of the second power management module includes a running state, a power-down preparation state, a deep sleep state, and a sleep-to-memory state. The state transitions satisfy one of the following conditions: Upon receiving the power-down preparation signal from the MCU, the system transitions from the running state to the power-down preparation state. Upon successful startup and receipt of the running status signal from the MCU, the system transitions from the power-down preparation state to the running state. Upon receiving a deep sleep signal from the MCU, the system transitions from the power-down preparation state to the deep sleep state and triggers the first operating system to power down. Upon receiving the sleep-to-memory signal from the MCU, the system transitions from the power-down preparation state to the sleep-to-memory state and triggers the first operating system to enter sleep mode. When the MCU sends a running status signal, the system transitions from deep sleep state or sleep state to memory state and then to running state.

4. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, include: The state machine of the third power management module includes a startup state, a running state, a power-down preparation state, a sleep state, and a power-off state. The state transitions satisfy one of the following conditions: When the second operating system finishes booting up and receives the running signal from the first operating system, or when the first operating system is powered on again and triggered, it transitions from the boot state to the running state. Upon receiving the power-down preparation signal from the first operating system, the system transitions from the running state to the power-down preparation state. Upon receiving the running signal from the first operating system, the system transitions from the power-down preparation state to the running state. Upon receiving a deep sleep signal from the first operating system, the system transitions from the power-down preparation state to the power-off state and shuts down the peripheral power supply in sequence. Upon receiving the hibernation to memory signal from the first operating system, the system transitions from the power-down preparation state to the hibernation state, saving the runtime state to support rapid recovery. When the first operating system is powered on again, it transitions from the shutdown or hibernation state to the startup state.

5. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, The power-on startup process includes: After detecting the power-on signal, the MCU enters the running state, powers on the core control chip and peripherals according to the preset timing, and continuously sends running status signals to the first operating system. After the first operating system starts up, it receives the running status signal, enters the running state, and triggers the second operating system to start. It continuously sends the running status signal to the second operating system and monitors the startup status of the second operating system. After the second operating system starts up, it receives the running status signal, enters the running state, powers on the associated peripherals according to the preset timing sequence, and sends a startup completion signal. The entire system has entered a stable operating state and the power-on process has been completed.

6. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, The process of switching from sleep to memory mode includes: After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system. After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system. After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare for hibernation. After the preset timeout condition is met, the MCU enters sleep mode to memory preparation mode and sends the corresponding mode signal to the first operating system. After receiving the signal, the first operating system enters sleep mode in memory and sends a mode signal to the second operating system. After the second operating system enters sleep mode, the first operating system enters sleep mode and feeds back to the MCU. After receiving the sleep feedback, the MCU monitors the sleep state of the core control chip, cuts off the power to the peripherals or forces them to power down according to the preset timing sequence, and completes the sleep process.

7. The dual-system power management method based on a smart cockpit according to claim 1, characterized in that, The deep sleep mode process includes: After detecting the power-off signal, the MCU enters the power-down preparation state and continuously sends power-down preparation signals to the first operating system. After receiving the signal, the first operating system enters the power-down preparation state and continuously sends power-down preparation signals to the second operating system. After receiving the signal, the second operating system enters the power-down preparation state and notifies the associated peripherals to prepare to shut down. After the preset timeout conditions are met, the MCU enters a deep sleep preparation state and sends the corresponding mode signal to the first operating system. After receiving the signal, the first operating system enters a deep sleep state and sends a mode signal to the second operating system. After the second operating system enters the power-off state, it powers down and sends feedback to the MCU. After receiving the power-down feedback, the MCU cuts off the power supply to the core control chip and peripherals according to the preset timing, enters the low-power monitoring state, and completes the deep sleep process.

8. A dual-system power management system based on an intelligent cockpit, characterized in that, include: Hardware layer: main control chip, MCU microcontroller, peripheral units. The main control chip is connected to the MCU via a communication bus, and the MCU is connected to the peripheral unit via the communication bus. The main control chip is equipped with a first operating system and a second operating system, and the two operating systems run independently. The power management core layer consists of a first power management module deployed on the MCU, a second power management module deployed on the first operating system, and a third power management module deployed on the second operating system. Each module contains an independent state machine and achieves state synchronization through message interaction. Power status detection unit: used to detect vehicle power start and stop signals, and realize power-on trigger and power-off trigger; The system supports stable operation and state switching in power-on startup, hibernation to memory mode, and deep hibernation mode through the coordinated state machines of each power management module.

9. An electronic device, characterized in that, include: The processor, communication interface, memory, and communication bus are connected, with the processor, communication interface, and memory communicating with each other via the communication bus. The memory stores a computer program that, when executed by the processor, causes the processor to perform the steps of the dual-system power management method based on a smart cockpit as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, It stores a computer program executable by an electronic device, which, when run on the electronic device, causes the electronic device to perform the steps of a dual-system power management method based on a smart cockpit as described in any one of claims 1-7.

Images