Industrial instrument data evidence storage middleware and pulse atomization signature method thereof

Abstract

This invention relates to the field of data evidence storage technology, and discloses an industrial instrument data evidence storage middleware and its pulse atomization signature method. The middleware includes a physical interface layer and a microcontroller unit (MCU). The transceiver circuit of the physical interface layer includes: an RC inverse attenuation network, connected in series in the receiving channel, attenuating the inverse command signal level to below the standard transceiver differential identification threshold, realizing one-way monitoring and authorization at the physical layer; and an optocoupler isolation circuit, connected in parallel in the pulse input channel, with its output directly connected to the MCU's highest priority external interrupt (EXTI) pin, forming a hard-coupled pulse triggering path. After EXTI triggering, the MCU enters the highest priority ISR, atomically locking the original evidence to a volatile buffer. After exiting the ISR, it asynchronously completes hash and PUF-derived private key signature operations in the background and sends the evidence storage frame using the bus idle window. The evidence storage data is written to the NVM logical partition through the ZoneLock mechanism and is irreversibly locked. Combined with chained hash verification, data integrity and timing are ensured.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to an industrial instrument data storage middleware and its pulse atomic signature method. Background Technology

[0002] In existing industrial instrument data storage technologies, instrument data is usually obtained by bypass monitoring or bus eavesdropping. However, due to the uncontrollability of the physical layer interface, traditional methods are difficult to achieve stable and reliable data capture without interfering with the original bus communication. At the same time, due to the lack of hardware-level atomic locking and real-time signature mechanisms, data is susceptible to tampering by system scheduling, malicious code or physical attacks during the acquisition, transmission and storage process, making it difficult to guarantee the authenticity and integrity of the stored data. In addition, existing solutions mostly rely on external key storage and centralized signature services, which pose risks of key leakage and single point of failure, making it difficult to meet the requirements of high security, high real-time performance and traceability for data storage in industrial control scenarios. Summary of the Invention

[0003] This invention provides an industrial instrument data storage middleware and its pulse atomic signature method to solve existing technical problems, thereby overcoming the shortcomings of existing technologies in terms of data capture interference, storage timeliness, key security, and data tamper-proofing.

[0004] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, an industrial instrument data storage middleware, comprising: The physical interface layer contains transceiver circuits that connect to the industrial instrument bus. The microcontroller unit (MCU) is electrically connected to the physical interface layer. The transceiver circuit includes: An RC reverse attenuation network, connected in series in the receiving channel, is configured to attenuate the reverse command signal level to below the standard transceiver recognition threshold in order to achieve one-way listening and confirmation at the physical layer. An optocoupler isolation circuit is connected in parallel to the pulse input channel, and its output is directly connected to the highest priority external interrupt EXTI pin of the MCU, forming a hard-coupled pulse triggering path. The MCU is configured as follows: When the EXTI pin detects a bus pulse, it enters the highest priority interrupt service routine (ISR). The evidence locking operation is performed atomically within the ISR: the current hardware timer count value is read and the bus data frame is captured, and the data frame and its corresponding timer count value are stored as original evidence in the volatile buffer. After exiting the ISR, the original evidence is read from the cache in the background task and the hardware cryptographic module is called to perform asynchronous signature calculation to generate a stored signature. Monitor the bus status, and when the continuous silence time of the bus reaches a preset threshold, use the bus idle window to send an independent evidence frame containing the evidence signature.

[0005] Furthermore, the MCU is also configured to autonomously derive keys based on the pin-physically non-clonable function (PUF): By measuring the threshold crossing time difference caused by parasitic capacitance differences on the EXTI pin or a specified general-purpose input / output (GPIO) pin. Extract the source of physical entropy; Crossing time difference of multiple measurements Sampling is performed, and unstable bits are filtered out using a dead-zone decision algorithm to directly generate a stable and unique private key that resides only in SRAM; The stability of the private key is determined based on the following formula for consistency verification: ; For the The threshold crossing time difference generated by the challenge If the variance of the sequence is less than the preset dead zone threshold, Then that bit The stability is determined by the number of values ​​in the sequence and is marked as stable; if the variance is greater than or equal to... If the bit is not found, it is marked as unstable and discarded to ensure that no auxiliary data is involved in the key generation process.

[0006] Furthermore, the atomic evidence locking operation is performed within the ISR, and the total time from hardware triggering to evidence storage in the cache is less than the minimum scheduling time slice of the operating system, so that the locking process of the original evidence is completed in a single, uninterruptible execution context.

[0007] Furthermore, the background asynchronous signature operation is decoupled from the ISR; the MCU calculates the original evidence digest through a hardware hash engine in the background task, and generates a digital signature through a hardware signature engine using a PUF-derived private key, thereby achieving the separation of evidence locking and signing in terms of time sequence.

[0008] Furthermore, the RC reverse attenuation network includes a resistor R and a capacitor C connected in series between the RX output terminal of the digital isolator receiver and the MCU receiver pin; its parameters are configured to permanently attenuate the reverse command signal level to below ±200 mV below the RS-485 standard transceiver differential identification threshold within a preset baud rate range.

[0009] Furthermore, the continuous silence time of the detection bus reaching a preset threshold includes: Use a hardware timer to monitor bus idle time; When the idle time reaches the frame interval T3.5 defined by the Modbus protocol, the bus is determined to enter the idle window period; where T3.5 is 3.5 character times, and when the baud rate is greater than 19200bps, T3.5 is fixed at 1.750ms; During the window period, the MCU inserts the evidence frame into the bus.

[0010] Furthermore, the protocol address field of the independent evidence frame is set to a reserved address or broadcast address of the industrial bus protocol, so that downstream standard instrument equipment, after receiving it, determines it as non-local data according to the protocol and silently discards it, thereby realizing bypass transparent transmission.

[0011] Furthermore, the MCU is configured to execute an event-triggered ZoneLock evidence chain locking mechanism: The internal non-volatile memory (NVM) is divided into multiple logical zones. Once an atomic evidence locking and asynchronous signing is completed, and the evidence frame is successfully written to the current active Zone of the NVM, the Zone is dynamically and irreversibly set to a read-only state. Subsequent evidence data is written to the next writable Zone, forming an immutable chain-like evidence storage structure based on atomic events; The integrity of the evidence storage chain is verified through a hash chain, and this verification follows the following logic: ; in, Represents the original evidence used for the i-th evidence preservation; This indicates the corresponding backend signature; This represents the chain hash value corresponding to the previous notarization, and is expressed through the chain hash value. Ensure the integrity and temporal sequence of historical data.

[0012] A pulse atomic signature method for an industrial instrument data storage middleware specifically includes the following steps: S1. Connect the physical interface layer of the middleware to the RS-485 bus in a high-impedance bypass manner. Use the RC reverse attenuation network to permanently attenuate the reverse command signal level to below ±200 mV of the differential identification threshold of the RS-485 standard transceiver. Without changing the original master station and slave station communication link, realize physical layer one-way listening and confirmation of rights. S2. When a pulse signal appears on the bus, the pulse is hard-coupled to the highest priority external interrupt EXTI pin of the MCU through the optocoupler isolation circuit, triggering the MCU to enter the highest priority interrupt service routine (ISR). S3. Perform evidence locking operation atomically within the ISR, read the current hardware timer count value to generate a precise timestamp, and capture the complete data frame transmitted on the bus based on the Modbus RTU protocol; atomically write the data frame and its corresponding timestamp as the original evidence into the volatile buffer; wherein, the total time from hardware triggering the interrupt to the evidence being stored in the buffer is less than the minimum scheduling time slice of the operating system. S4. After exiting the ISR, the original evidence is read from the cache in the background task, the hardware cryptographic module is called to perform hash operation, and the private key derived from the pin PUF is used to perform asynchronous signature operation to generate a certificate signature. S5. Monitor the continuous silence time of the bus using a hardware timer. When the silence time reaches the frame interval T3.5 defined by the Modbus protocol, determine that the bus has entered an idle window period. During the window period, insert an independent evidence frame containing the evidence signature into the bus. Here, T3.5 is 3.5 character times. When the baud rate is greater than 19200 bps, T3.5 is fixed at 1.750 ms. S6. Write the evidence data containing the original evidence and its signature into the currently active logical region Zone of the non-volatile memory NVM; after writing, dynamically and irreversibly set the Zone to read-only state and activate the next writable Zone. S7. Calculate the hash value of the evidence storage data in the current Zone, concatenate it with the hash value of the previous Zone, generate a chained hash verification value, and write it to the tail of the current Zone; the integrity of the evidence storage chain is verified through the following hash chain logic: ; in, Represents the original evidence used for the i-th evidence preservation; This indicates the corresponding backend signature; This represents the chain hash value corresponding to the previous evidence storage; during verification, the hash values ​​of each Zone are recalculated in Zone order and compared with the stored hash values ​​and signature values ​​to determine whether the data has been tampered with.

[0013] This invention provides an industrial instrument data storage middleware and its pulse atomization signature method. Compared with existing technologies, the advantages of this method are: 1. This invention achieves one-way monitoring and authorization of industrial bus communication through the design of RC reverse attenuation network at the physical layer, ensuring that the middleware can safely acquire data without interfering with the original instrument communication, and fundamentally solving the problem that traditional evidence storage devices may affect bus stability.

[0014] 2. This invention utilizes an optocoupler isolation circuit to hard couple to the highest priority external interrupt pin of the MCU, combined with atomic evidence locking operation, to ensure that the data capture triggered by the bus pulse signal has extremely low latency and is uninterruptible, effectively preventing malicious code or system scheduling from tampering with the original evidence.

[0015] 3. This invention autonomously derives private keys based on pin physical non-clonable functions, extracts physical entropy sources by measuring pin parasitic capacitance differences, and generates unique and stable device keys by combining dead-zone decision algorithms, achieving zero key storage and zero key distribution, which greatly improves the physical attack resistance of evidence storage signatures.

[0016] 4. This invention, through the time-series decoupling design of atomic evidence locking and background asynchronous signature operation, not only ensures the real-time performance of data locking, but also avoids the impact of complex operations in the interruption context on the system response, significantly improving the processing efficiency and reliability in high-frequency industrial data storage scenarios.

[0017] 5. This invention adopts an event-triggered ZoneLock evidence storage chain locking mechanism, which divides the non-volatile memory into multiple logical regions and irreversibly locks the current region after each evidence storage. Combined with hash chain verification, it constructs a hardware-level immutable evidence storage structure to ensure the integrity and time-series traceability of historical data. Attached Figure Description

[0018] Figure 1 This is a flowchart of the present invention; Figure 2 This illustrates the effect of the RC reverse attenuation network in this invention. Figure 3 This is a block diagram of the internal hardware principle in this invention; Figure 4 This is a detailed diagram of the RC attenuation network circuit in this invention; Figure 5 This is a flowchart of the PUF key derivation logic in this invention. Detailed Implementation

[0019] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Example 1

[0020] like Figure 1 and Figure 3 As shown, according to one aspect of the present invention, an industrial instrument data storage middleware is provided, comprising: a physical interface layer including transceiver circuits connected to an industrial instrument bus; and a microcontroller unit (MCU) electrically connected to the physical interface layer.

[0021] Physical layer bypass listening: Transceiver circuitry includes an RC inverse attenuation network (e.g., Figure 2 and Figure 4 (As shown) and an optocoupler isolation circuit. An RC reverse attenuation network is connected in series in the receiving channel. By precisely configuring the resistor and capacitor parameters, the reverse command signal level is attenuated to below the standard transceiver differential identification threshold, thereby achieving one-way listening and confirmation at the physical layer, ensuring that the middleware only receives data without interfering with the original bus communication. The optocoupler isolation circuit is connected in parallel in the pulse input channel, directly connected to the MCU's highest priority external interrupt EXTI pin, forming a hard-coupled pulse trigger path.

[0022] Interrupt-level atomic locking: When the EXTI pin detects a bus pulse, the MCU enters the highest-priority interrupt service routine (ISR); within the ISR, an evidence locking operation is atomically performed: the current hardware timer count value is read and the bus data frame is captured, and the data frame and its corresponding timer count value are stored as raw evidence in a volatile buffer. The total time from hardware triggering to evidence storage in the buffer is less than the minimum scheduling time slice of the operating system.

[0023] Background Signature and Evidence Output: After exiting the ISR, the MCU reads the original evidence from the buffer in a background task and calls the hardware cryptographic module to perform asynchronous signature calculation to generate an evidence signature. Subsequently, it monitors the bus status, and when the continuous silence time of the bus reaches a preset threshold, it sends an independent evidence frame containing the evidence signature using the bus idle window.

[0024] This embodiment ensures that data is not interfered with by system scheduling the moment it is generated through the dual protection of "read-only listening" and "ultra-fast interruption", which significantly improves the security and real-time performance of evidence acquisition. Example 2

[0025] like Figure 5 As shown, based on Example 1, the MCU is also configured to autonomously derive keys based on the pin-physically non-clonable function (PUF): By measuring the threshold crossover time difference caused by parasitic capacitance differences on the EXTI pin or a specified general-purpose input / output (GPIO) pin. Extract the physical entropy source; for the threshold time difference of multiple measurements Sampling is performed, and unstable bits are filtered out using a dead-zone decision algorithm to directly generate a stable and unique private key that resides only in SRAM.

[0026] The stability of the private key is determined based on the following formula for consistency verification: ; For the The crossing time difference generated by the challenge If the variance of the sequence is less than the preset dead zone threshold, Then that bit The stability is determined by the number of values ​​in the sequence and is marked as stable; if the variance is greater than or equal to... If the bit is not found, it is marked as unstable and discarded to ensure that no auxiliary data is involved in the key generation process.

[0027] The advantage of this embodiment is that it realizes the dynamic generation of private keys in SRAM and the loss of private keys upon power failure, with no auxiliary data involved throughout the process, providing a physical-level security foundation with zero storage for asynchronous signatures. Example 3

[0028] like Figure 2 and Figure 4 As shown, based on the above embodiment, the RC reverse attenuation network includes a resistor R and a capacitor C connected in series between the RX output terminal of the digital isolator receiver and the MCU receiver pin; its parameters are configured to permanently attenuate the reverse command signal level to below ±200 mV below the RS-485 standard transceiver differential identification threshold within a preset baud rate range, realizing physical layer logic disconnection and read-only authorization. The value of resistor R ranges from 470 Ω to 2.2 kΩ; the value of capacitor C ranges from 100 pF to 1 nF. Within this parameter range, the time constant of the RC network... At 0.047 Up to 2.2 between.

[0029] Meanwhile, detecting when the continuous silent time of the bus reaches a preset threshold includes: monitoring the bus idle time using a hardware timer; when the idle time reaches the frame interval T3.5 defined by the Modbus protocol, the bus is determined to have entered an idle window period; within the window period, the MCU inserts the evidence frame into the bus; where T3.5 is 3.5 character times, and when the baud rate is greater than 19200 bps, T3.5 is fixed at 1.750 ms. The protocol address field of the independent evidence frame is set to a reserved address or a broadcast address to achieve bypass pass-through. Example 4

[0030] like Figure 1 As shown, according to one aspect of the present invention, an industrial instrument data storage middleware is provided, wherein the MCU is configured to execute an event-triggered ZoneLock storage chain locking mechanism: The internal non-volatile memory (NVM) is divided into multiple logical zones. After an atomic evidence locking and asynchronous signing are completed and the evidence frame is successfully written to the current active zone of the NVM, the zone is dynamically and irreversibly set to a read-only state. Subsequent evidence data is written to the next writable zone, forming a chain-like evidence storage structure.

[0031] The integrity of the evidence storage chain is verified through a hash chain, which follows the logic below. ; in, Represents the original evidence used for the i-th evidence preservation; This indicates the corresponding backend signature, and is represented by a chained hash value. This mechanism ensures the integrity and chronological order of historical data. It implements a hardware-level anti-tampering structure that allows for "write once, read multiple times," making the chronological order of each piece of evidence verifiable. Example 5

[0032] like Figures 1 to 5 As shown, this embodiment provides a pulse atomic signature method for industrial instrument data storage middleware, specifically including the following steps: Step S1, Physical Layer One-Way Access and Listening Authority Confirmation: The middleware physical interface layer is connected to the RS-485 bus in a high-impedance bypass manner. The reverse command signal level is permanently attenuated to below the differential identification threshold ±200 mV through the RC reverse attenuation network to realize physical layer one-way listening authority confirmation. Step S2, Hard-coupled Pulse Trigger and Interrupt Response: When a pulse signal appears on the bus, it is hard-coupled to the EXTI pin of the MCU through the optocoupler isolation circuit, triggering the MCU to enter the highest priority ISR; Step S3, Atomized Evidence Locking within the ISR: Read the current hardware timer count value within the ISR to generate a timestamp and capture the complete data frame; atomically write both as original evidence into the volatile buffer; the total time taken is less than the minimum scheduling time slice of the operating system; Step S4, Background Asynchronous Signature Operation: After exiting ISR, read the original evidence in the background task, call the hash operation, and use the private key derived from PUF (Measure Pin Threshold Crossing Time Difference ΔT to Extract Physical Entropy Source) to perform asynchronous signature operation; Step S5, Bus Idle Window Bypass Transmission: Monitor the continuous silence time, determine that the idle window period has been entered when the T3.5 frame interval is reached, and send an independent evidence storage frame containing the evidence storage signature; Step S6, Partition Writing and Irreversible Locking: After writing the evidence data into the current active Zone of the NVM, set it to read-only irreversible state and activate the next writable Zone; Step S7, Chained Hash Verification: Calculate the hash value of the data in the current Zone, concatenate it with the hash value of the previous Zone, generate a chained hash verification value and write it to the end to ensure that the historical data time sequence is traceable. Example 6

[0033] like Figure 3 , Figure 4As shown, at the hardware implementation level, the microcontroller unit (MCU) integrates a hardware timer and static random access memory (SRAM), and has at least one pin supporting external edge-triggered interrupts. The cryptographic operation module can be a hardware encryption accelerator built into the MCU or an external security chip. The non-volatile memory can be Flash memory or EEPROM memory, connected to the MCU via an SPI interface or internal parallel bus. The non-volatile memory is divided into multiple logic regions, each with an independent write-protection control bit. A high-speed optocoupler is selected, with its input connected to the output of a digital isolator. Its output is connected to the MCU's operating voltage via a pull-up resistor, and simultaneously connected to the MCU's highest-priority external interrupt pin.

[0034] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A middleware for storing industrial instrument data, characterized in that, include: The physical interface layer contains transceiver circuits that connect to the industrial instrument bus. The microcontroller unit (MCU) is electrically connected to the physical interface layer. The transceiver circuit includes: An RC reverse attenuation network, connected in series in the receiving channel, is configured to attenuate the reverse command signal level to below the standard transceiver recognition threshold in order to achieve one-way listening and confirmation at the physical layer. An optocoupler isolation circuit is connected in parallel to the pulse input channel, and its output is directly connected to the highest priority external interrupt EXTI pin of the MCU, forming a hard-coupled pulse triggering path. The MCU is configured as follows: When the EXTI pin detects a bus pulse, it enters the highest priority interrupt service routine (ISR). The evidence locking operation is performed atomically within the ISR: the current hardware timer count value is read and the bus data frame is captured, and the data frame and its corresponding timer count value are stored as original evidence in the volatile buffer. After exiting the ISR, the original evidence is read from the cache in the background task and the hardware cryptographic module is called to perform asynchronous signature calculation to generate a stored signature. Monitor the bus status, and when the continuous silence time of the bus reaches a preset threshold, use the bus idle window to send an independent evidence frame containing the evidence signature.

2. The industrial instrument data storage middleware according to claim 1, characterized in that: The MCU is also configured to autonomously derive keys based on pin-physically non-clonable function (PUF) keys: By measuring the threshold crossing time difference caused by parasitic capacitance differences on the EXTI pin or a specified general-purpose input / output (GPIO) pin. Extract the source of physical entropy; Crossing time difference of multiple measurements Sampling is performed, and unstable bits are filtered out using a dead-zone decision algorithm to directly generate a stable and unique private key that resides only in SRAM; The stability of the private key is determined based on the following formula for consistency verification: ； For the The threshold crossing time difference generated by the challenge If the variance of the sequence is less than the preset dead zone threshold, Then that bit The stability is determined by the number of values ​​in the sequence and is marked as stable; if the variance is greater than or equal to... If the bit is not found, it is marked as unstable and discarded to ensure that no auxiliary data is involved in the key generation process.

3. The industrial instrument data storage middleware according to claim 1, characterized in that: The atomic evidence locking operation is executed within the ISR, and the total time from hardware triggering to evidence storage in the cache is less than the minimum scheduling time slice of the operating system, so that the locking process of the original evidence is completed in a single, uninterruptible execution context.

4. The industrial instrument data storage middleware according to claim 1, characterized in that: The background asynchronous signature operation is decoupled from the ISR; the MCU calculates the original evidence digest through the hardware hash engine in the background task, and generates a digital signature through the hardware signature engine using the PUF derived private key.

5. The industrial instrument data storage middleware according to claim 1, characterized in that: The RC reverse attenuation network includes a resistor R and a capacitor C connected in series between the RX output terminal of the digital isolator receiver and the MCU receiver pin; its parameters are configured to permanently attenuate the reverse command signal level to below ±200 mV below the RS-485 standard transceiver differential identification threshold within a preset baud rate range.

6. The industrial instrument data storage middleware according to claim 1, characterized in that: The continuous silence time of the detection bus reaching a preset threshold includes: Use a hardware timer to monitor bus idle time; When the idle time reaches the frame interval T3.5 defined by the Modbus protocol, the bus is determined to enter the idle window period; where T3.5 is 3.5 character times, and when the baud rate is greater than 19200bps, T3.5 is fixed at 1.750ms; During the window period, the MCU inserts the evidence frame into the bus.

7. The industrial instrument data storage middleware according to claim 1, characterized in that: The protocol address field of the independent evidence frame is set to a reserved address or broadcast address of the industrial bus protocol, so that downstream standard instrument equipment, after receiving it, determines it as non-local data according to the protocol and discards it silently.

8. The industrial instrument data storage middleware according to claim 1, characterized in that: The MCU is configured to execute an event-triggered ZoneLock evidence chain locking mechanism: The internal non-volatile memory (NVM) is divided into multiple logical zones. Once an atomic evidence locking and asynchronous signing is completed, and the evidence frame is successfully written to the current active Zone of the NVM, the Zone is dynamically and irreversibly set to a read-only state. Subsequent evidence data is written to the next writable Zone, forming an immutable chain-like evidence storage structure based on atomic events; The integrity of the evidence storage chain is verified through a hash chain, and this verification follows the following logic: ； in, Represents the original evidence used for the i-th evidence preservation; This indicates the corresponding backend signature; This represents the chain hash value corresponding to the previous notarization, and is expressed through the chain hash value. Ensure the integrity and temporal sequence of historical data.

9. A pulse atomic signature method for an industrial instrument data storage middleware, characterized in that, The pulse atomic signature method of the industrial instrument data storage middleware described in any one of claims 1-8 specifically includes the following steps: S1. Connect the physical interface layer of the middleware to the RS-485 bus in a high-impedance bypass manner. Use the RC reverse attenuation network to permanently attenuate the reverse command signal level to below ±200 mV of the differential identification threshold of the RS-485 standard transceiver. Without changing the original master station and slave station communication link, realize physical layer one-way listening and confirmation of rights. S2. When a pulse signal appears on the bus, the pulse is hard-coupled to the highest priority external interrupt EXTI pin of the MCU through the optocoupler isolation circuit, triggering the MCU to enter the highest priority interrupt service routine (ISR). S3. Perform evidence locking operation atomically within the ISR, read the current hardware timer count value to generate a precise timestamp, and capture the complete data frame transmitted on the bus based on the Modbus RTU protocol; atomically write the data frame and its corresponding timestamp as the original evidence into the volatile buffer; wherein, the total time from hardware triggering the interrupt to the evidence being stored in the buffer is less than the minimum scheduling time slice of the operating system. S4. After exiting the ISR, the original evidence is read from the cache in the background task, the hardware cryptographic module is called to perform hash operation, and the private key derived from the pin PUF is used to perform asynchronous signature operation to generate a certificate signature. S5. Monitor the continuous silence time of the bus using a hardware timer. When the silence time reaches the frame interval T3.5 defined by the Modbus protocol, determine that the bus has entered an idle window period. During the window period, insert an independent evidence frame containing the evidence signature into the bus. Here, T3.5 is 3.5 character times. When the baud rate is greater than 19200 bps, T3.5 is fixed at 1.750 ms. S6. Write the evidence data containing the original evidence and its signature into the currently active logical region Zone of the non-volatile memory NVM; after writing, dynamically and irreversibly set the Zone to read-only state and activate the next writable Zone. S7. Calculate the hash value of the evidence storage data in the current Zone, concatenate it with the hash value of the previous Zone, generate a chained hash verification value, and write it to the tail of the current Zone; the integrity of the evidence storage chain is verified through the following hash chain logic: ； in, Represents the original evidence used for the i-th evidence preservation; This indicates the corresponding backend signature; This represents the chain hash value corresponding to the previous evidence storage; during verification, the hash values ​​of each Zone are recalculated in Zone order and compared with the stored hash values ​​and signature values ​​to determine whether the data has been tampered with.

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