A method for producing laser-damaged back contact batteries

Abstract

This invention discloses a method for manufacturing a laser-damaged back-contact battery, comprising: double-sided polishing of an N-type silicon wafer; deposition of a first tunneling oxide layer and an intrinsic polycrystalline silicon layer on the back side, followed by phosphorus diffusion to form an N-type doped layer and a PSG mask; printing UV adhesive in the N-region; performing wet etching to remove the P-region mask, UV adhesive, intrinsic layer, and tunneling oxide layer, and forming a textured surface in the opening areas on the front and back sides; depositing a passivation antireflection layer on the front side; sequentially depositing an intrinsic amorphous silicon layer and a P-type doped layer on the back side; laser-cutting to remove the P-type stack above the N-region; depositing a transparent conductive film and forming an isolation trench; and finally metallizing. This invention replaces some laser processes with "UV adhesive + wet etching," avoiding laser damage and increasing the open-circuit voltage; simultaneously, it can reduce the polylayer thickness to 120nm, reducing parasitic absorption and increasing short-circuit current, thereby comprehensively improving the battery conversion efficiency.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a method for producing a laser-damage-free back contact battery, and more particularly to a method for producing a laser-damage-free and low parasitic absorption back contact battery by optimizing the doping sequence. Background Technology

[0002] Hybrid Tunnel Oxide Passivated Contact Back Contact Cell (HTBC), combining the core technologies of tunnel oxide passivated contact (TOPCon) and heterojunction (HJT) cells, is one of the most efficient technologies in the field of crystalline silicon solar cells and is considered the mainstream direction for next-generation ultra-efficient cells. As the efficiency of passivated emitter-back cell (PERC) technology approaches its limit, and efficiency improvements in tunnel oxide passivated contact (TOPCon) cells encounter bottlenecks, back contact cells (TBC / HBC) have become the focus of attention in industry and academia due to their unique advantages of completely eliminating front-side grid line shading and maximizing light absorption area.

[0003] In existing back-contact battery fabrication technologies, patterning the back electrode region is a core process, and the mainstream technology currently employs laser patterning. For example, patent document CN120957520A discloses a method for fabricating the surface structure of a back-contact battery. In the process of forming a first semiconductor region (P-region) and a second semiconductor region (N-region) spaced apart on the back side, laser engraving steps (S2, S4, S7) are used multiple times to form patterns or remove the mask layer. However, as a high-energy beam, the laser inevitably causes thermal damage and lattice defects to the underlying silicon substrate when ablating the mask layer or doped polycrystalline silicon layer, forming a laser-induced damage layer. These damage layers become severe recombination centers, leading to a decrease in the battery's open-circuit voltage (Voc) and minority carrier lifetime, limiting further improvements in photoelectric conversion efficiency. Simultaneously, to shield the laser-affected zone, traditional processes often require the deposition of a thick polycrystalline silicon layer. This not only increases process time and reduces equipment throughput but also enhances parasitic absorption of long-wavelength light, further damaging the battery's short-circuit current (Isc).

[0004] Another patent document, CN121262890A, discloses a back contact battery that reduces the thickness difference between the N-type and P-type regions. It reduces contact resistance and stress concentration by setting a concentration gradient (doped base layer and transition layer) within the doped layer. While this approach optimizes the electrical properties within the film, the patterning of the N / P regions primarily relies on mask-based ion doping, which is complex and requires extremely high mask alignment accuracy. It does not address the laser damage issue during patterning, nor does it involve fine-tuning the textured surface structure on the front side.

[0005] Furthermore, the applicant's earlier application (a method for manufacturing a laser-damaged back contact battery) proposed a solution that completely replaces laser processing using a UV adhesive patterning process. This method achieves laser-damaged manufacturing by forming all patterned openings through two processes: "printing UV adhesive + wet etching." While this solution is highly effective, the process flow is relatively long, and the complete elimination of laser steps presents certain challenges in terms of industrial compatibility.

[0006] Therefore, developing a novel back-contact battery structure and its fabrication method that can effectively avoid or reduce laser damage, reduce the thickness of the poly layer to reduce parasitic absorption, simplify the process flow, improve production efficiency, and take into account both high open-circuit voltage and high short-circuit current is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] The present invention aims to provide a sequentially optimized method for manufacturing laser-damaged back contact batteries, in order to solve the problems in the prior art such as thermal damage to the silicon substrate caused by laser patterning process, reduction of battery open circuit voltage, and increased parasitic absorption and extended process time caused by forced thickening of the poly layer to shield the damage layer.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: The present invention discloses a method for producing a laser-damaged back contact battery, comprising the following steps: (1) Substrate preparation and formation of the first conductivity type region: S1. Clean and double-sided polish the N-type bare silicon wafer to form a flat polished surface on both sides of the wafer; S2. A first tunneling oxide layer (SiO2 layer) and a first intrinsic polysilicon layer (poly layer) are sequentially deposited on the back side of the silicon wafer. S3. Perform the first doping in the N-type region to allow elemental phosphorus to diffuse into the first intrinsic polysilicon layer to form the first doped polysilicon layer and the first mask layer (such as borosilicate glass BSG). S4. In the region corresponding to the first doped polysilicon layer (i.e., the preset N region), UV adhesive is screen-printed and cured to form a first masking layer. S5. First, use hydrofluoric acid (HF) solution to remove the first mask layer in the area not covered by UV adhesive; then use alkaline solution to remove UV adhesive; then use alkaline solution to etch the exposed area (i.e., the preset P area) to completely remove the first intrinsic polysilicon layer and the first tunneling oxide layer in the area, forming the first patterned opening and exposing the silicon substrate. Simultaneously, an alkaline texturing solution is used to form a pyramidal texturing structure on the front side of the silicon wafer and at the first patterned opening; S6. An aluminum oxide layer (AlOx) and a silicon nitride mask layer (SiNx) are sequentially deposited on the front side of the silicon wafer to form a passivation and antireflection layer; S7. First, a second intrinsic amorphous silicon layer is deposited on the entire back side of the silicon wafer, and then a boron-doped amorphous silicon layer (P layer) is deposited to form a second doped amorphous silicon layer (P-type layer). S8. According to the battery pattern design, the second doped amorphous silicon layer and the second intrinsic amorphous silicon layer located above the first conductivity type region (N region) are removed by laser ablation to form a second patterned opening and expose the first doped polycrystalline silicon layer below. S9. Deposit a transparent conductive thin film layer on the back side of the silicon wafer; S10. In the boundary region between the first conductivity type region and the second conductivity type region, a transparent conductive film is removed to form an isolation trench, so as to achieve electrical isolation between the N region and the P region. S11. Metal electrodes are formed on the transparent conductive films corresponding to the first conductivity type region and the second conductivity type region, and ohmic contacts are formed by sintering.

[0009] Furthermore, in step S1, the polishing and cleaning temperature is 80±10℃, the time is 200±40s, and the reflectivity of the polished surface is 40%±2%.

[0010] Further, in step S2, the thickness of the first tunneling oxide layer is 1.4±0.2nm, and the thickness of the first intrinsic polycrystalline silicon layer is 120±20nm; the deposition is performed using low-pressure chemical vapor deposition (LPCVD) at a temperature of 600±40℃ for a time of 120±10min.

[0011] Further, in step S3, the process temperature for the first doping is 870±40℃ and the time is 115±10min; the sheet resistance of the first doped polysilicon layer (N-type Poly layer) is 360±80Ω / sq and the thickness of the first mask layer (PSG) is 35±10nm.

[0012] Further, in step S5, the alkaline solution is a mixture of potassium hydroxide and hydrogen peroxide, the reaction temperature is 80±10℃, and the time is 600±100s; the main components of the alkaline texturing solution are KOH, H2O, and texturing additives; the reflectivity of the formed pyramidal texturing surface is 11%±2%.

[0013] Further, in step S6, the passivation antireflection layer is a stack of aluminum oxide (AlOx) and silicon nitride (SiNx), wherein the aluminum oxide layer has a thickness of 8±2nm and the silicon nitride layer has a thickness of 160±20nm; the refractive index of the passivation antireflection layer is 1.8%±0.2%.

[0014] Further, in step S7, the thickness of the second intrinsic amorphous silicon layer is 8±2nm, and the thickness of the second doped amorphous silicon layer (P-type layer) is 20±4nm; the deposition is performed by plate chemical vapor deposition (CVD) at a temperature of 200±20℃ and a process time of 400±40s.

[0015] Furthermore, in step S9, the transparent conductive film is indium tin oxide (ITO) with a thickness of 100±20nm and a sheet resistance of 50±20Ω / sq.

[0016] Further, in step S10, the isolation groove is formed by printing acidic etching paste or laser etching, and its width is 120±20μm.

[0017] The present invention also provides a back-contact battery structure, which is prepared by any of the above-described methods. The battery structure includes: a silicon substrate having a pyramidal textured surface and a passivation antireflection layer on its front side; and a back-side structure including: Alternating first conductivity type regions (N region) and second conductivity type regions (P region); The first conductivity type region (N region) includes a first tunneling oxide layer and a first doped polysilicon layer sequentially formed on the back side of the silicon substrate. The second conductivity type region (P region) includes a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer (P type) sequentially formed on the back side of the silicon substrate. Above the first conductivity type region (N region), the second intrinsic amorphous silicon layer and the second doped amorphous silicon layer are removed by laser apertures; A transparent conductive film layer is applied over the first conductivity type region and the second conductivity type region, and an isolation groove is formed at the junction of the two regions. Metal electrodes are respectively disposed on the transparent conductive films corresponding to the first conductivity type region and the second conductivity type region.

[0018] Compared with the prior art, the technical solution provided by the present invention has the following significant advantages: (1) Reduced laser damage and increased open-circuit voltage: This invention replaces the laser etching step used in the traditional scheme to define the P-region window with a chemical method of "printing UV adhesive + wet etching". Wet etching is an isotropic chemical process that does not involve high-energy particle bombardment, completely avoiding thermal damage and lattice defects caused by laser to the silicon substrate. Therefore, the open-circuit voltage (Voc) of the battery is effectively improved. Experimental data show that the open-circuit voltage of the battery using this invention is increased by about 3mV compared to the pure laser scheme.

[0019] (2) Reducing Poly Layer Thickness and Increasing Short-Circuit Current: Since there is no need to retain an excessively thick Poly layer to shield the laser heat-affected zone, this invention can significantly reduce the thickness of the first intrinsic polycrystalline silicon layer (from approximately 250 nm in conventional processes to 120 nm). The thinner Poly layer greatly reduces parasitic absorption of long-wavelength incident light, allowing more photons to reach the silicon substrate and be absorbed, thereby effectively increasing the short-circuit current density (Isc) of the battery. Experimental data show that the short-circuit current density is increased by approximately 0.3 mA / cm². 2 .

[0020] (3) Simplified process flow and reduced environmental pressure: Compared with the company's previous completely laser-free solution, the present invention retains a precise laser opening step after the deposition of the P-type amorphous silicon layer. Although it introduces slight damage, it greatly simplifies the process flow, reduces the complexity caused by multiple "printing-etching" processes, and is more compatible with existing mainstream production lines. At the same time, the present invention eliminates the difficult-to-treat waste liquids such as nitric acid and sulfuric acid used in traditional acid polishing processes, and mainly uses KOH and HF, which significantly reduces the ammonia nitrogen content in the waste liquid and alleviates the environmental treatment pressure.

[0021] (4) Comprehensive improvement of photoelectric conversion efficiency: Through the above-mentioned dual optimization of open-circuit voltage and short-circuit current, the present invention ultimately achieves a significant improvement in the photoelectric conversion efficiency of the battery. Experimental comparison data show that the battery conversion efficiency of the embodiment of the present invention is improved by 0.11% in absolute terms compared with the traditional laser process, which has extremely high industrial application value. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the back contact battery structure in Example 1.

[0023] The markings in the diagram are as follows: 1-N-type bare silicon wafer, 111-pyramid textured structure, 112-first conductivity type region, 113-second conductivity type region, 2-first tunneling oxide layer, 3-first doped polycrystalline silicon layer, 4-alumina layer, 5-silicon nitride mask layer, 6-second intrinsic amorphous silicon layer, 7-second doped amorphous silicon layer, 8-first transparent conductive layer, 9-second transparent conductive layer, 11-negative electrode fine gate line, 12-positive electrode fine gate line. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] A back-contact battery structure includes: an N-type bare silicon substrate 1, the front side of which has a pyramidal textured structure 111 and a passivation antireflection layer; and a back-side structure including: Alternating first conductivity type region (N region) 112 and second conductivity type region (P region) 113; The first conductivity type region (N region) 112 includes a first tunneling oxide layer 2 and a first doped polysilicon layer 3 sequentially formed on the back side of the silicon substrate. The second conductivity type region (P region) 113 includes a second intrinsic amorphous silicon layer 6 and a second doped amorphous silicon layer (P type) 7 sequentially formed on the back side of the silicon substrate; Above the first conductivity type region (N region) 112, the second intrinsic amorphous silicon layer 6 and the second doped amorphous silicon layer 7 are removed by laser apertures; A first transparent conductive film layer 8 covers the first conductive type region 112, and a second transparent conductive film layer 9 covers the second conductive type region 113, forming an isolation groove at the junction of the two. Metal electrodes are respectively disposed on the transparent conductive films corresponding to the first conductivity type region 112 and the second conductivity type region 113.

[0026] Example 1 This embodiment provides a back contact battery structure and its fabrication method, with the specific steps as follows: S1. Pretreatment and Front Polishing: The N-type bare silicon wafer is placed in a tank cleaning machine for polishing and cleaning. The reaction solution is a mixture of KOH, H2O, and polishing additives. Process conditions: temperature 80±10℃, time 200±40s. Process indicators: flat polished surfaces are formed on both sides, reflectivity 40%±2%, weight reduction 0.45±0.1g.

[0027] S2. First Intrinsic Layer Deposition: The polished silicon wafer is placed in an LPCVD furnace, and a first tunneling oxide layer (SiO2) and a first intrinsic polycrystalline silicon layer (Poly) are sequentially deposited on the back side of the wafer. The reaction gases are SiH4, O2, and N2. Process conditions: temperature 600±40℃, time 120±10min. Process parameters: SiO2 thickness 1.4±0.2nm, Poly thickness 120±20nm.

[0028] S3. First doping to form the N-type region: The silicon wafer is placed in a phosphorus diffusion furnace for phosphorus diffusion. The reaction sources are POCl3, O2, and N2. Process conditions: temperature 870±40℃, time 115±10min. Process parameters: formation of an N-type doped polycrystalline silicon layer (N-Poly), sheet resistance 360±80Ω / sq, and formation of a phosphorus silicate glass (PSG) mask layer on the surface with a thickness of 35±10nm.

[0029] S4. Printing the first UV adhesive mask: On the N-region (i.e., the area where the N-Poly layer is located) on the back of the silicon wafer, the first UV adhesive is printed by screen printing, and then cured by UV lamp irradiation for 0.85±0.1s. This UV adhesive is resistant to acid corrosion.

[0030] S5. First wet etching and texturing: Immerse the printed silicon wafer in a 5% HF acid bath to remove the PSG mask layer in the area not covered by UV adhesive (i.e., the preset P area); after rinsing with water, immerse the silicon wafer in a KOH+H2O2 mixed solution bath (80±10℃) to remove the UV adhesive; then immerse the silicon wafer in a mixed texturing bath of KOH, H2O and texturing additive at a temperature of 80±10℃ for 600±100s.

[0031] This step achieves three objectives simultaneously: ① etching away the exposed N-Poly and SiO2 in the P-region to form the first patterned opening, exposing the silicon substrate; ② forming a pyramidal textured structure on the front side of the silicon wafer; ③ forming a pyramidal textured structure at the first patterned opening on the back side. Process specifications: reflectivity of the front and back opening areas 11%±2%, weight reduction 0.25±0.04g.

[0032] S6. Deposit front-side passivation and antireflection layer: Place the texturized silicon wafer into an ALD device and deposit aluminum oxide (AlOx) layers on both the front and back sides simultaneously, with a thickness of 8±2nm. Then place it into a tube-type PECVD furnace and deposit a silicon nitride mask layer (SiNx) on the front side, with a thickness of 160±20nm and a refractive index of 1.8%±0.2%.

[0033] S7, Deposit back-side stack (P-type region): First, remove the SiNx / AlOx deposited around the back side by chain-type HF cleaning; then perform RCA cleaning (SC: KOH+H2O2+H2O; SC2: HCl+H2O2+H2O) to clean the silicon wafer.

[0034] Finally, the wafer is placed in a plate CVD apparatus, where a second intrinsic amorphous silicon layer (i-layer, 8±2 nm thick) and a second doped amorphous silicon layer (P-layer, boron-doped, 20±4 nm thick) are sequentially deposited on the back side of the wafer. The process temperature is 200±20℃.

[0035] S8. Laser Aperture: Using a laser, the P and i layers above the N-region are precisely removed according to the pattern design, forming a second patterned aperture to expose the underlying N-Poly layer. Process specifications: Laser aperture width 150±20um.

[0036] S9. After the laser process, a SiO2 thin film will grow on the surface of the N-poly wafer. The laser-processed silicon wafer is placed in a chain-type HF acid cleaning machine with the front side facing up and the back side in contact with the rollers for transmission. The chain-type machine rollers carry liquid HF solution to etch the SiO2 layer. Process parameters: No SiO2 residue on the back side, no over-etching on the front side. HF acid concentration: 5%±1%, process temperature: room temperature, machine belt speed: 4.5±1 m / min.

[0037] S10, Deposition of transparent conductive film: The laser-treated silicon wafer is placed in a PVD device, and an ITO layer with a thickness of 100±20nm and a sheet resistance of 50±20Ω / sq is deposited on the back side.

[0038] S11. Forming Isolation Grooves: At the boundary between the N and P regions, acidic etching paste is screen-printed to etch away the ITO layer in that area, forming isolation grooves with a line width of 120±20um. Then, residual etching paste is cleaned with SC1 solution.

[0039] S12. Metallization: On the ITO layers corresponding to the N and P regions on the back side, metal paste is screen-printed to form main grid lines (500±20um wide) and fine grid lines (80±20um wide). Then, the battery manufacturing is completed through sintering, photoinjection and other processes.

[0040] Comparative Example 1 Comparative Example 1 uses a conventional laser patterning process. The main difference between Comparative Example 1 and Example 1 is that in step S5, instead of using a UV photoresist mask and wet etching, a conventional scheme of "depositing SiNx mask + laser windowing + acid polishing" is used.

[0041] The specific steps are as follows: S1. N-type bare silicon wafers are placed in a tank-type cleaning machine for polishing and cleaning. This removes mechanical damage to the wafer, cleans it, and forms a smooth microstructure on both sides. Process parameters: reflectivity 40%±2%, weight loss 0.45±0.1g. The reaction solution is a polishing solution, whose main components are KOH, H2O, and polishing additives. These materials are standard materials commonly used in the photovoltaic industry. The process reaction temperature is 80±10℃, and the process time is 200±40s.

[0042] S2. Place the polished silicon wafers into the LPCVD furnace, inserting two wafers side-by-side into a quartz boat. First, deposit a tunneling oxide layer (SiO2) on the back of the wafers, followed by an intrinsic polycrystalline silicon layer (poly). The main reacting gases are SiH4, O2, and N2. Process parameters: SiO2 thickness 1.4±0.2nm, poly thickness 120±20nm. Process reaction temperature 600±40℃, process time 120±10min.

[0043] S3. Place the silicon wafers from the previous process into a phosphorus diffusion furnace, inserting two wafers face-to-face into a quartz boat. Diffusion of the phosphorus generated in the reaction into the poly layer forms an N-type poly layer. The main reaction sources are POCl3, O2, and N2. Process parameters: Sheet resistance: 360±80Ω / sq, PSG thickness: 35±10nm. Process reaction temperature: 870±40℃, Process time: 115±10min.

[0044] S4. Place the phosphorus-diffused silicon wafer into a tube-type PECVD furnace and deposit a SiNx mask layer on the back of the silicon wafer. The main reacting gases are: SiH4, NH3, N2O, and N2. These specialty gases are standard materials. Process parameters: SiNx film thickness 40±10nm, refractive index 2.0%±0.2%. Process reaction temperature 500±40℃, process time 35±4min.

[0045] S5. Place the silicon wafer after the previous process into the laser. According to the cell pattern design, use laser ablation to remove the SiNx and PSG layers above the P-region on the back of the cell. Process specifications: P-region width 520±30um, no SiNx or PSG residue in the reaction area, and no burrs on the laser spot. The process is performed at room temperature, and the process time per wafer is calculated based on the cell pattern, laser spot size, and laser speed.

[0046] S6. Place the laser-treated silicon wafer into a chain-type HF acid cleaning machine, with the back side of the wafer facing upwards and the front side in contact with the rollers for transmission. A layer of PSG and SiNx thin film has been deposited around the perimeter of the front side of the wafer during the previous process. The chain-type machine rollers, carrying liquid HF solution, etch the aforementioned PSG and SiNx layers. Process parameters: No PSG or SiNx residue on the front side, no over-etching on the back side. HF acid solution concentration: 35±10%, machine belt speed: 4.0±1 m / min.

[0047] S7. The silicon wafers after the previous process are placed in a tank cleaning machine for texturing cleaning, forming a pyramidal microstructure at the laser openings on the front and back of the wafer. Process parameters: reflectivity 11%±2%, weight reduction 0.25±0.04g. The reaction solution is a texturing solution, the main components of which are KOH, H2O, and texturing additives. The process reaction temperature is 80±10℃, and the process time is 600±100s. The texturized silicon wafers are then placed in an acid bath, the main components of which are HF and H2O. The purpose is to use HF acid to etch the residual SiNx and PSG layers on the back side. Process parameters: no SiNx and PSG residue, process temperature is room temperature, and process time is 220±40s.

[0048] S8. Place the cleaned silicon wafer into the ALD equipment and deposit an AlOx thin film simultaneously on both sides of the wafer. The main reactive gases are: TMA, H2O, O3, and N2. Process parameters: AlOx film thickness 8±2nm. Process temperature: 220±40℃, process time 45±4min.

[0049] S9. Place the ALD-treated silicon wafer into a tube-type PECVD furnace and deposit a SiNx mask layer on the front side of the wafer. The main reacting gases are SiH4, NH3, N2O, and N2. These specialty gases are standard materials. Process parameters: SiNx film thickness 160±20nm, refractive index 1.8%±0.2%. Process reaction temperature 500±40℃, process time 60±4min.

[0050] S10. Place the SiNx-plated silicon wafer into a chain-type HF acid cleaning machine, with the front side facing up and the back side in contact with the rollers for transmission. A layer of SiNx has been deposited around the perimeter of the back side of the wafer during the previous process. The chain-type machine rollers, carrying HF solution, etch the aforementioned SiNx layer and the underlying AlOx layer. Process parameters: No SiNx or AlOx residue on the back side, no over-etching on the front side. HF acid concentration: 20±4%, process temperature: room temperature, machine belt speed: 3±0.4 m / min.

[0051] S11. Place the silicon wafers after the previous process into a tank cleaning machine for RCA cleaning. The purpose is to clean the silicon wafers and remove any residual organic dirt and metal ions from their surface. The silicon wafers are sequentially placed into SC1 and SC2 tanks for cleaning. The main components of the cleaning solution in SC1 are KOH, H2O2, and H2O; the main components of the cleaning solution in SC2 are HCl, H2O2, and H2O. Process parameters: No abnormalities in appearance. Process temperature: 55±10℃, process time: 200±20s.

[0052] S12. Place the silicon wafer after the previous process into a plate CVD machine. First, deposit an intrinsic amorphous silicon layer (i-layer) on the back side of the silicon wafer, and then deposit a boron-doped amorphous silicon layer (P-layer) on the i-layer. Process parameters: i-layer thickness 8±2nm, P-layer thickness 20±4nm. Process temperature: 200±20℃, process time 400±40s.

[0053] S13. Place the CVD-processed silicon wafer into a laser. Based on the cell pattern design, use laser ablation to remove the IP layer above the N-poly region of the cell. Process specifications: laser aperture width 150±20µm, no IP layer residue in the reaction area, and no burrs on the laser spot. The process is performed at room temperature, and the process time per wafer is calculated based on the cell pattern, spot size, and laser speed.

[0054] S14. Place the laser-processed silicon wafer into a chain-type HF acid cleaning machine, with the front side facing up and the back side in contact with the rollers for transmission. After the previous laser process, a SiO2 thin film will grow on the Npoly surface. The chain-type machine rollers carry liquid HF solution to etch the SiO2 layer. Process parameters: No SiO2 residue on the back side, no over-etching on the front side. HF acid concentration 5±1%, process temperature room temperature, machine belt speed 4.5±1m / min.

[0055] S15. Place the silicon wafer after the previous process into the PVD equipment and deposit a transparent conductive film (ITO layer) on the back of the silicon wafer. Process parameters: film thickness 100±20nm, sheet resistance 50±20Ω / sq. Process temperature 160±20℃, process time 300±40s.

[0056] S16. Place the silicon wafer after the previous process into a screen printing machine. Design the screen pattern according to the cell pattern and print the etching paste on the back of the silicon wafer. The etching paste is acidic and will etch away the ITO layer. The area where the etching paste is printed is the boundary between the N-region and the P-region. Process parameters: line width (aperture width) 120±20um, no broken gates. Process temperature is room temperature, and process time is 0.85±0.1s.

[0057] S17. Place the silicon wafer after etching paste printing into a tank cleaning machine and clean the residual etching paste using SC1 solution. The main components of SC1 solution are KOH, H2O2, and H2O. Process parameters: no etching paste residue and no abnormal appearance. Process temperature: 35±10℃, process time: 150±20s.

[0058] S18. On the ITO layer corresponding to the N and P regions on the back side, metal paste is screen-printed to form main grid lines (500±20um wide) and fine grid lines (80±20um wide). Then, the battery manufacturing is completed through sintering, photoinjection and other processes.

[0059] Test Experiment Example After calibration of the IV tester standard, batch electrical performance tests were conducted on the cells of Example 1 and Comparative Example 1. The test data (batch average value) comparison is detailed in Table 1 below. As shown in Table 1, the patterning process on the back of the battery in Example 1 using the technical solution of this invention employs UV adhesive patterning instead of laser processing, avoiding thermal damage to the silicon substrate caused by laser. Its open-circuit voltage is increased by 3mV compared to Comparative Example 1, and the final absolute value of the photoelectric conversion efficiency is increased by 0.11%. This fully demonstrates that this invention, by replacing part of the laser process with "UV adhesive patterning + wet etching," effectively reduces thermal damage to the silicon substrate caused by laser, thereby improving battery performance. Since the Poly layer thickness (120nm) of this invention is much lower than that of traditional laser processes (typically >200nm), parasitic absorption is effectively reduced, and the short-circuit current density is increased by 0.2mA / cm². 2 At the same time, it reduces two steps compared to the traditional process, achieving higher economic value.

Claims

1. A method for producing a laser-damaged back contact battery, characterized in that, Includes the following steps: S1. Polish and clean the N-type silicon wafer to form a polished surface; S2. A first tunneling oxide layer and a first intrinsic polycrystalline silicon layer are sequentially deposited on the back side of the silicon wafer; S3. Perform the first doping in the N-type region to allow elemental phosphorus to diffuse into the first intrinsic polysilicon layer to form the first doped polysilicon layer and the first mask layer. S4. Print UV adhesive in the region corresponding to the first doped polysilicon layer and cure it to form a first masking layer; S5. First, use acid to remove the first mask layer in the area not covered by the first UV adhesive, and then use alkaline solution to remove the UV adhesive. Subsequently, the exposed first intrinsic polysilicon layer and the first tunneling oxide layer are etched to form a first patterned opening; A pyramidal textured surface structure is formed on the front side of the silicon wafer and at the first patterned opening; S6. Deposit a passivation and antireflection layer on the front side of the silicon wafer; S7. First, a second intrinsic amorphous silicon layer is deposited on the entire back side of the silicon wafer, and then a boron-doped amorphous silicon layer is deposited to form a second doped amorphous silicon layer. S8. Use laser ablation to remove the second doped amorphous silicon layer and the second intrinsic amorphous silicon layer located above the first conductivity type region, forming a second patterned opening to expose the first doped polycrystalline silicon layer. S9. Deposit a transparent conductive thin film layer on the back side of the silicon wafer; S10. Remove the transparent conductive film at the boundary between the first conductivity type region and the second conductivity type region to form an isolation trench; S11, metallize to form a metal electrode.

2. The production method according to claim 1, characterized in that, In step S5, the alkaline solution is used simultaneously to remove UV adhesive, etch the polysilicon layer, and form a textured structure.

3. The production method according to claim 1, characterized in that, In step S1, the polishing and cleaning temperature is 80±10℃, the time is 200±40s, and the reflectivity of the polished surface is 40%±2%; in step S2, the thickness of the first tunneling oxide layer is 1.4±0.2nm, and the thickness of the first intrinsic polycrystalline silicon layer is 120±20nm; the deposition is performed using low-pressure chemical vapor deposition at a temperature of 600±40℃ and a time of 120±10min.

4. The production method according to claim 1, characterized in that, In step S3, the process temperature for the first doping is 870±40℃, the time is 115±10min, the first doped polycrystalline silicon layer is an N-type doped layer with a sheet resistance of 360±80Ω / sq, and the first mask layer is a phosphosilicate glass with a thickness of 35±10nm.

5. The production method according to claim 1, characterized in that, In step S5, the acid solution is a hydrofluoric acid solution, the alkaline solution is a mixture of potassium hydroxide and hydrogen peroxide, the reaction temperature is 80±10℃, and the time is 600±100s; the main components of the alkaline texturing solution are KOH, H2O and texturing additives; the reflectivity of the formed pyramidal texturing surface is 11%±2%.

6. The production method according to claim 1, characterized in that, In step S6, the passivation antireflection layer is a stack of an aluminum oxide layer and a silicon nitride layer, the aluminum oxide layer has a thickness of 8±2nm, the silicon nitride layer has a thickness of 160±20nm, and the refractive index is 1.8%±0.2%.

7. The production method according to claim 1, characterized in that, In step S7, the thickness of the second intrinsic amorphous silicon layer is 8±2nm, the thickness of the second doped amorphous silicon layer is 20±4nm, the deposition temperature is 200±20℃, the deposition is carried out by plate chemical vapor deposition, the temperature is 200±20℃, and the process time is 400±40s.

8. The production method according to claim 1, characterized in that, In step S9, the transparent conductive film is ITO with a thickness of 100±20nm and a sheet resistance of 50±20Ω / sq; in step S10, the width of the isolation groove is 120±20μm.

9. A back-contact battery, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 8.

10. The back contact battery according to claim 9, characterized in that, include: A silicon substrate with a pyramidal textured surface and a passivation antireflection layer on its front side; The back structure includes alternating first and second conductivity type regions; The first conductivity type region includes a first tunneling oxide layer and a first doped polysilicon layer sequentially formed on the back side of the silicon substrate. The second conductivity type region includes a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer sequentially formed on the back side of the silicon substrate; Above the first conductivity type region, the second intrinsic amorphous silicon layer and the second doped amorphous silicon layer are removed by laser apertures; A transparent conductive film layer is applied over the first conductivity type region and the second conductivity type region, and an isolation groove is formed at the junction of the two regions. Metal electrodes are respectively disposed on the transparent conductive films corresponding to the first conductivity type region and the second conductivity type region.

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