Method of manufacturing a semiconductor device

Abstract

This invention provides a method for manufacturing a semiconductor device. After forming a trench exposing the apex corner of the active region for forming a gate oxide layer by creating a side-hole device isolation structure, the apex corner of the active region exposed by the trench is first rounded by controlling the direction of the plasma beam to form a first angle with the top surface of the substrate. Then, the top surface of the active region is smoothed by controlling the direction of the plasma beam to form a second angle (the second angle is smaller than the first angle) with the top surface of the substrate. This improves the uniformity of the growth rate and thickness of the gate oxide layer during subsequent in-situ growth on the active region, increases the thickness at the edge of the gate oxide layer, and improves the sharp corner problem during gate oxide layer manufacturing. This improves the breakdown voltage of the device and ensures the stability of the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] For micron-level high-voltage devices, please refer to Figure 1 As shown, when growing the gate oxide layer GOX in situ on the silicon surface of the active region AA, at the apex corner of the active region AA (i.e., the sharp corner of the top boundary, such as...) Figure 1 As shown by the black dashed circle in the image, due to lattice defects and slow sidewall growth rates, the oxidation rate varies at different locations at the apex of the active region AA. This causes the silicon surface of the active region AA to bulge upwards at the apex after in-situ oxidation, resulting in a sharp corner problem. This phenomenon leads to the gate oxide layer (GOX) thickness at the apex of the active region AA being lower than the required range (e.g., ...). Figure 1 (As shown by the white dashed circle in the image), the breakdown voltage does not meet the actual requirements, thus affecting the reliability of high-voltage devices and product yield.

[0003] Therefore, ensuring the rounding of the apex corners of the active region has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor device that can round the corners of the active region before growing the gate oxide layer in situ, thereby improving device reliability and yield.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] A substrate is provided, and a device isolation structure is formed in the substrate to define the active region where the gate oxide layer is to be formed;

[0007] Side-cut etching is performed on the top corner of the isolation structure of the device to form a trench that exposes the top corner of the active region;

[0008] By controlling the direction of the plasma beam to form a first angle with the top surface of the substrate, the top corner of the active region is subjected to a first directional dry etching, so that the top corner of the active region exposed by the side trench is rounded.

[0009] By controlling the plasma beam direction to form a second angle with the top surface of the substrate, a second directional dry etching is performed on the top surface of the active region to make the top surface of the active region smooth, and the second angle is smaller than the first angle.

[0010] A gate oxide layer is formed on top of the active region.

[0011] Optionally, the step of performing a first directional dry etching on the apex corner of the active region includes:

[0012] The substrate is tilted and the direction of the plasma beam is at the first angle with the top surface of the substrate to perform a first directional dry etching on the apex of the active region.

[0013] The substrate is tilted in the opposite direction, and the plasma beam direction is made to form the first angle with the top surface of the substrate in a mirror-symmetrical manner, so as to perform the first directional dry etching on the top corner of the active region again, thereby rounding the top corner of the active region.

[0014] Optionally, the step of performing a first directional dry etching on the apex of the active region includes: tilting the substrate so that the direction of the plasma beam forms the first angle with the top surface of the substrate to perform a first directional dry etching on the apex of the active region, and rotating the substrate in the plane containing its top surface during the first directional dry etching process.

[0015] Optionally, the step of performing a second directional dry etching on the apex corner of the active region includes:

[0016] The tilt angle of the substrate is adjusted so that the direction of the plasma beam forms the second angle with the top surface of the substrate, so as to perform a second directional dry etching on the top surface of the active region.

[0017] The substrate is tilted in the opposite direction, and the plasma beam direction is again made to form the second angle between the top surface of the substrate in a mirror-symmetrical manner, so as to perform a second directional dry etching on the top surface of the active region, thereby smoothing the top surface of the active region.

[0018] Optionally, the step of performing a second directional dry etching on the apex of the active region includes: adjusting the tilt angle of the substrate so that the plasma beam direction and the top surface of the substrate form the second angle, so as to perform a second directional dry etching on the top surface of the active region, and rotating the substrate in the plane where its top surface is located during the second directional dry etching process.

[0019] Optionally, during the first directional dry etching and / or the second directional dry etching, the substrate is rotated in the plane containing its top surface.

[0020] Optionally, during the first directional dry etching and / or the second directional dry etching, at least one parameter among the following parameters in the etching process—pressure, radio frequency power, type and flow rate of the reaction gas, and temperature of the reaction chamber—is adjusted to control the silicon consumption of the active region and the consumption of the device isolation structure exposed at the trench.

[0021] Optionally, the manufacturing method further includes at least one of the following (1) to (7):

[0022] (1) Before forming a gate oxide layer on the top of the active region, an oxide film is grown in situ on the surface of the active region, and during the formation of the gate oxide layer, the apex of the active region remains rounded under the constraint of the oxide film.

[0023] (2) Before forming a gate oxide layer on the top of the active region, ions to improve the oxidation rate of the active region are doped into the exposed top of the active region by ion implantation or diffusion doping process.

[0024] (3) Before forming a gate oxide layer on the top of the active region, ions for consuming oxygen diffused into the device isolation structure are doped into the sidewalls of the device isolation structure exposed by the side trench by an ion implantation process or a diffusion doping process.

[0025] (4) Before performing the first directional dry etching on the apex of the active region, a blocking sidewall is also formed on the sidewall of the device isolation structure exposed by the trench.

[0026] (5) The top corner of the isolation structure of the device is side-etched by wet etching and the natural oxide layer on the surface of the active region is removed to form the side trench and expose the top surface of the active region.

[0027] (6) The first included angle can be variable or fixed, and the first included angle is 3° to 87°;

[0028] (7) The second included angle can be variable or fixed, and the second included angle is 3° to 50°.

[0029] Optionally, in step (1), the oxide film is formed on the apex surface of the active region by means of a rapid annealing process, a rapid thermal oxidation process, an atomic layer deposition process, or a process of low-temperature oxygen purging on the surface of the active region.

[0030] In (2), the ions used to improve the oxidation rate of the active region include at least one of oxygen ions, amorphous ions and halide ions, and the amorphous ions include at least one of silicon ions, germanium ions and argon ions.

[0031] In (3), the ions used to consume oxygen diffused into the device isolation structure include silicon ions and / or germanium ions;

[0032] In step (4), the sidewall of the device isolation structure exposed by the trench is converted into the barrier sidewall by ion doping or surface modification; or, the barrier sidewall is formed on the sidewall of the device isolation structure of the trench by material deposition combined with etching.

[0033] Optionally, in step (4), the ions used in the ion doping method include at least one of oxygen ions, nitrogen ions, and carbon ions, and the surface modification treatment includes plasma nitriding or annealing in a nitrogen atmosphere.

[0034] Compared with the prior art, the technical solution of the present invention, after forming a trench exposing the apex corner of the active region for forming the gate oxide layer in the side-hole device isolation structure, firstly, by controlling the plasma beam direction to form a first angle with the top surface of the substrate, performs a first directional dry etching on the apex corner of the active region exposed by the trench, so as to round the apex corner of the active region; then, by controlling the plasma beam direction to form a second angle with the top surface of the substrate (the second angle is smaller than the first angle), performs a second directional dry etching on the top surface of the active region, so as to smooth the top surface of the active region. As a result, when the gate oxide layer is subsequently grown in situ on the active region, the growth rate uniformity and thickness uniformity of the gate oxide layer can be improved, the thickness at the edge of the gate oxide layer can be increased, and the sharp corner problem during the manufacturing of the gate oxide layer can be improved, thereby improving the breakdown voltage of the device, ensuring the stability of device performance, and improving the reliability and yield of the device. Attached Figure Description

[0035] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0036] Figure 1 This is a scanning electron microscope (SEM) schematic diagram showing the upward-pointing sharp corners at both ends of the surface of the active region AA after in-situ growth of gate oxide using existing technology.

[0037] Figure 2 This is a schematic diagram of the manufacturing process of a semiconductor device according to the first embodiment of the present invention.

[0038] Figures 3 to 7 This is a schematic cross-sectional view of an example device in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0039] Figures 8 to 11 This is a schematic cross-sectional view of another example of a semiconductor device manufacturing method according to an embodiment of the present invention. Detailed Implementation

[0040] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0041] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0042] Please refer to Figure 2 This embodiment provides a method for manufacturing a semiconductor device, which includes the following steps:

[0043] S1, providing a substrate and forming a device isolation structure in the substrate to define an active region;

[0044] S2, perform side-cut etching on the top corner of the device isolation structure to form a side trench that exposes the top corner of the active region;

[0045] S3, by controlling the direction of the plasma beam to form a first angle with the top surface of the substrate, the top corner of the active region is subjected to a first directional dry etching, so that the top corner of the active region exposed by the side trench is rounded.

[0046] S4, by controlling the plasma beam direction to form a second angle with the top surface of the substrate, a second directional dry etching is performed on the top surface of the active region to make the top surface of the active region smooth, and the second angle is smaller than the first angle;

[0047] S5, a gate oxide layer is formed on top of the active region.

[0048] In step S1, please refer to Figure 3 First, the provided substrate 100 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI). Then, a device isolation structure 101 is formed in the substrate 100. This device isolation structure 101 can be a shallow trench isolation structure (STI) or a localized field oxide isolation structure (LOCOS). The device isolation structure 101 is used to define the active region AA and other active regions in the substrate 100 where the gate oxide layer is to be formed.

[0049] As an example, please refer to Figure 3 Taking a shallow trench isolation structure as an example, in step S1, the specific steps for forming the device isolation structure 101 and the active region AA in the substrate 100 include:

[0050] S1.1, a pad oxide layer (PAD OX, not shown) is formed on the substrate 100 by any suitable process such as thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition, and a hard mask layer such as silicon nitride is further deposited on the pad oxide layer by chemical vapor deposition, and the hard mask layer is etched by photolithography and etching processes to form a patterned hard mask layer (not shown) for defining the shallow trench formation region.

[0051] S1.2 Using the patterned hard mask layer described above as a mask, the pad oxide layer and the substrate 100 are etched to form shallow trenches (not shown) in the substrate 100.

[0052] S1.3, a linear oxide layer (not shown) is formed on the inner surface of the shallow trench through thermal oxidation, atomic layer deposition or plasma-enhanced chemical vapor deposition, and then an insulating dielectric material (not shown) is deposited through a high aspect ratio filling process or a high density plasma deposition process to fill the shallow trench.

[0053] S1.4, the top of the filled insulating dielectric material is planarized to the patterned hard mask layer by chemical mechanical polishing process, thereby removing excess insulating dielectric material, thus forming a shallow trench isolation structure STI filled in the shallow trench with a flat top surface and serving as a device isolation structure 101, defining an active region AA in the substrate 100 (the active region can be the active region of a high-voltage MOS device).

[0054] S1.5, the patterned hard mask layer is removed by wet etching process, and the top of the final device isolation structure 101 can be flush with or higher than the top of the substrate 100. At this time, the silicon surface at the top of the active region AA is exposed.

[0055] Optionally, before forming shallow trenches for manufacturing device isolation structures 101 in the etched substrate 100, or after forming device isolation structures 101, vertical ion implantation or tilted ion implantation plasma implantation processes are used to implant ions into the substrate 100 accordingly. For example, P-type ion implantation such as boron is performed to form a P-well region (not shown), or N-type ion implantation such as arsenic or phosphorus is performed to form an N-well region (not shown), or threshold voltage ion implantation is performed to adjust the threshold voltage of the device, etc.

[0056] Please refer to Figure 3 In step S2, firstly, a hard mask material such as silicon nitride is redeposited on the substrate surface, including the active region AA and the device isolation structure 101, using processes such as chemical vapor deposition, to form a new hard mask layer. Then, the new hard mask layer is photolithographically etched to form a patterned mask layer 102. This patterned mask layer 102 has an opening 102a, which exposes the top surface of the active region used to form the gate oxide layer and the apex corner of the device isolation structure 101 surrounding this region. The patterned mask layer 102 can be a single-layer film structure such as silicon nitride, or a multilayer composite structure composed of alternating layers of silicon oxide and silicon nitride. In this embodiment, the patterned mask layer 102 exposes the top and apex corners of the active region AA and the apex corner of the device isolation structure 101 near the active region AA. For ease of description, the active region AA to which the gate oxide layer is to be formed will be referred to as "the active region AA" or "the active region AA" in the following text. Next, under the masking of the patterned mask layer 102, a wet etching process, a dry etching process, or a combination of dry and wet etching processes are used to etch away the top corner of the device isolation structure 101 exposed by the opening 102a to form a side trench 101a. The side trench 101a exposes the top corner of the active region used to form the gate oxide layer. The etching process removes the natural oxide layer and the like on the surface of the active region while forming the side trench 101a.

[0057] In one example, please refer to Figure 8After the patterned mask layer 102 is formed and before the trench 101a is formed, the top of the active region AA exposed by the opening 102a is thermally oxidized under the masking effect of the patterned mask layer 102 to form a sacrificial oxide layer 105. Thus, before or during the etching process of removing the apex exposed by the opening 102a of the device isolation structure 101 to form the trench 101a, the sacrificial oxide layer 105 is also etched away to reduce the height of the top of the active region AA exposed by the opening 102a. After the trench 101a is formed, the height of the top of the active region AA exposed by the opening 102a is higher than the bottom of the trench 101a, thereby providing sufficient process window for subsequent processes.

[0058] Optionally, in this example, before forming the sacrificial oxide layer 105, under the masking effect of the patterned mask layer 102, a pre-amorphization implantation (PAI) is performed on the active region AA exposed by the opening 102a using vertical ion implantation or tilted ion implantation plasma implantation processes. This disrupts the crystal lattice of the active region AA surface, enhancing the oxidation rate of the top of the active region AA during the subsequent formation of the sacrificial oxide layer 105. The ions used in this pre-amorphization implantation can be any suitable type. The implanted ions can combine through one or more methods, such as physical bombardment or chemical bond breaking, to disrupt the crystal lattice of the active region AA surface, making the surface of the active region AA amorphous. For example, the ions used in this pre-amorphization implantation include silicon (Si) ions. On the one hand, this disrupts the crystal lattice of the active region AA surface, giving the silicon elements on the surface of the active region a loose structure through amorphization; on the other hand, it increases the silicon content in the surface layer of the active region AA, thereby compensating for silicon losses in the active region AA during subsequent processes.

[0059] In another example, please refer to Figure 9 In step S2, before or after forming the trench 101a, under the masking of the patterned mask layer 102, the top of the active region exposed by the opening 102a is etched to reduce the top height of the active region, providing a sufficiently large process window for the gate oxide layer subsequently grown in situ on the top of the active region. For example, under the masking of the patterned mask layer 102, the active region AA exposed by the opening 102a can be dry-etched first to reduce the top height of the active region AA, and then the top corner of the device isolation structure 101 exposed at the sidewall of the opening 102a can be wet-etched (i.e., the device isolation structure 101 is side-cut) to form the trench 101a connecting the opening 102a.

[0060] Optionally, in this example, before etching the top of the active region exposed by the opening 102a to reduce the top height of the active region, pre-amorphization implantation (PAI) is performed on the active region AA using vertical ion implantation or tilted ion implantation plasma implantation processes under the masking effect of the patterned mask layer 102. This disrupts the crystal lattice on the surface of the active region AA, enhancing the etching rate of the active region AA. The ions 106 used in this pre-amorphization implantation can be any suitable type. The implanted ions can disrupt the crystal lattice on the surface of the active region AA through one or more methods such as physical bombardment and chemical bond breaking, thus making the surface of the active region AA amorphous. For example, the ions used in this pre-amorphization implantation include silicon (Si) ions. On the one hand, this disrupts the crystal lattice on the surface of the active region AA, giving the silicon elements on the surface of the active region a loose structure through amorphization; on the other hand, it increases the silicon content in the surface layer of the active region AA, thereby compensating for silicon loss in subsequent etching processes such as etching the active region AA.

[0061] In steps S1 and S2, the top surface of the substrate 100 is placed in a horizontal direction. In step S3, by tilting the substrate 100, the plasma beam direction is made to form a first angle θ with the top surface of the substrate 100, so as to perform a first directional dry etching on the top corner of the active region AA exposed by the side trench 101a, thereby rounding the top corner of the active region AA.

[0062] In one example, step S3, which involves performing a first directional dry etching on the apex of the active region AA exposed by the trench 101a, includes:

[0063] S3.1, please refer to Figure 4A The substrate 100 can be tilted relative to the horizontal direction (e.g., tilted to the right) by adjusting the tilt direction and tilt angle of the support stage 200 on the machine, so that the top surface of the substrate 100 forms a first angle θ with the direction of the plasma beam. Thus, under the masking effect of the patterned mask layer 102, the apex corner of the active region AA exposed by the side trench 101a is subjected to a first directional dry etching. During this process, by tilting the substrate 100 to make the direction of the plasma beam form a first angle θ with the top surface of the substrate 100 for directional etching, the plasma beam can etch the sidewall of the apex corner of the active region AA exposed by the side trench 101a on one side of the opening 102a (e.g., the left side), and etch the top of the apex corner of the active region AA exposed by the side trench 101a on the other side of the opening 102a (e.g., the right side). Optionally, the first included angle θ can be variable (e.g., gradually decreasing from large) or fixed, and the first included angle θ is 3° to 87°, for example 45° to 87°.

[0064] S3.2, the tilt direction and tilt angle of the support stage 200 on the machine can be adjusted again to make the substrate 100 tilted in the opposite direction to the horizontal direction (e.g., tilted to the left), and the plasma beam direction can be mirror-symmetrically adjusted to form a first angle θ between the plasma beam direction and the top surface of the substrate 100, thereby continuing the first directional dry etching of the apex corner of the active region AA exposed by the side trench 101a. In this process, the reverse tilt of the substrate 100 allows the plasma beam to etch the sidewall of the apex corner of the active region AA exposed by the side trench 101a on the other side of the opening 102a (e.g., the right side), and to etch the top of the apex corner of the active region AA exposed by the side trench 101a on one side of the opening 102a (e.g., the left side).

[0065] Thus, by tilting the substrate in opposite directions twice in steps S3.1 and S3.2, the apex corners of the active region AA exposed on both sides of the opening 102a are trimmed from different directions, making the apex corners of the active region AA smooth.

[0066] It should be understood that the positional relationship between the substrate 100 and the plasma beam in step S3.1 and the positional relationship between the substrate and the plasma beam in step S3.2 can be achieved by any suitable means.

[0067] In one example, please refer to Figure 4A As shown, when the plasma beam is incident from above the substrate 100 in a vertical direction (which is perpendicular to the horizontal direction), the direction of the plasma beam can be kept unchanged, and the tilting direction of the substrate 100 in steps S3.1 and S3.2 can be reversed, so that the positional relationship between the substrate 100 and the plasma beam in step S3.1 is mirror-symmetrical with the positional relationship between the substrate and the plasma beam in step S3.2.

[0068] In another example, please refer to Figure 4B As shown, when the plasma beam 0 is incident horizontally from the side of the substrate 100, not only must the tilt direction of the substrate 100 in steps S3.1 and S3.2 be reversed, but the direction of the plasma beam also needs to be flipped by 180 degrees (for example, in step S3.1, the substrate 100 is tilted to the left and the plasma beam is incident horizontally from left to right; in step S3.2, the substrate 100 is tilted to the right and the plasma beam is incident horizontally from right to left) in order to achieve a mirror-symmetric relationship between the positional relationship of the substrate 100 and the plasma beam in step S3.1 and the positional relationship of the substrate and the plasma beam in step S3.2.

[0069] In other examples, the plasma beams used in steps S3.1 and S3.2 can also be incident from directions other than the horizontal and vertical directions, which need to meet the requirement of mirror symmetry for the two-step etching in steps S3.1 and S3.2.

[0070] Optionally, in the first directional dry etching process of step S3.1, at least one etching process parameter, such as etching pressure, type and flow rate of reaction gas that generates plasma beam, reaction chamber temperature, and radio frequency power, is adjusted to control the silicon consumption of the active region AA exposed by the opening 102a and the side trench 101a, as well as the oxide consumption of the device isolation structure 101 exposed by the side trench 101a.

[0071] Optionally, during the first directional dry etching process in step S3.1, the first included angle θ can be variable (e.g., gradually decreasing from large) or fixed. For example, the first included angle θ is 3° to 87°, such as 45° to 87°.

[0072] Optionally, during the first directional dry etching process in step S3.2, at least one etching process parameter, such as etching pressure, type and flow rate of reaction gas that generates plasma beam, reaction chamber temperature, and radio frequency power, is further adjusted to control the silicon consumption of the active region AA exposed by the opening 102a and the side trench 101a, as well as the oxide consumption of the device isolation structure 101 exposed by the side trench 101a.

[0073] Optionally, during the first directional dry etching process in step S3.2, the first included angle θ can be variable (e.g., gradually decreasing from large) or fixed. For example, the first included angle θ is 3° to 87°, such as 45° to 87°.

[0074] Further optional, please combine Figure 4A and Figure 4B To further improve the smoothness of the apex corners of the active region AA exposed by the side trenches 101a on both sides of the opening 102a, in at least one of steps S3.1 and S3.2, while performing the first directional dry etching, the substrate 100 can be rotated around its central axis. This allows the substrate 100 to rotate within the plane containing its top surface (the rotation method can be referred to...). Figure 5 (Example shown).

[0075] In another example, please refer to Figure 5Step S3, which involves performing a first directional dry etching on the apex corner of the active region AA exposed by the trench 101a, includes: adjusting the tilt direction and tilt angle of the support stage 200 on the machine to tilt the substrate 100 on the support stage 200 (e.g., tilting to the right), so that the top surface of the substrate 100 forms a corresponding angle with the horizontal direction. This creates a first angle θ between the plasma beam direction and the top surface of the substrate 100, enabling the first directional dry etching of the apex corner of the active region AA exposed by the trench 101a. During the first directional dry etching process, the support stage 200 rotates around its axis, causing the substrate 100 to rotate within the plane containing its top surface. This method also makes the apex corner of the active region AA exposed by the trench 101a smoother.

[0076] Please refer to Figure 6 In step S4, the angle of substrate tilt is adjusted so that the direction of the plasma beam is at a second angle α with the top surface of substrate 100, so as to perform a second directional dry etching on the top surface of the active region AA exposed by the opening 102a, so that the top surface of the active region AA is smooth.

[0077] In one example, step S4, which involves performing a second directional dry etching on the top surface of the active region AA exposed by the opening 102a, includes:

[0078] S4.1, by adjusting the tilt angle of the support stage 200 used to support the substrate 100 on the machine, a second included angle α can be achieved between the top surface of the substrate 100 on the support stage and the direction of the plasma beam. Then, under the masking effect of the patterned mask layer 102, the top surface of the active region AA exposed by the opening 102a is subjected to a second directional dry etching.

[0079] S4.2, the substrate 100 on the support stage 200 on the machine can be tilted in the opposite direction again by adjusting the tilt direction and tilt angle of the support stage 200 on the machine, and the plasma beam direction can be made to form a second included angle α with the top surface of the substrate 100 in a mirror symmetrical manner. Then, under the masking effect of the patterned mask layer 102, the top surface of the active region AA exposed by the opening 102a can be subjected to a second directional dry etching.

[0080] Thus, by tilting the substrate in opposite directions twice in steps S4.1 and S4.2, the top surface of the active region AA exposed by the opening 102a is trimmed from different directions, making the apex corner of the top surface of the active region AA exposed by the opening 102a smooth.

[0081] It should be understood that the positional relationship between the substrate 100 and the plasma beam in step S4.1 and the positional relationship between the substrate and the plasma beam in step S4.2 can be achieved by any suitable means.

[0082] In one example, please refer to Figure 6 As shown, when the plasma beam 0 is incident horizontally from the side of the substrate 100, not only must the tilt direction of the substrate 100 in steps S4.1 and S4.2 be reversed, but the direction of the plasma beam also needs to be flipped by 180 degrees (for example, in step S4.1, the substrate 100 is tilted to the left and the plasma beam is incident horizontally from left to right; in step S4.2, the substrate 100 is tilted to the right and the plasma beam is incident horizontally from right to left) in order to achieve a mirror-symmetric relationship between the positional relationship of the substrate 100 and the plasma beam in step S4.1 and the positional relationship of the substrate and the plasma beam in step S4.2.

[0083] In another example, when the plasma beam is emitted from above the substrate 100 and along a vertical direction (which is perpendicular to the horizontal direction, see reference 100)... Figure 4A When the plasma beam is incident (as shown), the direction of the plasma beam can be kept unchanged, and the tilting direction of the substrate 100 in steps S4.1 and S4.2 can be controlled to be opposite, so that the positional relationship between the substrate 100 and the plasma beam in step S4.1 is mirror-symmetrical with the positional relationship between the substrate and the plasma beam in step S4.2.

[0084] In other examples, the plasma beams used in steps S4.1 and S4.2 can also be incident from directions other than the horizontal and vertical directions, which need to meet the requirement of mirror symmetry for the two-step etching in steps S4.1 and S4.2.

[0085] Optionally, during the second directional dry etching process in step S4.1, at least one parameter, such as etching pressure, type and flow rate of reaction gas that generates plasma beam, reaction chamber temperature, and radio frequency power, is adjusted to control the silicon consumption of the active region AA exposed by the opening 102a and the side trench 101a, as well as the oxide consumption of the device isolation structure 101 exposed by the side trench 101a.

[0086] Optionally, during the second directional dry etching process in step S4.1, the second included angle α can be variable (e.g., gradually decreasing from large) or fixed. The second included angle α is 3° to 50°, for example, 5° to 20°, to achieve smoothing of the top surface of the active region AA exposed at the opening 102a, and to minimize the consumption of the planar silicon surface of the top surface of the active region AA, which is also beneficial to the uniform growth of the subsequent gate oxide layer.

[0087] Optionally, during the second directional dry etching process in step S4.2, at least one parameter, such as etching pressure, type and flow rate of reaction gas that generates plasma beam, reaction chamber temperature, and radio frequency power, is adjusted to control the silicon consumption of the active region AA exposed by the opening 102a and the side trench 101a, as well as the oxide consumption of the device isolation structure 101 exposed by the side trench 101a.

[0088] Optionally, during the second directional dry etching process in step S4.2, the second included angle α can be variable (e.g., gradually decreasing from large) or fixed. The second included angle α is 3° to 50°, for example, 5° to 20°, to achieve smoothing of the top surface of the active region AA exposed at the opening 102a, and to minimize the consumption of the planar silicon surface of the top surface of the active region AA, which is also beneficial to the uniform growth of the subsequent gate oxide layer.

[0089] Further optionally, to further improve the smoothness of the top surface of the active region AA exposed by the opening 102a, in at least one of steps S4.1 and S4.2, while performing the second directional dry etching, the substrate 100 can be rotated about its central axis, thereby allowing the substrate 100 to rotate within the plane containing its top surface (the rotation method can be referred to...). Figure 5 (As shown).

[0090] In another example, the step of performing a second directional dry etching on the top surface of the active region AA exposed by the opening 102a in step S4 can be performed using a similar method. Figure 5 The method shown includes adjusting the tilt direction and tilt angle of the support stage 200 on the machine to tilt the substrate 100 on the support stage 200 (e.g., tilting to the right), so that the top surface of the substrate 100 forms a corresponding angle with the horizontal direction. This creates a second angle α between the plasma beam direction and the top surface of the substrate 100, enabling second-directional dry etching of the top surface of the active region AA exposed by the opening 102a. During the second-directional dry etching process, the support stage 200 rotates around its axis, causing the substrate 100 to rotate within the plane containing its top surface. This method also makes the top surface of the active region AA exposed by the opening 102a smooth.

[0091] It is worth noting that the meaning of "the second included angle α is less than the first included angle θ" in this article can include one of the following situations: (1) When the first included angle θ and the second included angle α used in the above corresponding steps are both fixed values, the value of the second included angle α is less than the value of the first included angle θ; (2) When the first included angle θ is variable and the second included angle α is fixed, the value of the second included angle α is less than the minimum value or the average value of the first included angle θ; (3) When the first included angle θ is fixed and the second included angle α is variable, the maximum value or the average value of the second included angle α is less than the first included angle θ; (4) When both the first included angle θ and the second included angle α are variable, the maximum value or the average value of the second included angle α is less than the minimum value or the average value of the first included angle θ.

[0092] Please refer to Figure 7 In step S5, any suitable oxidation process, such as furnace tube oxidation, can be used to grow a sufficiently thick gate oxide layer 104 in situ on the surface of the active region AA. During the growth of the gate oxide layer 104, since the corners of the active region AA are rounded, the consistency of the oxidation rate between the corners and the central region of the active region AA can be improved. This increases the thickness of the gate oxide layer 104 at the corners of the active region AA compared to existing technologies under the same conditions, solving the problem that the gate oxide layer 104 at the corners of the active region AA is too thin and easily broken down. In this step, the side trench 101a can provide a certain space for the growth of the gate oxide layer 104, mitigating or avoiding the problem of compressive stress generated in the grown gate oxide layer 104, which is beneficial to improving the quality and reliability of the formed gate oxide layer 104.

[0093] Optionally, before growing the gate oxide layer 104 in step S5, a highly dense oxide film 103 is formed on the exposed surface of the active region AA exposed at the opening 102a using any suitable process, such as rapid annealing, rapid thermal oxidation (e.g., in-situ vapor generation ISSG process), atomic layer deposition, or low-temperature oxygen purging of the active region AA, under the masking of the patterned mask layer 102. This oxide film 103 can be used to restrict the rounded corners of the active region AA during the subsequent formation of the gate oxide layer 104, thereby improving the thickness uniformity of the gate oxide layer 104. Furthermore, this oxide film 103 has higher density than oxides formed by conventional thermal oxidation processes, and its thickness does not need to be too thick, as long as it can achieve the effect of maintaining the rounded corners of the active region AA in this step and subsequent processes. For example, the thickness of the oxide film 103 is...

[0094] In this process, a highly dense oxide film 103 is formed on the exposed surface of the active region AA using a rapid annealing process. This oxide film 103 can maintain the rounded corners of the active region AA during the subsequent growth process of the gate oxide layer 104. The oxide film 103 is relatively thin, and its formation consumes very little of the thickness of the active region AA. This rapid annealing process can not only form the required oxide film 103, but also repair the interface lattice damage caused to the surface of the active region AA by previous processes.

[0095] When forming the oxide film 103 using a low-temperature oxygen purging process on the surface of the active region AA, appropriate process parameters such as the specific process temperature (e.g., below 100°C), the specific oxygen concentration in the oxygen-containing atmosphere, and the specific surface treatment time can be set as needed. In this suitable oxygen-containing atmosphere, the active region AA is subjected to surface oxidation treatment, causing impurity ions such as boron ions and silicon elements on the surface of the active region AA to be oxidized to form the oxide film 103 (which is, for example, a combination of boron oxide and silicon dioxide). This eliminates impurity ions formed on the surface of the active region AA in previous steps, thereby ensuring the uniformity of the thickness of the gate oxide layer 104 grown in situ at different locations in the active region AA, improving device reliability and product yield. Furthermore, this oxygen-containing atmosphere can also repair the device isolation structure 101 exposed by the side trench 101a and increase the density of the exposed device isolation structure 101, preventing changes in the exposed device isolation structure 101 due to oxygen reaction during the subsequent growth of the gate oxide layer 104.

[0096] Furthermore, the reactive gas used in the process of forming the oxide thin film 103 includes ozone or a mixture of ozone and oxygen, thereby increasing the density of the formed oxide thin film 103. Moreover, the highly dense oxide thin film 103 can suppress the amount and rate of oxygen entry during the subsequent growth of the gate oxide layer, thereby controlling the uniformity of the growth rate and thickness of oxides at different positions on the surface of the active region AA exposed by the patterned mask layer 102. At the same time, it can improve the lattice defects caused by processes such as threshold voltage ion implantation in the active region AA.

[0097] Alternatively, please refer to Figure 10After completing step S2 and before proceeding to step S3, a barrier sidewall 107 is formed on the sidewall of the device isolation structure 101 exposed by the trench 101a using any suitable process. This barrier sidewall 107 can protect the sidewall of the device isolation structure 101 at the trench 101a during the etching processes of subsequent steps S3 and S4, and block the lateral diffusion of oxygen during the growth of the gate oxide layer in subsequent step S5, thus avoiding the bird beak problem. Alternatively, after completing step S3 or step S4 and before proceeding to step S5, a barrier sidewall 107 is formed on the sidewall of the device isolation structure 101 exposed by the trench 101a. This barrier sidewall 107 can block the lateral diffusion of oxygen during the growth of the gate oxide layer in subsequent step S5, thus avoiding the bird beak problem.

[0098] As an example, the process of forming the barrier sidewall 107 includes:

[0099] First, a stress buffer layer (not shown) is formed using any suitable process such as atomic layer deposition, plasma-enhanced chemical vapor deposition, or thermal oxidation. When the stress buffer layer is deposited using a deposition process, it covers the patterned hard mask layer 102, the exposed surface of the device isolation structure 101, and the exposed surface of the active region AA. This stress buffer layer can serve as a protective layer for the active region AA during the subsequent formation of the barrier sidewall 107, or as a stress buffer layer; its material can be any suitable, such as silicon oxide. When the stress buffer layer is formed using a thermal oxidation process, it only covers the exposed surface of the active region AA.

[0100] Then, by any suitable process such as atomic layer deposition or plasma-enhanced chemical vapor deposition, a barrier layer (not shown) is formed by depositing any suitable film layer such as silicon nitride or silicon oxynitride on the surface of the stress buffer layer and the exposed patterned hard mask layer 102 and device isolation structure 101. In this process, the stress buffer layer can buffer the stress caused to the active region AA during the formation of the barrier layer.

[0101] Next, by using any suitable dry etching process such as plasma etching, the barrier layer and stress buffer layer are etched to remove the barrier layer and stress buffer layer on the surface of the active region AA, while retaining the barrier layer and stress buffer layer on the sidewall of the device isolation structure 101 exposed by the side trench 101a, to form the required barrier sidewall 107. In this process, the stress buffer layer can act as a protective layer to prevent damage to the substrate 100 during the etching of the barrier layer to form the barrier sidewall 107.

[0102] As another example, a stress buffer layer is first formed using the method described above. Then, a portion of the sidewall of the device isolation structure 101 exposed at the trench 101a is converted into a barrier sidewall 107 by any suitable surface modification method, such as ion doping (using ions that may include at least one of oxygen, nitrogen, and carbon ions), plasma nitriding, or annealing in a nitrogen atmosphere. During this ion doping or surface modification process, the stress buffer layer acts as a protective layer to prevent the exposed surface of the active region AA from being adversely affected.

[0103] Optionally, the ions used in the ion doping method may include ions that can react with oxygen and consume oxygen. These ions in the barrier sidewall 107 formed by the ion doping method can react with the laterally diffused oxygen molecules during the thermal oxidation process when the gate oxide layer is formed in the subsequent step S5, thereby suppressing the lateral diffusion of oxygen molecules during the thermal oxidation process when the gate oxide layer is formed, and preventing oxygen molecules from passing through the top of the device isolation structure 101 and reacting with the active region on the other side of the device isolation structure 101 to form a bird's beak structure.

[0104] Alternatively, the ions used in the ion doping method may also include ions that can improve the density of the exposed top sidewall of the device isolation structure 101. The barrier sidewall 107 formed by the ion doping can directly block the transversely diffused oxygen molecules from passing through during the thermal oxidation process when the gate oxide layer is formed in the subsequent step S5, thereby suppressing the transverse diffusion of oxygen molecules during the thermal oxidation process when the gate oxide layer is formed in the subsequent step S5, and preventing oxygen molecules from passing through the top of the device isolation structure 101 and reacting with the active region on the other side of the top of the device isolation structure 101 to form a bird's beak structure.

[0105] Furthermore, surface modification methods such as plasma nitriding or annealing in a nitrogen atmosphere can transform the sidewalls of the device isolation structure 101 exposed by the trench 101a into a denser film such as silicon nitride or silicon oxynitride as a barrier sidewall 107. This barrier sidewall 107 can block the lateral diffusion of oxygen molecules during the thermal oxidation process when the gate oxide layer is formed in the subsequent step S5, making it difficult for oxygen molecules to pass through the top of the device isolation structure 101 and react with the active region on the other side of the top of the device isolation structure 101 to form a bird's beak structure.

[0106] Alternatively, please refer to Figure 11 After completing step S3 and before performing step S5 in situ growth of the gate oxide layer 104 (i.e., before growing the oxide film 103 or after growing the oxide film 103 and before growing the gate oxide layer 104), it further includes at least one of the following (1) and (2):

[0107] (1) By means of ion implantation or diffusion doping, ions 108 are doped into the exposed top of the active region AA to improve the oxidation rate of the active region AA in step S5.

[0108] (2) Ions that consume oxygen diffused into the device isolation structure 101 in step S5 are doped into the sidewall of the device isolation structure 101 exposed by the side trench 101a by means of ion implantation or diffusion doping.

[0109] In (1), the ion implantation process can be implemented by any suitable ion implantation process such as vertical ion implantation or tilted ion implantation. The implanted ions 108 used to improve the oxidation rate of AA in the active region may include at least one of oxygen ions, amorphous ions and halide ions.

[0110] The injection of oxygen ions can increase the oxygen content in the active region AA, thereby increasing the oxidation rate of the top of the active region AA in the subsequent step S5, accelerating the oxidation process of the surface of the active region AA, reducing the oxidation time, and thus reducing the beak size.

[0111] Amorphous ions include at least one of silicon ions, germanium ions, or argon ions. For example, when the intrinsic material of the active region AA is monocrystalline silicon, the implantation of amorphous ions can break the crystal lattice of the active region AA, causing the monocrystalline silicon in the active region AA to form amorphous silicon, making the surface of the active region AA more porous, thereby increasing the oxidation rate of the top oxidation of the active region AA in the subsequent step S5, accelerating the oxidation process of the surface layer of the active region AA, reducing the oxidation time, and thus reducing the beak effect.

[0112] Halogen ions include at least one of chloride ions (Cl), fluoride ions (F), and bromide ions (Br). The implantation of halide ions can act as a catalyst, reducing the Si-O bond energy in the active region AA. Therefore, when the gate oxide layer is formed by thermal oxidation in step S5, the SO bond energy of the SiO2 in the already formed upper gate oxide layer is weaker, making it easier for oxygen to diffuse in, thereby increasing the oxidation rate of the active region AA in step S5, accelerating the oxidation process of the active region AA surface, reducing the oxidation time, and thus reducing the beak size.

[0113] Furthermore, performing the process described in (1) after completing step S3 and before growing the oxide film 103 can improve the uniformity and formation rate of the oxide film 103.

[0114] In step (2), examples of doping in the sidewalls of the device isolation structure 101 exposed in the trench 101a may include silicon (Si) ions. Preferably, silicon (Si) ions are simultaneously implanted into the active region AA, causing amorphization of the surface layer of the active region AA, and providing sufficient Si ions in the device isolation structure 101 at the trench 101a. Thus, when the gate oxide layer 104 is grown in situ in step S5, oxygen diffuses into the device isolation structure 101 and is consumed by Si ions on the side of the device isolation structure 101 near the active region AA. The device isolation structure 101 becomes denser, thereby preventing oxygen from passing through the device isolation structure 101 to the other active region (e.g., the source / drain region), preventing the formation of a bird's beak, which is beneficial to improving the quality of the metal silicide subsequently formed on the other active region (e.g., the source / drain region) and reducing the resistance of the metal silicide.

[0115] In summary, the semiconductor device manufacturing method of this embodiment, after forming a trench exposing the apex corner of the active region for forming the gate oxide layer by side-cutting the device isolation structure, firstly, by controlling the plasma beam direction to form a first angle with the top surface of the substrate, performs a first directional dry etching on the apex corner of the active region exposed by the trench, rounding the apex corner of the active region; then, by controlling the plasma beam direction to form a second angle with the top surface of the substrate (the second angle is smaller than the first angle), performs a second directional dry etching on the top surface of the active region, smoothing the top surface of the active region. This improves the uniformity of the gate oxide growth rate and the uniformity of the generated thickness during subsequent in-situ growth of the gate oxide layer on the active region, increases the thickness at the edge of the gate oxide layer, and improves the sharp corner problem during gate oxide layer manufacturing, thereby increasing the breakdown voltage of the device and ensuring stable device performance.

[0116] It should be understood that those skilled in the art can combine any two or more of the technical solutions in the above examples to obtain other embodiments of the present invention, which will not be described in detail here.

[0117] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, and a device isolation structure is formed in the substrate to define the active region where the gate oxide layer is to be formed; Side-cut etching is performed on the top corner of the isolation structure of the device to form a trench that exposes the top corner of the active region; By controlling the direction of the plasma beam to form a first angle with the top surface of the substrate, the top corner of the active region is subjected to a first directional dry etching, so that the top corner of the active region exposed by the side trench is rounded. By controlling the plasma beam direction to form a second angle with the top surface of the substrate, a second directional dry etching is performed on the top surface of the active region to make the top surface of the active region smooth, and the second angle is smaller than the first angle. A gate oxide layer is formed on top of the active region.

2. The manufacturing method as described in claim 1, characterized in that, The step of performing a first directional dry etching on the apex of the active region includes: The substrate is tilted and the direction of the plasma beam is at the first angle with the top surface of the substrate to perform a first directional dry etching on the apex of the active region. The substrate is tilted in the opposite direction, and the plasma beam direction is made to form the first angle with the top surface of the substrate in a mirror-symmetrical manner, so as to perform the first directional dry etching on the top corner of the active region again, thereby rounding the top corner of the active region.

3. The manufacturing method as described in claim 1, characterized in that, The step of performing a first directional dry etching on the apex of the active region includes: tilting the substrate so that the direction of the plasma beam forms the first angle with the top surface of the substrate to perform a first directional dry etching on the apex of the active region, and rotating the substrate in the plane containing its top surface during the first directional dry etching process.

4. The manufacturing method as described in claim 1, characterized in that, The step of performing a second directional dry etching on the apex corner of the active region includes: The tilt angle of the substrate is adjusted so that the direction of the plasma beam forms the second angle with the top surface of the substrate, so as to perform a second directional dry etching on the top surface of the active region. The substrate is tilted in the opposite direction, and the plasma beam direction is again made to form the second angle between the top surface of the substrate in a mirror-symmetrical manner, so as to perform a second directional dry etching on the top surface of the active region, thereby smoothing the top surface of the active region.

5. The manufacturing method as described in claim 1, characterized in that, The step of performing a second directional dry etching on the top corner of the active region includes: adjusting the tilt angle of the substrate so that the direction of the plasma beam and the top surface of the substrate form the second angle, so as to perform a second directional dry etching on the top surface of the active region, and rotating the substrate in the plane where its top surface is located during the second directional dry etching process.

6. The manufacturing method according to any one of claims 1, 2, or 4, characterized in that, During the first directional dry etching and / or the second directional dry etching process, the substrate is rotated in the plane containing its top surface.

7. The manufacturing method according to any one of claims 1-5, characterized in that, During the first directional dry etching and / or the second directional dry etching, at least one parameter among the following parameters is adjusted during the etching process: pressure, radio frequency power, type and flow rate of reaction gas, and temperature of the reaction chamber, in order to control the silicon consumption of the active region and the consumption of the device isolation structure exposed at the trench.

8. The manufacturing method according to any one of claims 1-5, characterized in that, It also includes at least one of the following (1) to (7): (1) Before forming a gate oxide layer on the top of the active region, an oxide film is grown in situ on the surface of the active region, and during the formation of the gate oxide layer, the apex of the active region remains rounded under the constraint of the oxide film. (2) Before forming a gate oxide layer on the top of the active region, ions to improve the oxidation rate of the active region are doped into the exposed top of the active region by ion implantation or diffusion doping process. (3) Before forming a gate oxide layer on the top of the active region, ions for consuming oxygen diffused into the device isolation structure are doped into the sidewalls of the device isolation structure exposed by the side trench by an ion implantation process or a diffusion doping process. (4) Before performing the first directional dry etching on the apex of the active region, a blocking sidewall is also formed on the sidewall of the device isolation structure exposed by the trench. (5) The top corner of the isolation structure of the device is side-etched by wet etching and the natural oxide layer on the surface of the active region is removed to form the side trench and expose the top surface of the active region. (6) The first included angle can be variable or fixed, and the first included angle is 3° to 87°; (7) The second included angle can be variable or fixed, and the second included angle is 3° to 50°.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, In (1), the oxide film is formed on the apex surface of the active region by means of rapid annealing, rapid thermal oxidation, atomic layer deposition, or low-temperature oxygen purging of the active region surface. In (2), the ions used to improve the oxidation rate of the active region include at least one of oxygen ions, amorphous ions and halide ions, and the amorphous ions include at least one of silicon ions, germanium ions and argon ions. In (3), the ions used to consume oxygen diffused into the device isolation structure include silicon ions and / or germanium ions; In step (4), the sidewall of the device isolation structure exposed by the trench is converted into the barrier sidewall by ion doping process or surface modification process. Alternatively, a barrier sidewall can be formed on the sidewall of the device isolation structure of the trench through a process combining material deposition and etching.

10. The method for manufacturing a semiconductor device as described in claim 9, characterized in that, In (4), the ions used in the ion doping method include at least one of oxygen ions, nitrogen ions and carbon ions, and the surface modification treatment includes plasma nitriding or annealing in a nitrogen atmosphere.

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