Wafer level packaging method and wafer level packaging structure

Abstract

This invention relates to the field of semiconductor technology, providing a wafer-level packaging method and structure. The method includes: providing a MEMS suspended structure and a cover plate structure; etching trenches and electrode patterns on the bonding surface of the cover plate structure; directly bonding the MEMS suspended structure and the cover plate structure; etching the front side of the cover plate structure to achieve trench penetration; bonding the cover plate structure to a glass anode to form a glass sealing layer; melting the glass of the glass sealing layer at high temperature and reflowing it into the trenches to form an electrode isolation layer that isolates the through-penetrating electrodes; and thinning and polishing the glass sealing layer. This invention utilizes direct bonding technology combined with a glass reflow scheme to achieve wafer-level packaging of chips. The glass, as an isolation and sealing material, exists only in extremely fine trenches, solving the problem of poor temperature performance and low temperature linearity of devices caused by thermal stress mismatch when other materials are introduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a wafer-level packaging method and wafer-level packaging structure. Background Technology

[0002] MEMS (Micro-Electro-Mechanical System) wafer-level packaging technology is a technique that involves packaging the entire wafer after it has been manufactured, and then dicing it into individual chips. It significantly improves the performance and reliability of MEMS devices, enabling miniaturization and cost reduction. It is one of the key technologies for manufacturing MEMS devices and a foundation for their practical application.

[0003] Common wafer-level packaging technologies are implemented using through-silicon vias (TSVs), through-glass vias (GSVs / Glass-Silicon Vias / Glass Through Silicon Vias), and glass-silicon composite structures (GISs). The typical wafer-level packaging method involves fabricating MEMS structure prototypes and cover plate prototypes separately, then bonding them together. However, these methods cannot be implemented using direct silicon-to-silicon, silicon-to-silicon dioxide, or silicon-to-silicon dioxide bonding techniques because TSVs contain metal in the cover plate, TGVs contain both glass and metal, and GISs contain only glass in the cover plate.

[0004] In view of this, the present invention is provided.

[0005] The above description is provided as background information only and does not necessarily constitute prior art. Summary of the Invention

[0006] This invention provides a wafer-level packaging method and wafer-level packaging structure to address the shortcomings of existing technologies where direct silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide bonding cannot be used between MEMS structure samples and cover plate samples.

[0007] According to a first aspect of the present invention, a wafer-level packaging method includes: Step S100: Provide the MEMS suspended structure and the cover plate structure; Step S200: Grooves and electrode patterns are etched on the bonding surface of the cover plate structure; In step S300, the MEMS suspended structure and the cover plate structure are directly bonded together, and the bonding method is any one of silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide. Step S400: Etching is performed on the front side of the cover plate structure to achieve the penetration of the trench; In step S500, the cover plate structure is bonded to the glass anode to form a glass sealing layer; In step S600, after the glass of the glass sealing layer melts at high temperature, it flows back into the trench and forms an electrode isolation layer that isolates the through electrode in the trench. Step S700: Thinning and polishing the glass sealing layer.

[0008] According to one embodiment of the present invention, in step S200, the depth-to-width ratio of the trench is A, and the value of A is greater than 20:1.

[0009] Specifically, this embodiment provides an implementation of the aspect ratio of a trench.

[0010] According to one embodiment of the present invention, in step S200, wet etching or dry etching is used for the trenches and electrode patterns.

[0011] Specifically, this embodiment provides an implementation method for processing trenches and electrode patterns.

[0012] According to one embodiment of the present invention, in step S400, a plurality of trenches are etched on the front side of the cover plate structure using dry etching, wherein at least a portion of the trenches extend to the first bonding layer of the MEMS suspended structure, and at least another portion of the trenches extend to the second bonding layer of the MEMS suspended structure and the cover plate structure.

[0013] Specifically, this embodiment provides an implementation method for etching grooves on a cover plate structure.

[0014] According to one embodiment of the present invention, in step S500, the pressure at which the cover plate structure bonds with the glass anode is B, where B is between 1 Pa and 1000 Pa.

[0015] Specifically, this embodiment provides an implementation method for anodic bonding pressure.

[0016] According to one embodiment of the present invention, in step S600, the reflow temperature of the glass is C, where C is between 600 degrees Celsius and 1100 degrees Celsius.

[0017] Specifically, this embodiment provides an implementation method for glass reflow temperature.

[0018] According to a second aspect of the present invention, a wafer-level packaging structure includes: a substrate layer; a device layer having a first surface and a second surface, the first surface and the second surface being disposed opposite to each other, the first surface being bonded to the substrate layer; a cover plate layer bonded to the second surface of the device layer to form a sealed cavity, the cover plate layer having a trench for isolating through electrodes; a glass sealing layer bonded to the side of the cover plate layer away from the device layer; and an electrode isolation layer disposed within the trench.

[0019] According to one embodiment of the present invention, it further includes: a first bonding layer, the first bonding layer being disposed between the substrate layer and the device layer, and the first bonding layer being made of silicon dioxide material.

[0020] Specifically, this embodiment provides an implementation method for the first bonding layer.

[0021] According to one embodiment of the present invention, the device layer includes a functional region and a connection region; at least a second bonding layer is disposed between the cover plate layer and the connection region, the second bonding layer being made of silicon dioxide material.

[0022] Specifically, this embodiment provides an implementation method for functional areas and connection areas.

[0023] According to one embodiment of the present invention, the substrate layer, the device layer, the through electrode, and the cover plate layer are all made of silicon material.

[0024] Specifically, this embodiment provides an implementation method for fabricating materials for a substrate layer, a device layer, a through-electrode, and a cover plate layer.

[0025] According to one embodiment of the present invention, the glass sealing layer and the electrode insulating layer are made of glass material.

[0026] Specifically, this embodiment provides an implementation of a glass sealing layer and an electrode isolation layer.

[0027] According to one embodiment of the present invention, the trench includes a plurality of trenches; at least a portion of the trenches extends to the first surface, and at least another portion of the trenches extends to the second surface; wherein the depth-to-width ratio of the trenches is A, and the value of A is greater than 20:1.

[0028] Specifically, this embodiment provides an implementation of a trench.

[0029] The above-mentioned one or more technical solutions of the present invention have at least one of the following technical effects: The wafer-level packaging method provided by the present invention utilizes direct bonding technologies such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, combined with a glass reflow scheme, to achieve wafer-level packaging of chips. In the wafer-level MEMS structure provided by the present invention, glass, as an isolation and sealing material, exists only in extremely fine trenches. Therefore, the material system of the device is basically silicon, which can effectively avoid the introduction of other materials in other packaging technologies. Due to the inconsistent thermal properties of different materials, thermal stress mismatch leads to poor temperature performance and low temperature linearity of the device, which is of great significance for the fabrication of high-precision MEMS devices.

[0030] The present invention provides a wafer-level packaging structure that uses glass as an isolation and sealing material, existing only in extremely fine trenches. The material system of the device is basically silicon, which can be used to prepare MEMS devices with high precision and excellent temperature performance. It adopts direct bonding technology such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, combined with a glass reflow scheme to achieve wafer-level packaging of the chip. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic flowchart of the wafer-level packaging method provided by the present invention.

[0033] Figure 2 This is a schematic diagram of the MEMS suspended structure in the wafer-level packaging structure provided by the present invention.

[0034] Figure 3 This is a schematic diagram of the cover plate structure in the wafer-level packaging structure provided by the present invention.

[0035] Figure 4 This is a bonding schematic diagram of the wafer-level packaging structure provided by the present invention.

[0036] Figure 5 This is a schematic diagram of the etched trench forming a through-structure in the wafer-level packaging structure provided by the present invention.

[0037] Figure 6 This is a schematic diagram of the cover plate structure and glass anode bonding in the wafer-level packaging structure provided by the present invention.

[0038] Figure 7This is a schematic diagram of the glass hot-melt reflow forming the electrode isolation layer in the wafer-level packaging structure provided by the present invention.

[0039] Figure 8 This is a schematic diagram of the wafer-level packaging structure provided by the present invention.

[0040] Figure label: 10. MEMS suspended structure; 11. Substrate layer; 12. Device layer; 121. First surface; 122. Second surface; 123. Functional region; 124. Connection region; 13. First bonding layer; 20. Cover plate structure; 21. Groove; 22. Cover plate layer; 23. Through electrode; 30. Glass sealing layer; 40. Electrode isolation layer; 50. Sealed cavity; 60. Second bonding layer. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0042] In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0043] In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified. In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, B1 and / or B2 can represent: B1 existing alone, B1 and B2 existing simultaneously, and B2 existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0044] The following is combined Figures 1 to 8 The technical solution of the present invention will be described in detail below.

[0045] It should be noted that, Figures 1 to 8 The arrow in the image indicates that the current component is a virtual part, such as a process step, hole, slot, or plane.

[0046] Figure 1 This is one of the flowcharts of the wafer-level packaging method provided by the present invention, such as... Figure 1 As shown, the method includes the following: Step S100: Provide MEMS suspended structure 10 and cover structure 20; Step S200: Grooves 21 and electrode patterns are etched on the bonding surface of the cover plate structure 20; In step S300, the MEMS suspended structure 10 and the cover plate structure 20 are directly bonded together, and the bonding method is any one of silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide. In step S400, etching is performed on the front side of the cover plate structure 20 to achieve the penetration of the trench 21; Step S500: The cover plate structure 20 is bonded to the glass anode to form a glass sealing layer 30; In step S600, after the glass of the glass sealing layer 30 melts at high temperature, it flows back into the trench 21 and forms an electrode isolation layer 40 for isolating the through electrode 23 in the trench 21. Step S700: Thinning and polishing the glass sealing layer 30.

[0047] It should be noted that the bonding process has very high requirements for the surface quality and flatness of the sample, as well as the process requirements for the sealing cover. In the industrialization of MEMS devices, it is one of the important factors affecting the process yield.

[0048] In related technologies, the approach is to first fabricate a sealing cover and then use a bonding process to achieve wafer-level packaging.

[0049] Furthermore, the present invention first fabricates the MEMS suspended structure 10 and the cover plate structure 20 separately, and then seals them to form a MEMS sealed structure, that is, first fabricates the overall device structure, and then fabricates the sealed cover plate.

[0050] Understandably, the process steps preceding the bonding process of this invention will not affect the surface quality and warpage of the bonded sample, and therefore will not affect the bonding process, thus improving the process yield of MEMS devices.

[0051] In this embodiment, the present invention effectively solves the technical problems existing in the current MEMS wafer-level packaging technology, such as the inability to achieve direct bonding of silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, low process yield, poor device temperature performance, and difficulty in balancing sealing and isolation, by optimizing the process sequence step by step and precisely controlling the structure and material distribution. Moreover, the synergistic effect of each step further improves the reliability and practicality of the packaging structure, providing technical support for the industrialization of high-precision MEMS devices.

[0052] Regarding step S200, grooves 21 and electrode patterns are etched on the bonding surface of the cover plate structure 20.

[0053] This enables the effective application of direct bonding such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, improving the reliability and stability of the packaging structure. Step S200 only etches the trenches 21 and electrode patterns on the bonding surface of the cover plate structure 20, without introducing dissimilar materials such as metals or glass.

[0054] Regarding step S300, the MEMS suspended structure 10 and the cover plate structure 20 are directly bonded together, and the bonding method is any one of silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide.

[0055] Step S300 uses silicon-silicon direct bonding to combine the MEMS suspended structure 10 with the cover plate structure 20, which fully leverages the core advantages of direct bonding technologies such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, which are characterized by "low bonding interface stress and high reliability". This avoids the defects of existing TSV, TGV, and GIS cover plates, which cannot use direct bonding technologies such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide due to the presence of metal or glass. It reduces the risk of bonding interface failure and lays the foundation for the long-term stable operation of the packaging structure.

[0056] Furthermore, optimizing the process sequence significantly improves the yield of MEMS devices. The process path of "bonding first, then etching trench 21, and then glass sealing" (step S300 is performed before bonding, and subsequent steps S400-S700 are performed after bonding) avoids the damage to the surface quality, flatness, and warpage of the bonding surface caused by the previous cover plate fabrication process in the traditional "fabrication of cover plate first, then bonding" process. This reduces the probability of bonding failure from the source, solves a key problem affecting yield in industrialization, and is beneficial for the mass production of MEMS devices.

[0057] Furthermore, precise control of the glass distribution achieves reliable electrode isolation and cavity sealing, preventing device failure. In step S400, trench 21 is etched on the front side of the cover plate. In step S600, high temperature causes the glass to flow back into the trench 21 to form an electrode isolation layer 40. Combined with the structural design of the trench 21, it can effectively prevent the glass from flowing back into the sealed cavity of the MEMS suspended structure 10. This achieves effective isolation between the through electrodes 23 and avoids device failure caused by glass seeping into the sealed cavity, thus balancing the insulation of electrode isolation and the reliability of cavity sealing.

[0058] Furthermore, a quasi-all-silicon material system was constructed to improve the temperature performance and accuracy of the device. Throughout the packaging process, the MEMS suspended structure 10 and the cover plate structure 20 are both made of silicon, the bonding interface is a silicon-based compatible structure, and the glass is only used as the electrode isolation layer 40 confined within the trench 21. No large amount of dissimilar materials were introduced, which effectively solved the problem of thermal stress mismatch caused by the mismatch of thermal expansion coefficients of dissimilar materials in existing packaging technologies. This significantly improved the temperature performance and temperature linearity of the MEMS device, providing the necessary conditions for the fabrication of high-precision MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.).

[0059] In one embodiment of the present invention, in step S200, the depth-to-width ratio of the trench 21 is A, and the value of A is greater than 20:1.

[0060] Specifically, this embodiment provides an implementation of the depth-to-width ratio of the trench 21. The depth-to-width ratio of the trench 21 is set to A. The value of A is greater than 20:1, which can ensure the key process constraints of packaging reliability and device performance, accurately block glass backflow, avoid device sealing failure, and ensure uniform glass filling, thereby improving electrode isolation reliability.

[0061] In this embodiment, the aspect ratio A of the trench 21 is greater than 20:1, which can synergize with the high-temperature reflow process of the glass in the subsequent step S600. The aspect ratio greater than 20:1 can form a reasonable structural resistance of the trench 21. When the glass melts and reflows at high temperature, it can effectively prevent the molten glass from further penetrating into the sealed cavity of the MEMS suspended structure 10, completely solving the problem of device failure caused by glass penetrating into the sealed cavity, ensuring the sealing performance of the sealed cavity, and providing environmental protection for the normal operation of the MEMS suspended structure 10.

[0062] Furthermore, the trench 21 structure with a depth-to-width ratio greater than 20:1 allows the molten glass to fill smoothly and uniformly into the trench 21 during the reflow process, avoiding insufficient glass filling, gaps, or voids caused by the trench 21 being too deep or too narrow. This ensures the formation of a continuous and dense electrode isolation layer 40 within the trench 21, effectively achieving insulation isolation between the through electrodes 23, preventing electrode short circuits, and improving the electrical performance stability of the packaging structure.

[0063] In one embodiment of the present invention, in step S200, the trench 21 and the electrode pattern are subjected to wet etching or dry etching.

[0064] Specifically, this embodiment provides an implementation method for processing the trench 21 and electrode pattern. Wet etching and dry etching methods can be flexibly selected according to the actual production scenario to adapt to the design requirements of the trench 21 and electrode pattern.

[0065] Furthermore, dry etching has the advantages of high etching precision, good sidewall perpendicularity, and high pattern resolution. It can accurately prepare trench 21 and electrode patterns that meet the size requirements, and is especially suitable for scenarios with high pattern precision requirements, ensuring the effectiveness of subsequent electrode contact and the consistency of the trench 21 structure.

[0066] Furthermore, wet etching has the advantages of simple process, uniform etching rate and low cost, and can realize rapid batch etching of trench 21 and electrode pattern, which is suitable for industrialization scenarios with moderate accuracy requirements and pursuit of production efficiency.

[0067] In other words, the flexible choice between the two etching methods can ensure that the etched trench 21 and electrode pattern meet the process requirements of subsequent direct bonding processes such as silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide, as well as glass reflow, thus ensuring the stability of the packaging structure.

[0068] In one embodiment of the present invention, in step S400, a plurality of trenches 21 are etched on the front side of the cover plate structure 20 by dry etching, wherein at least a portion of the trenches 21 extend to the first bonding layer 13 of the MEMS suspended structure, and at least another portion of the trenches 21 extend to the second bonding layer of the MEMS suspended structure and the cover plate structure 20.

[0069] Specifically, this embodiment provides an implementation method for etching trenches 21 on the cover plate structure 20. Multiple trenches 21 are etched on the front side of the cover plate structure 20 using dry etching, and at least a portion of the trenches 21 are defined to extend to the first bonding layer 13 of the MEMS suspended structure 10, and at least another portion of the trenches 21 extend to the second bonding layer 60 between the MEMS suspended structure 10 and the cover plate structure 20. This is the key to realizing the wafer-level packaging electrode lead-out, structural sealing and functional adaptation of the present invention.

[0070] In this embodiment, at least a portion of the trench 21 extends to the first bonding layer 13 of the MEMS suspended structure 10, enabling the effective extraction of the surface electrodes of the MEMS suspended structure 10 and ensuring reliable contact between the surface electrodes and the subsequently formed through electrodes 23. At least another portion of the trench 21 extends to the second bonding layer 60 of the two structures, enabling the extraction of the deep electrodes or electrodes at the bonding interface of the MEMS suspended structure 10. The combination of the two extension methods can adapt to the extraction requirements of electrodes at different positions and of different types in the MEMS suspended structure 10, solving the problem that a single trench 21 extension method cannot take into account the extraction of electrodes at multiple positions, ensuring that the signals of each electrode of the MEMS device can be stably extracted, and ensuring the normal realization of the device function. The differentiated trench 21 extension design enables the precise extraction of multiple types of electrodes.

[0071] Furthermore, after being dry-etched, the differentiated extended trenches 21 can serve as precise channels for glass reflow. In subsequent steps, molten glass can smoothly fill each trench 21 to form a dense electrode isolation layer 40. At the same time, the trenches 21 extending to different bonding layers can reasonably constrain the glass reflow, preventing excessive diffusion of glass into the sealed chamber. This achieves effective isolation of the through electrodes 23 at different locations and further enhances the sealing performance of the encapsulation structure, taking into account both electrode insulation performance and cavity sealing performance.

[0072] It should be noted that dry etching can achieve gentle and precise etching of the silicon-based cover plate structure 20 without introducing foreign impurities. Furthermore, the differentiated trench 21 extension design only acts on the silicon-based bonding layer and does not damage the quasi-all-silicon material system of the entire packaging structure. This can effectively avoid the thermal expansion mismatch problem caused by the introduction of foreign materials, indirectly ensuring the temperature performance and temperature linearity of MEMS devices, and providing support for the stable operation of high-precision MEMS devices.

[0073] In one embodiment of the present invention, in step S500, the pressure at which the cover plate structure 20 is bonded to the glass anode is B, where B is between 1 Pa and 1000 Pa.

[0074] Specifically, this embodiment provides an implementation method for anodic bonding pressure, which enables reliable bonding between the glass and the cover plate structure 20, ensures the subsequent glass reflow effect and the overall performance of the encapsulation structure.

[0075] In this embodiment, a pressure range of 1 Pa to 1000 Pa allows the glass to be tightly bonded to the surface of the cover plate structure 20 (low-resistivity silicon), effectively eliminating defects such as micro-gaps and bubbles at the bonding interface. This promotes the full anodic bonding reaction between the glass and silicon, forming a strong and dense bonding interface. This not only ensures the connection stability between the glass sealing layer 30 and the cover plate structure 20, but also lays a solid foundation for subsequent glass reflow, electrode isolation, and cavity sealing. It avoids sealing failure caused by loose bonding, ensures the reliability of anodic bonding, and forms a dense sealing interface.

[0076] In one embodiment of the present invention, in step S600, the reflow temperature of the glass is C, where C is between 600 degrees Celsius and 1100 degrees Celsius.

[0077] Specifically, this embodiment provides an implementation method for glass reflow temperature, which enables effective glass reflow, forms a reliable electrode isolation layer 40, and ensures the performance of the packaging structure.

[0078] In this embodiment, the temperature range of 600 degrees Celsius to 1100 degrees Celsius allows the glass to reach a fully molten state, possessing good fluidity. This allows it to flow smoothly into the multiple trenches 21 formed by etching in step S400, thoroughly filling the voids and gaps inside the trenches 21. This avoids problems such as insufficient filling and voids caused by insufficient glass melting and insufficient fluidity, providing a foundation for forming a continuous and reliable electrode isolation layer 40 and ensuring effective insulation between the through electrodes 23.

[0079] In some specific embodiments of the present invention, such as Figures 2 to 8 As shown, this solution provides a wafer-level packaging structure, including: a substrate layer 11; a device layer 12, the device layer 12 having a first surface 121 and a second surface 122, the first surface 121 and the second surface 122 being disposed opposite to each other, the first surface 121 being bonded to the substrate layer 11; a cover plate layer 22, the cover plate layer 22 being bonded to the second surface 122 of the device layer 12 to form a sealed cavity 50, the cover plate layer 22 having a trench 21 for isolating the through electrode 23; a glass sealing layer 30, bonded to the side of the cover plate layer 22 away from the device layer 12; and an electrode isolation layer 40, the electrode isolation layer 40 being disposed in the trench 21.

[0080] It should be noted that, through the collaborative design of substrate layer 11, device layer 12, cover layer 22, glass sealing layer 30 and electrode isolation layer 40, the technical problems existing in the current MEMS wafer-level packaging structure, such as poor sealing reliability, poor electrode isolation effect, obvious material thermal mismatch, and insufficient device precision, are precisely solved. Moreover, the material system of the structure is basically silicon, which can effectively avoid the introduction of other materials in other packaging technology solutions. Different materials have inconsistent thermal properties, and due to thermal stress mismatch, the device's temperature performance is poor and the temperature linearity is low.

[0081] In some possible embodiments, such as Figures 2 to 8 As shown, where, Figure 3 The groove 21 is shown; although it is not directly shown in the other accompanying drawings, it is implied in conjunction with... Figure 3 As can be seen from the relative positions and dimensions of the other figures, the width of the groove 21 varies. The groove 21 on the side closer to the sealing cavity 50, which communicates with the sealing cavity 50, needs to be narrower than the groove 21 on the side closer to the edge to prevent the glass from flowing into the cavity after eutectic melting. The groove 21 on the side closer to the edge is wider than the groove 21 on the side closer to the sealing cavity 50, taking into account the isolation effect.

[0082] In some possible embodiments, the width ratio of the groove 21 near the edge to the groove 21 near the sealing cavity 50 is greater than 2:1.

[0083] In some possible embodiments, the depth of the trench 21 is related to the etching depth of the cover structure 20 and needs to be continuous with the trench 21 etched in the first step. The trench 21 on the side near the sealing cavity 50 should expose the sealing cavity 50, and the trench 21 on the side near the edge should expose the bonded silicon oxide layer.

[0084] In one embodiment of the present invention, it further includes: a first bonding layer 13, which is disposed between the substrate layer 11 and the device layer 12, and the first bonding layer 13 is made of silicon dioxide material.

[0085] Specifically, this embodiment provides an implementation of the first bonding layer 13. By adding a first bonding layer 13 disposed between the substrate layer 11 and the device layer 12, and the first bonding layer 13 being made of silicon dioxide material, it is a key structure for ensuring the stability of the wafer-level packaging structure and improving device performance.

[0086] In this embodiment, the silicon dioxide material has good bonding compatibility and can form a strong and dense bonding interface between the substrate layer 11 and the device layer 12, effectively enhancing the connection strength between the two, avoiding defects such as bond peeling and gaps, preventing delamination failure of the packaging structure, providing a solid connection foundation for the entire wafer-level packaging structure, ensuring the overall stability of the structure, realizing reliable bonding between the substrate layer 11 and the device layer 12, and improving the connection stability of the structure.

[0087] In one embodiment of the present invention, the device layer 12 includes a functional region 123 and a connection region 124; at least a second bonding layer 60 is disposed between the cover plate layer 22 and the connection region 124, the second bonding layer 60 being made of silicon dioxide material.

[0088] Specifically, this embodiment provides an implementation of functional region 123 and connection region 124, defining device layer 12 as including functional region 123 and connection region 124, and providing a second bonding layer 60 of silicon dioxide material between cover layer 22 and connection region 124 of device layer 12, thereby ensuring reliable connection between cover layer 22 and device layer 12, protecting core device functions, and improving packaging performance.

[0089] In this embodiment, the second bonding layer 60 is at least disposed between the connection area 124 of the cover layer 22 and the device layer 12. It can selectively isolate the cover layer 22 and the core functional area 123 of the device layer 12, preventing impurities, defects or stress on the surface of the cover layer 22 from directly acting on the functional area 123 (such as core components such as the MEMS suspended structure 10), preventing the functional area 123 from being scratched, contaminated or damaged by force, ensuring the normal realization of the core functions of the MEMS device, and improving the device's working reliability and service life.

[0090] Furthermore, the silica material has excellent bonding compatibility, and can form a strong and dense bonding interface between the cover plate layer 22 and the connection area 124 of the device layer 12, accurately aligning the connection area 124 of the device layer 12, effectively enhancing the connection strength between the two, avoiding defects such as gaps and peeling at the bonding interface, further reinforcing the sealed cavity 50 formed by the cover plate layer 22 and the device layer 12, improving sealing reliability, and providing a stable closed environment for the core functional structure of MEMS.

[0091] It should be noted that functional region 123 is the electrical connection region, which is in direct contact with the through electrode 23 on the cover structure 20, leading out the electrodes of the MEMS device. Connection region 124 is the bonding region, which is in direct contact with the silicon oxide on the cover, achieving a sealing function through bonding. The surface of functional region 123 and the contact area on the opposite cover structure 20 must expose low-resistivity silicon to ensure sufficient electrical contact. The contact area of ​​connection region 124 and the contact area on the opposite cover structure 20 must be clean and free of particles to ensure good bonding quality and meet the requirements of bonding strength and sealing. The silicon on the cover structure 20 in the contact area with functional region 123 is at the same height as or slightly higher than the silicon dioxide surface, with a height difference between 0 and 50 nm, including both extreme values.

[0092] In one embodiment of the present invention, the substrate layer 11, the device layer 12, the through electrode 23, and the cover plate layer 22 are all made of silicon material.

[0093] Specifically, this embodiment provides an implementation method for the materials used to fabricate the substrate layer 11, device layer 12, through-electrode 23, and cover layer 22. The substrate layer 11, device layer 12, through-electrode 23, and cover layer 22 are all made of silicon. Since all four are made of silicon, they have completely consistent coefficients of thermal expansion. This can fundamentally eliminate the thermal expansion mismatch caused by the introduction of dissimilar materials (such as glass and metal) in existing packaging structures, significantly reduce the thermal stress generated during temperature changes, and avoid problems such as warping, cracking, and bonding interface failure in the packaging structure. This significantly improves the temperature performance and temperature linearity of MEMS devices, providing core material support for the stable operation of high-precision MEMS devices.

[0094] In this embodiment, the silicon materials exhibit excellent bonding compatibility. The substrate layer 11 and device layer 12, as well as the device layer 12 and cover layer 22, can achieve high-quality "silicon-silicon direct bonding". The through electrode 23 can be tightly bonded to the silicon-based structure of device layer 12 and cover layer 22 without interface compatibility issues. This effectively avoids defects such as bond peeling and gaps, significantly improving the connection strength and mechanical stability of the entire packaging structure and extending the device's lifespan.

[0095] In one embodiment of the present invention, the glass sealing layer 30 and the electrode isolation layer 40 are made of glass material.

[0096] Specifically, this embodiment provides an implementation of a glass sealing layer 30 and an electrode isolation layer 40. Both the glass sealing layer 30 and the electrode isolation layer 40 are made of glass material, which can achieve seamless connection and synergistic effect between the two. The glass sealing layer 30 can form an overall sealed protection for the cover plate layer 22, and the electrode isolation layer 40 fills the groove 21 of the cover plate layer 22 to achieve through-electrode isolation of the electrode 23. The compatibility of the same material can avoid defects such as gaps and peeling at the interface between the two, which not only strengthens the overall sealing performance of the encapsulation structure, but also ensures the stability of the electrode isolation, and achieves the unity of sealing and isolation functions.

[0097] In this embodiment, the electrode isolation layer 40 fills the trench 21 to achieve precise isolation and sealing of the through-electrode 23. This is the core function of ensuring the electrical performance of the wafer-level packaging structure and improving the reliability of the device. The electrode isolation layer 40 fills the trench 21 to effectively isolate the through-electrode 23 in the trench 21 from the cover layer 22 (silicon material) and adjacent through-electrode 23. Utilizing its excellent insulation properties, it completely blocks the leakage current path between electrodes and between electrodes and the silicon-based cover layer, preventing electrical faults such as signal crosstalk and electrode short circuits. This ensures that each through-electrode 23 can transmit signals independently and stably, guaranteeing the electrical performance accuracy and normal operation of the MEMS device.

[0098] In one embodiment of the present invention, the trench 21 includes a plurality of trenches; at least a portion of the trenches 21 extends to the first surface 121, and at least another portion of the trenches 21 extends to the second surface 122; wherein the depth-to-width ratio of the trenches 21 is A, and the value of A is greater than 20:1.

[0099] Specifically, this embodiment provides an implementation of a trench 21, which includes multiple trenches, with at least a portion of the trenches 21 extending to the first surface 121 and at least another portion of the trenches 21 extending to the second surface 122. At the same time, the depth-to-width ratio A of the trenches 21 is limited to be greater than 20:1, so as to achieve precise lead-out of multiple electrodes, reliable isolation and sealing, and ensure packaging performance.

[0100] In this embodiment, multiple trenches 21 can correspond to different electrodes of the MEMS device, realizing the synchronous arrangement and lead-out of multiple sets of through electrodes 23. This solves the problem that a single trench 21 cannot meet the lead-out of multiple electrodes. At the same time, multiple trenches 21 can accurately match the electrode layout of different regions of the device layer 12, improve the integration of the packaging structure, adapt to the functional requirements of high-performance, multi-channel MEMS devices, and ensure that the signals of each electrode are transmitted independently and do not interfere with each other.

[0101] Furthermore, at least a portion of the trench 21 extends to the second surface 122, enabling the effective extraction of electrodes corresponding to the second surface 122 (such as surface electrodes of device layer 12), ensuring reliable contact between the surface electrodes and the through electrodes 23; at least another portion of the trench 21 extends to the first surface 121, enabling the precise extraction of electrodes corresponding to the first surface 121 (such as deep electrodes of device layer 12 and electrodes at bonding interfaces). The two extension methods work together to fully cover the electrode extraction requirements at different locations of the MEMS device, avoiding device functional loss due to incomplete electrode extraction, and ensuring the normal realization of the core performance of the device.

[0102] It should also be noted that the aspect ratio A being greater than 20:1 allows for precise control of the glass reflow range, preventing sealing failure. The aspect ratio constraint works synergistically with the subsequent glass reflow process. The trench 21 structure, with an aspect ratio greater than 20:1, can create reasonable flow resistance. When the glass melts and reflows, it can effectively prevent excessive diffusion of the molten glass, avoiding its infiltration into the sealed chamber of the MEMS device. This completely solves the problem of contamination and functional failure of the device's core structure caused by glass infiltration. At the same time, it ensures that the glass can be smoothly filled into the trench 21, providing a guarantee for the formation of the electrode isolation layer 40.

[0103] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "method," "specific method," or "some methods," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or method is included in at least one embodiment or method of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or method. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or methods. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or methods described in this specification, as well as the features of different embodiments or methods.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wafer level packaging method, characterized by, include: Step S100: Provide the MEMS suspended structure and the cover plate structure; Step S200: Grooves and electrode patterns are etched on the bonding surface of the cover plate structure; In step S300, the MEMS suspended structure and the cover plate structure are directly bonded together, and the bonding method is any one of silicon-silicon, silicon-silicon dioxide, and silicon dioxide-silicon dioxide. Step S400: Etching is performed on the front side of the cover plate structure to achieve the penetration of the trench; In step S500, the cover plate structure is bonded to the glass anode to form a glass sealing layer; In step S600, after the glass of the glass sealing layer melts at high temperature, it flows back into the trench and forms an electrode isolation layer that isolates the through electrode in the trench. Step S700: Thinning and polishing the glass sealing layer.

2. The wafer level packaging method of claim 1, wherein, In step S200, the depth-to-width ratio of the trench is A, and the value of A is greater than 20:

1.

3. The wafer level packaging method of claim 1, wherein, In step S200, wet etching or dry etching is used for the trenches and electrode patterns.

4. The wafer level packaging method according to any one of claims 1 to 3, wherein, In step S400, a plurality of trenches are etched on the front side of the cover plate structure using dry etching, wherein at least a portion of the trenches extend to the first bonding layer of the MEMS suspended structure, and at least another portion of the trenches extend to the second bonding layer of the MEMS suspended structure and the cover plate structure.

5. The wafer level packaging method according to any one of claims 1 to 3, wherein, In step S500, the pressure at which the cover plate structure bonds with the glass anode is B, where B is between 1 Pa and 1000 Pa.

6. The wafer level packaging method according to any one of claims 1 to 3, wherein, In step S600, the reflow temperature of the glass is C, which is between 600 degrees Celsius and 1100 degrees Celsius.

7. A wafer level package structure, characterized by, include: Substrate layer; A device layer having a first surface and a second surface disposed opposite to each other, the first surface being bonded to the substrate layer; A cover plate layer is bonded to the second surface of the device layer to form a sealed cavity, and the cover plate layer is provided with grooves for isolating through electrodes; A glass sealing layer is bonded to the side of the cover plate layer away from the device layer; An electrode isolation layer is disposed within the trench.

8. The wafer level package structure of claim 7, wherein, Also includes: A first bonding layer is disposed between the substrate layer and the device layer, and the first bonding layer is made of silicon dioxide material.

9. The wafer-level packaging structure according to claim 7, characterized in that, The device layer includes functional regions and connection regions; At least a second bonding layer is provided between the cover plate layer and the connection area, and the second bonding layer is made of silicon dioxide material.

10. The wafer-level packaging structure according to any one of claims 7 to 9, characterized in that, The substrate layer, the device layer, the through electrode, and the cover plate layer are all made of silicon.

11. The wafer-level packaging structure according to any one of claims 7 to 9, characterized in that, The glass sealing layer and the electrode isolation layer are made of glass material.

12. The wafer-level packaging structure according to any one of claims 7 to 9, characterized in that, The trench includes multiple trenches; At least a portion of the trenches extend to the first surface and at least another portion of the trenches extend to the second surface. The aspect ratio of the trenches is A, and A has a value greater than 20:1.

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