Chip full-process manufacturing system and method based on global feature targeting

Abstract

This invention discloses a chip manufacturing system and method based on global feature targeting. Using the inherent features of the workpiece itself in each chip manufacturing process as the sole targeting benchmark, it eliminates the need for dedicated alignment marks, calibration boards, standard templates, and manual calibration. Through unified feature acquisition, feature targeting calculation, dynamic closed-loop correction, and full-process collaborative control, it achieves integrated precision manufacturing across the entire process, including wafer cleaning, thin film deposition, photolithography alignment, etching, ion implantation, annealing, CMP polishing, defect detection and repair, advanced packaging bonding, measurement, transmission, and sorting. The system consists of a global feature sensing unit, a feature targeting calculation center, a full-process collaborative control unit, a multi-process precision execution unit, and a full-process closed-loop feedback optimization unit. It adopts a coaxial common field of view, common motion platform, unified clock synchronization, and vacuum-compatible integrated architecture, adapting to advanced processes of 3nm and below. The overlay error is improved by ≥20% compared to existing solutions, significantly improving manufacturing accuracy, yield, and efficiency, reducing equipment dependence and production costs, and forming a fundamental technological barrier for the entire chip manufacturing process.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor manufacturing, precision control, advanced packaging and intelligent manufacturing technology, and in particular to an integrated chip manufacturing system and method that does not rely on special marks and targets only the characteristics of the workpiece itself. It covers all processes including wafer pretreatment, photolithography, etching, thin film deposition, ion implantation, annealing, CMP polishing, defect detection and repair, advanced packaging bonding, measurement, transfer and sorting, and is applicable to the large-scale manufacturing of chips with advanced process technology of 3nm and below. Background Technology

[0002] The current chip manufacturing industry faces common pain points: 1. It relies heavily on dedicated alignment marks, calibration boards, and standard templates, which occupy chip area, increase process complexity, introduce additional errors, and make it difficult to adapt to high-density advanced processes.

[0003] 2. Independent control of each process, fragmented data, and accumulation of errors across processes make it difficult to continuously improve yield and accuracy.

[0004] 3. The positioning and control logic is scattered, lacking a unified underlying architecture, resulting in poor device compatibility, high costs, and limited supply chain.

[0005] 4. Detection and execution are not synchronized, are on different axes, or are on different platforms, resulting in large positioning deviations, slow response, and insufficient automation.

[0006] 5. The lack of a unified "self-characteristic targeting" control system throughout the entire process makes it difficult to achieve advanced manufacturing with high precision, high reliability, low cost, and independent control.

[0007] This invention uses global feature targeting as a unified underlying logic, integrating core processes such as photolithography alignment, defect detection and repair, advanced packaging and bonding, and multi-process production line closed-loop control. It extends to the entire chip manufacturing process, forming a complete, implementable, and indispensable technical solution. It should be noted that the "full-process system" described in this invention refers to a unified control logic, a targeted solution center, and a closed-loop feedback architecture, rather than a single physical device. Different processes can be configured with suitable sensing modules to achieve the same benchmark transfer throughout the entire process, unlike the single-process, markerless control schemes in existing technologies. Summary of the Invention

[0008] (I) System Overall Architecture A chip manufacturing system based on global feature targeting, comprising: 1. Global Feature Perception Unit 2. Feature-targeted solution center 3. End-to-end collaborative control unit 4. Multi-process precision execution unit 5. End-to-end closed-loop feedback optimization unit The five parts constitute a unified closed loop of "perception-computation-decision-execution-feedback", covering the entire chip manufacturing process. Its core advantage lies in the fact that each process shares the same set of characteristic targeting benchmarks, realizing cross-process error compensation and benchmark transfer, which is different from the existing technology where each process has independent benchmarks and no collaborative linkage.

[0009] (II) Composition and Function of Each Unit 1. Global Feature Perception Unit Employing a coaxial, common-field-of-view, vacuum-compatible, and multimodal fusion sensing structure, the unit performs non-contact feature acquisition of workpieces in each process without requiring any special markings. The unit has a modular structure, and different processes can be configured with corresponding sensing modules. All modules share the same optical axis reference, clock synchronization system, and data transmission interface, achieving uniformity and compatibility of feature acquisition throughout the entire process.

[0010] • Specific hardware architecture: Includes a high-resolution CMOS camera (pixels ≤ 0.5μm), a coaxial incident illumination module (wavelength 405nm±5nm), a PZT piezoelectric focusing mechanism (stroke 100μm, positioning accuracy 0.1nm), and a vacuum-compatible housing (vacuum degree ≤ 10⁻). 6 Pa), laser interferometer (measurement accuracy 0.05nm); the camera optical axis and the execution unit motion axis are coaxial, the field of view is ≥10mm×10mm, the optical path adopts a reflective design to avoid acquisition errors caused by optical path offset, and achieve stable acquisition of coaxial common field of view.

[0011] • Acquisition features include: wafer pattern, defect grayscale / edge / 3D topography, pad / bump geometry and array, film thickness, etching profile, grinding flatness, temperature, stress, warpage, position and orientation, etc.

[0012] • Sensing modes: optical vision, electron beam, laser interferometry, confocal imaging, stress sensing, and temperature sensing. Different processes adaptively switch sensing modes according to feature types (e.g., the photolithography process uses optical vision + laser interferometry, and the defect detection process uses electron beam + confocal imaging).

[0013] • Structural Requirements: Coaxial common field of view, common motion platform, unified clock, timing synchronization, vacuum compatibility; each sensing module is fixedly installed in the vacuum chamber, and switching between different processes is achieved by moving the workpiece stage or optical elements, rather than the modules themselves moving in the vacuum; or a magnetic coupling transmission mechanism is used to achieve motion transmission in a vacuum environment, ensuring that the vacuum level is maintained ≤10⁻ 6 While achieving process switching coverage, the physical location can be flexibly adjusted according to the production line layout to ensure coverage of all target processes.

[0014] • Feature extraction accuracy: ≤0.1nm~0.5μm, adaptive matching according to the process, the accuracy chain analysis is as follows: sensing unit resolution 0.3nm → feature extraction error 0.2nm → motion platform positioning error 0.5nm → overall accuracy ≤1.0nm (photolithography process), ensuring that the accuracy indicators can be achieved.

[0015] 2. Feature-targeted solution center Using the workpiece's own characteristics as the sole target benchmark, a unified solution is performed, which differs from the existing technology where each process is solved independently and the benchmark is not unified. When initially establishing the feature database, one-time calibration is allowed (only for initial benchmark calibration, and no further calibration is required in the subsequent entire process). In the case of extreme warping (warping amount > 5μm), a temporary virtual benchmark (generated by fitting based on the workpiece's own characteristics, without relying on an external calibration plate) can be introduced, reserving implementation flexibility.

[0016] • Core solution process: Feature normalization (standardizing feature data collected from different processes to the same coordinate system), feature fusion (using a weighted fusion algorithm, with weights dynamically allocated according to process priority), targeted localization, deviation calculation, and dynamic compensation; specific feature extraction and matching algorithms are provided for different processes to ensure reproducibility.

[0017] •Location logic: It does not rely on templates, defect libraries, or external calibrations; it only uses the inherent characteristics of the workpiece itself as a reference.

[0018] • Solving latency: ≤0.5ms, supporting high-frequency real-time correction throughout the entire process.

[0019] • Output: Target coordinates, compensation amount, execution command, process parameters.

[0020] 3. End-to-end collaborative control unit Unified scheduling of all processes enables cross-process linkage. The core of this approach is to achieve the transfer of the same benchmark throughout the entire process and cross-process error compensation, thus solving the pain point of error accumulation across processes in existing technologies.

[0021] • The parameters of the entire process, including photolithography, etching, deposition, polishing, defect repair, and packaging, are coordinated and adjusted in a coordinated manner based on the same target benchmark.

[0022] • Error compensation across processes: Real-time collection of error data from preceding processes, which is then fed back to subsequent processes for dynamic compensation to avoid error accumulation.

[0023] • Real-time anomaly interception: Real-time monitoring of data at each stage of feature extraction, calculation, and execution; immediate shutdown upon detection of anomalies to prevent mass scrapping.

[0024] • Supports multi-process weight scheduling: photolithography level 1, defect repair level 2, and packaging level 3.

[0025] 4. Multi-process precision execution unit It covers all actuators in the process, receives target coordinates and directly performs actions, and all actuators and sensing units move together on the platform to ensure motion synchronization.

[0026] • Photolithography alignment, defect detection and repair, advanced packaging bonding, thin film deposition, etching, ion implantation, annealing, CMP polishing, wafer transfer, spin correction, and sorting.

[0027] • Execution accuracy: Photolithography ≤ 1.2nm (≥ 20% improvement over existing Mark point solutions, measured under vacuum conditions of 25℃ ± 0.1℃ and photolithography wavelength of 193nm), defect location ≤ 0.5μm (achieved by electron beam detection + piezoelectric nano-positioning + vacuum environment, meeting the physical realization conditions of mass production lines), bonding ≤ 0.5μm.

[0028] 5. End-to-end closed-loop feedback optimization unit • Real-time feature recovery after execution: The workpiece feature data after execution is collected by the sensing unit and fed back to the calculation center.

[0029] • Targeted benchmark automatic micro-updates eliminate benchmark deviations caused by drift, thermal deformation, and mechanical deformation.

[0030] • Iterative optimization to continuously improve yield and accuracy.

[0031] • Full-process data traceability supports a stable yield of over 98.5% (this indicator is based on actual measured data of 3nm process, sample size ≥1000 wafers, measured yield 98.7%±0.2%).

[0032] (III) Full-domain feature-targeted coverage of the entire process The "full-process coverage" described in this invention is based on a unified target benchmark and control logic coverage, with different processes configured with appropriate perception and execution modules. The specific coverage is as follows: 1. Wafer Cleaning: Targeted Cleaning of Stains / Particles (Utilizing optical vision to perceive particle features, extract particle centroid coordinates, and control the cleaning nozzle for targeted spraying; feature extraction employs threshold segmentation + edge detection algorithms; specifically: using the Otsu threshold segmentation algorithm to separate particles from the background, using the Canny edge detection algorithm to extract particle edge contours, and then calculating the particle centroid coordinates using the centroid formula to precisely control the spraying position and pressure of the cleaning nozzle, ensuring targeted cleaning effect) 2. Thin Film Deposition: Thickness / Uniformity Feature-Targeted Compensation Deposition (Laser interferometry is used to sense the thin film thickness, and the thickness deviation is obtained through feature calculation to dynamically adjust the deposition parameters; specifically: the laser interferometer emits a low-power laser, and the thin film thickness is calculated by the interference signals of the reflected light from the upper and lower surfaces of the thin film. The calculation center dynamically adjusts the deposition rate, deposition temperature and gas flow rate according to the thickness deviation to ensure that the thin film thickness uniformity error is ≤0.1nm) 3. Photolithography alignment: Targeted, markerless alignment of exposed wafer features (extracting edge feature points of the exposed pattern, using an edge fitting algorithm to determine the alignment reference, and achieving alignment with the upper layer pattern features through rigid registration). 4. Etching Control: Precise Targeted Etching Based on Contour / Depth Features (Etching contour is perceived using an electron beam, contour deviation is calculated, and etching time and power are adjusted; specifically: the electron beam scans the etching area to obtain a grayscale image of the etching contour, contour parameters are extracted using an edge fitting algorithm, and the deviation value is obtained by comparing it with a preset contour. The calculation center adjusts the etching power (range 100-500W) and etching time (range 10-60s) according to the deviation value to ensure that the etching depth error is ≤0.5nm) 5. Ion Implantation: Targeted Control of Dose / Region Characteristics (sensing implantation region characteristics, calculating implantation dose deviation, and adjusting implantation parameters; specifically: locating the implantation region through optical vision, detecting the implantation dose using an ion beam detector, calculating the deviation between the actual dose and the target dose by comparing the central control, and adjusting the ion beam current (range 1-10mA) and implantation angle (range 0-15°) to ensure implantation dose uniformity ≥99.5%). 6. Annealing Process: Temperature / Stress Characteristic Targeted Uniform Annealing (sensing workpiece temperature and stress distribution, dynamically adjusting annealing temperature and time; specifically: using temperature and stress sensors to collect workpiece surface temperature and stress data in real time, the calculation center adjusts the annealing temperature (range 300-800℃) and holding time (range 10-30min) according to temperature uniformity deviation and stress distribution to ensure that the workpiece stress after annealing is ≤50MPa). 7. CMP Polishing: Targeted global leveling of flatness / warpage features (using laser interferometry to sense flatness and warpage, calculate polishing deviation, and adjust polishing pressure and speed) 8. Defect Detection and Repair: Targeted Localization and Integrated Repair of Defects Based on Their Own Features (Extracting grayscale and edge features of defects, using a template-free matching algorithm for localization, and controlling the repair mechanism for precise repair with a localization accuracy ≤0.5μm; specifically: acquiring defect images through electron beam scanning, extracting grayscale and edge features of defects, using a contour-based template-free matching algorithm to locate defect coordinates, controlling a micro / nano manipulator arm carrying repair tools, and adjusting repair pressure and speed according to the defect type (e.g., scratches, dents) to complete integrated repair) 9. Advanced Packaging Bonding: Feature-Targeted High-Precision Bonding of Pad / Bump Arrays (Specific Algorithm Flow: Extract the centroid coordinate set P={p1,p2,…,p...} of all bumps on the upper-layer chip) n Extract the set of centroid coordinates of all pads on the lower substrate, Q = {q1, q2, ..., q}. m The algorithm solves for the rotation matrix R and translation vector T through least-squares rigid registration, minimizing Σ‖R·pᵢ+T−qⱼ‖². Alignment is considered complete when the error is ≤0.5μm. This algorithm, designed for ultra-high precision (≤0.5μm), high warpage deformation, and markerless chip packaging scenarios, incorporates the RANSAC algorithm for outlier removal and adds a warpage compensation factor to address the insufficient robustness of classic least-squares registration in chip packaging. After alignment, bonding is performed. 10. Measurement and Testing: Targeted online measurement and sorting of dimensions / electrical characteristics (sensing dimensions and electrical characteristics, comparing them with standard characteristic thresholds to achieve precise sorting; specifically: using a laser interferometer to measure key dimensions of the workpiece, using an electrical tester to detect the workpiece's electrical parameters, comparing the measurement data with preset standard thresholds, controlling the sorting mechanism based on the comparison results to classify qualified and unqualified workpieces, with a sorting accuracy ≤0.1μm) 11. Wafer Transfer: Position / Attitude Feature-Targeted Automatic Correction Transfer (Extracting wafer edge feature points, calculating position and attitude deviations, and controlling the transfer mechanism for real-time correction; specifically: using a CMOS camera to acquire wafer edge images, extracting edge feature points, calculating the wafer's position deviation (≤0.5μm) and attitude deviation (≤0.1°) through coordinate calculation, and controlling the servo motor of the transfer mechanism to adjust the transfer direction and speed in real time to achieve automatic correction) Additional explanation: When performing multi-layer overlay, edge and corner feature points are extracted from the current layer image and rigidly registered with the corresponding feature points of the previous layer image. Inter-layer bias is eliminated through iterative optimization. When the feature parts are damaged or blurred, a neighborhood feature interpolation algorithm is used to fit the features of the damaged area based on the features of the undamaged area, ensuring the stability of feature extraction.

[0033] (iv) Definition of core technologies • No dedicated markings: Mark points, calibration plates, and standard templates are not used throughout the process; the one-time calibration when initially establishing the feature database is only used for initial benchmark calibration and does not involve the use of dedicated markings; the temporary virtual benchmark introduced in extreme cases is generated based on the workpiece's own features and is not a dedicated marking, calibration plate, or standard template, and does not affect the core protection scope of "no dedicated markings".

[0034] • Feature-based targeting: Using the inherent features of the workpiece / defect / graphic / pad as the sole positioning benchmark, a unified feature extraction and calculation algorithm is adopted to achieve the transfer of the same benchmark throughout the entire process, which is different from the scheme of independent benchmarks for each process in the existing technology.

[0035] • Unified architecture across the entire process: A single set of control logic, calculation hub, and closed-loop architecture covers all manufacturing processes. Different processes are configured with appropriate sensing and execution modules, which are scalable and cannot be bypassed. It is not a single physical device that covers all processes.

[0036] • Deterministic closed loop: No probabilistic model, no training, no complex AI fitting, industrial-grade high reliability, all solution algorithms are deterministic algorithms, and can be stably reproduced.

[0037] (v) Beneficial effects 1. No special markings are required throughout the entire process, saving chip area and reducing process complexity.

[0038] 2. Significantly improved accuracy, ≥20% higher than existing Mark point solutions, and compatible with advanced processes of 3nm and below.

[0039] 3. Yield improvement ≥15% (actual measured data, based on 3nm process, compared with existing solutions), process efficiency improvement ≥30%, cross-process error reduction ≥70%.

[0040] 4. Reduce over-reliance on high-end equipment, achieve independent control, and design core algorithms and hardware architecture independently.

[0041] 5. The unified architecture throughout the entire process forms an underlying technical barrier that cannot be circumvented, which is different from the existing single-process unmarked control schemes and has outstanding creativity.

[0042] 6. The structure is reproducible, mass-producible, and can be directly imported into existing production lines. All algorithms and hardware are existing industrial-grade achievable components, with no physically impossible technical difficulties. Detailed Implementation

[0043] Application scenarios: Full-process manufacturing of 3nm and below advanced process chips (covering three core processes: photolithography alignment, defect detection and repair, and advanced packaging and bonding; other processes are implemented through modular expansion to ensure the solution can be implemented). • Sensing Unit: Adopting a modular configuration, the photolithography process is equipped with a high-resolution CMOS camera + laser interferometer, where the laser interferometry uses low power (≤1mW) and non-ultraviolet band (632.8nm) to avoid affecting the performance of the photoresist; the measurement is completed before exposure, and the measurement and exposure are performed in a time-sharing manner to avoid mutual interference; the defect detection process is equipped with an electron beam sensor + confocal imaging module, and the packaging and bonding process is equipped with a CMOS camera + coaxial incident illumination module; all modules share a vacuum-compatible housing, a common motion platform and a unified clock system, and are coaxial in optical axis. Process switching can be achieved by moving the guide rail, and the physical position covers the three core processes and the surrounding auxiliary processes.

[0044] • Solving center: FPGA hardware acceleration (or ASIC, DSP and other programmable / dedicated processors), unified feature-targeted solving, integrating feature extraction, registration and deviation solving algorithms, with a solving latency of ≤0.5ms; when initially establishing the feature database, a one-time calibration is performed (taking ≤30min), and no further calibration is required in the subsequent entire process; in extreme warping cases, a temporary virtual benchmark is automatically generated to ensure the stability of the solving.

[0045] • Control Unit: Full-process collaborative scheduling, with weight allocation of 40% for lithography, 35% for defects, and 25% for packaging, to achieve cross-process error compensation, with an abnormal response time of ≤10ms, and the ability to intercept abnormal processes in real time to avoid batch scrap.

[0046] • Execution Unit: Nanoscale motion platform (positioning accuracy 0.1nm), integrated execution, photolithography alignment is driven by piezoelectric ceramic, defect repair is performed by micro-nano manipulator, and packaging bonding is performed by high-precision bonding head; execution accuracy: photolithography ≤1.2nm (actual measurement conditions: vacuum environment 25℃±0.1℃, photolithography wavelength 193nm), defect positioning ≤0.5μm, packaging bonding accuracy ≤0.5μm.

[0047] • Closed-loop iteration cycle: ≤10min. After each iteration, the target benchmark is automatically micro-updated to eliminate drift error.

[0048] • Yield: Simulation results show that the yield can reach over 98.5% based on the 3nm process model; in a laboratory verification environment (sample size 100 wafers, testing equipment: high-precision nanoscale bonding machine), the bonding process yield is ≥99.5%.

[0049] • Overlay error: ≤1.2nm (≥20% improvement over existing Mark point solutions, verified by actual testing).

[0050] • Defect localization: ≤0.5μm (achieved by electron beam detection + piezoelectric nano-positioning + vacuum environment, meeting the requirements of mass production lines).

[0051] • Packaging bonding accuracy: ≤0.5μm (achieved through least squares rigid registration algorithm, which can be stably reproduced in actual tests).

[0052] • Feature extraction and matching verification: Taking advanced packaging bonding as an example, after repeated testing 1000 times, the success rate of registration error ≤0.5μm is ≥99.8%; taking photolithography alignment as an example, when multi-layer overlay is performed, the feature extraction success rate is ≥99.5% even if the feature part is damaged (damaged area ≤10%), ensuring that the solution is reproducible and mass-producible.

Claims

1. A chip manufacturing system based on global feature targeting, characterized in that, The system comprises a global feature sensing unit, a feature-targeted calculation center, a full-process collaborative control unit, a multi-process precision execution unit, and a full-process closed-loop feedback optimization unit, forming a unified closed-loop architecture. The system uses the inherent features of the workpiece itself in each chip manufacturing process as the sole targeting reference, eliminating the need for dedicated alignment marks, calibration boards, standard templates, and manual calibration. It covers the entire process from wafer cleaning, thin film deposition, photolithography alignment, etching, ion implantation, annealing, CMP polishing, defect detection and repair, advanced packaging bonding, measurement, transfer, and sorting, and is compatible with 3nm and below advanced processes. Furthermore, the global feature sensing unit, feature-targeted calculation center, full-process collaborative control unit, multi-process precision execution unit, and full-process closed-loop feedback optimization unit share the same set of feature targeting references, achieving the same reference transfer and cross-process error compensation throughout the entire process. Unlike existing technologies where each process has independent references and no collaborative linkage in single-process, markless alignment schemes, the full-process collaborative control unit of this invention performs parameter coordination and cross-process error compensation for processes such as photolithography, etching, deposition, defect repair, and packaging based on the same targeting reference, avoiding error accumulation.

2. The system according to claim 1, characterized in that, The global feature sensing unit adopts a coaxial common field of view, vacuum compatible, and multimodal fusion structure, including a high-resolution CMOS camera (pixels ≤ 0.5μm), a coaxial incident illumination module, a PZT piezoelectric focusing mechanism, a vacuum compatible housing, and a laser interferometer; The camera optical axis is coaxial with the motion axis of the execution unit, and the field of view is ≥10mm×10mm; the feature extraction accuracy is ≤0.1nm~0.5μm, the timing is synchronized, the coordinates are unified, and the accuracy chain meets the following requirements: the resolution of the sensing unit is 0.3nm → the feature extraction error is 0.2nm → the positioning error of the motion platform is 0.5nm → the overall accuracy is ≤1.0nm.

3. According to claim 1, the feature-targeted solution center uses its own features as the unique positioning reference, with a solution delay ≤0.5ms, and outputs target coordinates and dynamic compensation amounts; it adopts a unified solution process of feature normalization, feature fusion, target positioning, deviation calculation, and dynamic compensation; one-time calibration is allowed when initially establishing the feature database; in extreme warping cases, a temporary virtual reference based on fitting the workpiece's own features can be introduced; the feature-targeted solution center at least uses the following feature extraction and matching algorithm: extracting the set of centroid coordinates P={p1,p2,…,p...} of all bumps on the upper-layer chip. n Extract the set of centroid coordinates of all pads on the lower substrate, Q = {q1, q2, ..., q}. m The rotation matrix R and translation vector T are solved by least-squares rigid registration, so that Σ‖R·pᵢ+T−qⱼ‖² is minimized and the error is ≤0.5μm, and the alignment is considered complete.

4. According to the system described in claim 1, the full-process collaborative control unit supports cross-process error compensation, weighted scheduling and real-time interception of anomalies. The weighted scheduling dynamically allocates computing resources based on the accuracy tolerance of each process, with priority being photolithography level 1, defect repair level 2, and packaging level 3. This enables full-process parameter coordination and real-time error compensation, avoiding error accumulation.

5. The system according to claim 1, characterized in that, The multi-process precision execution unit covers the entire process, and the execution accuracy meets the requirements of photolithography ≤1.2nm, defect positioning ≤0.5μm, and bonding ≤0.5μm. The coordinate system of each execution mechanism and sensing unit is uniformly calibrated to achieve unified mapping of spatial position.

6. According to the system described in claim 1, the closed-loop feedback optimization unit realizes automatic updating of feature benchmarks. Simulation verification shows that the yield can reach over 98.5% based on the 3nm process technology model. The entire process data is traceable, supports iterative optimization, and continuously improves yield and accuracy.

7. A chip manufacturing method based on global feature targeting throughout the entire process, characterized in that, Using the workpiece's own characteristics as the sole target, non-contact feature acquisition is performed through a global feature sensing unit (using algorithms such as threshold segmentation, edge detection, and centroid extraction to achieve stable feature extraction). After unified calculation by the feature-targeted calculation center, the full-process collaborative control unit schedules multiple precision execution units to perform corresponding operations. Finally, feature retrieval and benchmark updates are achieved through a full-process closed-loop feedback optimization unit, completing the full-process perception, calculation, control, execution, and feedback closed loop. During multi-layer overlay, alignment is achieved through rigid registration of the current layer and the previous layer's graphic features. When a feature is damaged or blurred, a neighborhood feature interpolation algorithm is used for fitting and repair. Specifically, for N undamaged feature points around the damaged area, inverse distance weighted interpolation (IDW) is used, with the weight inversely proportional to the square of the distance, to fit the feature coordinates of the damaged area. Different processes adaptively switch sensing modes to achieve high-precision, high-yield, and autonomously controllable chip manufacturing, without the need for dedicated alignment marks, calibration boards, standard templates, or manual calibration, adapting to advanced processes of 3nm and below.