Method for manufacturing a heteroepitaxial wafer

Abstract

This invention discloses a method for manufacturing a heteroepitaxial wafer, which is a method for epitaxially growing a 3C-SiC single crystal film on a single crystal silicon substrate. The method is characterized by the following steps: preparing a single crystal silicon substrate with a (111) orientation; removing the natural oxide film on the surface of the single crystal silicon substrate using a flash lamp device and hydrogen calcination; and supplying a source gas containing carbon and silicon to the flash lamp device to grow SiC single crystals on the surface of the single crystal silicon substrate. The natural oxide film removal step involves preheating at 300°C to 600°C and then performing hydrogen calcination at 900°C to 1350°C. The SiC single crystal growth step involves preheating at 300°C to 600°C and then performing SiC nucleation at 900°C to 1350°C. Therefore, a method for manufacturing a heteroepitaxial wafer is provided, which efficiently epitaxially grows a high-quality 3C-SiC single crystal film on a single crystal silicon substrate.

Description

Technical Field

[0001] This invention relates to a method for manufacturing heteroepitaxial wafers. Background Technology

[0002] SiC (silicon carbide) is a material with a wide band gap of 2.2 to 3.3 eV, which gives it high insulation breaking strength and high thermal conductivity. Therefore, it is expected to be used as a semiconductor material for various semiconductor devices such as power devices and high-frequency devices.

[0003] In addition, efforts are being made to utilize it as a platform for gallium nitride (GaN) growth (e.g., Patent Document 1 and Non-Patent Document 1). However, SiC wafers are mainly small-diameter, and are used for power devices and high-frequency devices. The goal is to increase the diameter. If a high-quality 3C-SiC single crystal film can be formed on a large-diameter substrate, it will become possible to fabricate large-diameter heteroepitaxial wafers with a high-quality GaN layer, in addition to using the 3C-SiC single crystal film itself.

[0004] Therefore, as a method for achieving this large-aperture growth, epitaxial growth on silicon (hereinafter also referred to as Si) substrates with good integration with device fabrication processes has been explored (for example, Patent Documents 1 and 2). These patent documents disclose the ability to grow 3C-SiC single crystal films on silicon substrates, and, depending on the type of reactor, the ability to grow 3C-SiC single crystal films on large-aperture substrates such as substrates with a diameter of 300 mm. The formation of 3C-SiC single crystal films in these patent documents is characterized by introducing two raw material gases, one containing a carbon source precursor and the other containing a silicon source precursor, together with a carrier gas into a reactor, and subjecting them to high-temperature treatment (~1200°C) or a combination of high-temperature treatment and plasma treatment to decompose these raw material gases for growth.

[0005] Furthermore, as an example of growing a 3C-SiC single crystal film on a silicon substrate, Patent Document 3 discloses using a single crystal silicon substrate with a planar orientation (110) to further reduce the lattice mismatch between silicon and SiC. While this is advantageous in terms of lattice mismatch, it is not desirable to limit the planar orientation to (110) when considering the fabrication of heteroepitaxial wafers. In addition, the formation of a 3C-SiC single crystal layer containing hydrogen is also disclosed, but it is anticipated that hydrogen will easily escape during the heating process in the epitaxial growth sequence, thus conditions independent of the amount of hydrogen are desired.

[0006] Furthermore, although Patent Document 4 mentions the deviation angle of the single-crystal silicon substrate, it involves carbonization with propane followed by growth with propane and silane gas, resulting in a wide variety of raw material gases that are not conducive to epitaxial growth.

[0007] Additionally, Patent Document 5 discloses a method that uses monomethylsilane as a raw material gas to grow a 3C-SiC single crystal layer on a single crystal silicon substrate with a face orientation of (111) and a diameter of less than 8 inches. However, the film formation conditions in this case involve maintaining a pressure of 2 × 10⁻⁶ within the chamber for 5 to 12 hours after the temperature of the single crystal silicon substrate reaches 1050–1100°C. -4 ~3×10 -4 The formation of 3C-SiC single crystal layers is carried out under conditions of Torr (0.02~0.03 Pa). However, due to the extremely low pressure conditions, the formation rate is slow.

[0008] Thus, although various formation methods have been developed and proposed, considering the lattice constants of silicon and SiC, it is preferable to use a Si(111) substrate (the lattice constant of Si(111) is 3.84 Å, close to the lattice constant of 3C-SiC, which is 4.36 Å). However, even if Si(111) is used with consideration of the lattice constant as in the past and the growth conditions are further designed, there are still problems in improving the crystallinity of 3C-SiC single crystal films. Existing technical documents Patent documents

[0009] Patent Document 1: Japanese Patent Publication No. 2018-522412 Patent Document 2: Japanese Patent Application Publication No. 2021-20819 Patent Document 3: Japanese Patent Application Publication No. 2006-253617 Patent Document 4: Japanese Patent Application Publication No. 2008-184361 Patent Document 5: Japanese Patent Application Publication No. 2017-39622 Non-patent literature

[0010] Non-patent literature 1: Japanese Journal of Applied Physics 53, 05FL09 (2014) Non-patent literature 2: Journal of the Japan Society for Crystallization Growth, Vol. 43, No.4, 213 (2016) Summary of the Invention The technical problem that the invention aims to solve

[0011] As a result of a more detailed investigation into the previously unconsidered surface structure of Si substrates, it was found that a narrow temperature band around 860°C on the Si(111) substrate surface induces a phase transition (Non-Patent Document 2). Enclosing this temperature band, the structure changes to a 7×7 structure at low temperatures and a 1×1 structure at high temperatures. Therefore, increasing the temperature causes a change in the surface structure, making it difficult to form a beautiful 3C-SiC / Si interface. Of course, growth at low temperatures up to the initiation of the phase transition was also considered, but due to the low surface energy, it would result in island-like growth. Thus, the unique problems of the Si(111) surface become an obstacle to the growth of 3C-SiC single crystal films.

[0012] Furthermore, compared to Si(111), Si(110) requires lower temperatures and is more prone to developing various surface structures, making it difficult to use as a substrate. Moreover, while Si(100) does not exhibit this phase transition (more precisely, although reports indicate 4×4 structures, its behavior under high vacuum is problematic), it is disadvantageous in terms of its lattice constant (5.4 Å, significantly higher than the 4.36 Å lattice constant of 3C-SiC / Si).

[0013] This invention was made to solve the above-mentioned problems, and its purpose is to provide a method for manufacturing heteroepitaxial wafers, which efficiently epitaxially grows high-quality 3C-SiC single crystal films on single crystal silicon substrates. Technical means to solve the problem

[0014] To solve the above problems, the method for manufacturing a heteroepitaxial wafer of the present invention is a method for manufacturing a heteroepitaxial wafer by epitaxially growing a 3C-SiC single crystal film on a single crystal silicon substrate. The method for manufacturing a heteroepitaxial wafer includes the following steps: a step of preparing a single crystal silicon substrate with a plane orientation of (111); a step of removing the natural oxide film on the surface of the single crystal silicon substrate by using a flash lamp device and calcining with hydrogen; a step of supplying a source gas containing carbon and silicon into the flash lamp device to grow SiC single crystals on the surface of the single crystal silicon substrate; the step of removing the natural oxide film is performed by preheating at 300°C or higher and 600°C or lower, followed by calcining with hydrogen at 900°C or higher and 1350°C; the step of growing SiC single crystals is performed by preheating at 300°C or higher and 600°C or lower, followed by SiC nucleation at 900°C or higher and 1350°C or lower.

[0015] If this heteroepitaxial wafer manufacturing method is used, SiC single crystals can be reliably formed by removing the natural oxide film on the surface of the single-crystal silicon substrate and then growing SiC single crystals. In addition, since a flash lamp device is used, it can be started up quickly and the temperature can be controlled in a short time, and it can be used for large-diameter substrates. Furthermore, the natural oxide film removal process is carried out by preheating at 300°C to 600°C and then calcining with hydrogen at 900°C to 1350°C. The SiC single crystal growth process is carried out by preheating at 300°C to 600°C and then forming SiC nuclei at 900°C to 1350°C. Both processes are preheated at temperatures between 300°C and 600°C, which is a temperature sufficiently lower than the phase transition temperature of Si (111) of 860°C. Therefore, a phase transition can be avoided during preheating. Furthermore, the movement from the temperature zone above 300°C and below 600°C to the temperature zone above 900°C and below 1350°C can be achieved in a short time using a flash lamp device. Therefore, it can be controlled to pass through the phase transition temperature in a very short time, and almost no phase transition is triggered during the movement of the temperature zone.

[0016] As described above, a simple manufacturing process can suppress the phase transition of a single-crystal silicon substrate, thereby efficiently manufacturing heteroepitaxial wafers with high-quality 3C-SiC single-crystal films.

[0017] In addition, it is preferable to set the hydrogen roasting time at 900°C or higher and 1350°C or lower to 10 milliseconds or higher and 100 milliseconds or lower, and the SiC nucleus formation time at 900°C or higher and 1350°C or lower to 1 millisecond or higher and 20 milliseconds or lower.

[0018] With this timeframe, it is possible to minimize the time required for both hydrogen calcination to remove the native oxide film and nucleation formation for growing SiC single crystals. By shortening the dwell time in the temperature band higher than the Si(111) phase transition temperature of 860°C, phase transitions during dwell can be suppressed significantly. Furthermore, the shorter the dwell time, the faster the temperature drops after heating, thus controlling the process so that phase transitions are hardly triggered even when the temperature drops. Moreover, by shortening both the dwell time and the temperature change time, the manufacturing time can be reduced, enabling efficient fabrication of heteroepitaxial wafers with 3C-SiC single crystal films.

[0019] In addition, it is preferable to use at least one of monomethylsilane and trimethylsilane as the source gas.

[0020] If the raw material gas is such, it is a gas containing both Si and C, which are the raw materials for SiC, so that both Si and C can be supplied as a single gas. Therefore, the previously used carbonization process before the growth of 3C-SiC single crystal film is eliminated, which is the process of forming nuclei by attaching carbon atoms to the surface of the single crystal silicon substrate through a gas containing carbon source precursors. Thus, 3C-SiC single crystal film can be formed in a very simple process. Invention Effects

[0021] If the method for manufacturing heteroepitaxial wafers of the present invention is adopted, SiC single crystals can be reliably formed by removing the natural oxide film on the surface of the single-crystal silicon substrate and then growing SiC single crystals. In addition, since a flash lamp device is used, it can be started up quickly and the temperature can be controlled in a short time, and it can be adapted to large-diameter substrates. Furthermore, the process of removing the natural oxide film is carried out by preheating at 300°C to 600°C and then calcining with hydrogen at 900°C to 1350°C. The process of growing SiC single crystals is carried out by preheating at 300°C to 600°C and then forming SiC nuclei at 900°C to 1350°C. Both processes are preheated at a temperature of 300°C to 600°C, which is a temperature that is sufficiently lower than the phase transition temperature of Si (111) of 860°C. Therefore, a phase transition can be avoided during preheating. Furthermore, the movement from the temperature zone above 300°C and below 600°C to the temperature zone above 900°C and below 1350°C can be achieved in a short time using a flash lamp device. Therefore, it can be controlled to pass through the phase transition temperature in a very short time, and almost no phase transition is triggered during the movement of the temperature zone.

[0022] As described above, a simple manufacturing process can suppress the phase transition of a single-crystal silicon substrate, thereby efficiently manufacturing heteroepitaxial wafers with high-quality 3C-SiC single-crystal films. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating an example of a method for manufacturing heteroepitaxial wafers according to the present invention. Figure 2 (a) is a schematic diagram showing the processing sequence of Example 1, and (b) is a graph showing the XRD spectrum. Figure 3 (a) is a schematic diagram showing the treatment sequence of Comparative Example 1, and (b) is a graph showing the XRD spectrum. Detailed Implementation

[0024] The present invention will now be described in detail, but it is not limited thereto.

[0025] As described above, a method for manufacturing heteroepitaxial wafers is sought to efficiently epitaxially grow high-quality 3C-SiC single-crystal films on single-crystal silicon substrates.

[0026] The inventors, through repeated and in-depth investigations into the aforementioned problems, have determined that a narrow temperature band around 860°C on the surface of a Si(111) substrate can induce a phase transition. Therefore, this temperature band can be enclosed, resulting in a 7×7 structure at low temperatures and a 1×1 structure at high temperatures. However, this change contributes to defect formation. Specifically, in the past, when growing 3C-SiC on a Si(111) substrate, initial seed crystals were formed simultaneously with the flow of carbide gas at low temperatures. This effectively utilized the phase transition, using the unstable (high surface energy) adjacent structures of the low-temperature 7×7 domains as the starting point (seed) for crystal growth. The temperature was then increased to grow 3C-SiC. However, the increased temperature causes a surface structure transformation, making it difficult to form a beautiful 3C-SiC / Si interface. Growth at low temperatures up to the initiation of the phase transition was also considered, but due to the low surface energy, it resulted in island-like growth. To address the unique problems of this Si(111) surface, the inventors explored the results of methods, particularly rapid passage through phase transition temperature zones, and discovered a method that, by passing through these temperature zones in a short time, can control the process to almost no phase transition and can grow high-quality 3C-SiC single crystals with few defects, thus completing the present invention.

[0027] That is, the method for manufacturing a heteroepitaxial wafer of the present invention is a method for manufacturing a heteroepitaxial wafer by epitaxially growing a 3C-SiC single crystal film on a single crystal silicon substrate. The method for manufacturing a heteroepitaxial wafer includes the following steps: a step of preparing a single crystal silicon substrate with a plane orientation of (111); a step of removing the natural oxide film on the surface of the single crystal silicon substrate by using a flash lamp device and calcining with hydrogen; a step of supplying a source gas containing carbon and silicon into the flash lamp device to grow SiC single crystals on the surface of the single crystal silicon substrate; the step of removing the natural oxide film is performed by preheating at 300°C or higher and 600°C or lower, followed by calcining with hydrogen at 900°C or higher and 1350°C or lower; the step of growing SiC single crystals is performed by preheating at 300°C or higher and 600°C or lower, followed by SiC nucleation at 900°C or higher and 1350°C or lower.

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a flowchart illustrating an example of a method for manufacturing a heteroepitaxial wafer according to the present invention. (Refer to...) Figure 1 The stages S1 to S3 describe each stage of the manufacturing process.

[0029] (Phase S1) First, stage S1 is the process of preparing a monocrystalline silicon substrate with a plane orientation of (111). The monocrystalline silicon substrate is placed in a flash lamp device.

[0030] (Phase S2) Next, stage S2 is a process of removing the natural oxide film on the surface of the monocrystalline silicon substrate by using a flash lamp device and roasting with hydrogen.

[0031] The native oxide film on the surface is removed by hydrogen annealing (H2 annealing). This is because if the oxide film remains, it will prevent SiC nucleation on the monocrystalline silicon substrate, which must be avoided. In this H2 annealing, the substrate is preheated at a temperature 300°C to 600°C, sufficiently lower than the phase transition temperature of 860°C. Subsequently, the temperature for removing the native oxide film from the surface of the monocrystalline silicon substrate is set to 900°C to 1350°C. This is because, when hydrogen annealing is performed at 900°C to 1350°C using a flash lamp device, wafer breakage due to thermal stress caused by rapid temperature rise is suppressed, without the preheating performed at 300°C to 600°C.

[0032] While not specifically limited here, a temperature range of 1000°C or higher but 1200°C or lower is more preferable. If the temperature is low, the processing time to prevent residual natural oxide film needs to be extended accordingly; if possible, a temperature of 1000°C or higher is more preferable. Conversely, if the temperature is high, the risk of slippage increases accordingly; if possible, a temperature of 1200°C or lower is more preferable. The pressure and time of the H2 annealing are not particularly limited in this case, as long as the natural oxide film can be removed.

[0033] Furthermore, it is preferable to set the hydrogen roasting time at 900°C or higher and 1350°C or lower to 10 milliseconds or higher and 100 milliseconds or lower. With this combination of temperature range and time, it is possible to ensure the time required for removing the natural oxide film while minimizing the dwell time in the temperature band higher than the phase transition temperature of Si (111) at 860°C.

[0034] It should be noted that when the temperature range is set to above 1000℃ and below 1200℃, although there are no specific restrictions, the time range can be set to above 20 milliseconds and below 60 milliseconds.

[0035] (Stage S3) Next, stage S3 is a process of supplying a source gas containing carbon and silicon into a flash lamp device to grow SiC single crystals on the surface of a single-crystal silicon substrate. First, the substrate is preheated at a temperature 300°C to 600°C, which is sufficiently lower than the phase transition temperature of Si (111) (860°C). Then, SiC nucleation is performed at a temperature 900°C to 1350°C. This is because, when nucleation is performed at 900°C to 1350°C using a flash lamp device, wafer breakage due to thermal stress caused by rapid temperature increases is suppressed when preheating at 300°C to 600°C is not performed.

[0036] Here, the source gas is preferably at least one of monomethylsilane and trimethylsilane. Compared to Si, C atoms are smaller and easier to vaporize. Therefore, although there is no particular limitation, trimethylsilane is more preferred considering feedstock efficiency, and trimethylsilane is also easier to set the conditions for.

[0037] Preferably, the nucleus formation time of SiC at temperatures above 900°C and below 1350°C is set to be more than 1 millisecond and less than 20 milliseconds. With this combination of temperature range and time, it is possible to ensure the time required for growing SiC single crystals while minimizing the dwell time in the temperature band higher than the phase transition temperature of Si (111) at 860°C.

[0038] While there are no particular limitations here, it is more preferable to set the temperature range to 1100°C or higher and 1300°C or lower. Furthermore, when the temperature range is set to 1100°C or higher and 1300°C or lower, while there are no particular limitations, it is more preferable to set the time to 5 milliseconds or higher and 10 milliseconds or lower.

[0039] The above simplified manufacturing process, from stage S1 to stage S3, can suppress the phase transition of the single-crystal silicon substrate, thereby efficiently manufacturing heteroepitaxial wafers with high-quality 3C-SiC single-crystal films.

[0040] It should be noted that, although there are no particular limitations, it is more preferable to use a flash lamp device with a pressure reduction (RP) mechanism or the like to manage the pressure during the process of growing SiC single crystals in stage S3.

[0041] Specifically, it is more preferable to set the pressure to 100 Torr or less when preheating at 300°C or higher and 600°C or lower, and then set the pressure to 10 Torr or less when SiC nucleation is performed at 900°C or higher and 1350°C or lower. In this way, by performing SiC nucleation under pressure and temperature conditions that facilitate SiC nucleation, heteroepitaxial wafers with the target 3C-SiC single-crystal film thickness can be manufactured more efficiently and effectively.

[0042] First, by setting the pressure below 100 Torr during preheating, secondary or higher-level reactions, such as reactions between reactive species and raw materials in the gas phase, can be prevented, thus ensuring that the SiC nucleation process is carried out reliably.

[0043] Next, by setting the pressure to below 10 Torr during SiC nucleation, it is possible to grow a 3C-SiC single crystal film while simultaneously forming a vacancy in the silicon layer directly beneath it. The presence of this vacancy not only mitigates the lattice mismatch between 3C-SiC and silicon but also alleviates the overall stress of the epitaxial layer. Therefore, even during subsequent growth of thicker 3C-SiC single crystal films, a 3C-SiC single crystal film free of crystal defects can be formed.

[0044] It should be noted that, regarding the source gas, compared to the previous two-stage method of forming a 3C-SiC single crystal film by attaching carbon atoms to the surface of a single crystal silicon substrate using a gas containing a carbon source precursor and a gas containing a silicon source precursor, this method makes it easier to control the reactive species in the gas phase, ensuring that the growth proceeds reliably. This allows for the continuous growth of 3C-SiC single crystals and the formation of single crystal films.

[0045] It should be noted that, under the above circumstances, the 3C-SiC film thickness can be as thin as 2 nm. Furthermore, by using the 3C-SiC single crystal film grown in the above manner as a seed layer that also serves as a nucleus for SiC, and further processing it through an RP-CVD device or similar apparatus, high-quality, thick 3C-SiC crystals can be grown. Example

[0046] The present invention will be illustrated in more detail below with examples and comparative examples, but the present invention is not limited to these examples.

[0047] [Example 1] Reference Figure 2 Please provide an explanation. Figure 2 (a) is a schematic diagram showing the processing sequence of Example 1, and (b) is a graph showing the XRD spectrum.

[0048] A monocrystalline silicon substrate with a diameter of 300 mm (111), boron doped, and a resistivity of 10 Ω·cm was prepared. The monocrystalline silicon substrate was placed in a flash lamp device, and the natural oxide film on the surface was removed by hydrogen calcination (H2 annealing). The H2 annealing at this time involved preheating the substrate at 500 °C, which is sufficiently lower than the phase transition temperature of 860 °C, and then annealing it at 1150 °C for 40 ms.

[0049] Next, the source gas containing carbon and silicon, namely trimethylsilane gas, was set to 100 sccm, and the chamber temperature was set to 10 Torr. The substrate was preheated to 500°C, which is sufficiently lower than the phase transition temperature of Si (111) at 860°C. Subsequently, SiC was grown on the single-crystal silicon substrate at 1300°C for 10 milliseconds. Here, the gas is introduced into a 10-millisecond image, which is as follows: Figure 2 (a) is a schematic diagram of the processing sequence, showing a narrow, pulsed image.

[0050] The crystallinity of the 3C-SiC single-crystal film formed on the Si(111) substrate was thus evaluated using in-plane X-ray diffraction (XRD). In-plane arrangement is a method that can obtain strong diffraction intensity even in thin films. Here, by using the Si(220) plane of the substrate as a reference, the type of orientation plane of the 3C-SiC parallel to it can be identified, thus determining whether the 3C-SiC is single-crystal or polycrystalline. Furthermore, information on crystallinity can be obtained from the full width at half maximum (FWHM) of the 3C-SiC peak. In Example 1, as... Figure 2 As shown in (b), the peak originating from 3C-SiC is only the (220) orientation. That is, no peaks representing polycrystalline originating from other crystal plane indices were identified, but a 3C-SiC film with monocrystalline growth was identified.

[0051] [Comparative Example 1] Reference Figure 3 Please provide an explanation. Figure 3 (a) is a schematic diagram showing the treatment sequence of Comparative Example 1, and (b) is a graph showing the XRD spectrum.

[0052] A single-crystal silicon substrate with a diameter of 300 mm (111), boron doping and a resistance of 10 Ω·cm was prepared and hydrogen-calcined in an epitaxial furnace at 1130 °C.

[0053] Next, while flowing trimethylsilane gas at 100 sccm, the temperature was increased from 300°C to 1100°C at a rate of 10°C / min. The pressure was set to 100 Torr at this point. The image of the gas introduction is shown below. Figure 3 (a) is a schematic diagram of the processing sequence, showing a wide-width image. Regarding the exposure time to temperatures higher than the phase transition temperature of 860°C, compared to Example 1 ( Figure 2 (a) Compared to Example 1, Comparative Example 1 is far superior to Example 1. Figure 2 (a) Exposure to high temperatures for a longer period of time.

[0054] Subsequently, the crystallinity of the grown 3C-SiC film was measured in-plane using XRD. The results are as follows: Figure 3As shown in (b), only the peak value of 3C-SiC(220) parallel to Si(220) appears, but compared to Example 1 ( Figure 2 (b) The peak value is lower and the width is wider, resulting in a larger full width at half maximum (FWHM). In other words, it can be seen that the crystallinity of Comparative Example 1 is worse than that of Example 1.

[0055] As can be seen from the above, compared with Comparative Example 1, 3C-SiC of Example 1 of the present invention has good crystallinity and the phase transition is suppressed.

[0056] It should be noted that the present invention is not limited to the embodiments described above. The embodiments described above are illustrative examples, and any technical solution having a substantially the same structure and performing the same effect as the technical concept described in the claims of the present invention is included within the technical scope of the present invention.

Claims

1. A method for manufacturing a heteroepitaxial wafer, comprising the method of epitaxially growing a 3C-SiC single crystal heteroepitaxial wafer on a single-crystal silicon substrate, characterized in that, It has the following processes: The process of preparing a single-crystal silicon substrate with a plane orientation of (111); The process of removing the natural oxide film on the surface of the monocrystalline silicon substrate using a flash lamp device and hydrogen roasting; and The process of supplying a source gas containing carbon and silicon into the flash lamp device to grow SiC single crystals on the surface of the single-crystal silicon substrate; The process of removing the natural oxide film involves preheating at a temperature above 300°C and below 600°C, followed by hydrogen roasting at a temperature above 900°C and below 1350°C. The process of growing the SiC single crystal involves preheating at a temperature above 300°C and below 600°C, followed by SiC nucleation at a temperature above 900°C and below 1350°C.

2. The method for manufacturing heteroepitaxial wafers according to claim 1, characterized in that, The hydrogen roasting time at temperatures above 900°C and below 1350°C is set to be above 10 milliseconds and below 100 milliseconds. The core formation time of SiC at temperatures above 900°C and below 1350°C is set to be above 1 millisecond and below 20 milliseconds.

3. The method for manufacturing a heteroepitaxial wafer according to claim 1 or 2, characterized in that, The source gas is set to at least one of monomethylsilane and trimethylsilane.

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