A fast dynamic response, high stability low dropout linear voltage regulator

Abstract

This invention belongs to the field of analog integrated circuit design, and particularly relates to a low-dropout linear regulator with fast dynamic response and high stability. It includes: an error amplifier, a Class AB buffer stage circuit, an output power transistor, a positive feedback resistor compensation circuit, an undervoltage detection circuit, and a startup circuit. The Class AB buffer stage circuit is used to improve the transient characteristics of the low-dropout linear regulator, and the positive feedback resistor compensation circuit is used to improve the phase margin of the low-dropout linear regulator. This invention achieves fast dynamic response, essentially eliminates overshoot and undershoot phenomena, and significantly shortens the recovery time. It also maintains high stability while ensuring loop gain and includes undervoltage detection functionality to ensure smooth system startup.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design, and particularly relates to a low dropout linear regulator with fast dynamic response and high stability. Background Technology

[0002] Low-dropout linear regulators (LDOs) are common voltage sources in analog integrated circuit design, widely used in various power management and signal chain chips. Their most prominent feature is their ability to convert high and unstable input voltages into precise, clean low-voltage DC. They also offer advantages such as simple structure, low quiescent power consumption, and low voltage noise. However, with increasingly demanding market requirements, their transient characteristics, stability, and startup issues have become a focus of research.

[0003] When the load conditions change dynamically, the output voltage of a low-dropout linear regulator is easily affected by disturbances, exhibiting significant overshoot and undershoot phenomena, and requiring a certain recovery time, which becomes a major challenge in improving its accuracy. Furthermore, low-dropout linear regulators typically require phase compensation, and some compensation methods can significantly reduce the loop gain of the feedback loop, affecting the accuracy of the output voltage and even leading to unnecessary power consumption.

[0004] In addition, the power supply voltage of some internal reference circuits of the chip is provided by the on-chip low dropout linear regulator. The feedback loop of the low dropout linear regulator can only work stably after the reference circuit has been started. Therefore, if the low dropout linear regulator cannot start in time and provide a high voltage when powered on, the system may not work properly, thus causing a fault. Summary of the Invention

[0005] This invention provides a low-dropout linear regulator with fast dynamic response and high stability, which can solve the technical problems mentioned in the background art, achieve fast dynamic response, have high stability, and also has undervoltage detection and other functions.

[0006] The technical solution of the present invention is as follows: a low dropout linear regulator with fast dynamic response and high stability, comprising: an error amplifier, a Class AB buffer stage circuit, an output power transistor, a positive feedback resistor compensation circuit, an undervoltage detection circuit, and a startup circuit; The non-inverting input of the error amplifier is connected to the reference voltage signal VREF. The output of the error amplifier is connected to the input of the Class AB buffer stage circuit and the output of the positive feedback resistor compensation circuit. The output of the Class AB buffer stage circuit is connected to the gate of the output power transistor. The drain of the output power transistor is connected to the power supply voltage signal VBB2. The source of the output power transistor is connected to the input of the positive feedback resistor compensation circuit and the input of the undervoltage detection circuit. The output of the undervoltage detection circuit is connected to the startup circuit. The Class AB buffer stage circuit is used to improve the transient characteristics of the low dropout linear regulator, and the positive feedback resistor compensation circuit is used to improve the phase margin of the low dropout linear regulator.

[0007] Furthermore, the error amplifier includes: a first transistor QN1, a second transistor QN2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, and a current sink I1; The base of the first transistor QN1 is connected to the reference voltage signal VREF. The emitter of the first transistor QN1 is connected to the emitter of the second transistor QN2 and one end of the current sink I1. The collector of the first transistor QN1 is connected to the source of the first NMOS transistor MN1. The collector of the second transistor QN2 is connected to the source of the second NMOS transistor MN2. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to the output voltage signal VOUT. The drain of the first NMOS transistor MN1 is connected to the drain and gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the output of the startup circuit. The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, the input of the Class AB buffer circuit, and the output of the positive feedback resistor compensation circuit. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage signal VBB1. The other end of the current sink I1 is connected to signal ground GND.

[0008] Furthermore, the Class AB buffer stage circuit includes: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a current source I2, and a current sink I3; The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are both connected to the output of the error amplifier. The source of the third PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN4 and one end of the current source I2. The drain of the third PMOS transistor MP3 is connected to signal ground GND. The drain of the third NMOS transistor MN3 is connected to the power supply voltage signal VBB1. The source of the third NMOS transistor MN3 is connected to the gate of the fourth PMOS transistor MP4 and one end of the current sink I3. The drain of the fourth PMOS transistor MP4 and the other end of the current sink I3 are both connected to signal ground GND. The source of the fourth PMOS transistor MP4 and the source of the fourth NMOS transistor MN4 are both connected to the gate of the output power transistor. The drain of the fourth NMOS transistor MN4 and the other end of the current source I2 are both connected to the power supply voltage signal VBB1.

[0009] Furthermore, the output power transistor is the fifth NMOS transistor MN5; The gate of the fifth NMOS transistor MN5 is connected to the output of the Class AB buffer circuit, the drain of the fifth NMOS transistor MN5 is connected to the power supply voltage signal VBB2, and the source of the fifth NMOS transistor MN5 is connected to the input of the positive feedback resistor compensation circuit and the input of the undervoltage detection circuit.

[0010] Furthermore, the positive feedback resistor compensation circuit includes: a fifth PMOS transistor MP5, a third resistor R3, a fourth resistor R4, and a current source I4; The gate of the fifth PMOS transistor MP5 is connected to the source of the output power transistor and the input of the undervoltage detection circuit. The drain of the fifth PMOS transistor MP5 is connected to signal ground GND. The source of the fifth PMOS transistor MP5 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the current source I4 and one end of the third resistor R3. The other end of the current source I4 is connected to the power supply voltage signal VBB1. The other end of the third resistor R3 is connected to the output of the error amplifier and the input of the Class AB buffer stage circuit.

[0011] Furthermore, the undervoltage detection circuit includes: a third transistor QN3, a fourth transistor QN4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13; The base of the third transistor QN3 is connected to the base of the fourth transistor QN4, one end of the tenth resistor R10, and one end of the eleventh resistor R11. The emitter of the third transistor QN3 is connected to one end of the seventh resistor R7. The collector of the third transistor QN3 is connected to the drain and gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the emitter of the fourth transistor QN4. The collector of the fourth transistor QN4 is connected to the drain of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8. The source of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7... The source of the eighth PMOS transistor MP8 and the other end of the tenth resistor R10 are all connected to the output voltage signal VOUT. The other end of the eighth resistor R8, one end of the ninth resistor R9, one end of the twelfth resistor R12, and the source of the eighth NMOS transistor MN8 are all connected to signal ground GND. The drain of the eighth PMOS transistor MP8 is connected to the other end of the ninth resistor R9 and outputs an undervoltage detection output signal. The gate of the eighth NMOS transistor MN8 is connected to the undervoltage detection feedback signal. The drain of the eighth NMOS transistor MN8 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the other end of the eleventh resistor R11 and the other end of the twelfth resistor R12.

[0012] Furthermore, the startup circuit includes: a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth resistor R5, and a sixth resistor R6; The gate of the sixth NMOS transistor MN6 is connected to the undervoltage detection output signal VD. The source of the sixth NMOS transistor MN6 and one end of the sixth resistor R6 are both connected to signal ground GND. The gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN7 and one end of the fifth resistor R5. The source of the seventh NMOS transistor MN7 is connected to the other end of the sixth resistor R6. The drain of the seventh NMOS transistor MN7 is connected to the drain of the first NMOS transistor MN1 and the drain and gate of the first PMOS transistor MP1. The other end of the fifth resistor R5 is connected to the power supply voltage signal VBB1.

[0013] Furthermore, it also includes: a first resistor R1 and a second resistor R2; One end of the first resistor R1 is connected to the source of the output power transistor, the input of the positive feedback resistor compensation circuit, and the input of the undervoltage detection circuit. The other end of the first resistor R1 is connected to one end of the second resistor R2 and the inverting input of the error amplifier. The other end of the second resistor R2 is connected to signal ground GND.

[0014] The beneficial effects of this invention are as follows: This invention can improve the transient characteristics of low dropout linear regulators, achieve fast dynamic response, basically eliminate overshoot and undershoot phenomena and significantly shorten recovery time. At the same time, it has high stability while ensuring loop gain, and has undervoltage detection and other functions to ensure smooth system startup. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of the present invention.

[0016] Figure 2 This is a schematic diagram of the undervoltage detection circuit in this invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] In the technical solution of the present invention, Figure 1 This is a schematic diagram of a low-dropout linear regulator with fast dynamic response and high stability according to the present invention, as shown below. Figure 1 As shown, the present invention includes: an error amplifier 1, a Class AB buffer stage circuit 2, an output power transistor, a positive feedback resistor compensation circuit 4, an undervoltage detection circuit 5, and a startup circuit 6. The non-inverting input terminal of the error amplifier 1 is connected to a reference voltage signal VREF. The output terminal of the error amplifier 1 is connected to the input terminal of the Class AB buffer stage circuit 2 and the output terminal of the positive feedback resistor compensation circuit 4. The output terminal of the Class AB buffer stage circuit 2 is connected to the gate of the output power transistor. The drain of the output power transistor is connected to a power supply voltage signal VBB2. The source of the output power transistor is connected to the input terminal of the positive feedback resistor compensation circuit 4 and the input terminal of the undervoltage detection circuit 5. The output terminal of the undervoltage detection circuit 5 is connected to the startup circuit 6. The Class AB buffer stage circuit 2 is used to improve the transient characteristics of the low dropout linear regulator, and the positive feedback resistor compensation circuit 4 is used to improve the phase margin of the low dropout linear regulator.

[0019] In an embodiment of the present invention, the error amplifier 1 includes: a first transistor QN1, a second transistor QN2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, and a current sink I1. Transistors are used as the input pair because they have high equivalent transconductance, high common-mode rejection ratio, low temperature drift, and low noise. The base of the first transistor QN1 is connected to the reference voltage signal VREF, the emitter of the first transistor QN1 is connected to the emitter of the second transistor QN2 and one end of the current sink I1, the collector of the first transistor QN1 is connected to the source of the first NMOS transistor MN1, the base of the second transistor QN2 is connected to the feedback voltage signal, and the collector of the second transistor QN2 is connected to the source of the second NMOS transistor MN2. Due to the virtual short characteristic of the operational amplifier, the feedback voltage signal and the reference voltage signal VREF are equal, and the ratio of the feedback voltage signal to the output voltage signal VOUT is related to the values ​​of the first resistor R1 and the second resistor R2, specifically... Therefore, the error amplifier, through negative feedback, fixes the output voltage signal VOUT to:

[0020] The first NMOS transistor MN1 and the second NMOS transistor MN2 primarily bear the voltage. Their gates are both connected to the output voltage signal VOUT. The drain of the first NMOS transistor MN1 is connected to the drain and gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the output of the startup circuit 6. The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, the input of the Class AB buffer circuit 2, and the output of the positive feedback resistor compensation circuit 4. The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage signal VBB1. The first PMOS transistor MP1 and the second PMOS transistor MP2 form a current mirror, capable of accurately replicating the current magnitude. The other end of the current sink I1 is connected to signal ground GND, serving as the tail current source of the error amplifier.

[0021] In an embodiment of the present invention, the Class AB buffer stage circuit 2 includes: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a current source I2, and a current sink I3. The third PMOS transistor MP3 and the third NMOS transistor MN3 function as level shifters, while the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 form a push-pull structure. The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are both connected to the output terminal of the error amplifier 1. The source of the third PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN4 and one end of the current source I2. The drain of the third PMOS transistor MP3 is connected to signal ground GND. The drain of the third NMOS transistor MN3 is connected to the power supply voltage signal VBB1. The source of the third NMOS transistor MN3 is connected to the gate of the fourth PMOS transistor MP4 and one end of the current sink I3. The drain of the fourth PMOS transistor MP4 and the other end of the current sink I3 are both connected to signal ground GND. The source of the fourth PMOS transistor MP4 and the source of the fourth NMOS transistor MN4 are both connected to the gate of the output power transistor. The drain of the fourth NMOS transistor MN4 and the other end of the current source I2 are both connected to the power supply voltage signal VBB1. The presence of the Class AB buffer circuit 2 enables the gate voltage of the output power transistor to have a sufficiently large current change rate, thereby achieving a fast dynamic response, essentially eliminating overshoot and undershoot phenomena, and significantly shortening the recovery time, thus significantly improving the transient characteristics of the low dropout linear regulator.

[0022] In an embodiment of the present invention, the output power transistor is a fifth NMOS transistor MN5. The gate of the fifth NMOS transistor MN5 is connected to the output terminal of the Class AB buffer stage circuit 2, and the drain of the fifth NMOS transistor MN5 is connected to the power supply voltage signal VBB2. Since the power transistor is an NMOS transistor, the power supply voltage signal VBB2 must typically be less than the power supply voltage signal VBB1. The source of the fifth NMOS transistor MN5 is connected to the input terminal of the positive feedback resistor compensation circuit 4 and the input terminal of the undervoltage detection circuit 5. The main reason for using an NMOS transistor instead of a PMOS transistor as the power transistor is that the electron mobility is much higher than the hole mobility. Under the same conditions and the same size, the on-resistance of an NMOS transistor is smaller and the switching speed is faster. In addition, it also has advantages such as smaller area and lower cost.

[0023] In an embodiment of the present invention, the positive feedback resistor compensation circuit 4 includes: a fifth PMOS transistor MP5, a third resistor R3, a fourth resistor R4, and a current source I4. The gate of the fifth PMOS transistor MP5 is connected to the source of the output power transistor and the input terminal of the undervoltage detection circuit 5. The drain of the fifth PMOS transistor MP5 is connected to signal ground GND. The source of the fifth PMOS transistor MP5 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the current source I4 and one end of the third resistor R3. The other end of the current source I4 is connected to the power supply voltage signal VBB1. The other end of the third resistor R3 is connected to the output terminal of the error amplifier 1 and the input terminal of the Class AB buffer stage circuit 2.

[0024] To explain the working principle of the positive feedback resistor compensation circuit 4 described in this invention, it is necessary to first analyze the stability of this low-dropout linear regulator without this module. The loop has two main poles at points A and B. At the sources of each MOS transistor in the Class AB buffer stage circuit 2, the equivalent resistance is the output resistance of the source follower, and the equivalent capacitance is the parasitic capacitance of the MOS transistor; both values ​​are small. Therefore, the poles at these locations are far from the origin, and their influence can be ignored. The open-loop gain and main poles of the circuit can be obtained as follows:

[0025] in, , The transconductance and output resistance of the first transistor QN1 and the second transistor QN2 are given. , The transconductance and output resistance of the corresponding NMOS transistor are given. The output resistance of the corresponding PMOS transistor is [value]. The gain of the Class AB buffer stage circuit 2 is close to 1. For load resistance, The equivalent output capacitance at point A is composed of parasitic capacitance. The equivalent output capacitance at point B is mainly the load capacitance. Because the second PMOS transistor MP2 has a relatively large length to reduce the impact of mismatch, the equivalent resistance at point A is large, on the order of 100MΩ. Furthermore, there is a small buffer stage MOS transistor between it and the output power transistor, resulting in a large equivalent capacitance. It is relatively small, on the order of 100 fF. For point B, a 1 μF load capacitor is typically connected externally, therefore the equivalent capacitance is... The resistance is relatively large, while its equivalent resistance is dominated by the output resistance of the source follower, which is relatively small, on the order of 10Ω. Estimation shows that the poles at points A and B are of the same order of magnitude and too close together. Without compensation, the circuit's phase margin will be insufficient, leading to serious stability problems.

[0026] If a resistor of 10K ohms is connected to signal ground GND at point A, although the pole will be pushed outward, the loop gain will be greatly reduced, affecting the accuracy of the output voltage. Furthermore, the small current diverted will cause the currents in the current mirror of the error amplifier 1 to be unequal, increasing circuit mismatch and affecting the accuracy of the output voltage. It may even cause the error amplifier 1 to malfunction.

[0027] After adding the positive feedback resistor compensation circuit 4 described in this invention, the DC characteristics are as follows: from point A to the output voltage signal VOUT, the gate-source voltage of one MOS transistor first rises, then the gate-source voltage of two MOS transistors falls, and the voltage drop is approximately equal to the gate-source voltage of the fifth NMOS transistor MN5. From the output voltage signal VOUT to point C, the gate-source voltage of the fifth PMOS transistor MP5 increases. Then, the voltage across the fourth resistor R4 is reduced. By adjusting the resistance value of the fourth resistor R4 and the current magnitude of the current source I4, the voltage at point C can be made similar to that at point A, and the current flowing through the third resistor R3 will also be smaller, so as not to affect the current mirror in the error amplifier.

[0028] Regarding stability, the equivalent impedance at point A, under the effect of positive feedback resistor compensation, can be calculated to become:

[0029] in, Let MN5 be the output resistance of the fifth NMOS transistor. This value is much smaller than the equivalent resistance at the original point A, therefore the pole at point A shifts away from the origin, while it is also much larger than the third resistor R3, so the loop gain will not decrease too much. The equivalent impedance at point B, under the effect of positive feedback resistor compensation, becomes:

[0030] The value is approximately The resistance is much greater than the equivalent resistance at point B, therefore the pole at point B moves towards the origin. Thus, the two poles split, greatly enhancing the circuit's stability.

[0031] It should be noted that the positive feedback resistor compensation circuit 4 will introduce an additional zero-pole pair outside the gain intersection point, but this zero-pole pair is far from the gain intersection point, so it will not affect the stability of the circuit.

[0032] The positive feedback resistor compensation circuit 4 increases the phase margin of the low dropout linear regulator, enabling it to have high stability while ensuring loop gain.

[0033] In an embodiment of the present invention, Figure 2 This is a schematic diagram of the undervoltage detection circuit 5 described in this invention, as shown below. Figure 2 As shown, the undervoltage detection circuit 5 includes: a third transistor QN3, a fourth transistor QN4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The base of the third transistor QN3 is connected to the base of the fourth transistor QN4, one end of the tenth resistor R10, and one end of the eleventh resistor R11. The emitter of the third transistor QN3 is connected to one end of the seventh resistor R7. The collector of the third transistor QN3 is connected to the drain and gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the emitter of the fourth transistor QN4. The collector of the fourth transistor QN4 is connected to the drain of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8. The source of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7... The source of the eighth PMOS transistor MP8 and the other end of the tenth resistor R10 are all connected to the output voltage signal VOUT. The other end of the eighth resistor R8, one end of the ninth resistor R9, one end of the twelfth resistor R12, and the source of the eighth NMOS transistor MN8 are all connected to signal ground GND. The drain of the eighth PMOS transistor MP8 is connected to the other end of the ninth resistor R9 and outputs an undervoltage detection output signal. The gate of the eighth NMOS transistor MN8 is connected to the undervoltage detection feedback signal. The drain of the eighth NMOS transistor MN8 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the other end of the eleventh resistor R11 and the other end of the twelfth resistor R12.

[0034] The undervoltage detection circuit 5 can detect whether the output voltage signal VOUT reaches a high level. When the output voltage signal VOUT is too low, neither the third transistor QN3 nor the fourth transistor QN4 is turned on, the collector of the fourth transistor QN4 is at a high level, and the undervoltage detection feedback signal is at a low level. When the output voltage signal VOUT increases, the third transistor QN3 and the fourth transistor QN4 begin to turn on. Since the number of third transistors QN3 connected in parallel is greater than that of the fourth transistor QN4, the current on them is also greater than the current on the fourth transistor QN4. The collector of the fourth transistor QN4 remains at a high level, and the undervoltage detection feedback signal is at a low level. When the output voltage signal VOUT rises to VOUT1, the output state reaches the critical point of transition. At this time, the current on the third transistor QN3 is equal to the current on the fourth transistor QN4, and thus:

[0035] in, It is the base-emitter voltage of the third transistor QN3.

[0036] Simultaneously, the base voltage of the third transistor QN3 is also related to the voltage division of the output voltage signal VOUT across the eleventh resistor R11, the twelfth resistor R12, and the thirteenth resistor R13, forming positive feedback with the undervoltage detection feedback signal. The undervoltage detection feedback signal graph exhibits hysteresis, and the detection thresholds are as follows:

[0037]

[0038] By adjusting the resistance values ​​of the tenth resistor R10, the eleventh resistor R11, the twelfth resistor R12, and the thirteenth resistor R13, different undervoltage detection thresholds and undervoltage detection hysteresis can be set.

[0039] In an embodiment of the present invention, the startup circuit 6 includes: a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth resistor R5, and a sixth resistor R6. The gate of the sixth NMOS transistor MN6 is connected to the undervoltage detection output signal VD. The source of the sixth NMOS transistor MN6 and one end of the sixth resistor R6 are both connected to signal ground GND. The gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN7 and one end of the fifth resistor R5. The source of the seventh NMOS transistor MN7 is connected to the other end of the sixth resistor R6. The drain of the seventh NMOS transistor MN7 is connected to the drain of the first NMOS transistor MN1 and the drain and gate of the first PMOS transistor MP1. The other end of the fifth resistor R5 is connected to the power supply voltage signal VBB1.

[0040] Upon power-up, the gate voltage of the sixth NMOS transistor MN6 is too low to conduct. The power supply voltage signal VBB1 charges the seventh NMOS transistor MN7, causing it to conduct. This pulls down the gate voltage of the second PMOS transistor MP2, enabling the low-dropout linear regulator to start. When the undervoltage detection output signal VD is normal (high level), the gate of the sixth NMOS transistor MN6 conducts, and the startup circuit fails. The undervoltage detection circuit 5 and the startup circuit 6 together ensure the smooth startup of the system.

[0041] In an embodiment of the present invention, the device further includes: a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected to the source of the output power transistor, the input terminal of the positive feedback resistor compensation circuit 4, and the input terminal of the undervoltage detection circuit 5. The other end of the first resistor R1 is connected to one end of the second resistor R2 and the inverting input terminal of the error amplifier 1. The other end of the second resistor R2 is connected to signal ground GND.

[0042] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A low-dropout linear regulator with fast dynamic response and high stability, characterized in that, include: Error amplifier (1), Class AB buffer stage circuit (2), output power transistor, positive feedback resistor compensation circuit (4), undervoltage detection circuit (5), startup circuit (6); The non-inverting input terminal of the error amplifier (1) is connected to the reference voltage signal VREF. The output terminal of the error amplifier (1) is connected to the input terminal of the Class AB buffer stage circuit (2) and the output terminal of the positive feedback resistor compensation circuit (4). The output terminal of the Class AB buffer stage circuit (2) is connected to the gate of the output power transistor. The drain of the output power transistor is connected to the power supply voltage signal VBB2. The source of the output power transistor is connected to the input terminal of the positive feedback resistor compensation circuit (4) and the input terminal of the undervoltage detection circuit (5). The output terminal of the undervoltage detection circuit (5) is connected to the startup circuit (6). The Class AB buffer stage circuit (2) is used to improve the transient characteristics of the low dropout linear regulator, and the positive feedback resistor compensation circuit (4) is used to improve the phase margin of the low dropout linear regulator.

2. The fast dynamic response, high stability, low dropout linear regulator as described in claim 1, characterized in that, The error amplifier (1) includes: a first transistor QN1, a second transistor QN2, a first NMOS transistor MN1, a second NMOS transistor MN2, a first PMOS transistor MP1, a second PMOS transistor MP2, and a current sink I1; The base of the first transistor QN1 is connected to the reference voltage signal VREF. The emitter of the first transistor QN1 is connected to the emitter of the second transistor QN2 and one end of the current sink I1. The collector of the first transistor QN1 is connected to the source of the first NMOS transistor MN1. The collector of the second transistor QN2 is connected to the source of the second NMOS transistor MN2. The gates of the first NMOS transistor MN1 and the second NMOS transistor MN2 are both connected to the output voltage signal VOUT. The drain of the first NMOS transistor MN1 is connected to the drain and gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2, and the output of the startup circuit (6). The drain of the second NMOS transistor MN2 is connected to the drain of the second PMOS transistor MP2, the input of the Class AB buffer circuit (2), and the output of the positive feedback resistor compensation circuit (4). The sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are both connected to the power supply voltage signal VBB1. The other end of the current sink I1 is connected to the signal ground GND.

3. The low-dropout linear regulator with fast dynamic response and high stability as described in claim 1, characterized in that, The Class AB buffer circuit (2) includes: a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth PMOS transistor MP4, a fourth NMOS transistor MN4, a current source I2, and a current sink I3; The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 are both connected to the output terminal of the error amplifier (1). The source of the third PMOS transistor MP3 is connected to the gate of the fourth NMOS transistor MN4 and one end of the current source I2. The drain of the third PMOS transistor MP3 is connected to signal ground GND. The drain of the third NMOS transistor MN3 is connected to the power supply voltage signal VBB1. The source of the third NMOS transistor MN3 is connected to the gate of the fourth PMOS transistor MP4 and one end of the current sink I3. The drain of the fourth PMOS transistor MP4 and the other end of the current sink I3 are both connected to signal ground GND. The source of the fourth PMOS transistor MP4 and the source of the fourth NMOS transistor MN4 are both connected to the gate of the output power transistor. The drain of the fourth NMOS transistor MN4 and the other end of the current source I2 are both connected to the power supply voltage signal VBB1.

4. The low-dropout linear regulator with fast dynamic response and high stability as described in claim 1, characterized in that, The output power transistor is the fifth NMOS transistor MN5; The gate of the fifth NMOS transistor MN5 is connected to the output terminal of the Class AB buffer circuit (2), the drain of the fifth NMOS transistor MN5 is connected to the power supply voltage signal VBB2, and the source of the fifth NMOS transistor MN5 is connected to the input terminal of the positive feedback resistor compensation circuit (4) and the input terminal of the undervoltage detection circuit (5).

5. The low-dropout linear regulator with fast dynamic response and high stability as described in claim 1, characterized in that, The positive feedback resistor compensation circuit (4) includes: a fifth PMOS transistor MP5, a third resistor R3, a fourth resistor R4, and a current source I4; The gate of the fifth PMOS transistor MP5 is connected to the source of the output power transistor and the input terminal of the undervoltage detection circuit (5). The drain of the fifth PMOS transistor MP5 is connected to the signal ground GND. The source of the fifth PMOS transistor MP5 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to one end of the current source I4 and one end of the third resistor R3. The other end of the current source I4 is connected to the power supply voltage signal VBB1. The other end of the third resistor R3 is connected to the output terminal of the error amplifier (1) and the input terminal of the Class AB buffer stage circuit (2).

6. The low-dropout linear regulator with fast dynamic response and high stability as described in claim 1, characterized in that, The undervoltage detection circuit (5) includes: a third transistor QN3, a fourth transistor QN4, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, an eighth NMOS transistor MN8, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a thirteenth resistor R13. The base of the third transistor QN3 is connected to the base of the fourth transistor QN4, one end of the tenth resistor R10, and one end of the eleventh resistor R11. The emitter of the third transistor QN3 is connected to one end of the seventh resistor R7. The collector of the third transistor QN3 is connected to the drain and gate of the sixth PMOS transistor MP6 and the gate of the seventh PMOS transistor MP7. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8 and the emitter of the fourth transistor QN4. The collector of the fourth transistor QN4 is connected to the drain of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8. The source of the sixth PMOS transistor MP6 and the source of the seventh PMOS transistor MP7... The source of the eighth PMOS transistor MP8 and the other end of the tenth resistor R10 are all connected to the output voltage signal VOUT. The other end of the eighth resistor R8, one end of the ninth resistor R9, one end of the twelfth resistor R12, and the source of the eighth NMOS transistor MN8 are all connected to signal ground GND. The drain of the eighth PMOS transistor MP8 is connected to the other end of the ninth resistor R9 and outputs an undervoltage detection output signal. The gate of the eighth NMOS transistor MN8 is connected to the undervoltage detection feedback signal. The drain of the eighth NMOS transistor MN8 is connected to one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is connected to the other end of the eleventh resistor R11 and the other end of the twelfth resistor R12.

7. The low-dropout linear regulator with fast dynamic response and high stability as described in claim 1, characterized in that, The startup circuit (6) includes: a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, a fifth resistor R5, and a sixth resistor R6; The gate of the sixth NMOS transistor MN6 is connected to the undervoltage detection output signal VD. The source of the sixth NMOS transistor MN6 and one end of the sixth resistor R6 are both connected to signal ground GND. The gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN7 and one end of the fifth resistor R5. The source of the seventh NMOS transistor MN7 is connected to the other end of the sixth resistor R6. The drain of the seventh NMOS transistor MN7 is connected to the drain of the first NMOS transistor MN1 and the drain and gate of the first PMOS transistor MP1. The other end of the fifth resistor R5 is connected to the power supply voltage signal VBB1.

8. The fast dynamic response, high stability, low dropout linear regulator as described in claim 1, characterized in that, Also includes: First resistor R1, second resistor R2; One end of the first resistor R1 is connected to the source of the output power transistor, the input of the positive feedback resistor compensation circuit (4) and the input of the undervoltage detection circuit (5). The other end of the first resistor R1 is connected to one end of the second resistor R2 and the inverting input of the error amplifier (1). The other end of the second resistor R2 is connected to the signal ground GND.

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