Task scheduling method and electronic device

Abstract

This application provides a task scheduling method and electronic device, relating to the field of computer technology. It can improve the utilization efficiency of scheduling resources in a multi-core processing system and increase task processing speed. For example, in a vehicle intelligent driving scenario, when a high-priority task such as collision warning is activated, it can quickly locate the core currently running the lowest-priority task and send a targeted notification, allowing high-priority safety tasks to be executed first, thereby ensuring driving safety. The task scheduling method includes: in response to the activation of a first task on a first core in the multi-core processing system, determining a second task; the second task is the lowest-priority task among all running tasks in the multi-core processing system; if the priority of the first task is greater than the priority of the second task, and the first task is not bound to a first core, controlling the first core to send an inter-core interrupt to the second core in the multi-core processing system, where the second core is the core running the second task.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a task scheduling method and electronic device. Background Technology

[0002] In existing priority-based symmetric multi-processing (SMP) real-time operating systems (RTOS), tasks are divided into two categories: global tasks not bound to any processor core, and local tasks bound to a specific processor core. When a new task is activated on a core due to an interrupt or system function call, existing scheduling methods handle it differently based on the task type. However, in scenarios where global task activation is frequent, these task scheduling methods incur unnecessary system overhead, resulting in resource waste. Summary of the Invention

[0003] The purpose of this application is to provide a task scheduling method and electronic device, which aims to solve the problem of low efficiency in scheduling resource utilization in existing scheduling methods.

[0004] In a first aspect, this application provides a task scheduling method applied to a multi-core processing system. The method includes: in response to the activation of a first task on a first core in the multi-core processing system, determining a second task; the second task is the lowest priority task among all running tasks in the multi-core processing system; and, if the priority of the first task is greater than the priority of the second task and the first task is not bound to the first core, controlling the first core to send an inter-core interrupt to the second core in the multi-core processing system, wherein the second core is the core running the second task.

[0005] It is understood that the task scheduling method provided in this application, when activating a new task, no longer broadcasts inter-core interrupts to all cores, but instead only searches for the core running the lowest priority task in the current system, and sends an interrupt to that single core only when conditions are met. Compared with the method of broadcasting interrupts to all cores in related technologies, the method of this application reduces the number of inter-core interrupts, avoids the problem of a large number of cores interrupting running tasks due to receiving irrelevant interrupts, thereby reducing system overhead and improving the overall processing efficiency of multi-core processing systems in scenarios where new tasks are frequently activated.

[0006] In some embodiments, the first task is marked as the task to be run.

[0007] In some embodiments, the method further includes: if the priority of the first task is greater than the priority of the second task, the first task is bound to the first core, and the third task is not bound to the first core, triggering a context switch of the first core to execute the first task, and triggering the first core to send a first core interrupt to the second core; wherein the third task is a task currently running on the first core, and the second task is marked as a task to be run.

[0008] In some embodiments, the method further includes: in response to the second core receiving a first inter-core interrupt, triggering a task interrupt handling process for the second core, wherein the task interrupt handling process is used to trigger the core that received the first inter-core interrupt to execute task scheduling so as to prioritize the processing of high-priority tasks.

[0009] In some embodiments, the method further includes: in response to the completion of the current task execution on the third core of the multi-core processing system, determining a fourth task and a fifth task; the fourth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the third core, and the fifth task is the highest priority task among all tasks to be run in the multi-core processing system that are bound to a core; if the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is not bound to the fourth core, controlling the third core to send a second core intermediate message to the fourth core; the sixth task is the task currently running on the fourth core.

[0010] In some embodiments, the method further includes: triggering a third core execution context switch to execute the fourth task when the priority of the fifth task is lower than the priority of the fourth task, or when the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is bound to the fourth core.

[0011] In some embodiments, the method further includes: in response to the fourth core receiving a second inter-core interrupt, determining a seventh task and an eighth task; wherein the seventh task is the highest priority task among all tasks to be run in the multi-core processing system and bound to the fourth core, and the eighth task is the lowest priority task among all running tasks in the multi-core processing system, and the eighth task runs on the fifth core; if the priority of the seventh task is greater than the priority of the eighth task, triggering the fourth core to perform an execution context switch to execute the seventh task, and sending a first inter-core interrupt to the fifth core.

[0012] In some embodiments, the method further includes: in response to the fifth core receiving a first inter-core interrupt, triggering the fifth core to execute a task interrupt handling process, wherein the task interrupt handling process is used to trigger the core that received the first inter-core interrupt to execute task scheduling so as to prioritize the processing of high-priority tasks.

[0013] In some embodiments, the task interruption handling process includes: determining the ninth task; the ninth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the core that received the first inter-core interrupt; if the priority of the ninth task is greater than the priority of the tenth task, triggering the execution context switch of the core that received the first inter-core interrupt to execute the ninth task; wherein, the tenth task is the task that the core that received the first inter-core interrupt is currently running.

[0014] Secondly, this application provides a task scheduling device 500, which includes a processing unit and a control unit; the processing unit is used to determine a second task in response to the activation of a first task on a first core in a multi-core processing system; the second task is the lowest priority task among all running tasks in the multi-core processing system; the control unit is used to control the first core to send a first inter-core interrupt to the second core in the multi-core processing system when the priority of the first task is greater than the priority of the second task and the first task is not bound to the first core, the second core being the core running the second task.

[0015] In some embodiments, the first task is marked as the task to be run.

[0016] In some embodiments, the control unit is further configured to, when the priority of the first task is greater than the priority of the second task, the first task is bound to the first core, and the third task is not bound to the first core, trigger the first core to execute the first task, and trigger the first core to send a first inter-core interrupt to the second core; wherein the third task is the task currently running on the first core, and the second task is marked as a task to be run.

[0017] In some embodiments, the control unit is further configured to, in response to the second core receiving a first inter-core interrupt, trigger a task interrupt handling process for the second core, wherein the task interrupt handling process is configured to trigger the core that received the first inter-core interrupt to execute task scheduling so as to prioritize the processing of high-priority tasks.

[0018] In some embodiments, the control unit is further configured to determine a fourth task and a fifth task in response to the completion of the current task execution of the third core in the multi-core processing system; the fourth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the third core, and the fifth task is the highest priority task among all tasks to be run in the multi-core processing system that are bound to a core; if the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is not bound to the fourth core, the control unit controls the third core to send a second core intermediate task to the fourth core; the sixth task is the task currently running on the fourth core.

[0019] In some embodiments, the control unit is further configured to trigger a third core execution context switch to execute the fourth task when the priority of the fifth task is lower than the priority of the fourth task, or when the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is bound to the fourth core.

[0020] In some embodiments, the control unit is further configured to, in response to the fourth core receiving a second inter-core interrupt, determine a seventh task and an eighth task; wherein the seventh task is the highest priority task among all tasks to be run in the multi-core processing system and bound to the fourth core, and the eighth task is the lowest priority task among all running tasks in the multi-core processing system, and the eighth task runs on the fifth core; if the priority of the seventh task is greater than the priority of the eighth task, a context switch is triggered on the fourth core to execute the seventh task and a first inter-core interrupt is sent to the fifth core.

[0021] In some embodiments, the control unit is further configured to, in response to the fifth core receiving a first inter-core interrupt, trigger the fifth core to execute a task interrupt handling process, the task interrupt handling process being configured to trigger the core that received the first inter-core interrupt to execute task scheduling, so as to prioritize the processing of high-priority tasks.

[0022] In some embodiments, the task interruption handling process includes: determining the ninth task; the ninth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the core that received the first inter-core interrupt; if the priority of the ninth task is greater than the priority of the tenth task, triggering the execution context switch of the core that received the first inter-core interrupt to execute the ninth task; wherein, the tenth task is the task that the core that received the first inter-core interrupt is currently running.

[0023] Thirdly, this application provides an electronic device comprising: a processor and a memory; the memory storing processor-executable instructions; when the processor is configured to execute the instructions, causing the electronic device to implement the method of the first aspect described above.

[0024] Fourthly, this application provides a computer-readable storage medium comprising: computer software instructions; which, when executed in an electronic device, cause the electronic device to implement the method described in the first aspect.

[0025] Fifthly, the present invention provides a vehicle that includes the electronic equipment described in the third aspect, or the vehicle that includes the computer-readable storage medium described in the fourth aspect.

[0026] Sixthly, this application provides a computer program product comprising a computer program; when the computer program is run in an electronic device, it causes the electronic device to implement the method described in the first aspect.

[0027] The beneficial effects of the second to sixth aspects mentioned above are described in the corresponding description of the first aspect and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 A flowchart illustrating a task scheduling method provided in an embodiment of this application; Figure 2 A flowchart illustrating another task scheduling method provided in this application embodiment; Figure 3 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 4 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 5 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 6 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 7 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 8 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 9 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 10 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 11 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 12 A flowchart illustrating yet another task scheduling method provided in this application embodiment; Figure 13 This is a schematic diagram of the structure of a task scheduling device provided in an embodiment of this application; Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] In the embodiments of this application, the terms "first," "second," "third," "fourth," "fifth," and "sixth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," "third," "fourth," "fifth," and "sixth" may explicitly or implicitly include one or more of that feature.

[0031] In embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0032] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0033] In existing priority-based symmetric multi-processing (SMP) real-time operating systems (RTOS), tasks are divided into two categories: global tasks not bound to any processor core, and local tasks bound to a specific processor core. When a new task is activated on a core due to an interrupt or system function call, existing scheduling methods handle it differently depending on the task type. However, in scenarios where global task activation is frequent, these scheduling methods incur unnecessary system overhead, leading to resource waste. This problem is particularly prominent in intelligent driving and vehicle control scenarios. For example, in intelligent driving domain controllers, safety-critical tasks such as automatic emergency braking are typically bound to specific cores, while computationally intensive global tasks such as LiDAR point cloud processing and image recognition are frequently activated. Existing scheduling methods need to trigger global scheduling decisions and lock operations each time a global task is activated. The accumulated system overhead may interfere with the real-time response of safety tasks on the bound core, posing a potential threat to driving safety. Therefore, how to reduce unnecessary scheduling overhead when tasks are frequently activated in a multi-core SMP RTOS has become an urgent technical problem to be solved.

[0034] To address the aforementioned technical problems, embodiments of this application provide a task scheduling method and electronic device, which can improve the resource utilization efficiency of task scheduling in a multi-core processing system. The task scheduling method is as follows: in response to the activation of a first task on a first core in a multi-core processing system, a second task is determined; the second task is the lowest priority task among all running tasks in the multi-core processing system; when the priority of the first task is greater than the priority of the second task, and the first task is not bound to the first core, the first core is controlled to send an inter-core interrupt to the second core in the multi-core processing system, where the second core is the core running the second task.

[0035] The task scheduling method provided in this application can be applied to a multi-core processing system containing at least two processor cores. These cores exchange data via shared memory and support inter-core interrupt mechanisms. Specifically, the multi-core processing system can be an automotive-grade multi-core chip in a smart driving domain controller or smart cockpit system, such as TDA4, Orin, or TC397. These automotive-grade multi-core chips need to simultaneously handle high real-time safety tasks such as automatic emergency braking and lane keeping assist, as well as computationally intensive tasks such as multi-sensor fusion and deep learning inference, in smart driving scenarios. This task scheduling method can be executed by any functional module within the multi-core processing system that possesses scheduling decision-making capabilities. These functional modules include, but are not limited to: a global scheduler running in the operating system kernel, scheduling logic instances running on each processor core, hardware scheduling circuits embedded in the processor core, or any combination thereof.

[0036] In order to implement the task scheduling method provided in this application embodiment during system operation, the system maintains two core data structures, namely the running task table and the pending task table.

[0037] The task execution table is a globally visible table used to record information about the tasks currently running on each processor core. Assuming the system contains N processor cores (hereinafter referred to as "cores"), the task execution table can be understood as an array of length N, where the i-th entry stores the identifier and priority of the task currently running on the i-th core. This table is dynamically updated during each task switch, allowing the system to know the real-time workload of all cores at any time, thus providing an accurate basis for scheduling decisions.

[0038] The pending task table is also a globally visible table used to store information about all tasks in the system that are currently ready but have not yet been granted execution rights by the Central Processing Unit (CPU). These tasks are ready to run and are waiting for a core to schedule them for execution. The pending task table is dynamically updated during scheduling; whenever a new task is activated or its status changes, the system adds or removes it from the table accordingly. This table is typically implemented using a priority queue data structure (such as a heap, red-black tree, or linked list) to quickly retrieve the highest-priority ready task.

[0039] For example, the running task table and the task to be run table can be global data structures, such as arrays or linked lists. The running task table can be organized in a way that maps task identifiers to priorities. Each table entry contains fields such as task identifier (ID), core number, and current priority.

[0040] In this application, the initialization process during system startup is as follows: First, the running task table and the pending task table are initialized to empty. After each processor core completes basic initialization operations and creates system tasks, all active tasks are added to the pending task table according to their priority and type (global task or local task). Subsequently, the system iterates through each core in turn. For the current core, a global spinlock is acquired to prevent concurrent access from multiple cores. A task with the highest priority and meeting the binding conditions is selected from the pending task table (local tasks must be bound to the current core, while global tasks have no binding restrictions). The information of this task is stored in the corresponding entry of the running task table for the current core. Then, the global spinlock is released, and the scheduler of the current core is started. After all cores have finished processing, initialization ends, and the system enters normal operation.

[0041] like Figure 1 As shown, the task scheduling method includes the following steps S101-S102: S101, In response to the activation of the first task on the first core of the multi-core processing system, determine the second task.

[0042] The second task is the lowest priority task among all running tasks in the multi-core processing system.

[0043] It should be noted that the activation of the first task means that the first task has changed from an inoperable state to a ready-to-run state, such as being woken up or newly created and then put into a ready-to-run state.

[0044] It is understandable that after a new task is activated, in order to assess whether the system needs to perform task scheduling, it is necessary to first determine the task with the lowest priority running in the entire multi-core processing system, as a reference basis for subsequent scheduling decisions.

[0045] As an optional implementation, all running tasks in a multi-core processing system and their corresponding priority information are stored in a running task table. The running task table is traversed to find the task with the lowest priority and then designated as the second task.

[0046] Specifically, during the traversal, a temporary variable is set to record the lowest priority value encountered at the moment and its corresponding task information. Initially, this temporary variable can be set to the highest priority value or the priority of the first task encountered. Then, the priority values ​​of each task in the table are compared in turn (in a system where a smaller priority value indicates a higher priority, the minimum value is compared; in a system where a larger priority value indicates a higher priority, the maximum value is compared), and finally, the task with the lowest priority in the entire system is obtained as the second task.

[0047] If multiple tasks have the same lowest priority during the traversal, one can be selected as the second task according to a preset strategy. For example, the preset strategy could be to select the task with the smaller task ID or the one with the higher core load, to facilitate task scheduling in subsequent steps.

[0048] S102. If the priority of the first task is higher than that of the second task, and the first task is not bound to the first core, control the first core to send an inter-core interrupt to the second core in the multi-core processing system.

[0049] Specifically, after determining the second task through S101, the priority relationship between the first task and the second task is further determined, as well as whether the first task has a binding constraint with the first core.

[0050] As an optional implementation, the priorities of the first task and the second task are compared. If the priority of the first task is higher than that of the second task, it indicates that the newly activated task is more urgent or important than a currently running task in the system. To ensure that the high-priority task runs first, scheduling optimization is required. Simultaneously, it is also necessary to determine whether the first task is bound to a first core. Task-core binding means that the task is restricted to running on only one or more specified cores through the operating system interface (e.g., CPU affinity settings). If the first task is bound to a first core, it means that the first task cannot be migrated to other cores for execution. In this case, it is not suitable to initiate an inter-processor interrupt (IPI) to adjust the running core of the first task. In the embodiments of this application, unless otherwise specified, by default, a task bound to a core is only bound to one core.

[0051] Therefore, if the following conditions are met for the first task: its priority is higher than the second task's priority, and the first task is not bound to the first core, then a cross-core scheduling operation is triggered: the first core sends an inter-core interrupt to the second core. The second core is the core currently running the second task.

[0052] The function of the first inter-core interrupt is to trigger the core that receives the interrupt to perform rescheduling according to the preset scheduling rules, so that the core that receives the first inter-core interrupt can prioritize the task that is more suitable to run.

[0053] As another possible implementation, before sending the first inter-core interrupt, it can be further determined whether the first core and the second core are the same core. If the first core and the second core are the same core, there is no need to send the first inter-core interrupt, because the first task and the second task are on the same core, and a local priority preemption mechanism can be used for handling this. Only when the first core and the second core are different cores should the step of sending the first inter-core interrupt be executed.

[0054] In this way, this embodiment can promptly notify the other core running the lowest priority task when a newly activated high-priority task is not bound to the current core in a multi-core processing system, thus providing a triggering mechanism for subsequent task reassignment and system response performance optimization.

[0055] Furthermore, such as Figure 2 As shown, the method also includes the following steps: S103. If the priority of the first task is higher than that of the second task, the first task is bound to the first core, and the third task is not bound to the first core, trigger the first core to execute the execution context switch to execute the first task, and trigger the first core to send an inter-core interrupt to the second core.

[0056] The third task is the task that the first core is currently running, while the second task is marked as a task to be run.

[0057] It's understandable that if the first task is bound to the first core, it means that the first task cannot be migrated to other cores for execution. In this case, it's necessary to check whether the task currently running on the first core (i.e., the third task) is bound to the first core. If the third task is not bound to the first core, then the third task has the possibility of being migrated to other cores for execution, and the first task can preferentially run on the first core.

[0058] As one possible implementation, if it is determined that the priority of the first task is higher than that of the second task, the first task is bound to the first core, and the third task is not bound to the first core, the first core first saves the context of the third task and puts the third task into the task list to be run, then restores the context of the first task and starts executing the first task; after saving the context of the third task and before restoring the context of the first task, the first core sends an inter-core interrupt to the second core.

[0059] This application embodiment also provides the following steps S104 and S105: S104. If the priority of the first task is higher than that of the second task, the first task is bound to the first core, the third task is bound to the first core, and the priority of the first task is higher than that of the third task, trigger the execution context switch of the first core to execute the first task.

[0060] It should be understood that when both the first task and the third task are bound to the first core, neither can be migrated to other cores for execution. In this case, if the first task has a higher priority than the third task, it must be executed first within its own core. Specifically, the context of the third task is saved and returned to the task list, the context of the first task is restored, and execution of the first task begins.

[0061] It should be noted that since both the first and third tasks are bound to the first core and do not require the participation of other cores, there is no need to send inter-core interrupts.

[0062] S105. If the priority of the first task is greater than the priority of the second task, the first task is bound to the first core, the third task is bound to the first core, and the priority of the first task is less than or equal to that of the third task, maintain the current running state and end the current scheduling process.

[0063] Specifically, if both the first task and the third task are bound to the first core, and the priority of the first task is less than or equal to that of the third task, then the currently running third task has a higher or equal priority, and the first task does not need to run first. Therefore, the first core continues to execute the third task, while the first task remains in a pending state, waiting for the next scheduling opportunity, and this scheduling process ends.

[0064] To more clearly illustrate the triggering process of the above situations, this application embodiment also provides a flowchart of another task scheduling method, such as... Figure 3 As shown, it includes the following steps: a1. The first task on the first core is activated.

[0065] a2. Determine the second task.

[0066] The second task is the lowest priority task among all currently running tasks in the multi-core processing system.

[0067] a3. Determine whether the priority of the first task is greater than the priority of the second task.

[0068] If so, proceed to step a4; If not, proceed to step a11.

[0069] a4. Determine whether the first task is bound to the first core.

[0070] If so, proceed to step a5; If not, proceed to step a10.

[0071] a5. Determine the third task.

[0072] The third task is the task currently running on the first core.

[0073] a6. Determine whether the third task is bound to the first core.

[0074] If so, proceed to step a7; If not, proceed to step a9.

[0075] a7. Determine whether the priority of the first task is higher than that of the third task.

[0076] If so, proceed to step a8; If not, proceed to step a11.

[0077] a8. Switching to the first core execution task.

[0078] Switching to the first core execution task refers to switching the currently running task to the first task.

[0079] After completing step a8, continue with step a11.

[0080] a9. The first core performs task switching and sends an inter-core interrupt to the second core.

[0081] After completing step a9, continue with step a11.

[0082] a10. The first core sends an inter-core interrupt to the second core.

[0083] a11. Terminate the current scheduling process.

[0084] This application also provides a processing flow for the second core after receiving an inter-core interrupt.

[0085] like Figure 4 As shown, the method also includes: S201. In response to the second core receiving an inter-core interrupt, the second core is triggered to execute the task interrupt handling process.

[0086] The task interrupt handling process is used to trigger the core execution task scheduling upon receiving the first inter-core interrupt, so that high-priority tasks can be processed first. The specific steps of this task interrupt handling process are described in S501-S502 below.

[0087] This embodiment, based on the above embodiments, further describes a scheduling method when a task on a certain core of a multi-core processing system finishes running.

[0088] like Figure 5 As shown, the method includes the following steps: S301. In response to the completion of the current task of the third core in the multi-core processing system, determine the fourth and fifth tasks.

[0089] The fourth task is the highest priority task among all tasks waiting to run in a multi-core processing system that can be run by the third core. In other words, among all tasks that are waiting to run and are not bound to other cores (or whose CPU affinity binding set includes the third core), the highest priority task is determined as the fourth task.

[0090] The fifth task is the highest-priority task among all tasks to be run in a multi-core processing system that are bound to a core. That is, among all tasks to be run that have CPU affinity constraints (such as being bound to one or more specific cores), the highest-priority task is determined to be the fifth task.

[0091] It's understandable that when a current task on a core finishes running, the system needs to select a new task from the waiting list to execute. To fully utilize multi-core resources and avoid high-priority bound tasks remaining unscheduled for extended periods, it's necessary to consider both the highest-priority locally available task and the highest-priority task among globally bound tasks.

[0092] S302. When the priority of the fifth task is higher than that of the fourth task, the fifth task is bound to the fourth core, and the sixth task is not bound to the fourth core, control the third core to send an inter-core interrupt to the fourth core.

[0093] The sixth task is the task currently running on the fourth core.

[0094] Specifically, if the priority of the fifth task is higher than that of the fourth task, it indicates that a high-priority bound task is waiting to be scheduled, and the core to which this task is bound (the fourth core) is currently running another task (the sixth task). In this case, if the sixth task is not bound to the fourth core (i.e., the sixth task can be migrated to another core), there is room for optimization. Therefore, the control third core sends a second inter-core interrupt to the fourth core. The second inter-core interrupt is used to trigger the fourth core to perform rescheduling according to preset scheduling rules, so that the task currently more suitable for execution is prioritized on the fourth core, rather than being limited to executing a specific task.

[0095] As one possible implementation, after the third core finishes running its task, it traverses the list of tasks to be run, selects the fourth and fifth tasks respectively, and determines whether to send an inter-core interrupt based on the above conditions.

[0096] Furthermore, this application also provides a scenario where no inter-core interrupt needs to be sent.

[0097] like Figure 6 As shown, the method includes the following steps: S303. If the priority of the fifth task is lower than that of the fourth task, or if the priority of the fifth task is higher than that of the fourth task, the fifth task is bound to the fourth core, and the sixth task is bound to the fourth core, the execution context switch of the third core is triggered to execute the fourth task.

[0098] Specifically, in the following two cases, there is no need to send an inter-core interrupt to the fourth core; instead, the third core directly performs the local task switch: Scenario 1: The priority of the fifth task is lower than that of the fourth task. In this case, the highest priority task that can be run locally (the fourth task) is higher than any bound task, and no cross-core intervention is required. The third core can directly execute the fourth task.

[0099] The second scenario: The fifth task has a higher priority than the fourth task, but the fifth task is bound to the fourth core, and the sixth task (the task currently running on the fourth core) is also bound to the fourth core. In this case, because the sixth task is also bound to the fourth core and cannot be migrated, even if the fifth task has a higher priority, it cannot be scheduled to execute on the fourth core, and cross-core interrupts do not bring scheduling benefits. Therefore, the fourth task is executed directly by the third core.

[0100] By employing the two scenarios described above, invalid inter-core interrupt transmissions can be avoided, thus reducing system overhead.

[0101] As one possible implementation, the third core saves the context of the current task, restores the context of the fourth task, and begins executing the fourth task when performing a context switch.

[0102] To more clearly illustrate the triggering process for each scenario after the completion of the aforementioned core current task, this application embodiment also provides a flowchart of another task scheduling method, such as... Figure 7 As shown, it includes the following steps: b1. The current task of the third core has ended.

[0103] b2. Determine the fourth and fifth tasks.

[0104] Among them, the fourth task is the highest priority task among all tasks currently waiting to run in the multi-core processing system that can be run by the third core, and the fifth task is the highest priority task among all tasks currently waiting to run in the multi-core processing system that are bound to the core.

[0105] b3. Determine whether the priority of the fifth task is greater than the priority of the fourth task.

[0106] If so, proceed to step b4; If not, proceed to step b6.

[0107] b4. Determine whether the sixth task is bound to the fourth core.

[0108] Among them, the sixth task is the task currently running on the fourth core, and the fourth core is the core bound to the fifth task.

[0109] If so, proceed to step b6; If not, proceed to step b5.

[0110] b5. The third core sends an inter-core interrupt to the fourth core.

[0111] b6. Switching to the third core execution task.

[0112] The third core task switching refers to switching the currently running task to the fourth task.

[0113] b7. Terminate the current scheduling process.

[0114] This application also provides a processing flow for the fourth core after receiving an inter-core interrupt.

[0115] like Figure 8 The methods implemented include: S401, in response to the fourth core receiving an inter-core interrupt from the second core, determines the seventh and eighth tasks.

[0116] The seventh task is the highest-priority task among all tasks bound to the fourth core in the multi-core processing system. In other words, the highest-priority task is selected as the seventh task from all tasks bound to the fourth core.

[0117] The eighth task is the lowest priority task among all running tasks in the multi-core processing system, and it runs on the fifth core. Specifically, the task list is traversed to find the lowest priority task among all running tasks, which is then designated as the eighth task, and its core is recorded as the fifth core.

[0118] It is understandable that when the fourth core receives an interrupt from the second core, it needs to further evaluate whether it needs to perform a task switch and whether it needs to initiate an interrupt to other cores in order to achieve cascading scheduling optimization.

[0119] S402. If the priority of the seventh task is higher than that of the eighth task, trigger the fourth core to execute the execution context switch to execute the seventh task and send the first core interrupt to the fifth core.

[0120] Specifically, the priorities of the seventh and eighth tasks are compared. If the priority of the seventh task is higher than that of the eighth task, it indicates that there is a high-priority bound task (the seventh task) waiting to be executed on the fourth core, while a lower-priority task (the eighth task) is occupying the fifth core. At this time, the fourth core performs a context switch: it saves the context of the currently running task (i.e., the sixth task), restores the context of the seventh task, and begins executing the seventh task. Simultaneously, the fourth core sends a first inter-core interrupt to the fifth core. The function of this interrupt is the same as that of the first inter-core interrupt in S102 above, both used to trigger the core that receives the first inter-core interrupt to execute the task scheduling process. For the specific processing flow, please refer to the descriptions in S701-S702 below.

[0121] To more clearly illustrate the scheduling process after the core receives the second inter-core interrupt, this application provides a flowchart of another task scheduling method, such as... Figure 9 As shown, it includes the following steps: c1, The fourth core received an inter-core interrupt.

[0122] c2. Determine the seventh and eighth tasks.

[0123] Among them, the seventh task is the highest priority task among all tasks waiting to run in the multi-core processing system and bound to the fourth core, and the eighth task is the lowest priority task among all tasks currently running in the multi-core processing system.

[0124] c3. Determine whether the priority of the seventh task is higher than the priority of the eighth task.

[0125] If so, proceed to step c4; If not, proceed to step c5.

[0126] c4, the fourth core performs task switching and sends an inter-core interrupt to the fifth core.

[0127] Among them, the fourth core task switching refers to switching the currently running task to the seventh task, and the fifth core is the core that runs the eighth task.

[0128] c5. Terminate the current scheduling process.

[0129] This application embodiment also provides a processing flow for the fifth core after receiving an inter-core interrupt.

[0130] like Figure 10 As shown, the method also includes: S601: In response to the fifth core receiving an inter-core interrupt, the fifth core is triggered to execute the task interrupt handling process.

[0131] The task interrupt handling process is used to trigger the core execution task scheduling upon receiving the first inter-core interrupt, so that high-priority tasks can be processed first. The specific steps of this task interrupt handling process are described in S501-S502 below.

[0132] Based on the above embodiments, this embodiment further refines the task interruption handling process, specifically describing how the core that receives the first inter-core interrupt determines whether to perform a task switch.

[0133] like Figure 11 As shown, the task interruption handling process includes: S701. Determine the ninth task.

[0134] Among them, the ninth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the core that receives the first inter-core interrupt, including tasks bound to the core that receives the first inter-core interrupt, or tasks not bound to any core (global tasks).

[0135] Specifically, after the core receives the first core, it traverses the task list to be run, filters out the highest priority task among the tasks that the core that received the first inter-core interrupt can run, and then compares the priorities of these candidate tasks, selecting the highest priority task as the ninth task.

[0136] S702. If the priority of the ninth task is greater than that of the tenth task, trigger a core execution context switch to execute the ninth task after receiving the first inter-core interrupt.

[0137] The tenth task is the task that the core is running when it receives the first inter-core interrupt.

[0138] It's understandable that the purpose of inter-core interrupts is to notify the target core (the core that received the first inter-core interrupt) that a higher-priority task needs to be scheduled. However, the target core cannot switch blindly; it needs to make a judgment based on its own actual situation. Specifically, the target core compares the priority of the ninth task (the highest-priority task among all pending tasks that the target core can run) with the currently running tenth task. If the priority of the ninth task is higher than that of the tenth task, it indicates that there is a higher-priority bound task waiting to be executed on this core, and the currently running task should yield processor resources.

[0139] As one possible implementation, the core that receives the first inter-core interrupt executes the following process: In response to receiving the first inter-core interrupt, it pauses the currently executing tenth task, saves the context of the tenth task, traverses the task list to be run, filters out all tasks bound to this core to be run, selects the task with the highest priority as the ninth task, and compares the priority of the ninth task with the priority of the tenth task. If the priority of the ninth task is greater than the priority of the tenth task, a context switch is performed: the context of the ninth task is restored, and the execution of the ninth task begins; at the same time, the status of the tenth task is updated to the pending state, and it is put back into the task list to be run. If the priority of the ninth task is less than or equal to the priority of the tenth task, no task switch is performed, and the execution of the tenth task is resumed.

[0140] As a further optimization, if the priority of the ninth task is equal to the priority of the tenth task, the system can handle it according to the default scheduling policy, such as continuing to execute the tenth task until its time slice is used up, or switching according to the round-robin scheduling policy.

[0141] It is understood that, through the above task interruption handling process, this embodiment ensures that the core that receives the inter-core interrupt will only perform task preemption switching when there is indeed a higher priority task that can run, thus avoiding unnecessary context switching overhead and ensuring that high-priority bound tasks can be processed in a timely manner.

[0142] Figure 12 The specific scheduling process of the task interruption procedure is shown, such as... Figure 12 As shown, it includes the following steps: d1. Determine the ninth task.

[0143] Among them, the ninth task is the highest priority task among all tasks that are waiting to run in the multi-core processing system and that can be run by the core that receives the first inter-core interrupt.

[0144] d2. Determine whether the priority of the ninth task is greater than the priority of the tenth task.

[0145] The tenth task is the task that the core is running when it receives the first inter-core interrupt.

[0146] If so, proceed to step d3; If not, proceed to step d4.

[0147] d3. Upon receiving the first inter-core interrupt, the core execution task is switched.

[0148] Among them, receiving the first inter-core interrupt and switching the core execution task refers to switching the currently running task to the ninth task.

[0149] d4. Terminate the current scheduling process.

[0150] It should be noted that the core number in this embodiment is only used to distinguish the descriptions in different processes and does not constitute a limitation on the core identity.

[0151] Through the above mechanism, this embodiment realizes the optimization of task scheduling cascaded between multiple cores, so that high-priority bound tasks can obtain execution resources step by step, and low-priority tasks are gradually pushed to more suitable cores.

[0152] As can be seen, the above mainly describes the solutions provided by the embodiments of this application from a methodological perspective. To achieve the above functions, the embodiments of this application provide corresponding hardware structures and / or software modules for executing each function. Those skilled in the art should readily recognize that, in conjunction with the modules and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed by hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0153] This application embodiment can divide the task scheduling device into functional modules according to the above method example. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware or as a software functional module. Optionally, the module division in this application embodiment is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0154] Figure 13 This is a schematic diagram of a task scheduling device provided in an embodiment of this application, used to implement the task scheduling method provided in the above embodiments, such as... Figure 13As shown, the task scheduling device 500 includes a processing unit 501 and a control unit 502; the processing unit 501 is used to determine a second task in response to the activation of a first task on a first core in a multi-core processing system; the second task is the lowest priority task among all running tasks in the multi-core processing system; the control unit 502 is used to control the first core to send a first inter-core interrupt to the second core in the multi-core processing system when the priority of the first task is greater than the priority of the second task and the first task is not bound to the first core, the second core being the core running the second task.

[0155] In some embodiments, the first task is marked as the task to be run.

[0156] In some embodiments, the control unit 502 is further configured to, when the priority of the first task is greater than the priority of the second task, the first task is bound to the first core, and the third task is not bound to the first core, trigger the first core to execute a context switch to execute the first task, and trigger the first core to send a first inter-core interrupt to the second core; wherein the third task is the task currently running on the first core, and the second task is marked as a task to be run.

[0157] In some embodiments, the control unit 502 is further configured to trigger a task interrupt handling process of the second core in response to the second core receiving an inter-core interrupt of the first core. The task interrupt handling process is configured to trigger the core that received the inter-core interrupt to execute task scheduling so as to prioritize the processing of high-priority tasks.

[0158] In some embodiments, the control unit 502 is further configured to, in response to the completion of the current task execution of the third core in the multi-core processing system, determine the fourth task and the fifth task; the fourth task is the highest priority task among all tasks to be run in the multi-core processing system that the third core can run, and the fifth task is the highest priority task among all tasks to be run in the multi-core processing system that are bound to a core; if the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is not bound to the fourth core, control the third core to send a second core intermediate message to the fourth core; the sixth task is the task currently running on the fourth core.

[0159] In some embodiments, the control unit 502 is further configured to trigger a third core execution context switch to execute the fourth task when the priority of the fifth task is lower than the priority of the fourth task, or when the priority of the fifth task is higher than the priority of the fourth task, the fifth task is bound to the fourth core, and the sixth task is bound to the fourth core.

[0160] In some embodiments, the control unit 502 is further configured to, in response to the fourth core receiving a second inter-core interrupt, determine a seventh task and an eighth task; wherein the seventh task is the highest priority task among all tasks to be run in the multi-core processing system and bound to the fourth core, the eighth task is the lowest priority task among all running tasks in the multi-core processing system, and the ninth task runs on the fifth core; if the priority of the seventh task is greater than the priority of the eighth task, the fourth core is triggered to perform a context switch to execute the seventh task and send a first inter-core interrupt to the fifth core.

[0161] In some embodiments, the control unit 502 is further configured to trigger a task interrupt handling process of the fifth core in response to the fifth core receiving a first inter-core interrupt. The task interrupt handling process is configured to trigger the core that received the first inter-core interrupt to execute task scheduling so as to prioritize the processing of high-priority tasks.

[0162] In some embodiments, the task interruption handling process includes: determining a ninth task; the ninth task is the highest priority task among all tasks to be run in the multi-core processing system that are bound to the core that received the first inter-core interrupt; if the priority of the ninth task is greater than the priority of the tenth task, triggering a core execution context switch to execute the ninth task; wherein the tenth task is the task that the core that received the first inter-core interrupt is currently running.

[0163] In the case of implementing the functions of the integrated modules described above in hardware, this embodiment of the invention provides a possible structural schematic diagram of the electronic device involved in the above embodiments. For example... Figure 14 As shown, the electronic device 600 includes: a processor 602, a communication interface 603, and a bus 604. Optionally, the electronic device 600 may also include a memory 601.

[0164] Processor 602 may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 602 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It may implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 602 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0165] Communication interface 603 is used to connect to other devices via a communication network. This communication network can be Ethernet, wireless access network, wireless local area network (WLAN), etc.

[0166] The memory 601 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0167] In one possible implementation, the memory 601 can exist independently of the processor 602. The memory 601 can be connected to the processor 602 via a bus 604 and is used to store instructions or program code. When the processor 602 calls and executes the instructions or program code stored in the memory 601, it can implement the task scheduling method provided in this embodiment of the invention.

[0168] In another possible implementation, the memory 601 can also be integrated with the processor 602.

[0169] Bus 604 can be an extended industry standard architecture (EISA) bus, etc. Bus 604 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 14 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0170] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the service calling device can be divided into different functional modules to complete all or part of the functions described above.

[0171] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be instructed by computer program instructions to be completed by related hardware. This program can be stored in the aforementioned computer-readable storage medium. When the computer program instructions are executed on a computer, they cause the computer to perform the task scheduling method as described in any of the above embodiments.

[0172] Exemplary examples of computer-readable storage media may include, but are not limited to: magnetic storage devices (e.g., hard disks, floppy disks, or magnetic tapes), optical discs (e.g., compact disks (CDs), digital versatile disks (DVDs), etc.), smart cards, and flash memory devices (e.g., erasable programmable read-only memory (EPROMs), cards, sticks, or key drives, etc.). The various computer-readable storage media described in this disclosure may represent one or more devices and / or other machine-readable storage media for storing information. The term "machine-readable storage medium" may include, but is not limited to, wireless channels and various other media capable of storing, containing, and / or carrying instructions and / or data.

[0173] This application also provides a computer program product, which includes a computer program that, when run on a computer, causes the computer to execute any of the task scheduling methods provided in the above embodiments.

[0174] In the description of the embodiments of this application, specific features, structures, materials or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0175] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A task scheduling method, characterized by, The method is applied to a multi-core processing system, and the method includes: In response to the activation of a first task on a first core of the multi-core processing system, a second task is determined; the second task is the lowest priority task among all running tasks in the multi-core processing system. If the priority of the first task is greater than that of the second task, and the first task is not bound to the first core, the first core is controlled to send a first inter-core interrupt to the second core in the multi-core processing system, where the second core is the core running the second task.

2. The method of claim 1, wherein, The first task is marked as a task to be run.

3. The method of claim 1, wherein, The method further includes: If the priority of the first task is greater than that of the second task, the first task is bound to the first core, and the third task is not bound to the first core, the first core is triggered to execute the execution context switch to execute the first task, and the first core is triggered to send the first inter-core interrupt to the second core. The third task is the task that the first core is currently running, while the second task is marked as a task to be run.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: In response to the second core receiving the first inter-core interrupt, the second core is triggered to execute a task interrupt handling process. The task interrupt handling process is used to trigger the core that received the first inter-core interrupt to execute task scheduling so that high-priority tasks can be processed first.

5. The method of claim 1, wherein, The method further includes: In response to the completion of the current task of the third core in the multi-core processing system, a fourth task and a fifth task are determined; the fourth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the third core, and the fifth task is the highest priority task among all tasks to be run in the multi-core processing system that are bound to the core. If the fifth task has a higher priority than the fourth task, and the fifth task is bound to the fourth core while the sixth task is not bound to the fourth core, then the third core is controlled to send the second inter-core intermediate data to the fourth core. The sixth task is the task that the fourth core is currently running.

6. The method according to claim 5, characterized in that, The method further includes: If the priority of the fifth task is lower than that of the fourth task, or if the priority of the fifth task is higher than that of the fourth task, and the fifth task is bound to the fourth core while the sixth task is bound to the fourth core, the execution context switch of the third core is triggered to execute the fourth task.

7. The method according to claim 5, characterized in that, The method further includes: In response to the fourth core receiving the second inter-core interrupt, a seventh task and an eighth task are determined; wherein, the seventh task is the highest priority task among all tasks to be run in the multi-core processing system and bound to the fourth core, and the eighth task is the lowest priority task among all running tasks in the multi-core processing system, and the eighth task runs on the fifth core. If the priority of the seventh task is greater than that of the eighth task, the fourth core execution context switch is triggered to execute the seventh task and send a first inter-core interrupt to the fifth core.

8. The method according to claim 7, characterized in that, The method further includes: In response to the fifth core receiving the first inter-core interrupt, the fifth core is triggered to execute a task interrupt handling process. The task interrupt handling process is used to trigger the core that received the first inter-core interrupt to execute task scheduling so that high-priority tasks can be processed first.

9. The method according to claim 4 or 8, characterized in that, The task interruption handling process includes: The ninth task is determined; the ninth task is the highest priority task among all tasks to be run in the multi-core processing system that can be run by the core that received the first inter-core interrupt. If the priority of the ninth task is greater than that of the tenth task, a core execution context switch is triggered upon receiving the first inter-core interrupt to execute the ninth task; The tenth task is the task that the core that received the first inter-core interrupt is currently running.

10. An electronic device, characterized in that, The vehicles include: Processor and memory; The memory stores processor-executable instructions; when the processor is configured to execute the instructions, the electronic device performs the method described in any one of claims 1-9.

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