Test structure and test method for drain-end disturbance reliability of memory cells

Abstract

The application discloses a test structure for drain end interference reliability of a storage unit and a test method thereof. The test structure is arranged in a cutting path of a wafer on which a storage chip is arranged. The test structure comprises at least two back-to-back storage units, i.e., a cycle storage unit and an interference storage unit. The cycle storage unit and the interference storage unit are each provided with a control gate, a floating gate, a tunneling dielectric layer and a blocking dielectric layer. The blocking dielectric layer is arranged between the control gate and the floating gate, the floating gate is arranged between the tunneling dielectric layer and the blocking dielectric layer, and the tunneling dielectric layer is arranged on the surface of a wafer substrate. The two drain ends of the cycle storage unit and the interference storage unit share one drain lead-out end. The source end / gate of the cycle storage unit and the source end / gate of the interference storage unit are respectively led out. During the test, the source end of the cycle storage unit is grounded, and the source end of the interference storage unit is applied with a test voltage. The application realizes efficient and accurate evaluation of the drain end interference problem of the NorFlash.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a test structure and test method for the reliability of drain interference in memory cells. Background Technology

[0002] In NorFlash memory, when a memory cell is repeatedly programmed or erased, a high voltage is applied to its drain. At this time, neighboring cells sharing the same bit line but whose word lines are not selected, although not actively operated, may experience floating gate charge disturbances due to the high electric field at the drain, causing threshold voltage drift. If the drift is too large, it can cause incorrect state flipping (e.g., "1" → "0"), constituting drain interference failure and severely affecting data retention reliability.

[0003] Currently, the industry commonly uses post-packaging chip reliability verification: performing up to 100,000 P / E cycles on the target cell while monitoring the V of neighboring cells. t Changes. This method has three major drawbacks: first, the testing cycle is long (weeks to months) and costly; second, it can only obtain the total V. t Drift makes it impossible to distinguish the contributions of different physical mechanisms such as inter-band tunneling and drain-source leakage; thirdly, it relies on post-packaging testing, which makes it impossible to identify risks in the early stages of wafer manufacturing, severely restricting process development efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a test structure and method for drain-end interference reliability testing of memory cells, in order to solve the problems of long testing cycles and high costs associated with the current industry-wide method of reliability verification using packaged chips, and the fact that only the total V value can be obtained. t The problems include drift, the inability to distinguish between contributions from different physical mechanisms such as inter-band tunneling and drain-source leakage; and reliance on post-packaging testing, which makes it impossible to identify risks early in the wafer manufacturing stage, severely restricting process development efficiency.

[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a test structure for the reliability of drain interference in memory cells. The test structure is disposed in the dicing channel of the wafer on which the memory chip is located. The test structure includes at least two back-to-back memory cells: a circulating memory cell and an interference memory cell. Each circulating memory cell and the interference memory cell is provided with a control gate, a floating gate, a tunneling dielectric layer and a blocking dielectric layer. The blocking dielectric layer is disposed between the control gate and the floating gate, the floating gate is disposed between the tunneling dielectric layer and the blocking dielectric layer, and the tunneling dielectric layer is disposed on the surface of the wafer substrate. The two drain terminals of the cyclic memory cell and the interference memory cell share a single drain lead; the source / gate terminals of the cyclic memory cell and the interference memory cell are each led out separately; during testing, the source terminal of the cyclic memory cell is grounded, and a test voltage is applied to the source terminal of the interference memory cell.

[0006] In one embodiment of the present invention, the tunneling medium layer is formed using the ISSG process.

[0007] In one embodiment of the present invention, the barrier dielectric layer is an ONO three-layer composite structure, which sequentially includes a bottom oxide layer, a silicon nitride layer and a top silicon oxide layer along the direction from the floating gate to the control gate.

[0008] In one embodiment of the present invention, the underlying oxide layer is formed using an in-situ water vapor fabrication process.

[0009] In one embodiment of the present invention, the silicon nitride layer is formed by a chemical vapor deposition process; the top silicon oxide layer is formed by a furnace tube thermal oxidation process.

[0010] In one embodiment of the present invention, the storage unit is a NOR flash memory.

[0011] The present invention also proposes a testing method for the test structure as described in the above embodiments, characterized in that it tests a plurality of test structures as described in the above embodiments in the wafer, and the testing method includes: S1. Initialize the storage state of the interference storage unit, and set the source terminal of the interference storage unit to the initial voltage; S2. The source voltage of the circular memory cell is set to ground. After performing erase and write operations on the circular memory cell at a preset frequency, the gate voltage of the interference memory cell is read. S3. Increase the source voltage of the interference storage cell by a preset bias amplitude, and repeat step S2. S4. Calculate the gate voltage of the interference memory cell read in step S3 and the gate voltage difference in step S2. If the gate voltage difference is greater than a first preset threshold, further increase the source voltage of the interference memory cell and repeat steps S2 and S3. If the gate voltage difference is less than or equal to the first preset threshold, end the test of this test structure.

[0012] In one embodiment of the present invention, step S2 includes at least three sequentially increasing frequencies: a first frequency, a second frequency, and a third frequency of erase / write operations, and at least the gate voltage of the interference memory cell after the third frequency is recorded.

[0013] In one embodiment of the present invention, it further includes: The gate voltage data of interfering memory cells in the test structures tested on several wafers were statistically analyzed: If the source voltage of the interference storage cell in the tested test structure is greater than or equal to the first preset bias voltage, the test structure is determined to be a leakage interference of the tunneling failure type. For the test structures of several tests, the remaining test structures after removing the test structures of the tunneling failure type are determined to be leakage interference of the leak-source leakage failure type.

[0014] In one embodiment of the present invention, the initial voltage set at the source end of the interference storage unit is zero.

[0015] This invention proposes a test structure and method for the reliability of drain interference in memory cells, achieving efficient and accurate evaluation of NorFlash drain interference problems. Specific beneficial effects are as follows: This invention adopts a standardized worst-case layout of "back-to-back shared drain", which forces the circular memory unit and the interference memory unit to share the same drain node, and truly reproduces the most severe electrical coupling scenario in the product array. This significantly improves the sensitivity, repeatability and worst-case representativeness of the test, and overcomes the problems of data dispersion and causal ambiguity caused by the random arrangement of units in traditional tests.

[0016] This invention employs an ISSG (In-situ Water Vapor Generation) process to form a tunneling dielectric layer after threshold voltage injection and before floating gate deposition. This significantly reduces the Si–H bond density in the oxide layer, effectively suppressing the formation of hydrogen traps. Consequently, it reduces Vt drift noise caused by non-interference factors, ensuring a purer test signal and improving the accuracy of reliability assessment.

[0017] This invention integrates an ISSG oxide / silicon nitride / furnace tube oxide (ONO) sandwich dielectric structure above the floating gate, which enhances the floating gate charge retention capability, significantly improves data retention performance, avoids the natural leakage of charge from masking the real drain interference effect during long-term testing, and ensures that the test results reflect the interference mechanism itself rather than the intrinsic degradation of the device.

[0018] This invention designs an iterative testing process for source voltage regulation. While keeping the drain high voltage constant, the source voltage of the interfering memory cell is gradually increased from 0 V, and the corresponding threshold voltage drift ΔVt is measured. Utilizing the strong dependence of drain-source leakage on the source-drain voltage, the programmable state threshold voltage offset ΔVt caused by drain interference is detected by increasing the source voltage. Combined with the convergence criterion of ΔVt ≤ 0.1 V, quantitative separation and proportional calculation of two types of interference mechanisms, drain-source leakage and inter-band tunneling, are achieved, providing a clear direction for process optimization. This method can quickly and cost-effectively complete a reliable assessment with a clear mechanism at the wafer level, completely eliminating the dependence on long-cycle testing after packaging and significantly shortening the development cycle.

[0019] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of threshold voltage injection and deposition of a tunneling dielectric layer in a manufacturing method of one embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of the deposition of a floating gate in a manufacturing method of one embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the deposition of a barrier medium layer in a manufacturing method of one embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the deposition and photolithography of a control gate in a manufacturing method of one embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of rapid thermal oxidation and lightly doped drain implantation in a manufacturing method of one embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram of N+ heavy doping implantation and sidewall formation in one embodiment of the manufacturing method of the present invention.

[0027] Figure 7 This is a schematic diagram of self-aligned silicide formation in a manufacturing method of one embodiment of the present invention.

[0028] Figure 8This is a schematic diagram of a test structure formed after back-end metal interconnection in a manufacturing method of one embodiment of the present invention.

[0029] Figure 9 This is a flowchart of a test method for drain interference in one embodiment of the present invention.

[0030] Figure 10 This is a flowchart of a test method for drain interference in a specific embodiment of the present invention.

[0031] Figure 11 This is a statistical diagram of drain interference for inter-band tunneling and drain-source leakage in one embodiment of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0035] The core of this invention lies in providing a test structure specifically for drain interference analysis. This structure is not a traditional memory array, but rather a pair of cells designed independently for electrical testing purposes, containing only the minimum necessary components. Its design philosophy is to simulate the relationship between adjacent cells in an array that is most susceptible to drain interference, while independently bringing out all critical nodes to allow for the application of complex biases and precise measurements.

[0036] Please see Figures 1 to 8According to an embodiment of the present invention, a test structure for the reliability of drain interference of a memory cell is provided. The test structure is disposed in the dicing channel of the wafer on which the memory chip is located. The test structure includes at least two back-to-back memory cells: a circular memory cell 110 and an interference memory cell 120. Both the circular memory cell 110 and the interference memory cell 120 are provided with a control gate 122, a floating gate 111, a tunneling dielectric layer 170 and a blocking dielectric layer 160. The blocking dielectric layer 160 is disposed between the control gate 122 and the floating gate 111, the floating gate 111 is disposed between the tunneling dielectric layer 170 and the blocking dielectric layer 160, and the tunneling dielectric layer 170 is disposed on the surface of the wafer substrate 100. In this embodiment, the two drain terminals of the cyclic memory cell 110 and the interference memory cell 120 share a single drain lead; the source terminals / gate terminals of the cyclic memory cell 110 and the interference memory cell 120 are each led out; during testing, the source terminal of the cyclic memory cell 110 is grounded, and a test voltage is applied to the source terminal of the interference memory cell 120.

[0037] In this embodiment, the test structure is set in the dicing area of ​​the wafer where the memory chip is located, thereby effectively avoiding occupying the effective functional area of ​​the chip and not affecting the layout and integration density of the main memory array.

[0038] In this embodiment, the construction and forming process of the test structure are as follows: Please see Figure 1 , Figure 8 As shown, in this embodiment, a semiconductor substrate 100, such as a P-type silicon substrate, is provided. A threshold voltage layer 101 is formed on the surface region of the substrate 100 by ion implantation to adjust the threshold voltage required for the memory cell. Depending on the process requirements, an N-well or P-well (not shown separately in the figure) can be formed on the substrate to accommodate the memory cell. Two adjacent memory cells symmetrically arranged about a common drain are formed on the substrate 100. These two cells are designed to be as consistent as possible in physical structure and electrical characteristics to eliminate test errors introduced by asymmetry. One is defined as a loop memory cell 110, and the other as a distractor memory cell 120. The two drains of the loop memory cell 110 and the distractor memory cell 120 share a single drain terminal. This drain terminal is located between the two cells and is formed by high-concentration doping (e.g., N+). This is a key design feature simulating the shared bit line contact between adjacent cells on the same column (bit line) in a real array. The loop memory cell 110 has its own independent source terminal 150, and the distractor memory cell 120 has its own independent source terminal 150. The source end is also a highly doped region (e.g., N+). Independent source end connections allow for individual control of the source end potential and measurement of the source end current for each cell.

[0039] Please see Figure 1 , Figure 2 , Figure 3 , Figure 8 As shown, in this embodiment, each memory cell includes a floating gate 111. The floating gate 111 of the loop memory cell 110 is located above the tunneling dielectric layer 170; the floating gate 111 of the interfering memory cell 120 is also located above the tunneling dielectric layer 170. The floating gate 111 is typically made of polysilicon. Above the floating gate 111, a barrier dielectric layer 160, such as an ONO (oxide-nitride-oxide) stack, is covered. Above the barrier dielectric layer 160, a control gate 122 for each cell is formed. The control gate 122 of the loop memory cell 110 and the control gate 122 of the interfering memory cell 120 are physically separate. The control gate 122 is also typically made of polysilicon and is connected upwards to the word line. In this test structure, the control gate 122 is led out as an independent electrical node.

[0040] Please see Figure 1 , Figure 2 , Figure 3 , Figure 8 As shown, in this embodiment, a high-quality tunneling dielectric layer 170 is formed between the substrate 100 and each floating gate 111. This is the main channel for charge to enter and exit the floating gate 111. Specifically, after threshold voltage injection and before floating gate 111 deposition, the tunneling dielectric layer 170 is formed using an ISSG (In-Situ Steam Generation) process, which significantly reduces the Si–H bond density in the oxide layer, effectively suppresses the formation of hydrogen traps, thereby reducing threshold voltage Vt drift noise caused by non-interference factors, ensuring a purer test signal, and improving the accuracy of reliability assessment.

[0041] In this configuration, the control gate 122 of the circular memory cell 110, the control gate 122 and drain of the interference memory cell 120, the source terminal 150 of the circular memory cell 110, the source terminal 150 of the interference memory cell 120, and the substrate 100 are all connected to the probe pads via back-end metal interconnects to support independent biasing and signal monitoring of each node during testing. For example, to achieve independent biasing and monitoring of all critical nodes, the following nodes are led out to the probe pads surrounding the test structure via back-end metal interconnect technology (e.g., multilayer metal wiring): Control gate pad of the circular memory cell: connected to the control gate 122 of the circular memory cell 110.

[0042] Interference memory cell control gate pad: Control gate 122 connected to interference memory cell 120.

[0043] The two drains of the circular memory cell and the interfering memory cell share a single drain lead: connected to the common drain. For example, the two drains of the circular memory cell and the interfering memory cell are connected to the same metal wire through a single drain lead and then led out to the probe pad.

[0044] Source pad of circular memory cell: connected to the source region 150 of circular memory cell 110.

[0045] Interference memory cell source region pad: connected to the source region 150 of interference memory cell 120.

[0046] Substrate / well contact pads: Connected to substrate 100 or the corresponding well region.

[0047] Please see Figure 8 As shown, in this embodiment, the barrier dielectric layer 160 is an ONO three-layer composite structure, sequentially comprising a bottom oxide layer, a silicon nitride layer, and a top silicon oxide layer along the direction from the floating gate 111 to the control gate 122. This structure has a high dielectric constant and excellent charge blocking capability, which is crucial for ensuring the programming / erasing efficiency and data retention of the memory cell. Its fabrication process strictly follows specific process flows and material selection, and the specific layered structure and formation method are as follows: Formation of the bottom oxide layer: On the top surface of the floating gate 111, a high-quality silicon dioxide film is grown using the same in-situ vapor generation (ISSG) oxidation process as the aforementioned tunneling dielectric layer 170, serving as the bottom oxide layer of the ONO stack. It is understood that the ISSG process can form a dense silicon dioxide layer with low defect density on the polysilicon surface, creating an excellent interface with the polysilicon of the floating gate 111, laying a solid foundation for the entire IPD structure. Since the tunneling dielectric layer 170 also uses the ISSG process, it is possible to prepare the critical oxide layer in the same process module or using similar process conditions, which is beneficial for process control and maintaining the consistency of film quality.

[0048] Formation of the silicon nitride layer: A thin silicon nitride film is deposited on top of the underlying oxide layer using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). As can be understood, the silicon nitride layer is the core of the ONO structure. Its dielectric constant is higher than that of silicon dioxide, effectively increasing the coupling capacitance per unit area of ​​the control gate 122-floating gate 111 (i.e., increasing the coupling ratio), which is crucial for reducing the programming / erasing operation voltage. Simultaneously, silicon nitride is an excellent charge blocking layer, significantly suppressing charge leakage through the IPD layer under high temperatures or high electric fields, enhancing data retention capabilities. By precisely controlling the proportions, temperature, pressure, and time of the reactant gases, the thickness, refractive index, and stress of the silicon nitride layer can be precisely controlled to optimize its electrical performance and reliability.

[0049] Formation of the top oxide layer: A top silicon dioxide layer is grown on top of the silicon nitride layer using a high-temperature furnace oxidation process. For example, a silicon wafer with a deposited silicon nitride layer is placed in a diffusion furnace and oxidized at high temperature. During this process, oxygen or water vapor passes through the growing top oxide layer and reacts with the underlying silicon nitride layer, converting a portion of its top layer into silicon dioxide. It is understandable that the furnace oxidation process not only grows a dense oxide layer but also forms a smooth, high-quality transition interface between the silicon nitride and the top oxide layer, significantly improving the overall charge blocking performance and breakdown voltage of the ONO structure. The resulting composite top layer effectively suppresses the trapping and release of charges in the silicon nitride layer, reducing the charge instability of the IPD layer itself, which is crucial for the long-term stability and measurement accuracy of the test structure.

[0050] Understandably, when using the test structure of this invention for drain interference evaluation, the cyclic memory cell 110 will be subjected to repeated high-voltage P / E stress. A high-quality ONO blocking dielectric layer 160 can: ensure the stability of the behavior of the cyclic memory cell 110 itself: excellent charge blocking performance ensures that parasitic charge transport occurring through the blocking dielectric layer 160 during the programming / erasing process of the cyclic memory cell 110 is minimized, making the stress conditions (high voltage) applied to the drain of the cyclic memory cell 110 purer and more controllable, mainly acting on the expected FN tunneling mechanism. Ensure the accuracy of the measurement of the interfering memory cell 120: for the interfering memory cell 120, the stability of the charge of its floating gate 111 is the basis for measuring the threshold voltage of the interfering memory cell 120. An ONO IPD layer with high charge blocking capability can maximize the isolation of coupling interference from the control gate 122 potential change of the interference storage cell 120 to the floating gate 111, and prevent charge disturbances in the environment or during the measurement process, ensuring that the measured interference monitoring cell threshold voltage mainly originates from the high electric field of the drain electrode of the tunneling dielectric layer 170 below it, rather than other parasitic paths.

[0051] Please see Figure 5 , Figure 6 , Figure 7 , Figure 8As shown, in this embodiment, the present invention specifically optimizes the sidewall structure and the morphology of the control gate 122 to accurately simulate the special physical structure of "back-to-back" adjacent cells and control the parasitic capacitance between them. A first sidewall 181 is defined and formed on the side where the two memory cells are close to each other, i.e., the gate sidewall facing the common drain. A second sidewall 182 is defined and formed on the side where the two memory cells are far apart, i.e., the gate sidewall facing their respective independent source ends. Through specific process control, the height of the first sidewall 181 is made higher than the height of the second sidewall 182. This height difference can be achieved through various methods, such as: after conformal deposition of the sidewall material, using an angle-dependent anisotropic etching technique combined with specific crystal orientation or mask blocking to achieve asymmetric removal of the sidewall material on both sides of the gate stack, thereby forming a height difference. As a direct result of or part of the collaborative design of the aforementioned asymmetric sidewall structure, the morphology of the control gate 122 also changes accordingly. The control gate 122 is highest at the top of the first sidewall 181, and then its top surface gradually and smoothly decreases from the first sidewall 181 towards the second sidewall 182, reaching a relatively low height at the top of the second sidewall 182. This results in the control gates 122 of the two memory cells exhibiting a "back-to-back" sloping profile with the top slightly higher inward (towards the drain).

[0052] Please see Figure 5 , Figure 6 , Figure 7 , Figure 8 As shown, in this embodiment, the control gate 122 of the circular memory unit 110, the control gate 122 of the interference memory unit 120, the source end 150 of the circular memory unit 110, the source end 150 of the interference memory unit 120, and the drain end surface are all formed with NiPt self-aligned silicide layers 190. Understandably, the NiPt self-aligned silicide layer 190 can significantly reduce contact resistance and series resistance: forming silicide on the control gate 122 reduces word line resistance, and forming silicide in the source / drain regions significantly reduces diffusion region resistance and contact resistance. This ensures that when a high-voltage pulse is applied to the circulating memory cell 110, the voltage can be effectively and losslessly applied to the common drain, generating an accurate interference electric field. Furthermore, when performing high-precision threshold voltage measurements or weak leakage current measurements in the interference memory cell 120, the influence of series resistance is minimized, improving the signal-to-noise ratio of the measurement signal and enabling the detection of smaller charge changes. It also improves test accuracy and consistency: the low and stable contact resistance reduces measurement errors introduced by probe contact pressure fluctuations or metal interface changes, improving repeatability between multiple tests. It ensures full compatibility of the test structure with mainstream manufacturing processes, and the high thermal stability of the NiPt silicide guarantees the reliability of the test structure's performance in subsequent tests.

[0053] In this embodiment, the storage unit is NOR flash memory. This test structure can realistically reproduce the most typical interference scenarios in actual devices and is fully compatible with standard NOR processes, facilitating rapid evaluation and optimization of reliability at the wafer level.

[0054] Please see Figures 1 to 8 As shown, this invention also proposes a method for manufacturing a test structure for drain interference reliability of memory cells, used to manufacture the back-to-back dual-cell test structure for drain interference described in the above embodiments. Specifically, the manufacturing method includes the following steps: Step S100: Provide a semiconductor substrate; Please see Figure 1 As shown, a single-crystal silicon wafer is provided as a semiconductor substrate 100, which is P-type conductive and has a certain resistivity. Before subsequent steps, a standard cleaning can be performed to remove surface contaminants and the native oxide layer.

[0055] Step S200: Threshold voltage Vt ion implantation; Please see Figure 1 As shown, threshold voltage-adjusted ion implantation is performed on the surface of the substrate 100 in the region where memory cells are to be formed. This step precisely sets the initial threshold voltage Vt required for the memory cell by implanting specific types (such as boron or phosphorus) and doses of impurity ions into the channel region. The implantation energy and dose are precisely calculated based on the target Vt value and the thermal budget for subsequent processes. A rapid thermal annealing step is typically performed after implantation to activate the implanted impurities and repair lattice damage.

[0056] Step S300: Grow the tunneling medium layer 170; Please see Figure 1 As shown, after Vt implantation and necessary surface treatment are completed, the tunneling dielectric layer 170 is grown immediately. For example, an in-situ water vapor generation (ISSG) oxidation process is used.

[0057] Step S400: Form floating gate 111; Please see Figure 2 As shown, a layer of doped polysilicon is deposited on the tunneling dielectric layer 170 using a low-pressure chemical vapor deposition (LPCVD) process to serve as the material layer for the floating gate 111. This polysilicon layer is patterned using photolithography and dry etching processes to form two adjacent floating gates 111 arranged symmetrically about the center, namely the floating gate 111 of the circular memory cell 110 and the floating gate 111 of the interfering memory cell 120.

[0058] Step S500: Form the ONO barrier dielectric layer 160 and the control gate 122; Please see Figure 3As shown, the ONO bottom oxide layer is deposited: using the same ISSG oxidation process as in step S300, a dense bottom oxide layer is grown on the polysilicon surface of the floating gate 111.

[0059] Please see Figure 3 As shown, a silicon nitride layer is deposited: a silicon nitride (Si3N4) layer is deposited on the underlying oxide layer using LPCVD or PECVD processes.

[0060] Please see Figure 3 As shown, the top oxide layer is grown by placing the silicon wafer in a high-temperature diffusion furnace tube and oxidizing the surface portion of the silicon nitride layer in a dry or humid oxygen atmosphere through a furnace tube thermal oxidation process to form the top oxide layer. Thus, the ONO three-layer composite barrier dielectric layer 160, consisting of the bottom oxide layer, the silicon nitride layer, and the top oxide layer, is formed.

[0061] Please see Figure 4 As shown, control gate 122 is formed by depositing another layer of doped polysilicon (or metal / polysilicon stack) on the ONO layer 160. This is then patterned into separate control gates 122 for the loop memory cell 110 and control gates 122 for the interfering memory cell 120 using photolithography and etching processes. These two control gates 122 are physically separated, corresponding to independent word lines.

[0062] Step S600: Form the LDD structure, sidewalls, and source / drain area; Please see Figure 5 As shown, surface oxidation treatment: After the control gate 122 is etched and cleaned as necessary, before LDD implantation, a rapid thermal oxidation treatment is performed on the device surface. This step grows an extremely thin but dense thermal oxide layer 102 on the sidewall of the floating gate 111, the sidewall of the ONO barrier dielectric layer 160, and the top and sidewall outer surfaces of the control gate 122.

[0063] Please see Figure 5 As shown, LDD light doping implantation: using the control gate 122 / floating gate 111 stack and its thin thermal oxide layer as a mask, a low dose of N-type impurities (such as phosphorus) is implanted into the substrate to form a lightly doped drain (LDD) region, thereby reducing the peak electric field at the drain end. It can be understood that... Please see Figure 6 As shown, sidewalls are formed by depositing a silicon nitride or composite dielectric film on the surface of the thermal oxide layer 102, followed by anisotropic dry etching to form sidewalls 181 and 182. In a preferred embodiment of the invention, a specific process can be used to make the height of the first sidewall 181, which is closer to the other side of the two units, higher than the height of the second sidewall 182, which is farther away from the other side.

[0064] Please see Figure 6As shown, N+ heavy doping implantation: using the control gate 122 stack and sidewalls as a composite mask, a high dose of N-type impurities (such as arsenic) is implanted to form a heavily doped N+ region. This defines a common drain region 130, an independent source region 150 for the loop memory cell 110, and an independent source region 150 for the interfering memory cell 120.

[0065] Please see Figure 7 As shown, step S700: forming NiPt self-aligned silicide; A thin film of nickel-platinum alloy is deposited.

[0066] A first rapid thermal annealing is performed to allow NiPt to react with the exposed silicon (control gate 122 polycrystalline silicon and source / drain monocrystalline silicon).

[0067] Unreacted metal is removed by selective wet etching.

[0068] A second rapid thermal annealing process is performed to form a stable, low-resistivity NiPt silicide layer 190. This silicide layer is selectively formed on the surfaces of the control gate 122 of the circulating memory cell 110, the control gate 122 of the interfering memory cell 120, the common drain region 130, the source region 150 of the circulating memory cell 110, and the source region 150 of the interfering memory cell 120.

[0069] Step S800: Formation of back-end metal interconnects and probe pads Please see Figure 8 As shown, through a back-end metal interconnect process, the control gate 122 of the circulating memory cell 110, the control gate 122 of the interference memory cell 120, the common drain region 130, the source region 150 of the circulating memory cell 110, the source region 150 of the interference memory cell 120, and the substrate are respectively connected to independent probe pads on the wafer to construct a back-to-back dual-cell test structure that supports wafer-level electrical testing.

[0070] Through steps S100 to S800 above, the back-to-back dual-cell test structure for drain interference is fabricated on the wafer. This structure has the following characteristics: two electrically symmetrical memory cells share a drain back-to-back; all critical electrodes (two control gates 122, two sources, a common drain, and substrate) are independently led out to a large probe pad through low-resistivity silicide and high-performance metal interconnects.

[0071] After manufacturing, the wafer can be placed directly on the wafer probe test stage without packaging. By precisely contacting the six (or more) independent pads with the probes, test engineers can apply high-speed P / E cyclic stress to the cyclic memory cell 110, while simultaneously monitoring changes in parameters such as threshold voltage and leakage current of the interfering memory cell 120 in real time and independently. This allows for rapid assessment and physical mechanism analysis of drain interference effects within hours to days.

[0072] Please see Figure 9 and Figure 10 As shown, this invention also proposes a test method for a test structure used to assess the reliability of drain interference in memory cells. This method utilizes the independent controllability of all critical nodes in the structure to design a precision electrical test process that can separate and quantify the contributions of different physical mechanisms (mainly inter-band tunneling and drain-source leakage) to drain interference. This method can be executed rapidly at the wafer probe stage, greatly accelerating reliability assessment and process diagnostics. The steps of the drain interference test method are as follows: Step S1: Initialize the storage state of the interference storage unit 120, and set the source terminal of the interference storage unit 120 to the initial voltage; S3. Increase the source voltage of the interference storage unit 120 by a preset bias amplitude, and repeat step S2. S4. Calculate the gate voltage of the interference storage unit 120 read in step S3 and the gate voltage difference in step S2. If the gate voltage difference is greater than the first preset threshold, then further increase the source voltage of the interference storage unit and repeat steps S2 and S3. If the gate voltage difference is less than or equal to the first preset threshold, then end the test of this test structure.

[0073] For example, when performing step S2, the source voltage of the interference storage cell 120 is set to the nth voltage, and its gate voltage is measured after the stress is completed, and recorded as the gate voltage V. tn .

[0074] Understandably, n=1,2,3…N represents the nth round of testing. In the first round of testing, the first voltage of the source voltage of the interfering memory cell 120 is set to 0V (i.e., the initial voltage of the source terminal of the interfering memory cell 120 is zero). This simulates the worst leakage conditions because at this time, there is the maximum potential difference between the drain and the source of the interfering memory cell 120, and the drain-source leakage current path is most unobstructed. Throughout the entire process of erasing and writing operations on the cyclic memory cell 110 at a preset frequency according to the above settings, after completing the preset number of erasing and writing operations while keeping the bias condition of the source voltage of the interfering memory cell 120 unchanged, the gate voltage of the interfering memory cell 120 is measured immediately (or after a short delay).

[0075] In this embodiment, step S2 includes at least three sequentially increasing frequencies: a first frequency, a second frequency, and a third frequency of erase / write operations, for example, 1K, 10K, and 100K erase / write operations, respectively, and at least the gate voltage of the interference memory cell is read after the third frequency erase / write operation is completed.

[0076] In step S3, the source voltage of the interference memory cell 120 is set to the nth voltage, which is increased by a preset threshold relative to the (n-1)th voltage. After performing erase and write operations on the cyclic memory cell 110 at a preset frequency, the gate voltage of the interference memory cell 120 is read and recorded as the gate voltage V. tn In one specific embodiment, the preset bias amplitude is 0.5V, that is, the first voltage is 0V, the second voltage is 0.5V, and the third voltage is 1V.

[0077] In step S4, V is calculated. tn With V t（n-1） The difference ΔVt is calculated and a judgment and mechanism analysis are performed. Specifically, it is determined whether the calculated ΔVt is greater than a preset first preset threshold (e.g., 0.1V). If not, the test ends, and according to the stated ΔV t Determine the contribution ratio of drain-source leakage to drain interference, and calculate the contribution ratio of drain interference caused by inter-band tunneling based on the contribution ratio of drain-source leakage to drain interference. If so, repeat steps S2 to S3 until ΔV t Less than or equal to the first preset threshold.

[0078] Please see Figure 11 As shown, Figure 11This is a statistical graph of drain interference caused by inter-band tunneling and drain-source leakage. The horizontal axis represents the source voltage of the interfering memory cell, which gradually increases from I to L. The vertical axis represents the statistical data of the gate voltage offset of the interfering memory cell after a special erase / write operation. H → A indicates the direction of numerical increase. This invention designs an iterative test process for source voltage regulation. While keeping the drain high voltage constant, the source voltage of the interfering memory cell 120 is gradually increased from 0 V, and the corresponding threshold voltage drift ΔVt is measured. Utilizing the strong dependence of drain-source leakage on the source-drain voltage, the programmable state threshold voltage offset ΔVt caused by drain interference is detected by increasing the source voltage. Combined with the convergence criterion of ΔVt ≤ 0.1 V, the quantitative separation and proportional calculation of the two types of interference mechanisms, drain-source leakage and inter-band tunneling, are achieved, providing a clear direction for process optimization. This method can quickly and cost-effectively complete a reliable assessment with a clear mechanism at the wafer level, completely eliminating the dependence on long-cycle testing after packaging and significantly shortening the development cycle. Specifically, in this embodiment, the gate voltage data of interfering memory cells in several test structures tested on the wafers are statistically analyzed: If the source voltage of the interfering memory cell in the tested structure is greater than or equal to the first preset bias voltage, the test structure is determined to be a leakage interference of the tunneling failure type. For the test structures of several tests, the remaining test structures after removing the test structures of the tunneling failure type are determined to be leakage interference of the leak-source leakage failure type.

[0079] Specifically, a wafer-level testing and determination method is provided for distinguishing drain interference failure mechanisms in non-volatile memory. This method is based on an iterative testing process of source voltage regulation and combines the measurement results of threshold voltage drift (ΔVt) to automatically classify the failure type of interfering memory cells.

[0080] Specifically, firstly, gate voltage data for each test structure under different source bias conditions are collected, and the drift ΔVt of its programmed state threshold voltage relative to the reference state is calculated accordingly. Then, all test structures are classified and statistically analyzed based on preset criteria. Determination of tunneling failure type: For any test structure under test, if the source voltage of the interference storage cell applied during the test is greater than or equal to the first preset bias voltage, and the measured ΔVt is still greater than the convergence threshold (e.g., ΔVt>0.1 V), then the leakage interference of the test structure is determined to be mainly caused by the inter-band tunneling (BTBT) mechanism and is classified as "leakage interference of tunneling failure type".

[0081] Determination of Drain-Source Leakage Failure Type: After removing structures identified as having tunneling failures from all tested structures, the remaining structures are uniformly classified as "Drain-Source Leakage Failure Type Leakage Interference." These structures typically exhibit the following behavior: as the source voltage increases, ΔVt decreases significantly, and when the source voltage reaches a certain value, it satisfies the convergence condition ΔVt ≤ 0.1 V, indicating that its interference behavior is highly sensitive to the source-drain voltage difference.

[0082] Using the above classification logic, efficient and automated failure mechanism statistics can be performed on a large number of test points on an entire wafer or even multiple wafers, obtaining the occurrence ratio of the two types of interference mechanisms. This result can directly guide process integration optimization.

[0083] In this embodiment, the interference memory cell 120 is reprogrammed to the same initial threshold voltage state each time step S1 is repeated. It is understood that the high electric field generated by the programming stress pulse applied to the cyclic memory cell 110 in step S2 may not only perturb the floating gate 111 charge of the interference memory cell 120 through leakage or tunneling, but may also cause weak, cumulative damage or charge trap filling to the tunneling dielectric layer 170 or the ONO blocking dielectric layer 160 of the interference memory cell 120. Without reprogramming, the device characteristics of the interference memory cell 120 will drift due to accumulated stress, causing a change in the baseline of subsequent tests, thus making the Vt values ​​measured in different rounds no longer directly comparable. Reprogramming to the same initial state resets the effects of the slow drift in device characteristics, making each round of testing an independent experiment of applying interference to a "fresh" device under the same initial conditions.

[0084] It is also understandable that the core of this method lies in comparing the Vt drift difference ΔVt of the interfering memory cell 120 under different source biases. The physical meaning of this difference is the contribution of the drain-source leakage mechanism. An important premise for this conclusion is that the amount of Vt drift caused by the inter-band tunneling mechanism is the same under the two bias conditions. If the initial charge state or device characteristics of the interfering memory cell 120 are inconsistent between the two tests, then even if the stress conditions are the same, the response of the tunneling effect may be different, which will contaminate the ΔVt signal and cause the mechanism separation to fail. By reprogramming to the same initial threshold voltage state each time, we maximize the consistency of the initial charge of the floating gate 111 and the initial conditions of the oxide electric field of the interfering memory cell 120, thereby ensuring the repeatability of the tunneling effect in two comparable tests, so that ΔVt can cleanly reflect the difference caused only by the change of source bias.

[0085] This invention proposes a testing method, testing structure, and manufacturing method for drain interference, achieving efficient and accurate evaluation of NorFlash drain interference problems. Specific beneficial effects are as follows: This invention adopts a standardized worst-case layout of "back-to-back shared drain" to force the circular storage unit 110 and the interference storage unit 120 to share the same drain node, which truly reproduces the most severe electrical coupling scenario in the product array, significantly improves the sensitivity, repeatability and worst-case representativeness of the test, and overcomes the data dispersion and causal ambiguity problems caused by the random arrangement of units in traditional tests.

[0086] This invention employs ISSG (In-situ Water Vapor Generation) technology to form a tunneling dielectric layer 170 after threshold voltage injection and before floating gate 111 deposition. This significantly reduces the Si–H bond density in the oxide layer, effectively suppresses the formation of hydrogen traps, thereby reducing Vt drift noise caused by non-interference factors, ensuring a purer test signal, and improving the accuracy of reliability assessment.

[0087] This invention integrates an ISSG oxide layer / silicon nitride / furnace tube oxide layer (ONO) sandwich dielectric structure above the floating gate 111, which enhances the charge retention capability of the floating gate 111, significantly improves data retention performance, avoids the natural leakage of charge from masking the true drain interference effect during long-term testing, and ensures that the test results reflect the interference mechanism itself rather than the intrinsic degradation of the device.

[0088] This invention designs an iterative test process for source voltage regulation. While keeping the drain high voltage constant, the source voltage of the interference memory cell 120 is gradually increased from 0 V, and the corresponding threshold voltage drift ΔVt is measured. Utilizing the strong dependence of drain-source leakage on the source-drain voltage, the programmable state threshold voltage offset ΔVt caused by drain interference is detected by increasing the source voltage. Combined with the convergence criterion of ΔVt ≤ 0.1 V, the quantitative separation and proportional calculation of two types of interference mechanisms, drain-source leakage and inter-band tunneling, are achieved, providing a clear direction for process optimization. This method can quickly and cost-effectively complete a reliable assessment with a clear mechanism at the wafer level, completely eliminating the dependence on long-cycle testing after packaging and significantly shortening the development cycle.

[0089] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A test structure for drain-end disturb reliability of a memory cell, comprising: The test structure is disposed in the dicing channel of the wafer where the memory chip is located. The test structure includes at least two back-to-back memory cells: a circulating memory cell and an interfering memory cell. Each of the circulating memory cell and the interfering memory cell is provided with a control gate, a floating gate, a tunneling dielectric layer and a blocking dielectric layer. The blocking dielectric layer is disposed between the control gate and the floating gate, the floating gate is disposed between the tunneling dielectric layer and the blocking dielectric layer, and the tunneling dielectric layer is disposed on the surface of the wafer substrate. The two drain terminals of the cyclic memory cell and the interference memory cell share a single drain lead; the source / gate terminals of the cyclic memory cell and the interference memory cell are each led out separately; during testing, the source terminal of the cyclic memory cell is grounded, and a test voltage is applied to the source terminal of the interference memory cell.

2. The test structure of claim 1, wherein, The tunneling medium layer is formed using the ISSG process.

3. The test structure according to claim 1, characterized in that, The barrier dielectric layer is an ONO three-layer composite structure, which includes, in sequence along the direction from the floating gate to the control gate: a bottom oxide layer, a silicon nitride layer, and a top silicon oxide layer.

4. The test structure according to claim 3, characterized in that, The bottom oxide layer is formed using an in-situ water vapor production process.

5. The test structure according to claim 4, characterized in that, The silicon nitride layer is formed using a chemical vapor deposition process; the top silicon oxide layer is formed using a furnace tube thermal oxidation process.

6. The test structure according to claim 5, characterized in that, The storage unit is a NOR flash memory.

7. A test method for the test structure as described in claim 1, characterized in that, The test method for testing a plurality of test structures as described in claim 1 in the wafer includes: S1. Initialize the storage state of the interference storage unit, and set the source terminal of the interference storage unit to the initial voltage; S2. The source voltage of the circular memory cell is set to ground. After performing erase and write operations on the circular memory cell at a preset frequency, the gate voltage of the interference memory cell is read. S3. Increase the source voltage of the interference storage cell by a preset bias amplitude, and repeat step S2. S4. Calculate the gate voltage of the interference memory cell read in step S3 and the gate voltage difference in step S2. If the gate voltage difference is greater than a first preset threshold, further increase the source voltage of the interference memory cell and repeat steps S2 and S3. If the gate voltage difference is less than or equal to the first preset threshold, end the test of this test structure.

8. The test method according to claim 7, characterized in that, Step S2 includes at least three sequentially increasing frequencies: a first frequency, a second frequency, and a third frequency of erase / write operations, and at least the gate voltage of the interference memory cell after the third frequency is read.

9. The test method according to claim 7, characterized in that, Also includes: The gate voltage data of interfering memory cells in the test structures tested on several wafers were statistically analyzed: If the source voltage of the interference storage cell in the tested test structure is greater than or equal to the first preset bias voltage, the test structure is determined to be a leakage interference of the tunneling failure type. For a number of test structures tested, the remaining test structures after removing the tunneling failure type are determined to be leakage interference of the leak-source leakage failure type.

10. The test method according to claim 9, characterized in that, The initial voltage set at the source end of the interference storage unit is zero.

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