Time-interleaved ADC with redundant channels and control method thereof

Abstract

This application discloses a time-interleaved ADC with redundant channels and its control method, relating to the field of integrated circuit technology. The time-interleaved ADC includes multiple analog signal input selection switches, multiple sub-ADCs, and an output data selector. Each sub-ADC is divided into a sampling conversion channel and a redundant channel. The sampling conversion channel is used to convert analog signals into digital signals, and the redundant channel is set to be in a non-data conversion state when the sampling conversion channel is working. Each sub-ADC is used to convert analog input signals into corresponding branched digital signals. The output data selector is used to combine the branched digital signals into a total digital signal by time-division multiplexing. This application improves the dynamic range performance of the time-interleaved ADC and eliminates the data dependency problem of ultra-high-speed ADCs by adding redundant sub-ADC channels.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a time-interleaved ADC with redundant channels and its control method. Background Technology

[0002] Existing time-interleaved ADCs can only cycle through their sampling and signal output sequences in a fixed order. However, in actual ADC circuit implementations, all sub-ADC channels are not perfectly identical; each channel exhibits varying degrees of gain mismatch, DC bias, time bias, bandwidth bias, and capacitance bias. These non-ideal factors result in significant spurious or noise spikes in the final output spectrum of the time-interleaved ADC, thus degrading its final output performance.

[0003] In addition, when the sampling rate of the time-interleaved ADC is particularly high, in ultra-high-speed sampling scenarios, since the sub-ADC is in working state at every moment, the sampling capacitors and other circuit nodes inside the ADC are prone to charge accumulation. Furthermore, due to the extremely high speed, insufficient discharge reset is also likely to occur in the reset state due to insufficient time, resulting in a data dependence effect, which further deteriorates the dynamic performance of the final output of the time-interleaved ADC, such as SNDR and SFDR. Summary of the Invention

[0004] The main objective of this application is to propose a time-interleaved ADC with redundant channels and its control method to improve the output accuracy of the time-interleaved ADC.

[0005] To achieve the above objectives, one aspect of this application provides a time-interleaved ADC with redundant channels, the time-interleaved ADC comprising: multiple analog signal input selection switches, a multi-channel sub-ADC, and an output data selector; Each of the sub-ADCs is divided into a sampling conversion channel and a redundant channel; the sampling conversion channel is used to convert analog signals into digital signals, and the redundant channel is set to be in a non-data conversion working state when the sampling conversion channel is working; The input terminal of each sub-ADC is connected to the first terminal of the corresponding analog signal input selection switch, and the output terminal of each sub-ADC is connected to the input terminal of the output data selector. The second terminal of each of the aforementioned analog signal input selection switches is used to connect to an analog input signal; Each of the sub-ADCs is used to convert the analog input signal into the corresponding digital signal of the branch; The output data selector is used to combine the various branch digital signals into a total digital signal by arranging them in a time-division sequence.

[0006] In some embodiments, for every four sampling conversion channels, one redundant channel is set accordingly.

[0007] In some embodiments, the sampling conversion channel is set to 4 channels, and the redundant channel is set to 1 channel; Alternatively, the sampling conversion channel can be set to 8 channels, and the redundant channel can be set to 2 channels; Alternatively, the sampling conversion channel can be set to 16 channels, and the redundant channel can be set to 4 channels; Alternatively, the sampling conversion channel can be set to 32 channels, and the redundant channel can be set to 8 channels; Alternatively, the sampling conversion channel can be set to 64 channels, and the redundant channel can be set to 16 channels.

[0008] In some embodiments, the redundant channel is configured to be in a non-data conversion working state, which is either idle, reset, or calibrated, when the sampling conversion channel is in operation.

[0009] In some embodiments, the time-interleaved ADC further includes a random number generator; The random number generator is used to randomly select several of the sub-ADCs from each of the sub-ADCs as the redundant channels.

[0010] To achieve the above objectives, another aspect of this application proposes a control method for a time-interleaved ADC with redundant channels. The control method is applied to a time-interleaved ADC with redundant channels as described above, and includes the following steps: At least one of the sub-ADCs is selected as a redundant channel from each sub-ADC, and the remaining sub-ADCs are used as sampling conversion channels. The analog input signal is converted into the corresponding split digital signal using each of the sampling conversion channels, while the redundant channels are set to a non-data conversion working state. The output data selector combines the individual digital signals into a total digital signal by arranging them in a time-division order.

[0011] In some embodiments, selecting at least one of the sub-ADCs as a redundant channel from among the sub-ADCs includes the following steps: At least one of the sub-ADCs is selected as the redundant channel from among the sub-ADCs using a random number generator.

[0012] The embodiments of this application include at least the following beneficial effects: This application provides a time-interleaved ADC with redundant channels and its control method. The time-interleaved ADC of this application includes multiple analog signal input selection switches, multiple sub-ADCs, and an output data selector. Each sub-ADC is divided into a sampling conversion channel and a redundant channel. The sampling conversion channel is used to convert analog signals into digital signals, and the redundant channel is set to be in a non-data conversion working state when the sampling conversion channel is working. The input terminal of each sub-ADC is connected to the first terminal of the corresponding analog signal input selection switch, and the output terminal of each sub-ADC is connected to the input terminal of the output data selector. The second terminal of each analog signal input selection switch is used to connect to the analog input signal. Each sub-ADC is used to convert the analog input signal into a corresponding split digital signal. The output data selector is used to combine the split digital signals into a total digital signal by time-division multiplexing. This application adds redundant sub-ADC channels, ensuring that one sub-ADC channel is in a non-data conversion state during each conversion cycle. Furthermore, through random rotation, the original periodic non-ideal factors are discretized, transforming stray or coupled energy with high accumulated energy during the cycle into noise, ultimately improving the dynamic range performance of the time-interleaved ADC. Additionally, because this application uses a rotation mechanism, each sub-ADC channel has the opportunity to be in a non-data conversion state, thus eliminating the data dependency problem of ultra-high-speed ADCs. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the structure of an optional time-interleaved ADC provided in an embodiment of this application; Figure 2 An example diagram of the sampling timing and data output of an optional time-interleaved ADC provided in this application embodiment; Figure 3 An example diagram illustrating the operating sequence of a sub-ADC in an optional time-interleaved ADC provided in this application embodiment; Figure 4 This is a structural example diagram of a time-interleaved ADC with redundant channels provided in an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a time-interleaved ADC that controls the working timing of the sub-ADC through a random number generator, as provided in an embodiment of this application. Figure 6An example diagram illustrating the working sequence of a time-interleaved ADC with added redundant channels, provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a time ADC with two redundant channels provided in an embodiment of this application; Figure 8 This is a schematic diagram illustrating the application of a time-interleaved ADC with redundant channels in the field of radiation protection, as provided in an embodiment of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0017] Terminology Explanation: Time-Interleaved ADC: A time-interleaved analog-to-digital converter is a technique that significantly improves the overall sampling rate of a system by parallelizing multiple ADC sub-channels. Its core principle is to sequentially distribute the high-speed analog input signal to N parallel ADC cores with relatively low sampling rates for sampling and digitization via a multi-phase clock controller. Then, a digital back-end processing unit interleaves and merges the data from each channel in sequence, ultimately outputting a high-speed data stream with an equivalent sampling rate N times that of a single ADC.

[0018] In high-speed, high-precision ADCs with sampling rates exceeding 1 Gsps, current technologies typically employ a time-interleaving architecture. This involves utilizing multiple parallel sub-ADC channels, operating simultaneously according to a specific sampling and quantization conversion order, and then merging the outputs of each sub-ADC channel in a predetermined sequence. This significantly improves the final sampling conversion rate of the entire ADC system. Each sub-ADC contains complete sampling and quantization conversion capabilities.

[0019] An optional time-interleaved ADC structure is as follows Figure 1As shown, the analog signal input is simultaneously connected to four sampling switches SW1, SW2, SW3, and SW4. Each sampling switch connects to a sub-ADC, forming a complete and independent sub-ADC channel. Each sub-ADC channel has complete sampling, quantization, and output functions, and the quantization accuracy of the sub-ADC channel is consistent with the quantization accuracy of the entire ADC. The main difference between the sub-ADC and the complete ADC is that the sampling time of the sub-ADC only occupies 1 / N of the total ADC time, where N is the number of sub-ADC channels in the entire ADC. Figure 1 Taking a complete ADC structure consisting of 4 sub-ADCs as an example, the sampling time of each sub-ADC only occupies 1 / 4 of the total ADC sampling time. Figure 1 The corresponding analog input signal sampling timing is as follows: Figure 2 As shown in (a) in the figure, it can be seen that SW1, SW2, SW3 and SW4 occupy only 1 / 4 of the cycle time for each sampling, and the cycle repeats.

[0020] The entire ADC data output, also consisting of the outputs of the four sub-ADC channels Dout1, Dout2, Dout3, and Dout4, is sequentially combined and output according to the sampling order, as shown below. Figure 2 As shown in (b) of the diagram.

[0021] The above analysis shows that all four sub-ADC channels are active throughout the entire ADC cycle, only their operating cycles are staggered. Furthermore, since each channel is active at all times, once the operating cycle sequence of the sub-ADC channels is fixed, all subsequent conversion cycles can only perform data conversion in the initially predetermined order; this order cannot be changed. Figure 3 for Figure 1 The diagram shows the sequential operation order of the four sub-ADCs. In the initial state, the operation order of the four sub-ADCs is 1->2->3->4. Therefore, the subsequent cycle order can only be 1->2->3->4, repeating continuously.

[0022] Figure 1 The time-interleaved ADC shown uses four sub-ADCs that sequentially receive analog input signals and output data at equal time intervals to a data mux module (output data selector). The data mux module then synthesizes the output data from each module to form the final data output. It can be seen that when one channel receives an analog signal, the other three channels do not receive analog signals and are in data conversion mode. These four sub-ADCs operate in a continuous time-division alternating state. Their sampling order and data output order can only be determined in a fixed, cyclical manner.

[0023] Because all channels are working continuously, only the timing of analog signal sampling and digital code output is staggered.

[0024] However, in actual ADC circuit implementations, not all sub-ADC channels are perfectly identical. Each sub-ADC channel exhibits varying degrees of gain mismatch, DC bias, time bias, bandwidth bias, and capacitance bias. These non-ideal factors result in significant spurious or noise spikes in the final ADC output spectrum, thus degrading the overall ADC output performance.

[0025] In related technologies, various calibration algorithms are typically used to compensate for non-ideal factors in actual ADC circuits, such as mismatch calibration, gain calibration, and time deviation calibration. However, due to the accuracy issues of calibration algorithms, and variations in the ADC input signal and operating state, the final calibration result is not entirely ideal and usually retains residuals. This makes the ADC's interleaving spur, SNDR, SFDR, and other performance metrics still susceptible to influence.

[0026] In addition, when the sampling rate of the ADC is particularly high, such as reaching 10Gsps or more, in such ultra-high-speed sampling scenarios, since the sub-ADC and the sampling conversion channel are in working state at every moment, the sampling capacitors inside the ADC and other circuit nodes are prone to charge accumulation. Furthermore, due to the extremely high speed, there is not enough time in the reset state, which can easily cause insufficient discharge reset, resulting in a data dependence effect, which further deteriorates the dynamic performance of the ADC's final output, such as SNDR and SFDR.

[0027] Therefore, the main purpose of this application is to solve the above two problems: one is the accuracy and residual problem of the ADC non-ideal factor calibration algorithm, and the other is the data dependence characteristics related to the input signal caused by the excessive speed of the ultra-high speed ADC.

[0028] This application primarily improves the dynamic range performance of the final ADC by adding redundant sub-ADC channels. This ensures that in each conversion cycle, one or more sub-ADC channels are in an "idle," reset, or calibration state. Through random rotation, the original periodic non-ideal factors are discretized, transforming stray or coupled energy, which would otherwise have high cumulative energy over the cycle, into noise. Furthermore, the rotation mechanism allows each sub-ADC channel to potentially be in an "idle," reset, or calibration state, thus eliminating the data dependence problem of ultra-high-speed ADCs.

[0029] The inventive points of this application include: Figure 1 The time-interleaved ADC shown is supplemented with redundant channels. Figure 1 In the time-interleaved ADC structure shown, all sub-ADC channels are always in the sampling and data conversion state. However, in the time-interleaved ADC structure with redundant channels proposed in this application, redundant channels are added on the basis of the typical time-interleaved ADC structure, so that only some sub-ADC channels are in the sampling and data conversion state, while some sub-ADC channels are in the idle, reset, calibration or other working states.

[0030] This application is based on Figure 1 Based on the time-interleaved ADC shown, one sub-ADC channel is added as a redundant channel, and its specific structure is as follows. Figure 4 As shown. Compared to Figure 1 The structure shown, Figure 4 A new SW5 and sub-ADC5 have been added. The analog input is simultaneously input to SW1, SW2, SW3, SW4 and SW5. Each SW is connected to its corresponding sub-ADC. Finally, through the data synthesis (Data Mux), the outputs Dout1, Dout2, Dout3, Dout4 and Dout5 of each sub-ADC channel are synthesized into the final ADC output data, Data output, in a certain order.

[0031] according to Figure 4 The structure shown is, with Figure 1 The diagram shows a 4-channel time-interleaved ADC as a base, with a 5th sub-ADC added. While the entire ADC operates normally, it still uses the 4 sub-ADCs as a complete cycle. However, due to the redundant channels, one sub-ADC can be left idle for other processing or placed in a reset state to wait.

[0032] Because there is channel redundancy, and the entire ADC's duty cycle consists of four sub-ADCs completing one full cycle, its selectable operating timing can be flexibly chosen. For Figure 1 The structure shown indicates that in each sub-ADC's duty cycle, the sub-ADCs sequentially do not participate in data conversion. However, for... Figure 4 In the structure shown, the sub-ADCs that do not participate in the conversion are in a random order, as long as the sampling time interval of the same sub-ADC is greater than or equal to the number of sub-ADCs participating in the conversion (in this embodiment, the number of sub-ADCs participating in the conversion is 4).

[0033] The following sections will provide a detailed description and explanation of some optional embodiments of this application, using specific application examples.

[0034] Example 1: The operating sequence control of the sub-ADC can be based on a pre-defined rule sequence or it can be completely random, such as... Figure 5 This describes the specific implementation method of controlling the working order of the sub-ADCs through a random number generator.

[0035] based on Figure 4 The time-interleaved ADC structure with redundant channels shown is selected and controlled according to the working order of the sub-ADCs. Its specific implementation can be as follows: Figure 5 The diagram shows how the timing of the sub-ADC is controlled via a random number generator. (Example:) Figure 5 As shown, a new random number generator module TRNG is added. For the time-interleaved ADC structure with 4 sub-ADC channels plus 1 redundant sub-ADC channel, since the data of 4 sub-ADCs is converted into a complete cycle, the random number generator TRNG outputs a random number between 1 and 5 for each complete ADC, that is, the data conversion cycle of 4 sub-ADCs. This is used to determine which sub-ADC between sub-ADC1 and sub-ADC5 does not participate in the data conversion of this cycle.

[0036] Example of selecting and determining the redundant channels of the sub-ADC, such as... Figure 6 .in, Figure 6 (a) in the diagram represents the sequential selection of redundant channels. For example, in the first cycle, sub-ADC channel 5 is used as the redundant channel; in the second cycle, sub-ADC channel 1 is used; in the third cycle, sub-ADC channel 2 is used; in the fourth cycle, sub-ADC channel 3 is used, and so on. Because it still selects redundant channels sequentially, it cannot adequately address the residuals from calibration for non-ideal factors, as well as the data dependence characteristics of the analog input data.

[0037] And when Figure 5 After introducing a random number generator to randomly select redundant channels, the selection of redundant channels becomes as follows: Figure 6As shown in (b), the first cycle is channel 5, the second cycle is channel 4, the third cycle is channel 3, the fourth cycle is channel 4, and so on. Because the selection of redundant channels is sufficiently random, the effects of ADC non-ideal characteristics are completely randomized into noise as the redundant channels are randomized, rather than being concentrated mixing energy or spurious signals, thus improving the ADC output dynamic range (SFDR). Regarding data dependence, when a sub-ADC channel is in a redundant state, its internal structure can be set to a reset mode, allowing each internal node to fully reset in this idle state. Furthermore, because the pseudo-random generator randomly selects redundant channels, it can effectively eliminate data dependence characteristics during ultra-high-speed data conversion.

[0038] Example 2: Adding redundant channels doesn't just mean adding one more channel. Since there's no upper limit to the number of sub-ADC channels in a time-interleaved ADC (currently, technology can support up to 32 or 64 sub-ADC channels for time interleaving), redundant channels can be increased as needed. For example... Figure 7 There are 8 sub-ADC channels, plus 2 redundant sub-ADC channels, for a total of 10 sub-ADC channels. Therefore, the redundant channel mode of this application is not limited to Embodiment 1 and Embodiment 2, and its redundant channels and sub-ADC channels participating in data conversion can be arbitrarily combined as needed.

[0039] Example 3: Time-interleaved ADCs with redundant channels not only improve ADC output performance but also enhance overall ADC reliability in radiation-resistant applications. Figure 8 The figure illustrates an application example of a time-interleaved ADC with redundant channels in the field of radiation resistance. As shown, suppose that sub-ADC channel 2 experiences a significant performance degradation, or even functional problems, due to the harsh working environment and radiation. To avoid affecting the overall ADC's operating speed and performance, redundant channel 5 can be used as a substitute for channel 2, participating in the ADC's operation. This ensures that the entire ADC does not fail due to the failure of a single sub-ADC channel, thereby improving its reliability in the radiation resistance field.

[0040] Beneficial effects: (1) By using redundant channels, the working order of the sub-ADCs is no longer fixed. Therefore, the spurious noise introduced by the ADC due to non-ideal factors can be evenly distributed into the background noise, thereby reducing the requirements for the ADC calibration algorithm and improving the overall dynamic range performance of the ADC. (2) By introducing redundant channels, in the field of ultra-high-speed ADC applications, the idle sub-ADC can be kept in a reset state for a long time, thereby improving the data dependency characteristics of the ultra-high-speed ADC output. (3) By introducing redundant channels, idle sub-ADCs can be used for other functions, such as calibration of the channel itself, thereby improving the performance of the ADC. (4) In the field of radiation protection applications, the overall reliability of ADC operation can be improved by increasing redundant ADC channels.

[0041] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0042] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0043] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0044] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A time-interleaved ADC with redundant channels, characterized in that, The time-interleaved ADC includes: multiple analog signal input selection switches, a multi-channel sub-ADC, and an output data selector; Each of the sub-ADCs is divided into a sampling conversion channel and a redundant channel; the sampling conversion channel is used to convert analog signals into digital signals, and the redundant channel is set to be in a non-data conversion working state when the sampling conversion channel is working; The input terminal of each sub-ADC is connected to the first terminal of the corresponding analog signal input selection switch, and the output terminal of each sub-ADC is connected to the input terminal of the output data selector. The second terminal of each of the aforementioned analog signal input selection switches is used to connect to an analog input signal; Each of the sub-ADCs is used to convert the analog input signal into the corresponding digital signal of the branch; The output data selector is used to combine the various branch digital signals into a total digital signal by arranging them in a time-division sequence.

2. The time-interleaved ADC with redundant channels according to claim 1, characterized in that, For every four sampling conversion channels set up, one redundant channel is set up accordingly.

3. The time-interleaved ADC with redundant channels according to claim 2, characterized in that, The sampling conversion channel is set to 4 channels, and the redundant channel is set to 1 channel; Alternatively, the sampling conversion channel can be set to 8 channels, and the redundant channel can be set to 2 channels; Alternatively, the sampling conversion channel can be set to 16 channels, and the redundant channel can be set to 4 channels; Alternatively, the sampling conversion channel can be set to 32 channels, and the redundant channel can be set to 8 channels; Alternatively, the sampling conversion channel can be set to 64 channels, and the redundant channel can be set to 16 channels.

4. The time-interleaved ADC with redundant channels according to claim 1, characterized in that, The redundant channel is configured to be in any one of the following non-data conversion working states when the sampling conversion channel is working: idle, reset, or calibration.

5. A time-interleaved ADC with redundant channels according to any one of claims 1 to 4, characterized in that, The time-interleaved ADC also includes a random number generator; The random number generator is used to randomly select several of the sub-ADCs from each of the sub-ADCs as the redundant channels.

6. A control method for a time-interleaved ADC with redundant channels, characterized in that, The control method is applied to a time-interleaved ADC with redundant channels as described in claim 1, and the control method includes the following steps: Select at least one of the sub-ADCs as a redundant channel from each sub-ADC, and use the remaining sub-ADCs as sampling conversion channels; The analog input signal is converted into the corresponding split digital signal using each of the sampling conversion channels, while the redundant channels are set to a non-data conversion working state. The output data selector combines the individual digital signals into a total digital signal by arranging them in a time-division order.

7. The control method for a time-interleaved ADC with redundant channels according to claim 6, characterized in that, Selecting at least one of the sub-ADCs as a redundant channel from among the sub-ADCs includes the following steps: At least one of the sub-ADCs is selected as the redundant channel from among the sub-ADCs using a random number generator.

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