Trench type radiation hardened high voltage IGBT and preparation method thereof

Abstract

This invention discloses a trench-type radiation-hardened high-voltage IGBT and its fabrication method, relating to the field of power semiconductor device technology. The trench-type radiation-hardened high-voltage IGBT includes a collector, a semiconductor layer disposed on the collector, and a trench embedded in the semiconductor layer. A gate-controlled N-type polysilicon is disposed in the trench. A P-shielding layer and a P+shielding layer are disposed directly below the trench. The P-shielding layer is in contact with the trench, and the P+shielding layer is located below the P-shielding layer. An N+ recombination center region is integrated in the central region of the P-shielding layer and is electrically connected to the emitter. This invention can improve the hole extraction efficiency during radiation transients, thereby improving the radiation resistance of the IGBT device. Furthermore, the IGBT provided by this invention only adds an ion implantation process after trench etching, making it highly compatible with existing IGBT manufacturing processes and requiring no adjustment to the main production line flow.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, and in particular to a trench-type radiation-hardened high-voltage IGBT and its fabrication method. Background Technology

[0002] Insulated gate bipolar transistors (IGBTs) have advantages such as low input impedance, low on-state voltage drop, and high switching frequency, making them a key component of power electronic conversion circuits in fields such as electric vehicles, train traction, grid-connected power transmission, and aerospace exploration. Among them, as a core component of flexible DC transmission, IGBT devices need to exhibit excellent reliability under many extreme operating conditions. Through the iteration of multiple generations of devices, current high-voltage IGBT devices have strong robustness against avalanche, short circuits, and overcurrent.

[0003] However, at high altitudes, IGBTs are continuously exposed to cosmic ray radiation, which can easily lead to problems such as gate oxide electric field distortion, single-event gate breakdown (SEGR), single-event burn-out (SEB), and excessive carrier accumulation failure. Studies have shown that at an altitude of 2500m, the failure rate of IGBT devices is four times that of devices at sea level. If operated according to conventional rated parameters, IGBT devices are prone to insulation breakdown and overheating failure. Typically, it is necessary to significantly reduce the rated parameters such as device operating voltage and current, and to adopt a redundant backup design to ensure that IGBT devices meet the requirements for safe operation under high-altitude conditions. However, this forced derating and redundancy configuration not only reduces the effective utilization rate of the devices, but also increases the number of devices used, the complexity of supporting circuits, and the overall system size, ultimately significantly increasing the overall cost of IGBT devices and their application systems. This restricts the economic viability and large-scale application of high-voltage IGBTs in high-altitude scenarios. Therefore, it is necessary to develop new IGBT devices with enhanced radiation resistance and compatibility with existing processes to meet the needs of high-altitude applications. Summary of the Invention

[0004] This invention provides a trench-type radiation-hardened high-voltage IGBT and its fabrication method, aiming to enhance the radiation resistance of IGBT devices.

[0005] The trench-type radiation-hardened high-voltage IGBT provided by this invention includes:

[0006] collector;

[0007] A semiconductor layer is disposed on the collector electrode; the semiconductor layer includes a P-type collector region, an N-type buffer layer, an N-type drift layer, a P-body region and an emitter region stacked sequentially, and the emitter region includes a P+ region and an N+ region;

[0008] A trench embedded in the semiconductor layer; the trench is embedded in the emitter region and the P-body region along a direction perpendicular to the surface of the emitter region and extends into the interior of the N-type drift layer, the N+ region is adjacent to the trench; the interior of the trench is provided with N-type polysilicon, the N-type polysilicon is wrapped with an insulating oxide dielectric.

[0009] A P-shielding layer and a P+shielding layer are disposed directly below the trench. The P-shielding layer is in contact with the trench, and the P+shielding layer is located below the P-shielding layer. An N+ composite central region is integrated in the central region of the P-shielding layer, and the N+ composite central region is in contact with the trench.

[0010] An isolation medium layer disposed above the trench; and,

[0011] An emitter located above the emitter region and the isolation dielectric layer;

[0012] The N-type polysilicon is a gate-controlled N-type polysilicon, and the N+ composite central region is electrically connected to the emitter.

[0013] Optionally, the doping concentration of the P-shielding layer is 1×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The doping concentration of the P+ shielding layer is 1×10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0014] Optionally, the insulating oxide medium is silicon oxide.

[0015] Optionally, the ratio of the width of the trench to the center-to-center distance between two adjacent trenches is 30% to 70%.

[0016] Optionally, the width of the trench is 1~10μm.

[0017] Optionally, the doping concentration of the N+ recombination center region is 1×10⁻⁶. 18 cm -3 ~5×10 19 cm -3 .

[0018] The trench-type radiation-hardened high-voltage IGBT provided by this invention can be prepared by the following method, including the following steps:

[0019] S1, Prepare a semiconductor layer, the semiconductor layer comprising a P-type collector region, an N-type buffer layer, an N-type drift layer, and a P-body region stacked sequentially;

[0020] S2, etch trenches along a direction perpendicular to the surface of the P-body region, the trenches extending into the interior of the N-type drift layer, perform vertical ion implantation at the bottom of the trenches, and sequentially form a P+ shielding layer, a P- shielding layer, and an N+ composite center region directly below the trenches, the N+ composite center region being integrated into the central region of the P- shielding layer and in contact with the trenches;

[0021] S3, silicon oxide is formed at the bottom and inner wall of the trench;

[0022] S4, N-type polysilicon is filled in the trench, a layer of silicon oxide is formed on the surface of the N-type polysilicon, and the N-type polysilicon is connected to the gate electrode;

[0023] S5, an emitter region is formed on the surface of the P-body region, the emitter region including a P+ region and an N+ region, the N+ region being adjacent to the trench;

[0024] S6, deposit an isolation dielectric layer above the trench, and prepare an emitter above the isolation dielectric layer and the emitter region, and prepare a collector on the surface of the P-type collector region;

[0025] S7, electrically connect the N+ composite center region to the emitter.

[0026] Alternatively, an emitter region can be prepared on the surface of the P-body region by ion implantation.

[0027] Optionally, in the step of forming the P+ shielding layer and the P- shielding layer by vertical ion implantation, the P-type doping element used is at least one of boron, indium, gallium, and aluminum.

[0028] Optionally, in the step of vertical ion implantation to form the N+ composite center region, the N-type dopant used is at least one of phosphorus, arsenic, and antimony.

[0029] The present invention has the following beneficial effects:

[0030] This invention incorporates a P-shielding layer and a P+shielding layer beneath the trench gate structure of an IGBT device. The central region of the P-shielding layer integrates an N+ recombination center region, which is led out to the emitter. The PN junction formed by the P-shielding layer, P+shielding layer, and N-type drift layer forms a depletion layer with reverse breakdown voltage, reducing the gate oxide electric field of the trench. The N+ recombination center region is clamped at the emitter potential. When the IGBT device is subjected to strong radiation, the transient high-concentration holes generated by the N-type drift layer diffuse towards the direction of decreasing doping concentration in the P-type shielding layer, and are rapidly extracted via the path P+shielding layer → P-shielding layer → N+ recombination center region → emitter. Simultaneously, some holes recombine when passing through the N+ recombination center region, preventing excessively high hole concentration in the P-type shielding layer. Therefore, this invention can improve hole extraction efficiency during radiation transients, thereby enhancing the radiation resistance of the IGBT device.

[0031] Furthermore, this invention sequentially fabricates a P+ shielding layer, a P- shielding layer, and an N+ composite center layer below the trench using a vertical ion implantation process. Compared to the traditional trench gate IGBT fabrication process, this only adds an ion implantation process after trench etching. The N+ composite center region integrated in the P- shielding layer can form an excellent contact interface, and the doping concentration and area of ​​the ion implantation process are controllable. The new IGBT device does not require the introduction of additional fabrication steps with large errors or stringent processes such as etching and deposition. Therefore, the trench-type radiation-hardened high-voltage IGBT provided by this invention is highly compatible with existing IGBT manufacturing processes and does not require adjustments to the main production line flow. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 These are schematic diagrams of some embodiments of the grooved radiation-resistant reinforced high-voltage IGBT of the present invention;

[0034] Figure 2 The flowcharts are for some embodiments of the preparation method of the grooved radiation-hardened high-voltage IGBT of the present invention.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1. Collector; 2. P-type collector region; 3. N-type buffer layer; 4. N-type drift layer; 5. P-body region; 6. P+ region; 7. N+ region; 8-1. P+ shielding layer; 8-2. P- shielding layer; 9. N+ composite center region; 10. N-type polysilicon; 11. Insulating oxide dielectric; 12. Isolating dielectric layer; 13. Emitter. Detailed Implementation

[0037] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] In the description of this invention, it should be understood that the terms "upper," "lower," "vertical," "horizontal," "top," "bottom," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention; in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0039] Trench gate IGBTs are power semiconductor structures created by etching trenches on the semiconductor layer of the IGBT and fabricating insulating oxide dielectric (also known as "gate oxide") and gate-controlled polysilicon within the trenches. Compared to planar gate IGBTs, trench gate IGBTs can significantly reduce on-state voltage drop, have higher reverse withstand voltage capability, and lower switching losses, making them suitable for high-frequency, high-current applications.

[0040] The core reason for IGBT failure due to cosmic ray irradiation is that when high-energy charged particles are incident, a large number of electron-hole pairs are generated inside the device (especially the N-type drift layer). If these charge carriers cannot be quickly removed, they will accumulate near the gate oxide, causing gate oxide breakdown.

[0041] In this embodiment of the invention, "+" and "-" are used to indicate the doping concentration of silicon material, which is a simplified expression commonly used in the semiconductor field; for example, the P+ region represents a heavily P-type doped region (P-type doping concentration is usually ≥1×10⁻⁶). 18 cm -3 High hole concentration and strong conductivity; the N+ region represents the heavily doped N-type region (N-type doping concentration is usually ≥1×10⁻⁶). 18 cm -3High electron concentration and strong conductivity; the P-region represents a lightly doped P-type region (P-type doping concentration is usually <1×10⁻⁶). 18 cm -3 The doping concentration of each semiconductor layer is set in accordance with the prior art unless otherwise specified in the embodiments of the present invention. It can be selected with reference to the conventional parameters of the prior art.

[0042] See Figure 1 In this embodiment of the invention, the trench-type radiation-hardened high-voltage IGBT includes a collector 1, a semiconductor layer disposed on the collector 1, and a trench embedded in the semiconductor layer; the semiconductor layer includes a P-type collector region 2, an N-type buffer layer 3, an N-type drift layer 4, a P-body region 5, and an emitter region stacked sequentially, the emitter region including a P+ region 6 and an N+ region 7; the trench is embedded in the emitter region and the P-body region 5 along a direction perpendicular to the surface of the emitter region and extends into the interior of the N-type drift layer 4, the N+ region 7 being adjacent to the trench; the interior of the trench is provided with N-type polysilicon 10, the N-type polysilicon 10 being encapsulated by an insulating oxide medium 11 (usually silicon oxide); the N-type polysilicon 10 is gate-controlled N-type polysilicon (used for electrical connection with the gate, the gate being located on the surface of the IGBT device), Figure 1 (Not shown in the image).

[0043] A P-shielding layer 8-2 and a P+shielding layer 8-1 are located directly below the trench. The P-shielding layer 8-2 is in contact with the trench, and the P+shielding layer 8-1 is located below the P-shielding layer 8-2. An N+ composite central region 9 is integrated in the central area of ​​the P-shielding layer 8-2, and the N+ composite central region 9 is in contact with the trench. An isolation dielectric layer 12 is located above the trench, completely covering the upper end of the trench. An emitter 13 is located above the emitter region and the isolation dielectric layer 12. The N+ composite central region 9 is electrically connected to the emitter 13, and the two can be electrically connected via external leads. Figure 1 The connection method shown is for illustrative purposes only. In actual processes, conductive holes can be etched in the isolation dielectric layer and the gate oxide dielectric (the location of the conductive holes needs to be reserved), and a conductive path can be formed by filling the contact holes with metal deposition, so that the N+ recombination center region can be directly connected to the emitter metal electrode. Alternatively, the N+ recombination center region can be extended to the edge region of the device, and the N+ recombination center region and the emitter can be connected in the edge region of the device.

[0044] In some preferred embodiments, the doping concentration of the P-shielding layer is 1×10⁻⁶. 16 cm -3 ~5×10 17 cm -3 The doping concentration of the P+ shielding layer is 1×10⁻⁶. 18 cm -3 ~5×10 19 cm -3The P-type doping element is one or more of boron, indium, gallium and aluminum.

[0045] In some preferred embodiments, the doping concentration of the N+ recombination center region is 1 × 10⁻⁶. 18 cm -3 ~5×10 19 cm -3 The N-type dopant element is one or more of phosphorus, arsenic, and antimony.

[0046] In trench-gate IGBT devices, the P-type collector region is the hole injection region on the collector side, used to inject minority carrier holes into the N-type buffer layer and N-type drift layer, achieving drift layer conductance modulation and reducing the on-state voltage drop. Simultaneously, it forms a reverse PN junction with the N-type buffer layer, participating in the device's forward blocking breakdown process and providing a good ohmic contact foundation for the back collector. The N-type buffer layer, as a field buffer layer, suppresses excessive extension of the depletion layer into the collector region during the off-state, preventing punch-through breakdown, improving high-voltage withstand stability, and alleviating interface electric field concentration in different doped regions, reducing interface defect proliferation. The N-type drift layer is... The core withstand voltage layer of the device withstands the forward blocking voltage. When turned off, it forms a wide depletion region within the layer to support the high voltage and also serves as the main transport channel for electrons and holes. The P-body region is the channel formation region of the device. When the gate is turned on, an inverse electron channel is formed at the interface between the P-body region and the gate oxide layer, enabling the device to conduct. The N+ region serves as the electron emission region, providing an electron injection path for the device to conduct, ensuring normal device turn-on and carrier transport. The P+ region is used to extract the potential of the P-body region, suppress the parasitic thyristor latch-up effect, improve the short-circuit withstand capability of the device, and ensure a stable ohmic contact between the emitter metal and the semiconductor.

[0047] Existing conventional trench gate IGBTs generally use a single P-type shielding layer at the bottom of the trench gate structure to protect the gate oxide electric field. Although this structure can slightly reduce the peak value of the gate oxide electric field under irradiation by clamping the potential of the shielding layer, the carrier extraction path of the single P-type shielding layer is limited and the extraction efficiency is limited. Excess holes generated during strong irradiation cannot be quickly discharged and recombinated, and tend to accumulate continuously at the gate oxide interface and drift region. As a result, the device has a long irradiation response period and extremely limited radiation resistance.

[0048] In this embodiment of the invention, a P-shielding layer and a P+shielding layer are disposed below the trench gate structure of the trench-type radiation-hardened high-voltage IGBT. The central region of the P-shielding layer integrates an N+ recombination center region, which is led out to the emitter. The PN junction formed by the P-shielding layer, P+shielding layer, and N-type drift layer forms a depletion layer in reverse breakdown voltage, reducing the gate oxide electric field of the trench. The N+ recombination center region is clamped at the emitter potential. When the IGBT device is subjected to strong radiation, the transient high-concentration holes generated by the N-type drift layer dope the P-type shielding layer. The diffusion direction of the impurity concentration decreases, and the holes are rapidly extracted through the path of P+ shielding layer → P- shielding layer → N+ recombination center region → emitter. At the same time, some holes recombine when passing through the N+ recombination center region, which avoids the hole concentration of the P-type shielding layer being too high. When the current flowing through the P-type shielding region is too large, it can trigger the NPN transistor (N-type drift layer - P+ / P- shielding layer - N+ recombination center) to conduct, accelerating the extraction of excess carriers. Therefore, this invention can improve the hole extraction efficiency during radiation transients, thereby improving the radiation resistance of IGBT devices.

[0049] Furthermore, this invention sequentially fabricates a P+ shielding layer, a P- shielding layer, and an N+ composite center layer below the trench using a vertical ion implantation process. Compared to the traditional trench gate IGBT fabrication process, this only adds an ion implantation process after trench etching. The N+ composite center region integrated in the P- shielding layer can form an excellent contact interface. Moreover, the doping concentration and area range of the ion implantation process are controllable. The new IGBT device does not require the introduction of additional fabrication steps with large errors or stringent processes such as etching and deposition (vertical ion implantation only requires control of three core parameters: energy, dose, and tilt angle, with extremely high equipment precision and the ability to correct deviations, while etching and deposition require strict control of many parameters, and problems such as inhomogeneity, damage, and stress are difficult to repair, requiring extensive experiments to optimize process parameters). Therefore, the trench-type radiation-hardened high-voltage IGBT provided by this invention is highly compatible with existing IGBT manufacturing processes and does not require adjustments to the main production line flow.

[0050] In some specific embodiments, to improve the short-circuit withstand capability of the device, the trench-type radiation-hardened high-voltage IGBT can adopt a wide trench design. The wide trench IGBT is an improved power device that optimizes the short-circuit withstand and radiation withstand performance of traditional trench IGBTs. Its core is to adopt an extremely wide gate trench design that occupies a larger area on the front side of the chip. By increasing the gate's ability to regulate the channel current, it effectively limits the saturation current and reduces the channel density of the IGBT, thereby reducing the device's saturation current and significantly improving the device's short-circuit withstand capability. However, the wider the trench, the larger the area it occupies on the front side, and the more space is originally distributed in the trench. The area of ​​the PN junction between the holes is compressed, which reduces the effective path for shallow holes generated by irradiation ionization to diffuse to the surface, be collected, and recombine (the P-type shielding layer at the bottom of the trench mainly extracts holes from the deeper N-type drift layer, while shallow holes near the device surface are led to the emitter through the P-body region and P+ region. The solution of this invention mainly targets the extraction of holes from the N-type drift layer by the P-type shielding layer). The transient accumulation time of holes near the gate dielectric interface is prolonged, thereby prolonging the device's irradiation response process. Therefore, in practical applications, it is necessary to adjust the width of the trench to achieve a trade-off between the device's short-circuit withstand capability and irradiation withstand capability.

[0051] In some preferred embodiments, the ratio of the width of the trench to the center-to-center distance between two adjacent trenches is 30% to 70%; in practical applications, the trench width range applicable to the IGBT device structure of the present invention is typically 1 to 10 μm.

[0052] See Figure 2 In some embodiments, the trench-type radiation-hardened high-voltage IGBT provided by the present invention can be prepared through steps S1 to S7:

[0053] S1, Fabricate a semiconductor layer, which includes a P-type collector region, an N-type buffer layer, an N-type drift layer, and a P-body region stacked sequentially.

[0054] This step employs semiconductor epitaxy, using heavily doped P-type silicon as a substrate (used as a P-type collector region). An N-type buffer layer is epitaxially grown on the P-type substrate, and then lightly doped N-type silicon is epitaxially grown on the N-buffer layer as an N-type drift layer. A P-body region is formed on the surface of the N-type drift layer through ion implantation and rapid thermal annealing. P-type ion implantation can use elements such as boron, indium, gallium, and aluminum (usually boron).

[0055] S2, etch trenches along a direction perpendicular to the surface of the P-body region, the trenches extending into the interior of the N-type drift layer, vertical ion implantation is performed at the bottom of the trenches, and a P+ shielding layer, a P- shielding layer and an N+ composite center region are formed sequentially below the trenches, the N+ composite center region is integrated into the central region of the P- shielding layer and is in contact with the trenches.

[0056] Specifically, the etching trenches are created using photolithography. Photoresist is spin-coated onto the semiconductor layer, and after exposure and development, the trench pattern is defined. Dry etching is then used to obtain a trench structure with a planarized bottom. Elements such as boron, indium, gallium, and aluminum are implanted stepwise along the vertical direction of the substrate towards the bottom of the trenches (boron is usually chosen, and the doping ions are boron ions or BF2). + To perform P-type doping, a lower P+ shielding layer can be formed first using high-energy implantation (e.g., 100~200keV), followed by a lower-energy implantation (e.g., 30~80keV) to form an upper P- shielding layer. Finally, a high-concentration N-type ion implantation is performed in a pre-defined area at the center of the P- shielding layer (e.g., a region occupying 30% of the plane area of ​​the P- shielding layer) to form an N+ recombination center region. N-type doping can be performed using one of the elements phosphorus, arsenic, or antimony. After vertical ion implantation, the device is thermally annealed to improve interface contact.

[0057] S3 forms silicon oxide at the bottom and inner wall of the trench.

[0058] In this embodiment of the invention, a layer of silicon oxide can be formed on the inner wall and bottom of the trench as a gate dielectric by thermal oxidation (preferably dry oxidation) process, and the thickness of the silicon oxide layer can be selected as 10~20nm; or a layer of silicon oxide can be deposited on the inner wall and bottom of the trench as a gate dielectric by PECVD process, so as to better control the thickness of the silicon oxide layer or obtain a thicker silicon oxide layer.

[0059] S4, fill the trench with N-type polysilicon, form a layer of silicon oxide on the surface of the N-type polysilicon, and connect the N-type polysilicon to the gate electrode.

[0060] Specifically, N-type polysilicon can be filled into the trench using chemical vapor deposition, and then thermally oxidized to form a layer of silicon oxide on its surface to completely encapsulate the N-type polysilicon with an insulating oxide dielectric. Alternatively, a layer of silicon oxide can be deposited on the surface of the N-type polysilicon using PECVD. Subsequently, electrode contact holes are etched in the isolation dielectric layer and the gate oxide layer and filled with metal to electrically connect the N-type polysilicon to the gate located on the surface of the IGBT device.

[0061] S5, an emitter region is prepared on the surface of the P-body region. The emitter region includes a P+ region and an N+ region, with the N+ region adjacent to the trench.

[0062] Specifically, P+ and N+ regions are defined by photolithography. The N+ region is adjacent to the trench sidewall to ensure that the channel is formed on the trench sidewall. Boron is implanted in the P+ region to form heavily doped P+ through ion implantation and annealing processes, and phosphorus or arsenic is implanted in the N+ region to form heavily doped N+. After ion implantation, overall annealing is used to repair damage and reduce contact resistance.

[0063] S6, deposit an isolation dielectric layer above the trench, and prepare an emitter above the isolation dielectric layer and the emitter region, and prepare a collector on the surface of the P-type collector region.

[0064] Specifically, an isolation dielectric layer is deposited above the trench using a PECVD process. The isolation dielectric layer can be Si3N4 or a SiO2 / Si3N4 stack, and it must completely cover the trench. Then, metal (copper, aluminum-copper alloy, or other metals) is sputtered over the isolation dielectric layer and the emitter region using a PVD process, and the emitter and gate regions on the surface of the IGBT device are defined by photolithography. In addition, the semiconductor substrate (P-type collector region) is thinned, and a metal layer (such as aluminum, titanium, silver, or a stacked structure of multiple metals) is prepared by magnetron sputtering on the back side of the thinned substrate to obtain the collector.

[0065] S7 electrically connects the N+ recombination center region to the emitter.

[0066] Specifically, conductive contact holes can be etched on the isolation dielectric layer covering the trench at the location corresponding to the N+ recombination center region (the size of the N-type polysilicon needs to be designed to reserve the position of the conductive contact holes in the N+ recombination center region). The contact holes are then filled with metal deposition to form a conductive path, allowing the N+ recombination center region to be directly connected to the upper emitter metal electrode; alternatively, the N+ recombination center region can be extended to the edge region of the device. Figure 1 The diagram shows the cross-sectional structure of the device. In a direction perpendicular to this cross-section, each functional layer can extend to the front and rear edges of the device and be connected to the emitter metal electrode through contact holes or leads in this lead-out area.

[0067] The core innovation of this invention lies in the key structural design of the trench-type radiation-hardened high-voltage IGBT (P+ shielding layer, P- shielding layer and N+ composite central region integrated in the central region of P- shielding layer) and the process steps of vertical ion implantation to form the innovative structure. For experimental methods, process equipment, material selection and specific process parameters not explicitly described in this technical solution, they are all conventional technical means in this field and can be directly reused from existing mature trench-type IGBT device manufacturing processes.

[0068] Specifically, the unit operations involved in the technical solution of this invention, such as epitaxial growth, ion implantation, dry etching, rapid thermal annealing, PECVD (plasma-enhanced chemical vapor deposition), and PVD (physical vapor deposition), utilize semiconductor epitaxial equipment, ion implanters, etching machines, annealing furnaces, chemical vapor deposition equipment, and physical vapor deposition equipment, all of which are general-purpose / commercial equipment in the semiconductor device manufacturing field and have a mature industrial application foundation. The silicon substrate material, doping impurities (boron / phosphorus / arsenic, etc.), insulating dielectric (silicon oxide / silicon nitride, etc.), gate material (N-type polysilicon, etc.), and metal electrode / interconnect material (copper, aluminum, titanium, silver, gold, aluminum alloy, copper alloy, etc.) are all standard commercial materials widely used in the field of power semiconductor devices, and their compatibility and reliability have been fully verified. The specific parameters such as epitaxial growth temperature and gas flow rate, ion implantation energy and dosage, etching gas ratio and power, annealing temperature and time, metal deposition thickness and annealing conditions can be determined by those skilled in the art based on existing process libraries through conventional process debugging methods such as orthogonal experiments and single-variable optimization, without needing to break through existing process boundaries.

[0069] The above-mentioned undetailed contents are all mature and reusable technical accumulations in the semiconductor manufacturing field. Those skilled in the art, in combination with the core process steps and structural design disclosed in this invention, can successfully implement this technical solution on the existing IGBT / CMOS / MEMS process platform without adding special equipment or carrying out creative process development, which can ensure the integrity, feasibility and industrialization feasibility of the technical solution of this invention.

[0070] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A trench type radiation-hardened high voltage IGBT, characterized by, include: collector; A semiconductor layer is disposed on the collector electrode; the semiconductor layer includes a P-type collector region, an N-type buffer layer, an N-type drift layer, a P-body region and an emitter region stacked sequentially, and the emitter region includes a P+ region and an N+ region; A trench embedded in the semiconductor layer; the trench is embedded in the emitter region and the P-body region along a direction perpendicular to the surface of the emitter region and extends into the interior of the N-type drift layer, the N+ region is adjacent to the trench; the interior of the trench is provided with N-type polysilicon, the N-type polysilicon is wrapped with an insulating oxide dielectric. A P-shielding layer and a P+shielding layer are disposed directly below the trench. The P-shielding layer is in contact with the trench, and the P+shielding layer is located below the P-shielding layer. An N+ composite central region is integrated in the central region of the P-shielding layer, and the N+ composite central region is in contact with the trench. An isolation medium layer is disposed above the trench; as well as, An emitter located above the emitter region and the isolation dielectric layer; The N-type polysilicon is a gate-controlled N-type polysilicon, and the N+ composite central region is electrically connected to the emitter.

2. The grooved radiation-hardened high-voltage IGBT according to claim 1, characterized in that, The doping concentration of the P- shielding layer is 1 x 10 16 cm -3 ~5 x 10 17 cm -3 The doping concentration of the P+ shielding layer is 1 x 10 18 cm -3 ~5 x 10 19 cm -3 .

3. The grooved radiation-hardened high-voltage IGBT according to claim 1, characterized in that, The insulating oxide medium is silicon oxide.

4. The grooved radiation-hardened high-voltage IGBT according to claim 1, characterized in that, The ratio of the width of the groove to the center-to-center distance between two adjacent grooves is 30% to 70%.

5. The grooved radiation-hardened high-voltage IGBT according to claim 1, characterized in that, The width of the groove is 1~10μm.

6. The grooved radiation-hardened high-voltage IGBT according to claim 1, characterized in that, The N+ complex center region has a doping concentration of 1 x 10 18 cm -3 ~5 x 10 19 cm -3 .

7. A method for preparing a grooved radiation-hardened high-voltage IGBT, characterized in that, Including the following steps: S1, Prepare a semiconductor layer, the semiconductor layer comprising a P-type collector region, an N-type buffer layer, an N-type drift layer, and a P-body region stacked sequentially; S2, etch trenches along a direction perpendicular to the surface of the P-body region, the trenches extending into the interior of the N-type drift layer, perform vertical ion implantation at the bottom of the trenches, and sequentially form a P+ shielding layer, a P- shielding layer, and an N+ composite center region directly below the trenches, the N+ composite center region being integrated into the central region of the P- shielding layer and in contact with the trenches; S3, silicon oxide is formed at the bottom and inner wall of the trench; S4, N-type polysilicon is filled into the trench, a layer of silicon oxide is formed on the surface of the N-type polysilicon so that the N-type polysilicon is wrapped by silicon oxide, and the N-type polysilicon is connected to the gate electrode; S5, an emitter region is formed on the surface of the P-body region, the emitter region including a P+ region and an N+ region, the N+ region being adjacent to the trench; S6, deposit an isolation dielectric layer above the trench, and prepare an emitter above the isolation dielectric layer and the emitter region, and prepare a collector on the surface of the P-type collector region; S7, electrically connect the N+ composite center region to the emitter.

8. The method for preparing a grooved radiation-hardened high-voltage IGBT according to claim 7, characterized in that, Emitter regions are prepared on the surface of the P-body region using an ion implantation process.

9. The method for preparing a grooved radiation-hardened high-voltage IGBT according to claim 7, characterized in that, In the step of forming the P+ shielding layer and the P- shielding layer by vertical ion implantation, the P-type doping element used is at least one of boron, indium, gallium, and aluminum.

10. The method for preparing a grooved radiation-hardened high-voltage IGBT according to claim 7, characterized in that, In the step of forming the N+ composite center region by vertical ion implantation, the N-type dopant used is at least one of phosphorus, arsenic, and antimony.

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