Semiconductor structure and method of forming the same

Abstract

A method for forming a gate structure according to embodiments of the present disclosure includes: receiving a precursor structure, the precursor structure including a substrate, a first nanostructure located above a first region of the substrate, and a second nanostructure located above a second region of the substrate; depositing a gate dielectric layer over the first nanostructure and the second nanostructure; depositing a first work function metal layer over the first nanostructure and the second nanostructure; depositing a diffusion barrier layer over the first work function metal layer; selectively removing the diffusion barrier layer and the first work function metal layer from the first nanostructure above the first region; depositing a second work function metal layer over the first nanostructure and the second nanostructure; and depositing a metal filler layer over the second work function metal layer. Embodiments of this application also relate to semiconductor structures and methods for forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization typically provides benefits through increased production efficiency and reduced associated costs. However, such miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. Fin field-effect transistors (FinFETs) and gate all-around (GAA) transistors (both also known as non-planar transistors) are examples of multi-gate devices, which have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have an elevated channel (e.g., the gates wrap the top and sidewalls of a semiconductor material “fin” extending from the substrate) that is surrounded by gates on more than one side. Compared to planar transistors, such a configuration provides better channel control and significantly reduces SCE (particularly by reducing subthreshold leakage, i.e., the coupling between the source and drain of the FinFET in the “off” state). GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because of this configuration, GAA transistors can also be called gate-around transistors (SGT) or multi-bridge channel (MBC) transistors. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. These shapes of the channel region also give GAA transistors different names. For example, a GAA transistor with a nanosheet channel region can be called a nanosheet transistor.

[0004] FinFETs have long been the primary choice for transistors when high-performance computing is desired. GAA transistors may eventually replace FinFETs because they offer improved channel control and enable further miniaturization. However, the fabrication of GAA transistors presents challenges. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a precursor structure including: a substrate; a first plurality of nanostructures located above a first region of the substrate; a second plurality of nanostructures located above a second region of the substrate; and an isolation member located above the substrate; depositing a gate dielectric layer above the surfaces of the first plurality of nanostructures and the second plurality of nanostructures; depositing a first work function metal layer above the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; depositing a diffusion barrier layer above the first work function metal layer such that the diffusion barrier layer encloses the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; selectively removing the diffusion barrier layer and the first work function metal layer from the first plurality of nanostructures above the first region; after the selective removal, depositing a second work function metal layer above the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; and depositing a metal fill layer above the second work function metal layer, wherein a portion of the gate dielectric layer extends along the top surface of the isolation member.

[0006] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a precursor structure including: a substrate; a first base fin and a second base fin located above the substrate; an isolation structure located above the substrate and disposed between the first base fin and the second base fin; a first nanostructure located above the first base fin; and a second nanostructure located above the second base fin; depositing a gate dielectric layer over the first base fin, the first nanostructure, the second base fin, the second nanostructure, and the isolation structure; depositing a p-type work function metal layer over the first nanostructure and the second nanostructure; depositing a diffusion barrier layer over the p-type work function metal layer such that the diffusion barrier layer encapsulates the first nanostructure and the second nanostructure; selectively removing the diffusion barrier layer and the p-type work function metal layer from the first nanostructure; after the selective removal, depositing an n-type work function metal layer over the first nanostructure and the second nanostructure; depositing a protective layer over the n-type work function metal layer; and depositing a metal fill layer over the protective layer, wherein the protective layer comprises a titanium-based material, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

[0007] Some embodiments of this application provide a semiconductor structure including: a first base fin and a second base fin, located above a substrate; an isolation member, located above the substrate and in contact with the sidewalls of the first base fin and the second base fin; a first plurality of nanostructures disposed above the first base fin; a second plurality of nanostructures disposed above the second base fin; a gate dielectric layer encapsulating the first plurality of nanostructures and the second plurality of nanostructures, the gate dielectric layer being disposed above the top surface of the first base fin, the second base fin and the isolation member; a first work function layer encapsulating the second plurality of nanostructures and being disposed above the second base fin; a diffusion barrier layer encapsulating the second plurality of nanostructures; a second work function layer encapsulating the first plurality of nanostructures above the first base fin and being disposed above the diffusion barrier layer above the second base fin; and a protective layer located above the second work function layer above the first base fin and the second base fin, wherein the diffusion barrier layer comprises titanium tungsten nitride. Attached Figure Description

[0008] The various aspects of embodiments of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the components are not drawn to scale. In fact, the dimensions of the components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be considered limiting, as the embodiments of this disclosure are equally well applicable to other embodiments.

[0009] Figure 1 This is a flowchart illustrating a method for forming a semiconductor device according to various aspects of embodiments of the present disclosure.

[0010] Figures 2 to 19 The first and second regions of the precursor structure are shown according to Figure 1 Partial cross-sectional views of each manufacturing stage of the method described.

[0011] Figure 20 The following are shown as various aspects of embodiments according to this disclosure. Figure 19 A partial cross-sectional view of line A-A' in the diagram.

[0012] Figure 21 The following aspects of embodiments according to this disclosure are shown. Figure 19 A partial cross-sectional view of line B-B' in the diagram.

[0013] Figure 22 The embodiments of the present disclosure are shown in which the gate structure includes at least one seam-optional semiconductor device.

[0014] Figure 23The diffusion rate of aluminum in different materials is shown. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0017] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to encompass values ​​within a reasonable range that takes into account variations inherent during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having numerically related characteristics, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer having a thickness of "about 5 nm" could include a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0018] GAA transistors have a gate structure that extends partially or completely around the channel region to provide access to the channel region on one or more sides. The channel region of a GAA transistor can include multiple sheet-like or wire-like nanoscale channel components, stacked one on top of another or placed side-by-side. The formation of GAA transistors faces its own challenges. For example, in the absence of a silicon-germanium channel to help reduce the threshold voltage for p-type GAA transistors, a work function metal layer with a work function closer to the valence band is needed to maintain a low threshold voltage. Impurities diffusing from the n-type work function metal layer to the p-type work function metal layer can affect the performance of p-type GAA transistors.

[0019] This disclosure relates to forming gate structures for p-type and n-type GAA transistors on a substrate. The precursor structure includes a first nanostructure over a first region and a second nanostructure over a second region. After forming an interface layer and a gate dielectric layer over the surfaces of the first and second nanostructures, a first work function metal (WFM) layer is deposited over the first and second regions. After depositing the first WFM layer, a diffusion barrier layer is deposited over the first WFM layer. The diffusion barrier layer and the first WFM layer are then selectively removed from the first region to expose the gate dielectric layer. After selective removal, a second WFM layer is deposited over the first and second regions. A binder layer and a metal filler are then deposited over the first and second regions. In some examples, the diffusion barrier layer comprises titanium tungsten nitride (TiWN).

[0020] Various aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating various aspects of a method 100 for forming a gate structure for stacking multi-gate devices according to embodiments of the present disclosure. Method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some steps described may be replaced, eliminated, or moved around. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 19 Description method 100, Figures 2 to 19 This is a partial cross-sectional view of the precursor structure 200 at different manufacturing stages according to an embodiment of method 100. Because the precursor structure 200 will be fabricated into a semiconductor device 200 at the end of the manufacturing process, the precursor structure 200 may be referred to as the semiconductor device 200, depending on the context. Furthermore, throughout this application and across different embodiments, the same reference numerals denote the same components having similar structures and compositions, unless otherwise stated. Source / drain regions may refer to the source or drain, individually or collectively, depending on the context.

[0021] refer to Figures 1 to 9Method 100 includes block 102, wherein a first nanostructure 2080 is formed between two first source / drain components 232N above a first region 1000 of substrate 202, and a second nanostructure 2080 is formed between two second source / drain components 232P above a second region 2000 of substrate 202. The operation in block 102 includes: forming a stack 204 above substrate 202. Figure 2 As shown in the diagram); a portion of the patterned stack 204 and substrate 202 is used to form a fin structure 212 (as shown in the diagram). Figure 3 As shown in the diagram); a dummy gate stack 220 is formed above the channel region of the fin structure 212 (as shown in the diagram). Figure 4 and Figure 5 As shown in the diagram); forming a gate spacer layer 226 and recessing the source / drain regions 212SD of the fin structure 212 (as shown in the diagram); Figure 6 As shown in the diagram); forming the first source / drain component 232N and the second source / drain component 232P ( Figure 7 As shown); deposited contact etch stop layer (CESL) 236 and interlayer dielectric (ILD) layer 238 (as shown); Figure 8 As shown in the figure); and removing the dummy gate stack 220 and releasing the first nanostructure 2080 and the second nanostructure 2080 in the first region 1000 and the second region 2000 (as ... Figure 9 As shown in the image).

[0022] refer to Figure 2 Substrate 202 is part of precursor structure 200 undergoing the various operations of method 100. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 may optionally include an epitaxial layer (epi layer), which may be strained for performance enhancement, and may include silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structures, and / or may have other suitable enhancement components. Substrate 202 may include various doping configurations as known in the art depending on design requirements. In the depicted embodiments, substrate 202 includes a first region 1000 and a second region 2000. Substrate 202 includes a p-type well 202P (i.e., a p-type dopant distribution) over the first region 1000 and an n-type well 202N (i.e., an n-type dopant distribution) over the second region 2000. In some embodiments, the n-type dopant used to form the n-type well 202N may include phosphorus (P) or arsenic (As), and the p-type dopant used to form the p-type well 202P may include boron (B). Suitable doping for the n-type well 202N or the p-type well 202P may include ion implantation and / or diffusion processes of the dopant.

[0023] Still referencing Figure 2 The stack 204 includes a sacrificial layer 206 of a first semiconductor, interleaved with a channel layer 208 composed of a second semiconductor. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layer 206 comprises silicon germanium (SiGe), and the channel layer 208 comprises silicon (Si). It should be noted that the three (3) layers of the sacrificial layer 206 and the three (3) layers of the channel layer 208 are arranged alternately, as shown below. Figure 2 The illustrations shown are for illustrative purposes only and are not intended to limit the scope beyond what is specifically set forth in the claims. It will be understood that any number of epitaxial layers may be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0024] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 5 nm and about 10 nm, and all channel layers 208 may have a substantially uniform second thickness between about 2 nm and about 8 nm. The first and second thicknesses may be identical or different. As described in more detail below, channel layers 208 or portions thereof may be used as channel members for subsequently formed multi-gate devices, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layers 206 in the channel regions may eventually be removed and used to define the vertical distance between adjacent channel regions for subsequently formed multi-gate devices, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0025] The layers in stack 204 can be deposited at temperatures between about 600°C and about 800°C using molecular beam epitaxy (MBE), vapor deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some instances, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer, and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free (i.e., having a dopant content from about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 (intrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204.

[0026] refer to Figure 3 The fin-shaped structure 212 is formed by a portion of the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 can be deposited over the stack 204. Figure 2(As shown in the diagram) to form an etching mask. The hard mask layer 210 can be a single layer or multiple layers. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer above the pad oxide layer. The fin structure 212 can be partially patterned from the stack 204 and the substrate 202 using photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. Figure 3 As shown, the etching process forms trenches extending through portions of the stack 204 and the substrate 202. The trenches define a fin structure 212, including a base fin formed from the substrate 202. Figure 3 The diagram shows a first base fin 212PB and a second base fin 212NB. In some embodiments, dual patterning or multiple patterning processes can be used to define fin structures having a pitch, for example, smaller than that achievable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching portions of the stack 204 and the substrate 202. Figure 3 As shown, the fin structure 212, together with the sacrificial layer 206 and the channel layer 208 therein, extends vertically along the Z direction and longitudinally along the X direction.

[0027] Adjacent to the fin structure 212 forms an isolation component 214. In some embodiments, the isolation component 214 may be formed in a trench to isolate the fin structure 212 from an adjacent active region, which may be another fin structure. The isolation component 214 may also be referred to as a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over a substrate 202 to fill the trench. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, spin-coating processes, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by dry etching processes, wet etching processes, and / or combinations thereof to form the STI component 214. Figure 3As shown, the lower portions of the first base fin 212PB and the lower portions of the second base fin 212NB are disposed in or surrounded by the STI component 214, and the remaining portion of the fin structure 212 formed by the stack 204 rises above the STI component 214 after being recessed. The upper portions of the first base fin 212PB and the second base fin 212NB also rise above the STI component 214.

[0028] Now for reference Figure 4 and Figure 5 A dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 220 serves as a placeholder to undergo various processes and is removed and replaced by a functional gate structure. Other processes and configurations are possible. Figure 5 In some embodiments shown, a dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 in the first region 1000 and the second region 2000 can each be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0029] The formation of the dummy gate stack 220 may include depositing layers in the dummy gate stack 220 and patterning these layers. (See reference...) Figure 4 A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be deposited over the precursor structure 200. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), ALD, oxygen plasma oxidation, thermal oxidation, or other suitable processes. In some instances, the dummy dielectric layer 216 may comprise silicon oxide. When the dummy dielectric layer 216 is formed using an oxidation process, it can be selectively formed on the exposed surfaces of the fin structure 212, such as... Figure 4 As shown in the diagram. Subsequently, the dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 may comprise polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, as shown. Figure 5As shown in the diagram. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. Figure 5 As shown, no dummy gate stack 220 is disposed above the source / drain region 212SD of the fin structure 212.

[0030] Now for reference Figure 6 At least one gate spacer layer 226 is deposited over the dummy gate stack 220 in the first region 1000 and the second region 2000. In some embodiments, the at least one gate spacer layer 226 is conformally deposited over the precursor structure 200, including over the top surface and sidewalls of the dummy gate stack 220. The term “conformal” is used herein to conveniently describe a layer having a substantially uniform thickness over the respective regions. The at least one gate spacer layer 226 may be a single layer or multiple layers. In the depicted embodiments, the at least one gate spacer layer 226 includes a first spacer layer 226-1 and a second spacer layer 226-2 disposed above the first spacer layer 226-1. The composition of the first spacer layer 226-1 may differ from the composition of the second spacer layer 226-2. In some embodiments, the dielectric constant of the first spacer layer 226-1 is greater than the dielectric constant of the second spacer layer 226-2. At least one gate spacer layer 226 (including a first spacer layer 226-1 and a second spacer layer 226-2) may comprise silicon oxide, silicon carbonitride, silicon carbon oxycarbonate, silicon carbonitride, or silicon nitride. At least one gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as CVD, subatmospheric pressure CVD (SACVD), ALD, or other suitable processes. For ease of reference and simplicity, at least one gate spacer layer 226 may also be referred to as gate spacer layer 226.

[0031] Still referencing Figure 6The source / drain regions 212SD of the fin structure 212 are recessed to form a source / drain trench 228. In some embodiments, the source / drain regions 212SD not covered by the dummy gate stack 220 and the gate spacer layer 226 are etched by dry etching or a suitable etching process to form the source / drain trench 228. For example, the dry etching process can be implemented with oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 6 In some embodiments illustrated, the source / drain regions 212SD of the fin structure 212 are recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends into the substrate 202 beneath the stack 204.

[0032] refer to Figure 7An internal spacer component 230 is formed. After forming the source / drain trench 228, the sacrificial layer 206 in the channel region 212C is selectively and partially recessed to form internal spacer recesses, while the exposed channel layer 208 is substantially unetched. In embodiments where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), selectively and partially recessing the sacrificial layer 206 may include a SiGe oxidation process followed by SiGe oxide removal. In this embodiment, the SiGe oxidation process may include the use of ozone (O3). In some other embodiments, selective recessing may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree to which the sacrificial layer 206 is recessed is controlled by the duration of the etching process. A selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. A selective wet etching process may include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). After forming the internal spacer recess, an internal spacer material layer is deposited over the precursor structure 200 (including within the internal spacer recess). The internal spacer material layer may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material, and may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The deposited internal spacer material layer is then etched back to remove excess internal spacer material layer located above the sidewalls of the gate spacer layer 226 and the channel layer 208, thereby forming the internal spacer component 230. In some embodiments, the etching process for forming the internal spacer component 230 can be a dry etching process, which includes using oxygen-containing gases, hydrogen (H2), nitrogen (N2), fluorine-containing gases (e.g., NF3, CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof. Although not explicitly shown, a cleaning process can be performed after the etching process to remove native oxides and debris from the surface of the channel layer 208.

[0033] Still referencing Figure 7A first source / drain component 232N is formed over the source / drain region 212SD in the first region 1000, and a second source / drain component 232P is formed over the source / drain region 212SD in the second region 2000. Each of the first source / drain component 232N and the second source / drain component 232P can be epitaxially and selectively formed from the exposed sidewalls of the channel layer 208 and the exposed surface of the substrate 202, while the sidewalls of the sacrificial layer 206 remain covered by the internal spacer component 230. Suitable epitaxial processes for forming the first source / drain component 232N and the second source / drain component 232P include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process may use a gaseous precursor that interacts with the composition of the substrate 202 and the channel layer 208. In some embodiments, the parameters of the epitaxial growth process are selected such that the first source / drain component 232N and the second source / drain component 232P are not epitaxially deposited on the internal spacer component 230. That is, overgrowth of the first source / drain component 232N and the second source / drain component 232P can be merged on some of the internal spacer components 230.

[0034] The first source / drain component 232N and the second source / drain component 232P can have different conductivity types, and each can include more than one epitaxial layer. Figure 7In some embodiments illustrated, the first source / drain component 232N above the first region 1000 may be an n-type source / drain component comprising silicon (Si) doped with an n-type dopant (such as phosphorus (P) or arsenic (As)), and the second source / drain component 232P above the second region 2000 may be a p-type source / drain component comprising silicon germanium (SiGe) doped with a p-type dopant (such as boron (B)). When each of the first source / drain components 232N comprises multiple epitaxial layers, the epitaxial layers closer to the channel layer 208 and the substrate 202 may include a lower n-type dopant concentration, and the epitaxial layers farther from the channel layer 208 and the substrate may include a higher n-type dopant concentration. Similarly, when each of the first source / drain components 232N comprises multiple epitaxial layers, the epitaxial layers closer to the channel layer 208 and the substrate 202 may include a lower p-type dopant concentration, and the epitaxial layers farther from the channel layer 208 and the substrate may include a higher p-type dopant concentration. Furthermore, when each of the first source / drain components 232N comprises multiple epitaxial layers, the epitaxial layers closer to the channel layer 208 and the substrate 202 may include a lower germanium (Ge) content, and the epitaxial layers farther from the channel layer 208 and the substrate may include a higher germanium (Ge) content. Because the first source / drain components 232N and the second source / drain components 232P have different compositions and are formed in different regions, they are formed separately. In one embodiment, a patterned mask layer, such as a photoresist layer or a bottom anti-reflective coating (BARC) layer, may be formed to cover the second region 2000, while the first source / drain component 232N is formed in the first region 1000. Then, another patterned mask layer may be formed to cover the first region 1000, while the second source / drain component 232P is formed in the second region 2000. In another embodiment, the order may be reversed, and the second source / drain component 232P is formed first in the second region 2000. Although not explicitly shown in the figure, annealing processes can be performed to obtain the desired electronic contribution of dopants in the semiconductor host, such as silicon-germanium (SiGe) or silicon (Si). Annealing processes can include rapid thermal annealing (RTA), laser-spiked annealing, flash annealing, or furnace annealing. Annealing processes can include peak annealing temperatures between approximately 900°C and approximately 1000°C. In these embodiments, the peak annealing temperature can be maintained for a duration measured in seconds or microseconds.

[0035] refer to Figure 8A contact etch stop layer (CESL) 236 and an interlayer dielectric (ILD) layer 238 are deposited over the first source / drain component 232N and the second source / drain component 232P. CESL 236 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art. ILD layer 238 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, CESL 236 is first conformally deposited over the first region 1000 and the second region 2000 using CVD, ALD, plasma-enhanced chemical vapor deposition (PECVD) processes and / or other suitable deposition or oxidation processes, and ILD layer 238 is deposited over CESL 236 using spin coating, FCVD, CVD, or other suitable deposition techniques. In some embodiments, after forming the ILD layer 238, the precursor structure 200 may be annealed to improve the integrity of the ILD layer 238. For example... Figure 8 As shown, after depositing CESL 236 and ILD layers 238, planarization processes, such as chemical mechanical polishing (CMP), can be performed to remove excess material. Figure 8 As shown, the planarization process also exposes the dummy electrode layer 218 of the dummy gate stack 220 in the first region 1000 and the second region 2000.

[0036] Now for reference Figure 9The exposed dummy gate stack 220 is removed, and the sacrificial layer 206 in the channel region 210C is selectively removed to release the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000. Removal of the dummy gate stack 220 may include one or more etching processes selectively targeting the material in the dummy gate stack 220. For example, removal of the dummy gate stack 220 may be performed using selective wet etching, selective dry etching, or a combination thereof. After removal of the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 210C are exposed. Thereafter, the sacrificial layer 206 in the channel region 210C is selectively removed to release the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000. The first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000 may also be referred to as channel members. Selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some other embodiments, selective removal includes SiGe oxidation followed by removal of silicon germanium oxide. For example, oxidation can be provided by ozone cleaning, and then silicon germanium oxide can be removed by an etchant such as NH4OH.

[0037] refer to Figure 1 and Figure 10 Method 100 includes block 104, wherein an interface layer 240 is formed over the first nanostructure 2080 and the second nanostructure 2080. For example... Figure 10 As shown, a first nanostructure 2080 is disposed above a first base fin 212PB in a first region 1000, and a second nanostructure 2080 is disposed above a second base fin 212NB in ​​a second region 2000. Because the first base fin 212PB is patterned by a p-type well 202P, it has the same composition as the p-type well 202P. Because the second base fin 212NB is patterned by an n-type well 202N, it has the same composition as the n-type well 202N. Figure 10In this configuration, the first region 1000 can be connected to the second region 2000. Therefore, the p-type well 202P can be connected to the n-type well 202N. The interface layer 240 may comprise silicon oxide or silicon oxynitride or other suitable materials. In some embodiments, the interface layer 240 may be deposited using suitable methods on the surface of the first nanostructure 2080, the surface of the second nanostructure, the top surfaces of the first base fin 212PB and the second base fin 212NB, and above the sidewalls of the portions of the first base fin 212PB and the second base fin 212NB located above the isolation member 214, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), ozone oxidation, thermal oxidation, or other suitable methods. The interface layer 240 serves to control and reduce gate leakage current and improve the gate dielectric layer 242 ( Figure 11 The interface layer 240 (shown in the diagram) functions as an interfacial bonding layer between the semiconductor surface and the nanostructure (including the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000). In the depicted embodiment, the interface layer 240 is formed using thermal oxidation, and the interface layer 240 is selectively deposited on the semiconductor surface rather than on the dielectric surface, such as the top surface of the isolation member 214.

[0038] refer to Figure 1 and Figure 11 Method 100 includes block 106, wherein a gate dielectric layer 242 is deposited over interface layer 240. In some embodiments, gate dielectric layer 242 is a high-k dielectric layer because its dielectric constant is greater than that of silicon dioxide (~3.9). In some embodiments, gate dielectric layer 242 may include doped or undoped hafnium oxide (HfO2), doped or undoped zirconium oxide (ZrO2), doped or undoped titanium oxide (TiO2), or doped or undoped aluminum oxide (Al2O3). For example, gate dielectric layer 242 may include hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), or hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO2), hafnium titanium oxide (HfTiO), or combinations thereof. At the end of the operation in box 106, each of the first nanostructure 2080 in the first region 1000 and the second nanostructure 2080 in the second region 2000 is enclosed by the interface layer 240 and the gate dielectric layer 242. Furthermore, as... Figure 11 As shown, the deposition of the gate dielectric layer 242 may not be selective, and the gate dielectric layer 242 may be deposited over the isolation member 214.

[0039] refer to Figure 1 and Figure 12Method 100 includes block 108, wherein a first work function metal (WFM) layer 244 is deposited over a first region 1000 and a second region 2000. In some embodiments, the first WFM layer 244 may be a p-type WFM layer and may include titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten carbonitride (WCN), molybdenum (Mo), or other suitable p-type work function materials. In one embodiment, the first WFM layer 244 includes titanium nitride (TiN). The first WFM layer 244 may be deposited using ALD at a temperature between about 350°C and about 450°C. Figure 12 As shown, the thickness of the first WFM layer 244 is such that the gap between two adjacent first nanostructures 2080 or second nanostructures 2080 is not completely filled. In some instances, the thickness of the first WFM layer 244 can be between about 7 Å and 13 Å. When the first WFM layer 244 is formed from a two-component material (such as titanium nitride), it has a grain size greater than 3.5 nm, such as between 3.5 nm and about 4.5 nm.

[0040] refer to Figure 1 and Figure 13 Method 100 includes block 110, wherein a diffusion barrier layer 246 is deposited over a first WFM layer 244. The diffusion barrier layer 246 is used to block or prevent impurities from diffusing from a second WFM layer 250 into the first WFM layer 244. In some embodiments, the diffusion barrier layer 246 comprises titanium (Ti), tungsten (W), and nitrogen (N) to block aluminum (Al) from diffusing from the second WFM layer 250 into the first WFM layer 244. As described below, the second WFM layer 250 comprises aluminum (Al) and may be referred to as an aluminum-containing layer. It has been observed that aluminum (Al) diffusion into the first WFM layer 244 affects the performance of p-type GAA transistors. In particular, aluminum (Al) diffusion into the first WFM layer 244 can increase the threshold voltage (Vt) of the p-type GAA transistor. Referring now to... Figure 23 , Figure 23 The diffusion rates of aluminum (Al) in different materials are shown, including titanium aluminum carbide (TiAlC), titanium nitride (TiN), titanium oxynitride (TiNO), hafnium oxide (HfO), and tungsten nitride (WN). Figure 23As shown, aluminum exhibits the highest diffusion rate in titanium aluminum carbide (TiAlC) and the lowest in tungsten nitride (WN). The diffusion rate of aluminum in titanium oxynitride (TiNO) falls between that in titanium nitride (TiN) and tungsten nitride (WN). While tungsten nitride (WN) possesses excellent ability to block or slow down aluminum diffusion, it also exhibits a wide range of electrical conductivities. Experimental results show that the resistivity of deposited tungsten nitride (WN) can exceed 10000 µΩ / cm, which is one to two orders of magnitude higher than that of titanium nitride (TiN). This implies that when the diffusion barrier layer 246 is formed solely of tungsten nitride (WN), its high resistivity may increase the gate resistance, which may not be desirable in all applications.

[0041] According to embodiments of the present disclosure, the diffusion barrier layer 246 can be deposited using atomic layer deposition (ALD) at a temperature between about 350°C and about 400°C. In some embodiments, the ALD process for depositing the diffusion barrier layer 246 includes using a titanium-containing precursor, a tungsten-containing precursor, and a nitrogen-containing precursor. In these embodiments, the diffusion barrier layer 246 may include titanium (Ti), tungsten (W), and nitrogen (N). According to embodiments of the present disclosure, the ALD deposition of the diffusion barrier layer 246 may include at least one tungsten nitride cycle and at least one titanium nitride cycle. In some embodiments, the tungsten nitride ALD cycle includes using a tungsten-containing precursor (such as tungsten hexafluoride (WF6) or tungsten hexacarbonyl (W(CO)6)) and a nitrogen-containing precursor (such as ammonia (NH3)). The titanium nitride ALD cycle involves the use of titanium-containing precursors (such as TDMAT (tetra(dimethylamino)titanium), titanium tetrachloride (TiCl4), TDEAT (tetra(diethylamino)titanium), or TEMATi (tetra(ethylmethylamino)titanium)) and nitrogen-containing precursors (such as ammonia (NH3)). It should be noted that each ALD cycle also includes the use of a purge gas in each precursor cycle to remove excess precursors.

[0042] In terms of composition, the diffusion barrier layer 246 may comprise titanium tungsten nitride (TiWN) having a tungsten content between about 10% and about 70%. When the tungsten content is less than 10%, the diffusion barrier layer 246 may not satisfactorily block aluminum diffusion. When the tungsten content is greater than 70%, the diffusion barrier layer 246 may increase the gate resistance and make it difficult to selectively remove the diffusion barrier layer 246 in block 112. In some examples, the resistivity of the diffusion barrier layer 246 may be between about 980 µΩ / cm and about 42000 µΩ / cm. The grain size of the diffusion barrier layer 246 may be between about 2.85 nm and about 3.16 nm. The density of the diffusion barrier layer 246 may be about 5.63 g / cm³. 3 Approximately 9.2 g / cm 3Between. Typically, diffusion barrier layer 246 exhibits greater aluminum diffusion blocking capability at higher densities. Furthermore, diffusion barrier layer 246 exhibits greater aluminum diffusion blocking capability at higher resistivity. When diffusion barrier layer 246 is formed from a three-component material such as titanium tungsten nitride (TiWN), it has a grain size between 2.8 nm and approximately 3.2 nm. It should be noted that the grain size of diffusion barrier layer 246 is smaller than the grain size of the first WFM layer 244.

[0043] like Figure 13 As shown, the diffusion barrier layer 246 is deposited such that it encloses each of the first nanostructures 2080 above the first region 1000 and each of the second nanostructures 2080 above the second region 2000.

[0044] refer to Figure 1 , Figure 14 and Figure 15 Method 100 includes block 112, wherein a first WFM layer 244 and a diffusion barrier layer 246 are selectively removed over a first region 1000. To selectively remove the diffusion barrier layer 246 and the first WFM layer 244 over the first region 1000, a bottom antireflective coating (BARC) layer 248 is formed over a second region 2000, while the first region 1000 is exposed. In an exemplary process, a blanket BARC layer is deposited over the first region 1000 and the second region 2000, and then a photoresist layer is deposited over the blanket BARC layer. The photoresist layer is pre-baked, patterned by exposure to patterned radiation reflected through or from the mask, post-baked, and developed using a developer in a development process to form a patterned photoresist layer. The patterned photoresist layer is used as an etch mask to pattern the blanket BARC layer to form the BARC layer 248, as shown. Figure 14 As shown in the diagram. With the BARC layer 248 covering the second region 2000, the diffusion barrier layer 246 and the first WFM layer 244 above the first region 1000 are removed. The removal of the diffusion barrier layer 246 and the first WFM layer 244 can be performed using one or more etching processes. For example, the diffusion barrier layer 246 and the first WFM layer 244 can be removed using a wet etching process comprising a mixture of sulfuric acid and hydrogen peroxide (SPM), a mixture of ammonium hydroxide and hydrogen peroxide (SC1), or a mixture of hydrochloric acid and hydrogen peroxide (SC2), or a dry etching process using plasma containing chlorine gas (e.g., Cl2 and / or BCl3) and argon (Ar). After removing the diffusion barrier layer 246 and the first WFM layer 244 from the first region 1000, the BARC layer 248 can be removed from the second region 2000 using an ashing or selective etching process, such as... Figure 15As shown in the diagram, the diffusion barrier layer 246 and the first WFM layer 244 can be considered as p-type WFM layers. In some instances, the total thickness of the diffusion barrier layer 246 and the first WFM layer 244 can be between about 10 Å and about 33 Å. In some embodiments, the thickness of the diffusion barrier layer 246 is greater than the thickness of the first WFM layer 244.

[0045] refer to Figure 1 and Figure 16 Method 100 includes block 114, wherein a second WFM layer 250 is deposited over a first region 1000 and a second region 2000. The second WFM layer 250 has a different conductivity type than the first WFM layer 244. In some embodiments, the second WFM layer 250 is an n-type WFM layer, while the first WFM layer 244 is a p-type WFM layer. The second WFM layer 250 comprises aluminum and may be referred to as an aluminum-containing layer. In some embodiments, the second WFM layer 250 may comprise aluminum titanium (TiAl), aluminum titanium carbide (TiAlC), aluminum tantalum (TaAl), aluminum tantalum carbide (TaAlC), aluminum titanium nitride (TiAlN), or combinations thereof. In one embodiment, the second WFM layer 250 comprises aluminum titanium carbide (TiAlC). The second WFM layer 250 may be deposited using ALD at a temperature between about 350°C and about 380°C. Figure 16 As shown, due to the presence of a diffusion barrier layer 246 above the second region 2000, a second WFM layer 250 is deposited above the diffusion barrier layer 246, and no portion of the second WFM layer 250 extends vertically between two adjacent nanostructures 2080, or between the top surface of the second base fin 212nm and the bottom surface of the bottommost nanostructure 2080. Above the first region 1000, the second WFM layer 250 encloses each of the nanostructures 2080. That is, the second WFM layer 250 extends between the intervals between two adjacent first nanostructures 2080 in the first region 1000 and between the top surface of the first base fin 212nm and the bottom surface of the bottommost nanostructure above the first region 1000. In some instances, the thickness of the second WFM layer 250 can be between about 10 Å and about 33 Å. When the second WFM layer 250 is formed from a three-component material such as titanium aluminum carbide (TiAlC), it has a grain size between 2.4 nm and about 2.8 nm. It should be noted that the grain size of the second WFM layer 250 is smaller than the grain size of the first WFM layer 244 or the grain size of the second WFM layer 246.

[0046] refer to Figure 1 and Figure 17Method 100 includes block 116, in which a protective layer 252 is deposited over a second WFM layer 250. In block 116, the protective layer 252 is deposited over the second WFM layer 250 and serves to prevent the second WFM layer 250 from being oxidized. The protective layer 252 may comprise a titanium-based material. In some embodiments, the protective layer 252 may comprise titanium nitride (TiN) and is formed in situ after the deposition of the second WFM layer 250. This prevents oxygen in ambient air from contacting the second WFM layer 250 when the vacuum is broken. In some embodiments, the protective layer 252 may be formed by ALD (Alternating Current Deposition). Figure 17 As shown, because the spaces between the first nanostructures 2080 are filled with the second WFM layer 250, and the spaces between the second nanostructures 2080 are filled with the diffusion barrier layer 246, the protective layer 252 does not extend between two adjacent first nanostructures 2080 or two adjacent second nanostructures 2080. In some instances, the protective layer 252 comprises a thickness between about 8 Å and about 20 Å.

[0047] refer to Figure 1 and Figure 18 Method 100 includes block 118, in which a semiconductor capping layer 254 is deposited over a protective layer 252. The semiconductor capping layer 254 may include silicon (Si) and serves to prevent the protective layer 252 from being oxidized during subsequent manufacturing processes. In some embodiments, the semiconductor capping layer 254 may be deposited using an ALD and a silicon-containing precursor, such as silane (SiH4) or disilane (Si2H6) . In one embodiment, disilane is used as a precursor for the semiconductor capping layer 254. In some instances, the semiconductor capping layer 254 may have a thickness between about 5 Å and about 15 Å. In some embodiments, after depositing the semiconductor capping layer 254, the precursor structure or wafer having the structure formed in blocks 102-118 is removed from the vacuum chamber. Exposure to ambient air can form a thin silicon oxide layer on the surface of the semiconductor capping layer 254. This thin silicon oxide layer may not be removed before depositing further layers.

[0048] refer to Figure 1 and Figure 19 Method 100 includes block 120, in which a metal filler layer 260 is deposited over a semiconductor capping layer 254. Although not explicitly shown in the figure, an adhesive layer may be deposited over the semiconductor capping layer 254 to improve adhesion of the metal filler layer 260. The adhesive layer may include titanium nitride. In some embodiments, the metal filler layer 260 may include tungsten (W) and may be deposited using ALD or CVD. Reference Figure 19The deposition of the semiconductor capping layer 254, the adhesive layer, and the metal filling layer 260 allows the semiconductor capping layer 254 to react with the protective layer 252 at the interface of the two layers to form a compound protective layer 256, which may include silicon titanium nitride (SiTiN).

[0049] Figure 20 It shows along Figure 19 A partial cross-sectional view of section AA. Line A-A' longitudinally cuts through the first nanostructure 2080 in the first region 1000. (See diagram below.) Figure 20 As shown, each of the first nanostructures 2080 extends along the X direction between two first source / drain components 232N. An interface layer 240, a gate dielectric layer 242, and a second WFM layer 250 enclose each of the first nanostructures 2080 in the first region 1000. A protective layer 252, a semiconductor capping layer 254, and a metal filler layer 260 are disposed above the first nanostructures 2080 but do not extend between two adjacent first nanostructures 2080. The interface layer 240, gate dielectric layer 242, second WFM layer 250, protective layer 252, semiconductor capping layer 254, and metal filler layer 260 can be considered as an n-type gate structure.

[0050] Figure 21 It shows along Figure 19 A partial cross-sectional view of section BB. Line B-B' longitudinally cuts through the second nanostructure 2080 in the second region 2000. (See diagram below.) Figure 21 As shown, each of the second nanostructures 2080 extends along the X-direction between two second source / drain components 232P. An interface layer 240, a gate dielectric layer 242, a first WFM layer 244, and a diffusion barrier layer 246 enclose each of the second nanostructures 2080 in the second region 2000. A second WFM layer 250, a protective layer 252, a semiconductor capping layer 254, and a metal filler layer 260 are disposed above the second nanostructures 2080 but do not extend between two adjacent second nanostructures 2080. The interface layer 240, gate dielectric layer 242, first WFM layer 244, diffusion barrier layer 246, second WFM layer 250, protective layer 252, semiconductor capping layer 254, and metal filler layer 260 can be considered as a p-type gate structure. Because the n-type gate structure and the p-type gate structure share all these layers except for the diffusion barrier layer 246 and the first WFM layer 244, they can be collectively referred to as a gate structure or a shared gate structure.

[0051] Figure 22 A semiconductor structure 200 formed using method 100 is shown. Figure 22 The semiconductor structure 200 is basically similar to Figure 19In the semiconductor structure, the second WFM layer 250 above the first region 1000 includes a first seam 262, and the diffusion barrier layer 246 above the second region 2000 includes a second seam 264. The first seam 262 and the second seam 264 are formed when the layers filling the gaps between two adjacent first nanostructures 2080 or two adjacent second nanostructures 2080 prematurely merge before filling the gaps. In fact, the diffusion barrier layer 246 filling the gaps between the first nanostructures 2080 may prematurely merge, thus forming the first seam 262 in the diffusion barrier layer 246. The second WFM layer 250 filling the gaps between the second nanostructures 2080 may prematurely merge, thus forming the second seam 264 in the diffusion barrier layer 246. As described above, the grain size of the second WFM layer 250 is smaller than the grain size of the diffusion barrier layer 246. It has been observed that the smaller grain size allows the second WFM layer 250 to have better hole-filling characteristics, which results in a smaller seam length along the Y direction. On average, the first average length L1 of the first seam 262 along the Y direction is less than the second average length L2 of the second seam 264 along the Y direction. It should also be noted that the seams closer to the first base fin 212PB and the second base fin 212NB tend to have a longer length along the Y direction.

[0052] This disclosure provides embodiments of a process for forming a gate structure of a multi-gate device. In one embodiment, a method is provided. The method includes: receiving a precursor structure, the precursor structure including: a substrate; a first plurality of nanostructures located over a first region of the substrate; a second plurality of nanostructures located over a second region of the substrate; and an isolation member located over the substrate; depositing a gate dielectric layer over a surface of each of the first plurality of nanostructures and each of the second plurality of nanostructures; depositing a first work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; depositing a diffusion barrier layer over the first work function metal layer such that the diffusion barrier layer encloses each of the first plurality of nanostructures over the first region and each of the second plurality of nanostructures over the second region; selectively removing the diffusion barrier layer and the first work function metal layer from the first plurality of nanostructures over the first region; after selective removal, depositing a second work function metal layer over the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region; and depositing a metal fill layer over the second work function metal layer. A portion of the gate dielectric layer extends along the top surface of the isolation member.

[0053] In some embodiments, the diffusion barrier layer comprises TiWN. In some embodiments, the first work function metal layer comprises a p-type work function metal layer. In some embodiments, the second work function metal layer comprises an n-type work function metal layer. In some embodiments, the second work function metal layer comprises aluminum. In some instances, the first work function metal layer comprises titanium nitride. In some embodiments, the total thickness of the first work function metal layer and the diffusion barrier layer is between about 10 Å and about 33 Å. In some embodiments, the deposition of the diffusion barrier layer comprises an atomic layer deposition (ALD) process, and the ALD process comprises at least one tungsten nitride cycle and at least one titanium nitride cycle. In some instances, the tungsten content in the diffusion barrier layer is between about 10% and about 70%.

[0054] In another embodiment, a method is provided. The method includes: receiving a precursor structure, the precursor structure including: a substrate; a first base fin and a second base fin, located above the substrate; an isolation structure, located above the substrate and disposed between the first base fin and the second base fin; a first nanostructure, located above the first base fin; and a second nanostructure, located above the second base fin; depositing a gate dielectric layer over the first base fin, the first nanostructure, the second base fin, the second nanostructure, and the isolation structure; depositing a p-type work function metal layer over the first nanostructure and the second nanostructure; depositing a diffusion barrier layer over the p-type work function metal layer such that the diffusion barrier layer encloses each of the first nanostructure and each of the second nanostructure; selectively removing the diffusion barrier layer and the p-type work function metal layer from the first nanostructure; after selective removal, depositing an n-type work function metal layer over the first nanostructure and the second nanostructure; depositing a protective layer over the n-type work function metal layer; and depositing a metal fill layer over the protective layer. The protective layer comprises a titanium-based material. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

[0055] In some embodiments, the p-type work function metal layer comprises titanium nitride, and the n-type work function metal layer comprises titanium aluminum nitride. In some embodiments, the protective layer comprises a thickness between about 8 Å and about 20 Å. In some embodiments, the tungsten content in the diffusion barrier layer is between about 10% and about 70%. In some instances, the thickness of the n-type work function metal layer comprises a thickness between about 10 Å and about 33 Å. In some embodiments, selective removal comprises removing the p-type work function metal layer between two adjacent first nanostructures. In some embodiments, the deposition of the diffusion barrier layer comprises an atomic layer deposition (ALD) process, and the ALD process comprises at least one tungsten nitride cycle and at least one titanium nitride cycle.

[0056] In a further embodiment, a semiconductor structure is provided. The semiconductor structure includes: a first base fin and a second base fin, located above a substrate; an isolation member, located above the substrate and in contact with the sidewalls of the first base fin and the second base fin; a first plurality of nanostructures disposed above the first base fin; a second plurality of nanostructures disposed above the second base fin; a gate dielectric layer encapsulating each of the first plurality of nanostructures and each of the second plurality of nanostructures, the gate dielectric layer being disposed above the top surface of the first base fin, the second base fin, and the isolation member; a first work function layer encapsulating each of the second plurality of nanostructures and disposed above the second base fin; a diffusion barrier layer encapsulating each of the second plurality of nanostructures; a second work function layer encapsulating each of the first plurality of nanostructures above the first base fin and disposed above the diffusion barrier layer above the second base fin; and a protective layer located above the second work function layer above the first base fin and the second base fin. The diffusion barrier layer comprises titanium tungsten nitride.

[0057] In some embodiments, the protective layer comprises titanium silicon nitride. In some embodiments, the total thickness of the first work function layer and the diffusion barrier layer is between about 10 Å and about 33 Å. In some embodiments, the diffusion barrier layer between the second plurality of nanostructures includes a seam.

[0058] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a precursor structure including: a substrate; a first plurality of nanostructures located above a first region of the substrate; a second plurality of nanostructures located above a second region of the substrate; and an isolation member located above the substrate; depositing a gate dielectric layer above the surfaces of the first plurality of nanostructures and the second plurality of nanostructures; depositing a first work function metal layer above the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; depositing a diffusion barrier layer above the first work function metal layer such that the diffusion barrier layer encloses the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; selectively removing the diffusion barrier layer and the first work function metal layer from the first plurality of nanostructures above the first region; after the selective removal, depositing a second work function metal layer above the first plurality of nanostructures above the first region and the second plurality of nanostructures above the second region; and depositing a metal fill layer above the second work function metal layer, wherein a portion of the gate dielectric layer extends along the top surface of the isolation member.

[0059] In some embodiments, the diffusion barrier layer comprises TiWN. In some embodiments, the first work function metal layer comprises a p-type work function metal layer. In some embodiments, the second work function metal layer comprises an n-type work function metal layer. In some embodiments, the second work function metal layer comprises aluminum. In some embodiments, the first work function metal layer comprises titanium nitride. In some embodiments, the total thickness of the first work function metal layer and the diffusion barrier layer is between about 10 Å and about 33 Å. In some embodiments, the deposition of the diffusion barrier layer comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises at least one tungsten nitride cycle and at least one titanium nitride cycle. In some embodiments, the tungsten content in the diffusion barrier layer is between about 10% and about 70%.

[0060] Other embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a precursor structure including: a substrate; a first base fin and a second base fin located above the substrate; an isolation structure located above the substrate and disposed between the first base fin and the second base fin; a first nanostructure located above the first base fin; and a second nanostructure located above the second base fin; depositing a gate dielectric layer over the first base fin, the first nanostructure, the second base fin, the second nanostructure, and the isolation structure; depositing a p-type work function metal layer over the first nanostructure and the second nanostructure; depositing a diffusion barrier layer over the p-type work function metal layer such that the diffusion barrier layer encapsulates the first nanostructure and the second nanostructure; selectively removing the diffusion barrier layer and the p-type work function metal layer from the first nanostructure; after the selective removal, depositing an n-type work function metal layer over the first nanostructure and the second nanostructure; depositing a protective layer over the n-type work function metal layer; and depositing a metal fill layer over the protective layer, wherein the protective layer comprises a titanium-based material, and wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

[0061] In some embodiments, the p-type work function metal layer comprises titanium nitride, wherein the n-type work function metal layer comprises titanium aluminum nitride. In some embodiments, the protective layer comprises a thickness of about 8 Å and about 20 Å. In some embodiments, the tungsten content in the diffusion barrier layer is between about 10% and about 70%. In some embodiments, the thickness of the n-type work function metal layer comprises a thickness between about 10 Å and about 33 Å. In some embodiments, the selective removal comprises removing the p-type work function metal layer between two adjacent first nanostructures. In some embodiments, the deposition of the diffusion barrier layer comprises an atomic layer deposition process, wherein the atomic layer deposition process comprises at least one tungsten nitride cycle and at least one titanium nitride cycle.

[0062] Some embodiments of this application provide a semiconductor structure including: a first base fin and a second base fin, located above a substrate; an isolation member, located above the substrate and in contact with the sidewalls of the first base fin and the second base fin; a first plurality of nanostructures disposed above the first base fin; a second plurality of nanostructures disposed above the second base fin; a gate dielectric layer encapsulating the first plurality of nanostructures and the second plurality of nanostructures, the gate dielectric layer being disposed above the top surface of the first base fin, the second base fin and the isolation member; a first work function layer encapsulating the second plurality of nanostructures and being disposed above the second base fin; a diffusion barrier layer encapsulating the second plurality of nanostructures; a second work function layer encapsulating the first plurality of nanostructures above the first base fin and being disposed above the diffusion barrier layer above the second base fin; and a protective layer located above the second work function layer above the first base fin and the second base fin, wherein the diffusion barrier layer comprises titanium tungsten nitride.

[0063] In some embodiments, the protective layer comprises titanium silicon nitride. In some embodiments, the total thickness of the first work function layer and the diffusion barrier layer is between about 10 Å and about 33 Å. In some embodiments, the diffusion barrier layer between the second plurality of nanostructures includes a seam.

[0064] The features of several embodiments have been summarized above to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a base to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the embodiments of this disclosure. For example, by implementing different thicknesses for bit line conductors and word line conductors, different resistances for the conductors can be achieved. However, other techniques can also be used to change the resistance of metallic conductors.

Claims

1. A method for forming a semiconductor structure, comprising: A receiving precursor structure includes: a substrate; a first plurality of nanostructures located above a first region of the substrate; a second plurality of nanostructures located above a second region of the substrate; and an isolation component located above the substrate. A gate dielectric layer is deposited above the surfaces of the first plurality of nanostructures and the second plurality of nanostructures; A first work function metal layer is deposited over the first plurality of nanostructures above the first region and over the second plurality of nanostructures above the second region; A diffusion barrier layer is deposited over the first work function metal layer, such that the diffusion barrier layer encapsulates the first plurality of nanostructures over the first region and the second plurality of nanostructures over the second region. The diffusion barrier layer and the first work function metal layer are selectively removed from the first plurality of nanostructures above the first region; Following the selective removal, a second work-function metal layer is deposited over the first plurality of nanostructures above the first region and over the second plurality of nanostructures above the second region; and A metal filler layer is deposited above the second work function metal layer. A portion of the gate dielectric layer extends along the top surface of the isolation component.

2. The method of claim 1, wherein, The diffusion barrier layer comprises TiWN.

3. The method of claim 1, wherein, The first work function metal layer includes a p-type work function metal layer.

4. The method of claim 1, wherein, The second work function metal layer includes an n-type work function metal layer.

5. The method of claim 1, wherein, The second work function metal layer comprises aluminum.

6. The method according to claim 1, wherein, The first work function metal layer includes titanium nitride.

7. The method according to claim 1, wherein, The total thickness of the first functional metal layer and the diffusion barrier layer is between about 10 Å and about 33 Å.

8. The method according to claim 1, in, The deposition of the diffusion barrier layer includes an atomic layer deposition process. The atomic layer deposition process includes at least one tungsten nitride cycle and at least one titanium nitride cycle.

9. A method for forming a semiconductor structure, comprising: A receiver precursor structure includes: a substrate; a first base fin and a second base fin located above the substrate; an isolation structure located above the substrate and disposed between the first base fin and the second base fin; a first nanostructure located above the first base fin; and a second nanostructure located above the second base fin. A gate dielectric layer is deposited over the first base fin, the first nanostructure, the second base fin, the second nanostructure, and the isolation structure; A p-type work function metal layer is deposited on the first nanostructure and the second nanostructure; A diffusion barrier layer is deposited above the p-type work function metal layer, thereby encapsulating the first nanostructure and the second nanostructure. Selectively remove the diffusion barrier layer and the p-type work function metal layer from the first nanostructure; After the selective removal, an n-type work function metal layer is deposited over the first nanostructure and the second nanostructure; A protective layer is deposited above the n-type work function metal layer; and A metal filler layer is deposited above the protective layer. The protective layer comprises a titanium-based material. The dielectric constant of the gate dielectric layer is greater than the dielectric constant of the isolation structure.

10. A semiconductor structure, comprising: The first and second base fins are located above the substrate; An isolation component is located above the substrate and is in contact with the sidewalls of the first base fin and the second base fin; A plurality of nanostructures are disposed above the first base fin; The second plurality of nanostructures are disposed above the second base fin; A gate dielectric layer encapsulates the first plurality of nanostructures and the second plurality of nanostructures, and the gate dielectric layer is disposed above the top surface of the first base fin, the second base fin and the isolation component; The first work function layer encapsulates the second plurality of nanostructures and is disposed above the second base fin; A diffusion barrier layer encapsulates the second or more nanostructures; The second function layer encapsulates the first plurality of nanostructures above the first base fin and is disposed above the diffusion barrier layer above the second base fin; as well as A protective layer is located above the second function layer above the first and second base fins. The diffusion barrier layer comprises titanium tungsten nitride.

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