A power supply circuit and a semiconductor process apparatus

Abstract

The application discloses a power supply circuit and a semiconductor process equipment, a self-excitation oscillation circuit is used for generating a first voltage, each group of voltage doubling rectification circuits comprises two voltage doubling rectification sub-circuits, the output ends of the two voltage doubling rectification sub-circuits are connected with one of two power supply output ends respectively, the polarities of the voltages output by the two voltage doubling rectification sub-circuits connected with the same power supply output end are opposite, each selection circuit is connected with a group of voltage doubling rectification circuits, the selection circuit is used for transmitting the first voltage to the corresponding group of voltage doubling rectification circuits when being selected, and a switching control circuit is used for outputting selection signals to the two groups of selection circuits respectively, so that only one group of selection circuits is selected at the same time. Because the voltage received by the selection circuit is the first voltage which is lower, the selection circuit does not need to adopt a high-voltage relay which is high in pressure, and can adopt a MOS tube which is low in pressure, small in size and low in cost, so that the size and cost of the power supply circuit can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor processing technology, specifically to a power supply circuit and semiconductor process equipment. Background Technology

[0002] Current electrostatic chuck power circuits are generally bipolar, consisting of two output terminals that output positive and negative high voltages of opposite polarities. While relays can switch the polarity of the output voltages (positive high voltage at the first output terminal and negative high voltage at the second, or vice versa), the high voltage received by the relay necessitates the use of high-voltage relays. The high voltage withstand capability of these relays is closely related to their size and cost; a higher withstand capability results in a larger and more expensive power circuit for the electrostatic chuck. Summary of the Invention

[0003] This invention discloses a power supply circuit and semiconductor process equipment to reduce the size and cost of the power supply circuit for an electrostatic chuck.

[0004] In a first aspect, the present invention discloses a power supply circuit, comprising a self-excited oscillation circuit, two sets of voltage doubler rectifier circuits, two sets of selection circuits, a switching control circuit, and two power output terminals; the self-excited oscillation circuit is used to generate a first voltage through self-excited oscillation; one of the two output terminals of the self-excited oscillation circuit is grounded, and the other output terminal outputs the first voltage; each set of voltage doubler rectifier circuits includes two voltage doubler rectifier sub-circuits, and the output terminals of the two voltage doubler rectifier sub-circuits are respectively connected to one of the two power output terminals; in each set of voltage doubler rectifier circuits, one voltage doubler rectifier sub-circuit is used to convert the first voltage into a second voltage, and the other voltage doubler rectifier circuit is used to convert the first voltage into a second voltage. The first voltage is converted into a third voltage; the two power supply output terminals are respectively used to output the second voltage and the third voltage; the second voltage and the third voltage have opposite polarities, and the difference between the second voltage and the third voltage is greater than the first voltage; the voltages output by the two voltage doubler rectifier circuits connected to the same power supply output terminal have opposite polarities; each set of selection circuits is connected to a set of voltage doubler rectifier circuits; the selection circuit is used to transmit the first voltage to the corresponding set of voltage doubler rectifier circuits when selected; the switching control circuit is used to output selection signals to the two sets of selection circuits respectively, so that only one set of selection circuits is selected at the same time.

[0005] In some embodiments of the present invention, each set of selection circuits includes two selection sub-circuits, and the two selection sub-circuits are respectively connected to the input terminals of two voltage doubler rectifier sub-circuits corresponding to the set of voltage doubler rectifier circuits.

[0006] In some embodiments of the present invention, the selection circuit or the selection sub-circuit includes a first switch and a second switch; the control terminal of the first switch is used to receive a corresponding selection signal; the first terminal of the first switch is used to receive a first reference voltage; the second terminal of the first switch is connected to the control terminal of the second switch; the selection signal is used to control the first switch to be in an on state or an off state; the first switch is used to transmit the first reference voltage to the control terminal of the second switch when it is in an on state; the first reference voltage is used to control the second switch to be in an on state; the first terminal of the second switch is used to receive the first voltage, and the second terminal of the second switch is connected to the input terminal of a corresponding set of voltage doubler rectifier circuits or a voltage doubler rectifier sub-circuit; the second switch is used to transmit the first voltage to a corresponding set of voltage doubler rectifier circuits or a voltage doubler rectifier sub-circuit when it is in an on state.

[0007] In some embodiments of the present invention, the selection circuit or the selection sub-circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor; a first terminal of the first resistor is used to receive a corresponding selection signal, and a second terminal of the first resistor is connected to the control terminal of the first switch; a first terminal of the second resistor is connected to the control terminal of the first switch, and a second terminal of the second resistor is connected to the first terminal of the first switch; a first terminal of the third resistor is connected to the second terminal of the first switch, and a second terminal of the third resistor is connected to the control terminal of the second switch; a first terminal of the fourth resistor is connected to the first terminal of the second switch, and a second terminal of the fourth resistor is connected to the control terminal of the second switch.

[0008] In some embodiments of the present invention, one of the first switching transistors and the second switching transistor is a PMOS transistor and the other is an NMOS transistor.

[0009] In some embodiments of the present invention, one of the two voltage doubler rectifier circuits connected to the same power output terminal includes a first capacitor, a second capacitor, a third capacitor, a first diode, a second diode, and a third diode; the first terminal of the first capacitor is grounded, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the corresponding power output terminal; the cathode of the first diode is connected to the output terminal of the corresponding selection circuit or selection sub-circuit, and the anode of the first diode is connected to the second terminal of the first capacitor; the first terminal of the third capacitor is connected to the cathode of the first diode, the second terminal of the third capacitor is connected to the anode of the second diode, the cathode of the second diode is connected to the anode of the first diode; the cathode of the third diode is connected to the anode of the second diode, and the anode of the third diode is connected to the second terminal of the second capacitor.

[0010] In some embodiments of the present invention, one of the two voltage doubler rectifier circuits connected to the same power output terminal includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a fourth diode, a fifth diode, and a sixth diode; the first terminal of the fourth capacitor is grounded, the second terminal of the fourth capacitor is connected to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is connected to the corresponding power output terminal; the cathode of the fourth diode is connected to the second terminal of the fourth capacitor, and the anode of the fourth diode is connected to the output terminal of the corresponding selection circuit or selection sub-circuit; the first terminal of the sixth capacitor is connected to the anode of the fourth diode, the second terminal of the sixth capacitor is connected to the cathode of the fifth diode, and the anode of the fifth diode is connected to the cathode of the fourth diode; the anode of the sixth diode is connected to the cathode of the fifth diode, and the cathode of the sixth diode is connected to the second terminal of the fifth capacitor.

[0011] In some embodiments of the present invention, the interlocking circuit includes an AND gate, a NOT gate, a latch, and a combination gate circuit; the first input terminal of the AND gate is used to receive an enable control signal, the second input terminal of the AND gate is used to receive an interlocking control signal, and the output terminal of the AND gate is connected to the input terminal of the NOT gate; the output terminal of the NOT gate is connected to the first input terminal of the latch, the second input terminal of the latch is used to receive a polarity control signal, the output terminal of the latch is connected to the input terminal of the combination gate circuit, and the first and second output terminals of the combination gate circuit are used to output two selection signals, which are respectively used to select the two sets of selection circuits.

[0012] In some embodiments of the present invention, the self-excited oscillation circuit includes a seventh capacitor, an eighth capacitor, a transistor, a fifth resistor, a sixth resistor, and a transformer. The transformer includes a primary winding, a feedback winding, and a secondary winding. The primary winding and the feedback winding are arranged on the same side, while the secondary winding is arranged on a different side from the primary winding and the feedback winding. The first terminal of the seventh capacitor is used to receive a second reference voltage, and the second terminal of the seventh capacitor is grounded. The first terminal of the primary winding is connected to the first terminal of the seventh capacitor, and the second terminal of the primary winding is connected to the first terminal of the transistor, which is grounded. The control terminal of the transistor is connected to the first terminal of the fifth resistor, and the second terminal of the fifth resistor is connected to the first terminal of the primary winding. The first terminal of the eighth capacitor is connected to the first terminal of the fifth resistor, and the second terminal of the eighth capacitor is connected to the first terminal of the sixth resistor. The second terminal of the sixth resistor is connected to the first terminal of the feedback winding, which is grounded. The first terminal of the secondary winding is used to output the first voltage, and the second terminal of the secondary winding is grounded.

[0013] In a second aspect, the present invention discloses a semiconductor process apparatus, including an electrostatic chuck and a power supply circuit as described in any of the preceding claims, wherein the electrostatic chuck includes two electrodes, the two electrodes being respectively connected to two power output terminals of the power supply circuit.

[0014] The power supply circuit and semiconductor process equipment disclosed in this invention include a self-excited oscillation circuit, two sets of voltage doubler rectifier circuits, two sets of selection circuits, a switching control circuit, and two power output terminals. The self-excited oscillation circuit generates a first voltage through self-excited oscillation. Each set of voltage doubler rectifier circuits includes two voltage doubler rectifier sub-circuits, and the output terminals of the two voltage doubler rectifier sub-circuits are respectively connected to one of the two power output terminals. In each set of voltage doubler rectifier circuits, one voltage doubler rectifier sub-circuit is used to convert the first voltage to a second voltage, and the other voltage doubler rectifier circuit is used to convert the first voltage to a third voltage. The difference between the second voltage and the third voltage is greater than the first voltage. Each set of selection circuits is connected to a set of voltage doubler rectifier circuits. The selection circuit is used to transmit the first voltage to the corresponding set of voltage doubler rectifier circuits when selected. Because the voltage received by the selection circuit is the lower first voltage, the selection circuit does not need to use a high-voltage resistant switch such as a high-voltage relay. Instead, it can use a low-voltage resistant, small-sized, and low-cost switch such as a MOSFET, thereby reducing the size and cost of the power supply circuit of the electrostatic chuck.

[0015] Furthermore, the switching control circuit is used to output selection signals to the two sets of selection circuits respectively, so that only one set of selection circuits is selected at a time. This avoids the problem of short circuit in the power supply circuit of the electrostatic chuck and damage to the electrostatic chuck caused by the simultaneous transmission of the second and third voltages with opposite polarities to the same power output terminal and the same electrostatic chuck electrode. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the background art, the accompanying drawings used in the embodiments of the present invention or the background art will be described below.

[0017] Figure 1 This is a schematic diagram of the structure of a semiconductor process equipment disclosed in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the power supply circuit of an electrostatic chuck connected to a high-voltage relay, as disclosed in an embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of a power supply circuit disclosed in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0023] Figure 7 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of another power supply circuit disclosed in an embodiment of the present invention.

[0026] Figure 10 This is a schematic diagram of a switching control circuit disclosed in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] like Figure 1 As shown, a conventional semiconductor process apparatus includes a process chamber 9 and an electrostatic chuck disposed within the process chamber 9. The electrostatic chuck includes a chuck base 5 and a ceramic layer 4, with a first electrode 7 and a second electrode 8 embedded within the ceramic layer 4. The power supply circuit 11 of the electrostatic chuck has a first power output terminal HV+ and a second power output terminal HV-. The positive high voltage output from the first power output terminal HV+ and the negative high voltage output from the second power output terminal HV- are filtered by the filter circuit 10 and then transmitted to the first electrode 7 and the second electrode 8, respectively.

[0029] like Figure 2 As shown, the first power output terminal HV+ of the power supply circuit 11 is connected to the input terminals of the first relay T1 and the second relay T2. The second power output terminal HV- of the power supply circuit 11 is connected to the input terminals of the third relay T3 and the fourth relay T4. The output terminals of the first relay T1 and the third relay T3 are connected to the third power output terminal HV1+. The third power output terminal HV1+ is used to connect to the first electrode 7. The output terminals of the second relay T2 and the fourth relay T4 are connected to the fourth power output terminal HV1-. The fourth power output terminal HV1- is used to connect to the second electrode 8.

[0030] Based on this, by controlling the first relay T1 and the fourth relay T4 to be on, and the second relay T2 and the third relay T3 to be off, a positive high voltage can be transmitted to the first electrode 7 and a negative high voltage to the second electrode 8, causing the electrostatic chuck to generate an electrostatic attraction to adhere and fix the wafer 3. Alternatively, by controlling the second relay T2 and the third relay T3 to be on, and the first relay T1 and the fourth relay T4 to be off, a negative high voltage can be transmitted to the first electrode 7 and a positive high voltage to the second electrode 8, causing the electrostatic chuck to generate an opposite electrostatic attraction to neutralize the charge, thereby separating or de-adsorbing the wafer 3 from the electrostatic chuck.

[0031] However, since the voltage received by the first relay T1 to the fourth relay T4 is high voltage, the first relay T1 to the fourth relay T4 must be high voltage relays with high voltage resistance. The high voltage resistance value of the high voltage relay is closely related to its size and cost. That is, the higher the high voltage resistance value of the high voltage relay, the larger its size and the higher its cost. Therefore, the power supply circuit 11 of the electrostatic chuck will be larger and more expensive.

[0032] Based on this, the present invention discloses a power supply circuit. By placing the selection circuit between the self-excited oscillation circuit and the voltage doubler rectifier circuit, the voltage received by the selection circuit is a lower voltage. This avoids the need for the selection circuit to use a high-voltage switch such as a high-voltage relay, thereby reducing the size and cost of the power supply circuit of the electrostatic chuck.

[0033] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a power supply circuit, such as... Figure 3 As shown, the power supply circuit 11 includes a self-excited oscillation circuit 30, two sets of selection circuits, two sets of voltage doubler rectifier circuits, a switching control circuit 33, and two power output terminals. These two power output terminals may include a first power output terminal HV+ and a second power output terminal HV-.

[0034] The self-excited oscillation circuit 30 is used to generate a first voltage through self-excited oscillation. Specifically, one of the two output terminals of the self-excited oscillation circuit 30 is grounded, and the other output terminal outputs the first voltage.

[0035] Each voltage doubler rectifier circuit includes two voltage doubler rectifier sub-circuits, and the output terminals of the two voltage doubler rectifier sub-circuits are respectively connected to one of the two power supply output terminals. For example... Figure 3 As shown, the first group of voltage doubler rectifier circuits includes a first voltage doubler rectifier circuit 321 and a second voltage doubler rectifier circuit 322. The output terminal of the first voltage doubler rectifier circuit 321 is connected to the first power output terminal HV+, and the output terminal of the second voltage doubler rectifier circuit 322 is connected to the second power output terminal HV-. The second group of voltage doubler rectifier circuits includes a third voltage doubler rectifier circuit 323 and a fourth voltage doubler rectifier circuit 324. The output terminal of the fourth voltage doubler rectifier circuit 324 is connected to the first power output terminal HV+, and the output terminal of the third voltage doubler rectifier circuit 323 is connected to the second power output terminal HV-.

[0036] In each voltage doubler rectifier circuit, one voltage doubler rectifier circuit converts the first voltage to the second voltage, and the other voltage doubler rectifier circuit converts the first voltage to the third voltage. Two power supply output terminals are used to output the second and third voltages, respectively. For example... Figure 3As shown, the first voltage doubler rectifier circuit 321 converts the first voltage to the second voltage, and the second voltage doubler rectifier circuit 322 converts the first voltage to the third voltage. The first power output terminal HV+ outputs the second voltage, and the second power output terminal HV- outputs the third voltage. The third voltage doubler rectifier circuit 323 converts the first voltage to the second voltage, and the fourth voltage doubler rectifier circuit 324 converts the first voltage to the third voltage. The first power output terminal HV+ outputs the third voltage, and the second power output terminal HV- outputs the second voltage.

[0037] In this system, the second and third voltages have opposite polarities, can have the same amplitude, and the difference between the second and third voltages is greater than that of the first voltage. Specifically, one of the second and third voltages is positive and the other is negative, and the difference between the positive and negative voltages is greater than the absolute value of the first voltage. Furthermore, the voltages output by the two voltage doubler rectifier circuits connected to the same power supply output terminal have opposite polarities. For example... Figure 3 As shown, the voltages output by the first voltage doubler rectifier circuit 321 and the fourth voltage doubler rectifier circuit 324, which are connected to the first power output terminal HV+, have opposite polarities. Similarly, the voltages output by the second voltage doubler rectifier circuit 322 and the fourth voltage doubler rectifier circuit 324, which are connected to the second power output terminal HV-, have opposite polarities.

[0038] Each selection circuit corresponds to a set of voltage doubler rectifier circuits. The selection circuit is used to transmit the first voltage to the corresponding set of voltage doubler rectifier circuits when selected. For example... Figure 3 As shown, these two sets of selection circuits may include a first set of selection circuits 311 and a second set of selection circuits 312. The first set of selection circuits 311 is connected to a first set of voltage doubler rectifier circuits, and is used to transmit a first voltage to the first set of voltage doubler rectifier circuits when selected. The second set of selection circuits 312 is connected to a second set of voltage doubler rectifier circuits, and is used to transmit the first voltage to the second set of voltage doubler rectifier circuits when selected.

[0039] The switching control circuit 33 is used to output selection signals to the two sets of selection circuits respectively, so that only one set of selection circuits is selected at a time. For example... Figure 3As shown, the switching control circuit 33 outputs a first selection signal PE to the first selection circuit 311 and a second selection signal PD to the second selection circuit 312. The first selection signal PE and the second selection signal PD ensure that only one of the first selection circuit 311 and the second selection circuit 312 is selected at any given time. Specifically, when the first selection signal PE causes the first selection circuit 311 to be selected, the second selection signal PD causes the second selection circuit 312 to be unselected. Conversely, when the second selection signal PD causes the second selection circuit 312 to be selected, the first selection signal PE causes the first selection circuit 311 to be unselected.

[0040] Because the selection circuit receives a lower first voltage, it does not need to use a high-voltage resistant switch such as a high-voltage relay. Instead, it can use a low-voltage resistant, small-sized, and low-cost switch such as a MOSFET. This reduces the size and cost of the electrostatic chuck's power supply circuit and increases its integration. Furthermore, using MOSFETs and other switches can improve polarity switching speed, switching stability, and lifespan. In addition, because the switching control circuit 33 allows only one selection circuit to be selected at a time, it avoids the problem of short circuits and damage to the electrostatic chuck caused by the simultaneous transmission of second and third voltages of opposite polarities to the same power output terminal and the same electrostatic chuck electrode.

[0041] Of course, the present invention is not limited thereto. In some other embodiments, each set of selection circuits may include two selection sub-circuits, which may be connected to the input terminals of the two voltage doubler rectifier sub-circuits corresponding to a set of voltage doubler rectifier circuits, respectively. For example... Figure 4 As shown, the first selection circuit 311 includes a first selection sub-circuit 3111 and a second selection sub-circuit 3112, and the second selection circuit 312 includes a third selection sub-circuit 3121 and a fourth selection sub-circuit 3122.

[0042] The input terminals of these four selection sub-circuits are all used to receive the first voltage output by the self-excited oscillation circuit 30, and the output terminals of these four selection sub-circuits are respectively connected to the input terminals of four voltage doubler rectifier sub-circuits. For example, the input terminals of the first selection sub-circuit 3111 to the fourth selection sub-circuit 3122 are all used to receive the first voltage output by the self-excited oscillation circuit 30, and the output terminals of the first selection sub-circuit 3111 to the fourth selection sub-circuit 3122 are respectively connected to the input terminals of the first voltage doubler rectifier sub-circuit 321 to the fourth voltage doubler rectifier sub-circuit 324. Any selection sub-circuit, when selected, transmits the first voltage output by the self-excited oscillation circuit 30 to the corresponding voltage doubler rectifier sub-circuit. For example, the first selection sub-circuit 3111, when selected, transmits the first voltage output by the self-excited oscillation circuit 30 to the first voltage doubler rectifier sub-circuit 321.

[0043] Furthermore, when the first selection signal PE selects the first selection sub-circuit 3111 and the second selection sub-circuit 3112, the second selection signal PD deselects the third selection sub-circuit 3121 and the fourth selection sub-circuit 3122. Conversely, when the second selection signal PD selects the third selection sub-circuit 3121 and the fourth selection sub-circuit 3122, the first selection signal PE deselects the first selection sub-circuit 3111 and the second selection sub-circuit 3112.

[0044] In some embodiments of the present invention, such as Figure 5 As shown, each selection circuit includes a first switch K1 and a second switch K2. Specifically, the first selection circuit 311 and the second selection circuit 312 each include a first switch K1 and a second switch K2.

[0045] In this circuit, the control terminal of the first switch K1 receives a corresponding selection signal, such as a first selection signal PE or a second selection signal PD. The selection signal controls the first switch K1 to be in an on or off state. The first terminal of the first switch K1 receives a first reference voltage, such as a ground voltage. The second terminal of the first switch K1 is connected to the control terminal of the second switch K2. When the first switch K1 is in the on state, it transmits the first reference voltage to the control terminal of the second switch K2, which controls the second switch K2 to be in the on state.

[0046] The first terminal of the second switch K2 is used to receive the first voltage output by the self-excited oscillation circuit 30. The second terminal of the second switch K2 is connected to the input terminal of a corresponding voltage doubler rectifier circuit, such as the first or second voltage doubler rectifier circuit. When the second switch K2 is in the on state, it is used to transmit the first voltage to the corresponding voltage doubler rectifier circuit, such as the first or second voltage doubler rectifier circuit.

[0047] Of course, the present invention is not limited thereto; in other embodiments, such as Figure 6 As shown, each selection sub-circuit includes a first switch K1 and a second switch K2. Specifically, the first selection sub-circuit 3111 to the fourth selection sub-circuit 3122 all include a first switch K1 and a second switch K2. The connection relationship between the first switch K1 and the second switch K2 is basically the same as in the above embodiment, except that the second terminal of the second switch K2 is connected to the input terminal of the corresponding voltage doubler rectifier circuit, for example, to the first voltage doubler rectifier circuit 321, the second voltage doubler rectifier circuit 322, the third voltage doubler rectifier circuit 323, or the fourth voltage doubler rectifier circuit 324. The second switch K2 is used to transmit the first voltage to the corresponding voltage doubler rectifier circuit when it is in the on state, for example, to the first voltage doubler rectifier circuit 321, the second voltage doubler rectifier circuit 322, the third voltage doubler rectifier circuit 323, or the fourth voltage doubler rectifier circuit 324.

[0048] In some embodiments of the present invention, one of the first switching transistor K1 and the second switching transistor K2 is a PMOS transistor and the other is an NMOS transistor. For example... Figure 5 or Figure 6 As shown, taking an NMOS transistor as the first switch K1 and a PMOS transistor as the second switch K2 as an example, when the selection signal received by the first switch K1 is a high-level signal, the first switch K1 is turned on, transmitting the low-level signal at the ground terminal to the second switch K2, controlling the second switch K2 to be turned on, so that the second switch K2 transmits the first voltage output by the self-excited oscillation circuit 30 to the corresponding voltage doubler rectifier circuit. When the selection signal received by the first switch K1 is a low-level signal, the first switch K1 is turned off, the second switch K2 is turned off, and the first voltage output by the self-excited oscillation circuit 30 cannot be transmitted to the corresponding voltage doubler rectifier circuit.

[0049] In some embodiments of the present invention, any selection circuit or selection sub-circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor. For example... Figure 7 As shown, the explanation will only take the example of any selector circuit also including a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

[0050] In this circuit, the first terminal of the first resistor R1 is used to receive the corresponding selection signal, such as the first selection signal PE or the second selection signal PD. The second terminal of the first resistor R1 is connected to the control terminal of the first switch K1. The first terminal of the second resistor R2 is connected to the control terminal of the first switch K1, and the second terminal of the second resistor R2 is connected to the first terminal of the first switch K1. The first terminal of the third resistor R3 is connected to the second terminal of the first switch K1, and the second terminal of the third resistor R3 is connected to the control terminal of the second switch K2. The first terminal of the fourth resistor R4 is connected to the first terminal of the second switch K2, and the second terminal of the fourth resistor R4 is connected to the control terminal of the second switch K2.

[0051] Of course, the present invention is not limited to this. In other embodiments, each selection circuit or selection sub-circuit may include three, four, or even more switching transistors and resistors, etc., which will not be elaborated here. It is understood that setting a resistor at the control terminal of the switching transistor can increase the voltage at the control terminal of the switching transistor, which is more conducive to the rapid conduction of the switching transistor. Setting a resistor between the control terminal and the first terminal of the switching transistor can make the resistor parallel with the body resistance of the switching transistor, thereby reducing the body resistance of the switching transistor, which is more conducive to the rapid conduction of the switching transistor.

[0052] In some embodiments of the present invention, such as Figure 8 As shown, one of the two voltage doubler rectifier circuits connected to the same power output terminal, such as the first voltage doubler rectifier circuit 321 and the third voltage doubler rectifier circuit 323, includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode D1, a second diode D2, and a third diode D3.

[0053] In this circuit, the first terminal of the first capacitor C1 is grounded, and the second terminal of the first capacitor C1 is connected to the first terminal of the second capacitor C2. The second terminal of the second capacitor C2 is connected to the corresponding power output terminal, for example, the second terminal of the second capacitor C2 is connected to the first power output terminal HV+ or the second power output terminal HV-. The cathode of the first diode D1 is connected to the output terminal of the corresponding selection circuit or selection sub-circuit, for example, the cathode of the first diode D1 is connected to the output terminal of the first selection sub-circuit 3111 or the third selection sub-circuit 3121.

[0054] The anode of the first diode D1 is connected to the second terminal of the first capacitor C1. The first terminal of the third capacitor C3 is connected to the cathode of the first diode D1, and the second terminal of the third capacitor C3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the anode of the first diode D1. The cathode of the third diode D3 is connected to the anode of the second diode D2, and the anode of the third diode D3 is connected to the second terminal of the second capacitor C2.

[0055] Based on this, in some embodiments of the present invention, such as Figure 8 As shown, one of the two voltage doubler rectifier circuits connected to the same power output terminal, such as the second voltage doubler rectifier circuit 322 and the fourth voltage doubler rectifier circuit 324, includes a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a fourth diode D4, a fifth diode D5, and a sixth diode D6.

[0056] In this circuit, the first terminal of the fourth capacitor C4 is grounded, the second terminal of the fourth capacitor C4 is connected to the first terminal of the fifth capacitor C5, and the second terminal of the fifth capacitor C5 is connected to the corresponding power output terminal, for example, the second terminal of the fifth capacitor C5 is connected to the first power output terminal HV+ or the second power output terminal HV-. The cathode of the fourth diode D4 is connected to the second terminal of the fourth capacitor C4, and the anode of the fourth diode D4 is connected to the output terminal of the corresponding selection circuit or selector circuit, for example, the anode of the fourth diode D4 is connected to the output terminal of the second selector circuit 3112 or the fourth selector circuit 3122.

[0057] The first terminal of the sixth capacitor C6 is connected to the positive terminal of the fourth diode D4, and the second terminal of the sixth capacitor C6 is connected to the negative terminal of the fifth diode D5. The positive terminal of the fifth diode D5 is connected to the negative terminal of the fourth diode D4. The positive terminal of the sixth diode D6 is connected to the negative terminal of the fifth diode D5, and the negative terminal of the sixth diode D6 is connected to the second terminal of the fifth capacitor C5.

[0058] In some embodiments of the present invention, the second voltage output by the first voltage doubler rectifier circuit 321 and the third voltage doubler rectifier circuit 323 is a negative voltage, and the third voltage output by the second voltage doubler rectifier circuit 322 and the fourth voltage doubler rectifier circuit 324 is a positive voltage.

[0059] When the first selection signal PE is high and the second selection signal PD is low, the first selection sub-circuit 3111 and the second selection sub-circuit 3112 are turned on, while the third selection sub-circuit 3121 and the fourth selection sub-circuit 3122 are turned off. The first voltage doubler rectifier sub-circuit 321 outputs a second voltage to the first power supply output terminal HV+, and the fourth voltage doubler rectifier sub-circuit 324 outputs a positive third voltage to the second power supply output terminal HV-. When the first selection signal PE is low and the second selection signal PD is high, the first selection sub-circuit 3111 and the second selection sub-circuit 3112 are turned off, while the third selection sub-circuit 3121 and the fourth selection sub-circuit 3122 are turned on. The second voltage doubler rectifier sub-circuit 322 outputs a third voltage to the first power supply output terminal HV+, and the third voltage doubler rectifier sub-circuit 323 outputs a second voltage to the second power supply output terminal HV-.

[0060] In some embodiments, the second voltage is a positive voltage and the third voltage is a negative voltage; in other embodiments, the second voltage may also be a negative voltage and the third voltage may also be a positive voltage.

[0061] In some embodiments of the present invention, such as Figure 9 As shown, the self-excited oscillation circuit 30 includes a seventh capacitor C7, an eighth capacitor C8, a transistor Q, a fifth resistor R5, a sixth resistor R6, and a transformer T. The transformer T includes a primary winding TA, a feedback winding TB, and a secondary winding TC. The primary winding TA and the feedback winding TB are arranged on the same side, while the secondary winding TC is arranged on a different side from the primary winding TA and the feedback winding TB.

[0062] The first terminal of the seventh capacitor C7 is used to receive the second reference voltage Vin, and the second terminal of the seventh capacitor C7 is grounded. The first terminal of the primary winding TA is used to receive the second reference voltage Vin, and the second terminal of the primary winding TA is connected to the first terminal of the transistor Q. The second terminal of the transistor Q is grounded, and the control terminal of the transistor Q is connected to the first terminal of the fifth resistor R5. The second terminal of the fifth resistor R5 is connected to the first terminal of the primary winding TA.

[0063] The first terminal of the eighth capacitor C8 is connected to the first terminal of the fifth resistor R5. The second terminal of the eighth capacitor C8 is connected to the first terminal of the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the first terminal of the feedback winding TB. The second terminal of the feedback winding TB is grounded. The first terminal of the secondary winding TC is used to output the first voltage, and the second terminal of the secondary winding TC is grounded.

[0064] The self-excited oscillation circuit 30 is used to convert DC signals into AC signals. The voltage doubler rectifier circuit is used to rectify and boost the AC signals. The operation of the self-excited oscillation circuit 30 and the voltage doubler rectifier circuit, such as the first voltage doubler rectifier circuit 321, is as follows:

[0065] The second reference voltage Vin reaches the control terminal (base) of transistor Q through the fifth resistor R5, activating transistor Q. This causes the first terminal (emitter) and the second terminal (collector) of transistor Q to conduct, generating an induced electromotive force (EMF) of + on and - on the primary winding TA. Based on the same-name terminal relationship, the feedback winding TB also generates an induced EMF of + on and - on, supplying power to the control terminal (base) of transistor Q through the eighth capacitor C8 and the sixth resistor R6. This accelerates the conduction of transistor Q, increasing the current at the second terminal (collector) of transistor Q. This reduces the conduction losses at the first terminal (emitter) and the second terminal (collector) of transistor Q, increasing the induced voltage in the primary winding TA. Based on the same-name terminal relationship, the induced voltage in the feedback winding TB also increases. The power supply current to the control terminal (base) of transistor Q through the eighth capacitor C8 and the sixth resistor R6 further increases, causing transistor Q to enter the saturation region, further increasing the induced voltage in the primary winding TA.

[0066] During this process, the eighth capacitor C8 continuously charges. As the voltage of the eighth capacitor C8 increases, the supply current from the feedback winding TB to the control terminal (base) of the transistor Q through the eighth capacitor C8 and the sixth resistor R6 continuously decreases. This reduces the conduction current at the first terminal (emitter) and the second terminal (collector) of the transistor Q, causing the transistor Q to exit the saturation region and enter the amplification region. This also increases the conduction losses at the first terminal (emitter) and the second terminal (collector) of the transistor Q, resulting in a decrease in the induced voltage of the primary winding TA. Based on the relationship between the same terminals, the induced voltage of the feedback winding TB also decreases. The supply current from the eighth capacitor C8 and the sixth resistor R6 to the control terminal (base) of the transistor Q also decreases, causing the transistor Q to turn off. This results in an induced electromotive force (EMF) of upper - lower + on the primary winding TA.

[0067] Based on the relationship between the same terminals, an induced electromotive force (EMF) of up-down-up is also generated on the secondary winding TC, causing the first diode D1 to conduct, thus reducing the current flowing through the secondary winding TC. Due to the oscillation of residual energy on the secondary winding TC, an induced EMF of up-down-up is generated on the feedback winding TB, which is again fed back to the control terminal (base) of transistor Q through the eighth capacitor C8 and the sixth resistor R6, causing the first terminal of transistor Q to conduct as the emitter and the second terminal as the collector. This cycle continues until the oscillation of transformer T is completed. Furthermore, during this process, the voltage doubler rectifier circuit connected to it will output a second or third voltage.

[0068] In some embodiments of the present invention, such as Figure 10 As shown, the switching control circuit 33 includes an AND gate U1, a NOT gate U2, a latch U3, and a combination gate circuit U4. The control signals received by the switching control circuit 33 include an enable control signal K. S Interlocking control signal K L and polarity control signal K J Among them, latch U3 can be a D latch.

[0069] The first input of AND gate U1 is used to receive the enable control signal K. S The second input terminal of AND gate U1 is used to receive the interlocking control signal K. L The output of AND gate U1 is connected to the input of NOT gate U2; the output of NOT gate U2 is connected to the first input of latch U3, and the second input of latch U3 is used to receive the polarity control signal K. J The output of latch U3 is connected to the input of combination gate circuit U4. The first and second outputs of combination gate circuit U4 are used to output two selection signals, such as the first selection signal PE and the second selection signal PD. These two selection signals are used to select two sets of selection circuits respectively.

[0070] The switching control circuit 33 provided in this application has an interlock protection function. In specific implementation, when the power supply circuit has a high voltage output, regardless of whether there is a polarity control signal K, the switching control circuit 33 will be interlocked. J The enabling and power supply circuits must maintain a polarity-locked state to prevent sudden polarity switching under high-voltage output, which could cause arcing in the electrostatic chuck. This requires latching the polarity state of the power output terminals, allowing polarity switching only when there is no high-voltage output. The entire workflow is as follows:

[0071] When the enable control signal K S and interlock control signal K L When both are high, AND gate U1 outputs a high level to NOT gate U2, and NOT gate U2 outputs a low level to latch U3, causing latch U3 to be in a latched state, meaning that the output of latch U3 does not follow the polarity control signal K. J Changes. Assuming latch U3 outputs a low level when in latched state, the first selection signal PE from combinational gate U4 remains low, and the second selection signal PD remains high. Conversely, assuming latch U3 outputs a high level when in latched state, the first selection signal PE from combinational gate U4 remains high, and the second selection signal PD remains low.

[0072] When the enable control signal K S and interlock control signal K L When not both are high, AND gate U1 outputs a low level to NOT gate U2, and NOT gate U2 outputs a high level to latch U3. At this time, the output of latch U3 follows the polarity control signal K. J It changes with the change. If the polarity control signal K... J A high-level signal is emitted, latch U3 outputs a high level, and the first selection signal PE from combinational gate U4 remains high, while the second selection signal PD remains low. If the polarity control signal K... J When the signal is low, latch U3 outputs a low level signal, and the first selection signal PE of combinational gate circuit U4 remains low and the second selection signal PD remains high.

[0073] It should be noted that the combinational gate circuit U4 is composed of logic gates. This invention does not limit its specific structure, as long as it can output the required selection signal.

[0074] This application effectively improves the speed and integration of power circuit polarity switching by performing polarity switching on the low-voltage side, while avoiding the drawbacks of short lifespan, slow speed, and high cost associated with using high-voltage relays. Furthermore, the design of a switching control circuit with interlocking protection effectively enhances the stability of power circuit polarity switching.

[0075] As an optional implementation of the disclosure of this invention, an embodiment of this invention discloses a semiconductor process apparatus, such as... Figure 1 As shown, the semiconductor process equipment includes an electrostatic chuck and a power supply circuit 11 as disclosed in any of the above embodiments.

[0076] The electrostatic chuck includes at least two electrodes, such as a first electrode 7 and a second electrode 8. These two electrodes are connected to the two power output terminals of the power supply circuit 11, for example, the first electrode 7 and the second electrode 8 are connected to the first power output terminal HV+ and the second power output terminal HV- of the power supply circuit 11, respectively. Specifically, the first electrode 7 and the second electrode 8 can be connected to the first power output terminal HV+ and the second power output terminal HV-, respectively, through a filter circuit 10.

[0077] like Figure 1 As shown, the semiconductor process equipment may also include a plasma generation system 1, which generally includes an RF coil, an upper matching unit, and an upper RF power supply. The high-frequency magnetic field generated by the system excites the process gas entering the process chamber 9 into plasma 2. The lower RF power supply 15 generates a plasma sheath layer 16 on the upper surface of the wafer 3 through the high-frequency magnetic field generated by the lower matching unit 14. The voltage difference (DC self-bias) between the plasma sheath layer 16 and the wafer 3 forms an electric field, attracting various charged particles in the plasma 2 to perform deposition or etching processes on the surface of the wafer 3.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The above embodiments are merely illustrative of several implementation methods described in detail, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the protection scope of this specification. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A power supply circuit, characterized in that, It includes a self-excited oscillation circuit, two sets of voltage doubler rectifier circuits, two sets of selection circuits, a switching control circuit, and two power output terminals; The self-excited oscillation circuit is used to generate a first voltage through self-excited oscillation; one of the two output terminals of the self-excited oscillation circuit is grounded, and the other output terminal outputs the first voltage; Each of the voltage doubler rectifier circuits includes two voltage doubler rectifier sub-circuits, and the output terminals of the two voltage doubler rectifier sub-circuits are respectively connected to one of the two power supply output terminals; in each group of voltage doubler rectifier circuits, one voltage doubler rectifier sub-circuit is used to convert the first voltage into a second voltage, and the other voltage doubler rectifier circuit is used to convert the first voltage into a third voltage; the two power supply output terminals are used to output the second voltage and the third voltage, respectively; the polarity of the second voltage and the third voltage are opposite, and the difference between the second voltage and the third voltage is greater than the first voltage; Two voltage doubler rectifier circuits connected to the same power output terminal output voltages have opposite polarities. Each set of the selection circuits is connected to a set of the voltage doubler rectifier circuits; The selection circuit is used to transmit the first voltage to the corresponding set of voltage doubler rectifier circuits when selected; The switching control circuit is used to output selection signals to the two sets of selection circuits respectively, so that only one set of selection circuits is selected at any given time.

2. The power supply circuit according to claim 1, characterized in that, Each set of selection circuits includes two selection sub-circuits, which are respectively connected to the input terminals of the two voltage doubler rectifier sub-circuits of the corresponding set of voltage doubler rectifier circuits.

3. The power supply circuit according to claim 1 or 2, characterized in that, The selection circuit or the selection sub-circuit includes a first switching transistor and a second switching transistor; The control terminal of the first switch is used to receive a corresponding selection signal; the first terminal of the first switch is used to receive a first reference voltage; the second terminal of the first switch is connected to the control terminal of the second switch; the selection signal is used to control the first switch to be in an on or off state; the first switch is used to transmit the first reference voltage to the control terminal of the second switch when it is in an on state; the first reference voltage is used to control the second switch to be in an on state. The first terminal of the second switch is used to receive the first voltage, and the second terminal of the second switch is connected to the input terminal of a corresponding set of voltage doubler rectifier circuits or a voltage doubler rectifier sub-circuit; the second switch is used to transmit the first voltage to the corresponding set of voltage doubler rectifier circuits or a voltage doubler rectifier sub-circuit when it is in the on state.

4. The power supply circuit according to claim 3, characterized in that, The selection circuit or the selection sub-circuit further includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first end of the first resistor is used to receive the corresponding selection signal, and the second end of the first resistor is connected to the control terminal of the first switch. The first end of the second resistor is connected to the control terminal of the first switch, and the second end of the second resistor is connected to the first end of the first switch. The first end of the third resistor is connected to the second end of the first switch transistor, and the second end of the third resistor is connected to the control terminal of the second switch transistor; the first end of the fourth resistor is connected to the first end of the second switch transistor, and the second end of the fourth resistor is connected to the control terminal of the second switch transistor.

5. The power supply circuit according to claim 3, characterized in that, One of the first switching transistors and the second switching transistor is a PMOS transistor and the other is an NMOS transistor.

6. The power supply circuit according to claim 1 or 2, characterized in that, One of the two voltage doubler rectifier circuits connected to the same power output terminal includes a first capacitor, a second capacitor, a third capacitor, a first diode, a second diode, and a third diode; The first terminal of the first capacitor is grounded, the second terminal of the first capacitor is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the corresponding power output terminal. The negative terminal of the first diode is connected to the output terminal of the corresponding selection circuit or selection sub-circuit, and the positive terminal of the first diode is connected to the second terminal of the first capacitor; the first terminal of the third capacitor is connected to the negative terminal of the first diode, the second terminal of the third capacitor is connected to the positive terminal of the second diode, the negative terminal of the second diode is connected to the positive terminal of the first diode; the negative terminal of the third diode is connected to the positive terminal of the second diode, and the positive terminal of the third diode is connected to the second terminal of the second capacitor.

7. The power supply circuit according to claim 6, characterized in that, The other voltage doubler rectifier circuit in the two voltage doubler rectifier circuits connected to the same power output terminal includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a fourth diode, a fifth diode, and a sixth diode; The first terminal of the fourth capacitor is grounded, the second terminal of the fourth capacitor is connected to the first terminal of the fifth capacitor, and the second terminal of the fifth capacitor is connected to the corresponding power output terminal. The negative terminal of the fourth diode is connected to the second terminal of the fourth capacitor, and the positive terminal of the fourth diode is connected to the output terminal of the corresponding selection circuit or selection sub-circuit; the first terminal of the sixth capacitor is connected to the positive terminal of the fourth diode, the second terminal of the sixth capacitor is connected to the negative terminal of the fifth diode, and the positive terminal of the fifth diode is connected to the negative terminal of the fourth diode; the positive terminal of the sixth diode is connected to the negative terminal of the fifth diode, and the negative terminal of the sixth diode is connected to the second terminal of the fifth capacitor.

8. The power supply circuit according to claim 1 or 2, characterized in that, The switching control circuit includes AND gates, NOT gates, latches, and combination gate circuits. The first input terminal of the AND gate is used to receive an enable control signal, the second input terminal of the AND gate is used to receive an interlock control signal, and the output terminal of the AND gate is connected to the input terminal of the NOT gate. The output of the NOT gate is connected to the first input of the latch; The second input terminal of the latch is used to receive a polarity control signal, and the output terminal of the latch is connected to the input terminal of the combination gate circuit. The first and second output terminals of the combined gate circuit are used to output two selection signals, which are used to select the two sets of selection circuits respectively.

9. The power supply circuit according to claim 1 or 2, characterized in that, The self-excited oscillation circuit includes a seventh capacitor, an eighth capacitor, a transistor, a fifth resistor, a sixth resistor, and a transformer. The transformer includes a primary winding, a feedback winding, and a secondary winding. The primary winding and the feedback winding are arranged on the same side, while the secondary winding is arranged on a different side from the primary winding and the feedback winding. The first terminal of the seventh capacitor is used to receive the second reference voltage, and the second terminal of the seventh capacitor is grounded; the first terminal of the primary winding is connected to the first terminal of the seventh capacitor, the second terminal of the primary winding is connected to the first terminal of the transistor, the second terminal of the transistor is grounded, the control terminal of the transistor is connected to the first terminal of the fifth resistor, and the second terminal of the fifth resistor is connected to the first terminal of the primary winding. The first terminal of the eighth capacitor is connected to the first terminal of the fifth resistor, the second terminal of the eighth capacitor is connected to the first terminal of the sixth resistor, the second terminal of the sixth resistor is connected to the first terminal of the feedback winding, and the second terminal of the feedback winding is grounded; the first terminal of the secondary winding is used to output the first voltage, and the second terminal of the secondary winding is grounded.

10. A semiconductor process apparatus, characterized in that, The device includes an electrostatic chuck and a power supply circuit as described in any one of claims 1 to 9, wherein the electrostatic chuck includes two electrodes, which are respectively connected to two power output terminals of the power supply circuit.

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