PC and SOC based distributed numerical control system

Abstract

This invention discloses a distributed CNC system based on a PC and a System-on-a-Chip (SoC), relating to the field of CNC technology. The system connects a host computer and a slave computer via a PCIe link. The host computer uses XDMA to write motion commands into the slave computer's DDR circular buffer. The slave computer's CNC unit monitors the buffer data level in real time, dynamically generating a time scaling factor and modulating the execution speed after smoothing and filtering, thus transforming discrete communication jitter into smooth speed changes. Furthermore, the system observes clock frequency differences and adjusts the slave computer's hardware timer reload value to synchronize the time base. The host computer then uses a pre-distortion scaling factor to correct the position increment, offsetting the physical speed deviation caused by the time base adjustment. This invention effectively solves the communication fluctuations and heterogeneous hardware clock drift problems of non-real-time operating systems, ensuring the continuity and accuracy of the machining process.

Description

Technical Field

[0001] This invention relates to the field of numerical control technology, specifically to a distributed numerical control system based on PC and SOC. Background Technology

[0002] As the manufacturing industry demands higher processing efficiency and system openness, distributed CNC systems based on general-purpose personal computers (PCs) and embedded motion control units (such as FPGAs, ARMs, or dedicated motion control cards) are becoming increasingly popular. Compared to fully software-based CNC systems that centralize all control functions on a PC, this distributed architecture leverages the PC's powerful computing capabilities to handle complex human-machine interactions, G-code parsing, and trajectory interpolation. Simultaneously, it utilizes the strong real-time characteristics of lower-level hardware to execute low-level motor servo control. The two systems interact via a communication bus, thus balancing system performance limits with control stability.

[0003] However, in practical applications, general-purpose PCs typically run non-real-time operating systems such as Windows or Linux. Their kernel task scheduling mechanisms prioritize system throughput over deterministic response, leading to unpredictable random jitter in the interpolation data transmission interval. When performing high-density, small-segment machining (such as precision mold machining), the transmission of large amounts of data places extremely high demands on the stability of the communication link. If the lower-level machine adopts only a fixed buffering strategy, when the upper-level machine experiences data transmission delays due to excessive system load, the lower-level machine is highly susceptible to being forced to interrupt interpolation due to depleted buffer data. This unexpected pause causes sudden changes in feed axis speed, resulting in machine tool vibration and irreparable tool marks on the workpiece surface. While increasing the buffer capacity can mitigate jitter, this significantly increases system latency and reduces response speed during emergency stops or feed rate adjustments.

[0004] Furthermore, in this distributed architecture, the host computer and the slave computer each rely on independent hardware crystal oscillators as clock sources, inevitably resulting in physical frequency deviations. During long, continuous machining tasks, these minute frequency differences accumulate over time, causing a gradual disconnect between logical and physical time. If the slave computer's clock is too fast, buffered data will be prematurely emptied; if the slave computer's clock is too slow, buffer overflow will occur. Existing solutions often rely on expensive real-time operating system extensions (such as RTX) or dedicated hardware synchronization clock lines, which not only significantly increases the system's construction cost but also limits its versatility and portability based on standard PC hardware platforms. Therefore, how to address the impact of communication jitter and clock drift on machining quality without relying on dedicated real-time systems is a pressing issue for current open CNC systems. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a distributed CNC system based on PC and SOC, which solves the problem of machining interruptions caused by communication jitter due to the non-real-time operating system of general PCs, as well as the problems of cumulative position deviation and buffer overflow caused by clock asynchrony in distributed heterogeneous hardware architecture.

[0006] This invention provides a distributed numerical control system based on a PC and a System-on-a-Chip (SoC). The system employs a master-slave heterogeneous hardware architecture, with the host computer handling non-real-time trajectory planning and human-machine interaction, while the slave computer, using a System-on-a-Chip (SoC) architecture, handles real-time motion control. The two are connected via a PCIe communication link, leveraging the high bandwidth of PCIe to ensure the transmission of large amounts of data.

[0007] In terms of data interaction, the host computer generates motion command data containing position increment information and writes the data into the ring buffer in the lower-level DDR storage module through the PCIE device driver library and XDMA interface, using the buffer to smooth out data transmission fluctuations.

[0008] To address the issue of data stream fluctuations affecting execution continuity, the CNC machining control unit within the lower-level FPGA logic module monitors the data stream status while reading data. By calculating the difference between the write and read pointers in real time to obtain the current valid data level, the system adjusts its execution speed accordingly: when the data level drops below an alarm threshold, a time scaling factor is automatically generated to modulate the execution speed. This mechanism transforms discrete communication jitter into continuous speed variation, preventing downtime due to data exhaustion.

[0009] Furthermore, the CNC machining control unit performs smoothing filtering on the time scaling factor based on rate of change, limiting the amount of factor change between adjacent moments to prevent sudden speed changes from impacting the mechanical structure. The pulse generation units of each axis and the spindle control unit latch the scaling factor through a global synchronization signal, maintaining the interpolation linkage between each axis.

[0010] The system's internal bus adopts a separate design. Motion command data is transmitted through the AXI-MM channel to ensure bandwidth, while logic control commands are transmitted through the AXI-Lite channel to reduce latency.

[0011] The clock synchronization and speed compensation mechanisms of the above system are as follows:

[0012] To address the frequency deviation between the host computer's logic clock and the slave computer's physical clock, the ARM processor module calculates the clock frequency difference ratio by statistically analyzing the hardware counter time and the number of received XDMA data packets, and performs low-pass filtering to obtain the clock compensation coefficient.

[0013] Based on this coefficient, the system performs two-stage regulation: First, implement lower-level machine time base synchronization. The ARM processor calculates the adjustment ratio based on the clock compensation coefficient and data level deviation, and adjusts the reload value of the lower-level machine hardware timer. By fine-tuning the physical duration of the lower-level machine interpolation cycle, the lower-level machine's physical clock rate is made to follow the upper-level machine's logic clock rate, eliminating accumulated errors.

[0014] Secondly, speed consistency compensation is implemented on the host computer. The host computer calculates the pre-distortion scaling factor based on the clock compensation coefficient and pre-corrects the theoretical position increment of each axis when generating motion commands. This process offsets the physical speed changes caused by the lower computer's time base adjustment, ensuring that the machining dimensions and speed meet the set requirements.

[0015] In summary, this invention utilizes ring buffer level modulation technology to solve the communication jitter problem, and combines hardware time base fine-tuning and data predistortion technology to solve the clock drift problem, thereby realizing high-performance CNC machining based on a general PC platform.

[0016] This invention provides a distributed numerical control system based on a PC and a System-on-a-Chip (SOC). It has the following advantages: 1. This invention utilizes a DDR memory module to construct a large-capacity circular buffer in the lower-level machine and establishes a dynamic mapping relationship between data level and execution speed through a CNC machining control unit. When communication jitter causes a significant drop in data level, the system automatically reduces the execution speed to maintain continuous data flow. Combined with a smoothing filtering algorithm based on rate limiting, discrete communication fluctuations are transformed into smooth speed changes, avoiding downtime caused by data exhaustion and achieving highly continuous CNC machining under a non-real-time operating system.

[0017] 2. To address the cumulative error caused by the inconsistency between the crystal oscillator frequencies of the PC and the embedded motion control unit, this invention adopts a two-way compensation strategy that combines hardware timer reload and data predistortion. On the one hand, it adjusts the ebb rate of the physical time base of the lower-level machine to follow the logical data flow of the upper-level machine, preventing buffer overflow or underflow (data exhaustion) caused by clock asynchrony. On the other hand, it pre-corrects the position increment by the upper-level machine to offset the physical speed change caused by the time base adjustment, ensuring that the actual cutting speed strictly conforms to the process setting.

[0018] 3. This invention designs a separate on-chip interconnect bus architecture, directly writing high-volume motion command data to DDR via the AXI-MM channel, ensuring high data throughput requirements during complex surface machining; simultaneously, logic control commands with weak real-time requirements are transmitted via the AXI-Lite channel, reducing access latency to control signals. This architecture fully utilizes the computing advantages of the host computer and the real-time control capabilities of the slave computer, improving the overall processing efficiency of the system while reducing dedicated hardware costs. Attached Figure Description

[0019] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is a logic diagram of the dynamic caching and speed smoothing adjustment of the present invention; Figure 3 This is a flowchart of the heterogeneous clock domain synchronization control of the present invention.

[0020] Among them, 100 is the host computer; 110 is the CNC processing module; 120 is the machine tool control module; 130 is the PCIE device driver library; 200 is the slave computer; 210 is the XDMA communication module; 220 is the DDR storage module; 230 is the AXI interconnect bus; 240 is the FPGA logic module; 241 is the Local Bus communication bus; 242 is the AXI to Local Bus conversion unit; 243 is the CNC machining control unit; 244 is the spindle control unit; 245 is the pulse generation unit for each axis; 250 is the ARM processor module; and 300 is the PCIE communication link. Detailed Implementation

[0021] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] See attached document Figure 1 This invention provides a dynamic caching and speed smoothing adjustment method for a distributed CNC system based on heterogeneous clock domain synchronization. This method is applied to a distributed CNC system based on PC and SOC. The distributed CNC system based on PC and SOC includes a host computer 100, a slave computer 200, and a PCIe communication link 300 connecting the two for data transmission.

[0023] The host computer 100 adopts a general-purpose computer hardware architecture and is equipped with a non-real-time operating system. The host computer 100 includes a CNC processing module 110, a machine tool control module 120, and a PCIE device driver library 130. The CNC processing module 110 is used to parse, smooth, plan speeds, and perform interpolation calculations on the input G-code trajectory file, generating periodic motion command data containing incremental position information for each axis. The machine tool control module 120 is used to process weak real-time logic control commands, including spindle start / stop signals, coordinate setting signals, and status monitoring signals. The PCIE device driver library 130 is developed based on the XDMA driver interface and is equipped with a direct memory access interface and register read / write interface for the slave computer 200.

[0024] The lower-level machine 200 adopts a system-on-a-chip (SoC) architecture, integrating an FPGA logic module 240, an ARM processor module 250, and a DDR memory module 220. The lower-level machine 200 is physically connected to the PCIe communication link 300 via an XDMA communication module 210. The XDMA communication module 210 is connected to the DDR memory module 220 and the FPGA logic module 240 respectively via an on-chip high-speed AXI interconnect bus 230.

[0025] The data transmission channels of the PC- and SOC-based distributed CNC system are logically divided into a large data flow channel and a control command channel. The large data flow channel transmits motion command data. The data path is as follows: the host computer 100 sends data to the XDMA communication module 210 via the PCIE communication link 300, and then directly writes it to the preset circular buffer in the DDR memory module 220 via the AXI-MM memory mapping channel in the AXI interconnect bus 230. The control command channel transmits logic control commands. The data path is as follows: the host computer 100 accesses the XDMA communication module 210 via the PCIE communication link 300, and then accesses the AXI-Lite lightweight channel in the AXI interconnect bus 230 to connect to the AXI-to-Local Bus conversion unit 242 inside the FPGA logic module 240, thereby accessing the various functional submodules mounted on the Local Bus communication bus 241.

[0026] In this embodiment, the AXI to Local Bus conversion unit 242 acts as a bridge, configured as a slave on the AXI bus. It is responsible for converting the high-speed full-duplex channel of the AXI protocol into a logically simple half-duplex Local Bus protocol. Specifically, the physical signals defined by the Local Bus communication bus 241 include: an access address signal indicating the location of the target register, a read strobe signal indicating the start of a read operation, a write strobe signal indicating the start of a write operation, a read data output signal carrying the read result, and a write data input signal carrying the data to be written. This simplified signal definition aims to reduce the interface logic complexity of various functional sub-modules (such as the CNC machining control unit 243).

[0027] The FPGA logic module 240 integrates multiple hardware logic modules, all connected to the Local Bus communication bus 241. These hardware logic modules include a CNC machining control unit 243, a spindle control unit 244, and axis pulse generation units 245. The CNC machining control unit 243 is configured to read motion command data from the ring buffer of the DDR memory module 220 via the AXI interconnect bus 230. The spindle control unit 244 generates electrical signals to control the spindle speed. The axis pulse generation units 245 generate differential pulse signals and direction signals to drive the servo motors based on the motion command data.

[0028] The ARM processor module 250 and the FPGA logic module 240 interact via an on-chip bus to perform floating-point operations and monitor system status. The ARM processor module 250 is configured to read the hardware counter within the FPGA logic module 240, calculate the deviation between the physical time elapsed and the logic interpolation time, and feed back the clock compensation coefficient to the host computer 100 via the PCIe communication link 300.

[0029] Based on the above hardware architecture, the method of the present invention executes the following workflow: The CNC processing module 110 performs interpolation calculations in the host computer 100 to generate motion command data packets. The host computer 100 calls the PCIE device driver library 130 to maintain a write pointer variable and continuously writes the motion command data packets into the circular buffer in the DDR storage module 220 of the slave computer 200.

[0030] The CNC machining control unit 243 maintains a read pointer variable in the lower-level machine 200 and sequentially reads motion command data from the circular buffer of the DDR memory module 220. During the reading process, the CNC machining control unit 243 calculates the difference between the write pointer variable and the read pointer variable in real time to obtain the current valid data level in the circular buffer.

[0031] The CNC machining control unit 243 generates a time scaling factor based on the current valid data level using its internally preset mapping logic. This time scaling factor, after smoothing and filtering, is simultaneously input to both the axis pulse generation unit 245 and the spindle control unit 244. The axis pulse generation unit 245 modulates the output frequency of the motion command data according to the time scaling factor, changing the feed rate of each axis; the spindle control unit 244 modulates the spindle speed command according to the same time scaling factor, changing the spindle rotation speed. Both maintain a synchronized proportional change.

[0032] During system operation, the ARM processor module 250 periodically calculates the physical time consumed by the actual data executed by the FPGA logic module 240, and calculates the drift ratio of the lower-level machine 200's physical clock relative to the upper-level machine 100's logic clock. The ARM processor module 250 writes the drift ratio to a designated storage area for the upper-level machine 100 to read. The upper-level machine 100 reads the drift ratio and, when the numerical control processing module 110 performs subsequent trajectory interpolation calculations, corrects (or pre-distorts) the position increment of the generated motion command based on the drift ratio, thereby compensating for the clock frequency deviation between the upper and lower-level machines 200 at the upstream data generation end and achieving closed-loop synchronous control.

[0033] See attached document Figure 2 The circular cache built in the DDR memory module 220 is essentially a data channel constructed end-to-end in the linear physical address space through modulo operations of logical pointers. This channel utilizes the high-density storage characteristics of DDR to transform the discontinuous data stream generated in the non-real-time domain into the continuous instruction stream required in the real-time domain. The specific implementation process includes the following steps: S101: Allocation and mapping of physical storage space. During the initialization phase, the host computer 100 configures the slave computer 200 via the PCIe communication link 300. Within the physical address space of the DDR storage module 220, a contiguous storage region is reserved as a circular cache. This region is defined by the starting physical address... and total capacity definition.

[0034] Of which, total capacity This indicates the maximum number of interpolated data packets that the circular buffer can hold. This is to adapt to the internal binary operation logic of the FPGA and optimize modulo efficiency. The preferred value is 2. powers (e.g.) to ),and The specific value should be based on the interpolation period. With expected internet outage tolerance time Confirmed, satisfied .

[0035] in, This indicates the maximum number of interpolated data packets (in bytes) that the circular buffer can hold. Furthermore, to adapt to the internal binary operation logic of the FPGA and optimize modulo efficiency, The value of is preferably set to a power of 2 (e.g., to ); This represents the system's expected network outage tolerance time (unit: seconds), which is the maximum time that the lower-level machine 200 can maintain normal processing by relying on cached data in the event that the communication between the upper-level machine 100 and the lower-level machine 200 is completely interrupted. This indicates the interpolation control cycle of the CNC system (unit: seconds).

[0036] End physical address of the circular buffer The following relationship must be satisfied: ; in, This indicates the end address boundary of the circular cache in the DDR physical memory space; This indicates the starting physical base address of the circular buffer, which is allocated by the system memory management unit in the free memory region; The total capacity of the circular buffer (i.e., the total number of data packets) determined by the aforementioned calculation. This indicates the storage space occupied by a single interpolation data packet (in bytes).

[0037] The value depends on the number of control axes and the data precision (for example, for a five-axis CNC system, which includes 32-bit position incremental data for 5 axes and 32-bit control head data, the basic length is 24 bytes), and The data bus width needs to be rounded up to an integer multiple of the data bus width, based on the burst transaction characteristics of AXI communication for DDR read and write.

[0038] This physical address range is marked as a dedicated area in the SOC internal bus interconnect matrix. Through the permission settings of the address decoder, only the AXI-MM channel of the XDMA communication module 210 and the CNC machining control unit 243 are allowed to perform write access and read access, thus isolating the memory access paths of other non-real-time tasks at the hardware level.

[0039] S102: Definition and register configuration of read / write pointer variables. The system defines two index pointer variables for managing data flow: the write pointer... and read pointer Both pointers can take values ​​within a certain range. The integer. In the configuration register space of FPGA logic module 240, two specific 32-bit register addresses are allocated: the write pointer register... and read pointer register .

[0040] Write pointer register Configured to allow the host computer 100 to write and update via the AXI-Lite channel, while also allowing the CNC machining control unit 243 to read; read pointer register. It is configured to be updated by the CNC machining control unit 243 according to the reading progress, while allowing the host computer 100 to read the status of the slave computer 200 through the AXI-Lite channel. For the specific circuit implementation of the registers and the AXI bus address decoding logic, those skilled in the art can use standard bus bridging IP cores.

[0041] S103: Address calculation and pointer update for data written by the host computer 100. After generating motion command data, the numerical control processing module 110 of the host computer 100 does not directly operate on the absolute physical address, but instead updates the write pointer based on the currently maintained address. Calculate the target physical address The calculation formula is as follows: ; in, This indicates the DDR physical target address where motion command data is currently to be written; Indicates the starting physical base address of the circular buffer; Indicates the current time The write pointer index value maintained by the host computer 100 has a value range of 0 to 100. Integers; This indicates the number of storage bytes occupied by a single interpolation data packet.

[0042] The host computer 100 calls the large data transmission interface of the PCIe device driver library 130 to write motion command data. The pointer points to the DDR space. After the data transfer is complete and the write is confirmed to be successful, the host computer 100 updates the local write pointer variable and sets the updated value to the specified value. The value is written to the write pointer register of the lower-level machine 200 through a small data control channel. .

[0043] To ensure the circular nature of the write logic, the update of the write pointer follows the modulo operation rule: ; in, This indicates the write pointer index value at the next moment after the data has been written and updated; This represents the modulo operator, used to reset the write pointer to 0 when it reaches its maximum value, thus achieving circular wrap-around. This indicates the total capacity of the circular buffer.

[0044] when When the value is a power of 2, the above modulo operation is replaced by a bitwise AND operation in the specific code implementation: This is to reduce computational overhead.

[0045] in, This represents the binary bitwise AND operator. This represents the mask value, used to quickly retain the low-order bits and truncate the high-order bits from overflowing.

[0046] S104: Address resolution and pointer feedback for lower-level machine 200 data reading. The CNC machining control unit 243 queries the write pointer register during each interpolation cycle or pre-read cycle. The value and its own maintained read pointer The two values ​​are compared. If they are not equal, it is determined that there is unprocessed data in the buffer. The CNC machining control unit 243 then determines the data based on the current read pointer. Calculate the source physical address : ; in, This indicates the physical source address in DDR of the interpolated data packet that the lower-level machine 200 needs to read. Indicates the starting physical base address of the circular buffer; Indicates the current time The read pointer index value maintained by the lower-level machine 200 points to the position of the earliest unprocessed data packet; This indicates the number of storage bytes occupied by a single interpolation data packet.

[0047] The CNC machining control unit 243 initiates a read transaction through the AXI master interface, from... The interpolation data packet is acquired and sent to the subsequent processing pipeline. After the data reading operation is completed, the CNC machining control unit 243 updates the read pointer. The value of the update logic also follows the modulo operation rules: ; in, This indicates the next read pointer index value to be updated after the current data read is completed; This represents the modulo operator, used to implement the circular wraparound logic for reading pointers; This indicates the total capacity of the circular buffer.

[0048] The updated value is immediately reflected in the FPGA's registers, which the host computer 100 can read when needed to determine the remaining space in the buffer. Through the above address mapping and pointer interaction mechanism, the host computer 100 and the slave computer 200 can build a flexible asynchronous data interaction channel using the DDR storage module 220, even under conditions where the physical clocks are not synchronized and communication delays exist.

[0049] See attached document Figure 3 The real-time water level refers to the number of valid data packets currently stored in the circular buffer that have not yet been executed by the lower-level machine 200. It is a quantitative indicator of the system's data backlog and a core input variable for subsequent speed adaptive control algorithms. Because the read / write pointers continuously cycle within the circular address space, the linear difference in physical addresses cannot directly reflect the actual data storage volume. Therefore, it is necessary to map it to logically continuous storage volume through modulo arithmetic logic. The specific calculation process is executed by combinational logic circuits or sequential logic circuits within the FPGA logic module 240, including the following steps: S105: Real-time sampling and synchronization of pointer variables. The CNC machining control unit 243 concurrently reads and writes the pointer register within each FPGA system clock cycle (e.g., 100MHz or higher). The current value in and read pointer register The current value in These two pointer variables are defined internally by a bit width of [value missing]. An unsigned integer that satisfies .

[0050] because It is written by the host computer 100 through the PCIe asynchronous clock domain. In order to eliminate the metastability that may occur during cross-clock domain transmission, the CNC machining control unit 243 reads... Previously, a multi-stage or multi-stage D flip-flop series method was used to perform timing synchronization processing on the signal to ensure that the pointer values ​​involved in the calculation were stable and valid.

[0051] S106: Relative position determination and difference operation. To resolve the state ambiguity caused by overlapping read and write pointers in a circular queue (i.e., inability to distinguish whether the buffer is empty or full), this embodiment adopts a strategy of reserving one storage unit (One Slot Open), that is, the maximum effective data volume of the circular buffer is limited to... Based on this strategy, the arithmetic logic unit inside the FPGA... and Based on the numerical relationship, perform piecewise calculation logic: When sampling time satisfy This indicates that the write pointer is located after the read pointer in the logical linear space and has not yet wrapped around; at this time, the effective data level is... The direct difference between the two: ; in, This indicates the number of valid interpolated data packets accumulated in the circular buffer at the current moment, awaiting processing by the lower-level machine 200; This represents the write pointer value at the current sampling moment; This indicates the value of the read pointer at the current sampling time.

[0052] When sampling time satisfy This indicates that the write pointer has reached the maximum physical address of the cache and has wrapped around, jumping to a lower address region, while the read pointer has not yet completed its current loop. At this point, the effective data level... It consists of two parts: the amount of data from the read pointer to the end of the cache, and the amount of data from the start address of the cache to the write pointer. The calculation formula is: ; in, The total capacity of the aforementioned circular buffer is expressed in units of the number of interpolated data packets. This indicates the amount of valid data remaining from the current read pointer position to the end of the buffer; In this scenario, it is equivalent to the effective amount of data from the beginning of the cache to the current write pointer.

[0053] To improve the computational efficiency of FPGA hardware circuits, the aforementioned segmented logic is synthesized into a unified modular addition and subtraction circuit in a hardware description language (HDL). When Values ​​are integer powers of 2 (i.e.) When using the natural overflow property of binary two's complement arithmetic, the calculation formula simplifies to: ; In the formula, Indicates a bitwise AND operation; Represents the binary mask used for fast modulo operations; This formula requires no comparators or multiplexers; it can be calculated within one clock cycle using only a subtractor and bit truncation. Even if... Even if the result of the operation is negative, the correct ring difference can be automatically obtained through bitwise AND masking.

[0054] S107: Abnormal state monitoring and boundary clamping. (Based on calculations...) Then, the CNC machining control unit 243 further determines the validity of the value.

[0055] The decision logic is as follows: like If the cache is empty, the CNC machining control unit 243 will pause the reading operation to prevent reading invalid data and set the "starvation waiting" status flag to the host computer 100.

[0056] like If the error occurs, a buffer overflow is detected. This situation usually indicates a write logic error or pointer update anomaly on the host computer. The system will trigger a fatal error interrupt, stopping all axis movements to protect the device.

[0057] like If the water level is within the range, then the water level is considered valid.

[0058] in, This represents the number of valid interpolated data packets in the current circular buffer, calculated using the preceding steps. This indicates the maximum allowed effective data storage capacity of the circular buffer under the One Slot Open policy. This represents the total physical capacity of the cache. The three logical judgments above correspond to the three states of the circular buffer: idle state (data exhausted), fault state (data out of bounds), and normal working state (valid data exists).

[0059] Verified The value is output to the subsequent time scaling factor generation module as a real-time basis for adjusting the system's operating rhythm.

[0060] The core principle of this embodiment lies in constructing a negative feedback adjustment loop based on cache level. When the data supply rate of the non-real-time host computer 100 is lower than the consumption rate of the slave computer 200, the physical execution time base of the slave computer 200 is actively reduced by monitoring the precursor signal of a decrease in cache level. This adjustment mechanism transforms discrete communication blockages into continuous speed smooth decay, thereby maintaining the continuity of the processing. The specific implementation logic includes the following steps: S201: Configuration of control threshold and scaling parameters. During the initialization phase, the system sets key control parameters in the registers of the CNC machining control unit 243 via the AXI-Lite configuration interface. These parameters include the safety water level threshold. Alarm water level threshold and minimum speed proportional coefficient .

[0061] The above parameters are determined as follows: Safe water level threshold Used to define the boundaries for stable system operation. Its value is determined according to the formula... Confirmed. Among them, The maximum statistical delay jitter time (e.g., 50ms) measured for the PCIe communication link 300. The interpolation frequency (e.g., 1kHz). This is the safety margin factor (ranging from 1.2 to 1.5).

[0062] Alarm water level threshold This is used to define the critical boundary before data starvation occurs. Its value should be greater than 0 to reserve sufficient deceleration buffer distance, preventing the cache from being exhausted before the rate drops to a safe level. It is typically set to [value missing]. 5% to 10%.

[0063] Minimum speed proportional coefficient Defines the minimum operating speed at extremely low water levels. The preferred value range is 0.01 to 0.1. This avoids the feed axis from entering a completely stationary state, thus avoiding the nonlinear jump caused by overcoming static friction (Stiction) when restarting. If the speed is directly reduced to 0, "creeping" or instantaneous positional changes will occur when resuming motion because the static friction is significantly greater than the dynamic friction, which seriously affects the surface finish of precision-machined surfaces.

[0064] S202: Calculation of the piecewise mapping function. The mapping logic circuit inside the CNC machining control unit 243 calculates based on the real-time water level. The target time scaling factor is calculated based on a preset piecewise linear function within the given interval. The calculation formula is as follows: ; in, Indicates at time The calculated target time scaling factor is a dimensionless scaling factor with a value range of [value range missing]. ; This indicates the current real-time effective data level within the circular buffer. This indicates the preset safe water level threshold, which defines the boundary for stable system operation; This indicates the preset alarm threshold, which defines the emergency boundary where data starvation is about to occur; This indicates the preset minimum speed scaling factor (e.g., 0.01), used to prevent the speed from dropping to 0, which could cause the servo system to lose lock or the interpolation to be interrupted. This indicates the system's nominal full-speed operating status; intermediate term of formula In fact, it represents the normalized relative position of the current water level between the alarm threshold and the safety threshold.

[0065] The physical meaning of this piecewise function is: when At this time, the system is in the stable region, and the output speed is 1.0 at full speed to ensure processing efficiency.

[0066] when At this point, the system enters the linear adjustment zone. The output ratio is positively linearly correlated with the water level; as the water level decreases, the execution speed slows down linearly, thus prolonging the time it takes for the remaining data to be exhausted.

[0067] when At this point, the system enters the low-speed holding region and outputs a fixed minimum ratio. Waiting for the host computer to restore the data stream 100.

[0068] S203: Optimized implementation of hardware arithmetic logic. In order to efficiently execute the division and multiplication operations described in S202 in the FPGA and avoid directly implementing a high-latency divider in the logic circuit, this embodiment adopts a method combining slope pre-calculation and fixed-point arithmetic.

[0069] First, the host computer 100 pre-calculates the slope coefficient of the adjustment range during the configuration phase. And write it to the FPGA register: ; in, The slope coefficient represents the linear adjustment interval, and its physical meaning is the reduction in the time scaling factor caused by a unit drop in water level; This indicates the preset minimum speed proportionality coefficient; This indicates the preset safe water level threshold; This indicates the preset alarm water level threshold; This represents the nominal proportionality coefficient corresponding to full-speed operation.

[0070] because Typically, these are decimals less than 1 and need to be converted to fixed-point integer format when transmitted to the FPGA. For example, using Q16.16 format, the floating-point slope value is multiplied by... Then round down before transmission.

[0071] Secondly, in the FPGA hardware logic, the calculation formula for the linear adjustment region is converted into a multiply-accumulate operation form: ; in, This represents the target time scaling factor currently calculated by the FPGA hardware logic; This indicates the current real-time cache level. This represents the alarm water level threshold that serves as the starting point for linear regulation. This represents the slope coefficient that was pre-calculated and stored in fixed-point number format in the preceding steps; This represents the minimum velocity scaling factor used as the base offset.

[0072] During the operation, the FPGA calls the dedicated hardware multiplier unit (DSP Block) integrated within the chip to perform the multiplication operation. The result is then right-shifted by the corresponding fixed-point number of bits (e.g., right-shifted by 16 bits) to restore the actual scaling value. This logic path is designed as a pipelined structure to ensure that the mapping operation can be completed in a single or a very short number of clock cycles, meeting the high real-time requirements of the CNC system.

[0073] The original target time scaling factor generated by the aforementioned steps Essentially, it's a step signal that jumps with the buffer water level range. However, the actuators (motor and mechanical load) of the servo feed system are rigid bodies, and their rate of change is limited by the maximum output torque and mechanical rigidity. If the scaling factor of the step change is directly applied to the drive system, it will generate a huge jerk at the physical level, leading to servo alarms or mechanical shocks. Therefore, this embodiment introduces a digital filtering stage based on the rate limiter into the FPGA logic to reconstruct the step-form target instruction into a ramp instruction that conforms to the machine tool dynamics characteristics. The specific implementation process includes the following steps: S204: Definition and conversion of dynamic constraint parameters. The system needs to set a maximum allowable rate of change of the time scaling factor, which is used to limit the fastest response time for the system to transition from the current velocity to the target velocity.

[0074] During the initialization phase, the host computer 100 calculates the normalized step limit value based on the machine tool's dynamic parameters. The calculation process is as follows: First, determine the maximum allowable physical acceleration of the machine tool. (Unit: mm / s) 2 ) and the maximum rapid traverse speed of the machine tool design (Unit: mm / s). Due to time scaling factor It is a domain of The dimensionless ratio, with a value of 1.0 corresponding to physical velocity. Therefore, the rate of change of the scaling factor The corresponding physical meaning is .

[0075] To adapt to discrete-time control systems using FPGAs, continuous acceleration constraints need to be converted into single FPGA control cycles. Maximum permissible increment within (unit: s) The formula is as follows: ; in, This represents the maximum allowable change in the time scaling factor within a single FPGA control cycle (i.e., the normalized acceleration limit step size). This indicates the maximum permissible physical acceleration of the machine tool's mechanical structure and drive system (unit: mm / s²). 2 ); This represents the maximum design rapid traverse speed of the machine tool when the scaling factor is 1.0 (unit: mm / s). It is preferable to set it to an integer multiple of the interpolation period (e.g., ).Should The value is stored as a fixed-point constant in the FPGA's configuration register and serves as the maximum slope clamping threshold for the smoothing filter.

[0076] S205: Deviation calculation and rate clamping. In each control cycle At any given moment, the smoothing control logic first reads the current target scaling factor. And the smoothing scaling factor already output at the previous time step. The logic circuit calculates the deviation between the two. ; ; Subsequently, the logic circuit determines whether the absolute value of the deviation exceeds the preset maximum step increment. .

[0077] like This indicates that the current target speed change is within a safe range, and the motor torque is sufficient to support the acceleration, limiting the deviation value. Direct value .

[0078] like This indicates that the target velocity is changing too rapidly, exceeding the physical system's response capability. In this case, the system must forcibly limit the rate of change, limiting the deviation value. Perform clamping according to the following formula: ; in, This represents the final effective deviation step size after dynamic constraints. This is a sign function used to extract the positive and negative directions of the deviation (i.e., return +1 if the deviation is positive, and return -1 if the deviation is negative), ensuring that the direction of velocity change after clamping is consistent with the original target; This refers to the maximum allowable scaling factor change within a single period, as defined in the preceding steps. Through this step, the system shapes the input step signal into a ramp signal with a constant slope.

[0079] S206: Output Integration and State Update. The system updates the current output value using the clamped deviation value and performs discrete-time integration (accumulation) calculation: ; in, Indicates the current control cycle The updated final execution scaling factor used to drive subsequent modules; Indicates the previous control cycle Saved execution scaling factor state value; This indicates the safety deviation step size for this adjustment after the aforementioned rate clamping process.

[0080] In FPGA hardware implementation, to prevent precision loss (underflow) during multiple accumulation processes, storage... The registers employ an extended bit-width design. For example, if If the output requires 16-bit precision, the internal accumulator register is designed to be 32 bits or higher in width. All decimal places are retained during the operation, and the high-order bits are truncated only when the final output is given to the next level module.

[0081] Furthermore, boundary saturation handling logic needs to be added after the integration operation. If the calculation result... If so, then it will be forcibly set to 1.0; if Then force set to .

[0082] 1.0 indicates the maximum nominal speed ratio allowed by the system (corresponding to 100% feed rate); This indicates the minimum speed ratio required for the system to maintain interpolation synchronization across all axes, preventing servo lockout or control flow interruption due to speed dropping to zero.

[0083] Through the processes described in S204 to S206, this invention constructs a digital filter with inertial characteristics at the FPGA hardware level. Regardless of the interruption of the data stream from the host computer 100, the speed command ultimately applied to the motor always follows a preset acceleration / deceleration curve, effectively suppressing mechanical shocks to the equipment caused by communication jitter. This is the execution scaling factor ultimately used to adjust the system time base.

[0084] The final execution scaling factor is generated after the aforementioned smoothing and filtering process. Then, the FPGA logic module 240 distributes it in parallel to the pulse generation units 245 of each axis and the spindle control unit 244.

[0085] The control strategy in this embodiment is based on the precision machining principle of constant feed per tooth. During CNC cutting, the feed per tooth of the tool... The cutting load and surface roughness are determined by the following formula: (in For feed rate, Main spindle speed (Number of cutting teeth). When the system must reduce the feed rate due to insufficient cached data. At that time, if the spindle speed If it remains unchanged, it will lead to A sharp drop in speed results in a scratching effect rather than effective cutting, leading to rapid tool wear (tool burning) and workpiece surface hardening. Therefore, this invention establishes a rigid coupling mechanism between the feed axis and the spindle through FPGA hardware logic, ensuring that they operate strictly in the same proportion. Synchronization modulation is performed. The specific implementation process includes the following steps: S207: Pulse modulation and remainder compensation of feed axis interpolation data. Each axis pulse generation unit 245 receives raw position increment data from the CNC machining control unit 243. ( Represents the axis number (unit: encoder feedback pulse equivalent). A scaling factor is introduced. Subsequently, the pulse generation logic does not perform simple frequency multiplication, but instead executes high-precision pulse allocation operations that include remainder compensation: First, calculate the theoretical scaling increment. : ; in, This represents the theoretical position increment after time scaling. This value usually includes a decimal part and represents the physical displacement requirement under ideal conditions. This indicates the number of data points parsed from the interpolated data packet within the current control cycle. Original position increment of axis (integer); Indicates the current control cycle The corresponding global execution scaling factor.

[0086] because The result is usually a decimal. Including integer part and decimal part To prevent the cumulative position error (i.e., "missed steps") caused by directly discarding the decimal part, each axis pulse generation unit 245 internally maintains a 32-bit remainder accumulator register. .

[0087] Secondly, perform the accumulation and carry judgment: ; when At that time, a carry pulse is generated. At the same time, update the remainder register. ;otherwise .

[0088] Ultimately, the actual number of output pulses in the current control cycle. for: ; in, and These represent the minute displacement residual values ​​stored in the remainder accumulation register between the current time and the previous time, respectively; express The integer part of the value is the basic number of pulses that can be directly output in the current cycle. express The fractional part, i.e. the subpulse quantity that cannot be directly output in the current cycle due to resolution limitations; This represents the carry compensation value, which is 1 when the accumulated subpulse quantity reaches the equivalent of one pulse, and 0 otherwise; This represents the actual integer pulse command that is ultimately sent to the servo driver.

[0089] The algorithm is mathematically equivalent to digital differential analyzer (DDA) logic, ensuring performance even at extremely low scaling speeds (such as...). Under the condition that all the small displacements that are not output are temporarily stored in the accumulator, and are immediately compensated and output after accumulating a pulse equivalent, thus ensuring that the geometric accuracy of the machining trajectory is completely consistent with the original code.

[0090] Furthermore, before finally generating the physical level signal, each axis pulse generation unit 245 performs a physical layer security check. The module reads the driver pulse frequency limit parameter (Flimit) and pulse width limit parameter (Twidth) pre-configured in the register. The logic circuit limits the calculated instantaneous pulse frequency to ensure that it does not exceed the maximum receiving frequency of the servo driver; at the same time, when generating the pulse waveform, it ensures that the high-level duration is greater than Twidth (e.g., 2µs) to match the minimum conduction time of the optocoupler isolation circuit and prevent the driver from losing steps due to the pulse being too narrow.

[0091] S208: Modulation of spindle speed command. The spindle control unit 244 adopts different modulation strategies according to the current machining mode: In general cutting mode, the spindle control unit 244 receives the target speed set by the host computer 100. (RPM), and calculate the actual output speed command by combining it with the scaling factor: ; in, Indicates the current control cycle The actual speed command output to the spindle driver, which dynamically follows the system's adjustment cycle; This indicates the nominal target speed (RPM) set by the host computer 100 according to the machining process. This represents the global execution scaling factor generated by the aforementioned steps, thereby achieving synchronous proportional adjustment of the spindle speed and feed rate to ensure a constant cutting speed.

[0092] This command drives the spindle motor via a D / A converter or PWM generator, causing its speed to decrease synchronously with the feed rate.

[0093] In rigid tapping mode, to strictly guarantee the tap pitch, the spindle control unit 244 automatically switches to position servo mode (C-axis mode). At this time, the spindle no longer acts as a simple speed source, but participates in system linkage as a rotary interpolation axis. Its control logic switches to executing the pulse modulation and remainder compensation process described in step S207, that is, directly adjusting the spindle's rotation angle increment. The scaling mechanism ensures that the spindle rotation angle remains constant throughout the tap insertion and withdrawal process. With Z-axis feed displacement Always strictly satisfy the lead relationship ; in, It represents the linear displacement of the Z-axis (feed axis) during rigid tapping; This indicates the pitch parameter of the tap currently in use, which is the theoretical feed distance along the Z-axis when the spindle rotates one revolution; This indicates the cumulative rotation angle of the spindle (which is used as a servo axis in this case) in radians. This represents the circumference constant, used to convert rotation angles into the number of rotations.

[0094] Even if the system slows down to near a standstill due to data interruption, no thread breakage or tap breakage will occur.

[0095] S209: Global synchronization latch for the entire system time base. To eliminate clock skew caused by multi-channel parallel processing within the FPGA and to prevent instantaneous speed direction deviation due to slight differences in the timing of scaling factor readings of each axis, the system employs a global synchronization mechanism.

[0096] The FPGA logic module 240 internally incorporates a high-fan-out, low-latency global write enable signal line (GlobalUpdate Strobe). At the start clock edge of each interpolation cycle, this signal line simultaneously triggers the shadow registers of the axis pulse generation units 245, the spindle control unit 244, and the auxiliary function control modules, forcing all modules to update and latch the current data at the same nanosecond interval. value.

[0097] Through the above mechanism, the system achieves precise control over the time dimension of the processing at the physical level, ensuring that at any instant... feed rate With spindle speed The ratio is constant: ; in, and Representing time respectively The instantaneous combined feed rate and actual spindle speed actually executed by the machine tool; and These represent the nominal feed rate and nominal spindle speed originally set in the CNC program (NC code); This represents the execution time scaling factor that enables simultaneous activation across the entire system at the current moment. The constant ratio represents a constant ratio. Its physical meaning is to prove that even if the system operating speed changes due to data buffer fluctuations, the core process parameters such as feed per revolution or cutting pitch remain unchanged and do not change with the speed of the overall operating cycle.

[0098] This enables the distributed CNC system of the present invention to exhibit the characteristic of adaptive speed change with equal process parameters when dealing with non-real-time communication jitter, fundamentally solving the impact of heterogeneous clock domain synchronization problem on machining quality.

[0099] In a heterogeneous computing architecture, the host computer 100 (x86 architecture) and the slave computer 200 (SOC / FPGA architecture) are each provided with a clock reference by an independent crystal oscillator. Due to manufacturing process errors and temperature drift characteristics of the crystal oscillator, an inherent frequency deviation (typically between 10ppm and 100ppm) inevitably exists between the two clock domains. This minute deviation, accumulated over a long period, can cause unexpected "steep" rises or falls in the cache level of the slave computer 200, ultimately leading to data overflow or readout. To address this, the system constructs a statistically based clock drift observer on the ARM processor side to reconstruct the relative rate relationship between the two clock domains from discrete data packet arrival events. The specific implementation process includes the following steps: S301: Definition of observed variables and construction of sampling space. The system defines two dimensions of time measurement: Physical Time and Logical Time.

[0100] Physical Time This refers to the elapsed time recorded by the local high monotonicity hardware timer of the lower-level machine (200), serving as the absolute benchmark for observation. This embodiment utilizes the 64-bit system counter integrated within the ARM processor (e.g., Cortex-A53) to obtain its frequency. This is a fixed value (e.g., 25MHz). Using a 64-bit counter ensures that the system can operate continuously for years without numerical overflow or wraparound.

[0101] Logical time This refers to the theoretical time span contained in the motion command data sent by the host computer 100. In the equal-period interpolation mode, each interpolation data packet represents a fixed time increment. (For example, 1ms), the logical time is strictly proportional to the cumulative number of data packets received.

[0102] To enable effective observation, the ARM processor allocates a circular sampling queue in memory. Used to store the most recent The number of observation pairs. Window size. The value of M determines the frequency response characteristics of the observer: the larger the value of M, the stronger the ability to suppress noise interference generated by PCIe bus jitter during clock drift estimation, thus enabling more accurate convergence to the true frequency difference, but the slower the response to dynamic changes in clock frequency. In this embodiment, The optimal setting is 500 to 2000, corresponding to an observation period of approximately 0.5 to 2 seconds, to filter out non-periodic transmission delays caused by operating system scheduling.

[0103] S302: Atomic sampling of data packet arrival events. A synchronous sampling operation is performed whenever the XDMA controller completes writing a set of data packets and triggers a completion interrupt, or during the ARM processor's periodic polling task. This involves simultaneously reading and recording the current local physical time value and the total amount of data received as a pair, ensuring a strict temporal correspondence between the timestamp and the data volume, and preventing data mismatches caused by the order in which data is read.

[0104] The sampling process is as follows: 1. Read the total received packet count register (Total Byte Count / PacketSize) in the DMA controller to obtain the current total received packet count. .

[0105] 2. Within the same critical section, immediately read the current system physical counters. .

[0106] 3. Calculate the current physical time and logical timestamp using the following formula: ; ; in, Indicates the first The absolute physical time of the system (in seconds) calculated at the next sampling time; Indicates the first The raw count value of the underlying hardware system counter read at the next sampling time; This indicates the fixed operating clock frequency (in Hz) of the system counter, used to convert the count value into a standard time unit; Indicates the first The logical time corresponding to the next sampling moment is the theoretical elapsed time based on the cumulative data transmission volume; Indicates up to the number At each sampling time, the DMA controller counts the total number of valid interpolated data packets received. This represents the nominal time increment (i.e., the interpolation period, for example, 0.001s) represented by a single interpolated data packet.

[0107] 4. Pairs Push into sampling queue If the queue is full, the oldest data will be overwritten.

[0108] S303: Differential estimation of the frequency ratio. To accurately calculate the frequency deviation of the host computer's 100 clock relative to the slave computer's 200 clock, the observation model calculates the ratio of the average rate of change of physical time to logical time within a sliding window.

[0109] Assume the actual clock frequency of the host computer 100 is... The nominal frequency of the lower-level machine is 200. Define the frequency difference ratio. This is the ratio of the two. This embodiment uses the long baseline difference estimation algorithm, selecting the latest time point within the sampling window. and the oldest moment The sample points are calculated using the following formula: ; Substituting the original variables, the calculation formula becomes: ; in, Indicates at time The estimated clock frequency difference ratio reflects how fast the upper computer's 100 logic clock elapses relative to the lower computer's 200 physical clock. and These represent the logical timestamps corresponding to the latest and oldest timestamps in the sliding sampling window, respectively. and These represent the physical timestamps corresponding to the latest and oldest timestamps in the sliding sampling window, respectively. This represents the cumulative increment of interpolated data packets actually received by the lower-level machine 200 within the observation window span; This represents the nominal logical time increment represented by a single interpolated data packet; This represents the increment of the number of clock cycles actually traversed by the hardware counter of the lower-level 200 system within the observation window span; This indicates the inherent operating frequency of the lower-level machine 200 hardware counter, used to convert the hardware count value into standard seconds. This represents the sampling depth of the sliding observation window, which is the time span (number of samples) between two sample points involved in the difference calculation.

[0110] The physical meaning of this formula is: 200 seconds have passed in the lower-level machine. Within the physical duration of one clock cycle, the host computer 100 actually generated Business data for each period. If... A value of 1 indicates that the host computer's clock speed is too fast, and the data transmission rate is higher than the local consumption rate; conversely, a value of 1 indicates that the host computer's clock speed is too slow.

[0111] S304: Filtering and Confidence Determination for Drift Trends. Original Calculated Values It may still contain noise caused by communication fluctuations or system nondeterministic delays. The system first calculates the relative deviation of the frequency difference ratio. : ; in, It represents the absolute deviation of the frequency difference ratio at the current sampling time from the ideal value, and is used to measure the severity of clock drift; This represents the estimated instantaneous frequency difference ratio obtained by long-baseline differential calculation in the aforementioned steps; This represents the nominal ratio when the clocks of the host computer 100 and the slave computer 200 are perfectly synchronized under ideal conditions. This indicates that the absolute value operation is performed to ensure that the deviation is non-negative regardless of whether the clock is fast or slow, so that it can be compared with the dead zone threshold.

[0112] The system presets an effective observation dead zone threshold. (Usually the value is taken as) That is, 2ppm, which is slightly larger than the short-time jitter variance of the crystal oscillator. like Determine that the current system clock is basically synchronized, and force output. To avoid introducing fluctuations due to excessive adjustments.

[0113] like If this is the case, then a valid clock drift has been detected. At this point, [the following will occur]. The input is smoothed by a first-order infinite impulse response (IIR) low-pass filter to obtain the final compensation coefficients. : ; in, This represents the final clock compensation coefficient used for the current control cycle after low-pass filtering and smoothing. This represents the historical state value of the compensation coefficient calculated in the previous control cycle; This represents the noisy instantaneous frequency difference observation value input at the current moment; This is a smoothing factor, with a value range of (0, 1). In this embodiment... The value is set to a small value (e.g., 0.01) to achieve a larger time constant, ensuring that the output compensation coefficient reflects the long-term temperature drift trend of the crystal oscillator rather than instantaneous jitter.

[0114] Through the above observation model, this invention can quantify the relative rate deviation between heterogeneous clock domains using only the time characteristics of the service data stream itself, without the need for IEEE1588 hardware stamping support, thus providing accurate numerical basis for subsequent precision frequency compensation.

[0115] The smoothed clock frequency offset ratio was obtained through the observation model. Then, the ARM processor executes the clock synchronization control algorithm.

[0116] The control architecture of this embodiment is essentially a software-defined digital phase-locked loop (PLL). This control loop includes a frequency feedforward path and a phase feedback path: the frequency feedforward path uses the observed frequency difference ratio to quickly match the physical time elapse rate of the upper and lower computer 200; the phase feedback path uses the deviation of the buffer level for fine-tuning to eliminate accumulated phase errors during long-term operation. The algorithm ultimately calculates the reload value used to correct the hardware timer of the lower computer 200, so that the physical time base of the lower computer 200 dynamically follows the logical time base of the upper computer 100. The specific implementation process includes the following steps: S305: Synthesis of composite control variables. To achieve zero steady-state error synchronous control, the ARM processor first samples the current average cache water level. This value represents the real-time water level within the most recent control cycle (e.g., 1 second). The arithmetic mean is used instead of the instantaneous value to filter out high-frequency noise in the water level caused by PCIE packet arrival jitter.

[0117] Subsequently, the system constructs a composite adjustment ratio. The calculation formula is as follows: ; in, This represents the total adjustment ratio after synthesis. This parameter will be used as the final correction coefficient to apply to the hardware timer of the lower-level machine 200. This is the feedforward control term, specifically the compensation coefficient output in step S304 that reflects the inherent frequency difference between the upper and lower computer clocks (if...). This indicates that the clock speed of the host computer 100 is too fast, and the timing period of the slave computer 200 needs to be shortened proportionally to achieve acceleration. The second item is the proportional feedback item, which is used to stabilize the buffer level at the ideal value; This is the proportional gain coefficient of the position loop (water level loop), used to adjust the response intensity to water level deviations; This represents the smoothed average cache level during the current control cycle; This represents the set ideal balance level (usually the total cache capacity). The water level is set to 50% to 80%, and preferably to be greater than or equal to the safety water level threshold in the aforementioned embodiments, to ensure that the system operates at full speed in a steady state. This indicates the total capacity of the FPGA-side data buffer (unit: number of data packets or bytes), used to normalize the water level deviation.

[0118] This is the position loop gain coefficient. Its value is determined based on the system's closed-loop time constant. Confirmed, the formula is: .

[0119] in, The closed-loop regulation time constant (unit: seconds) of the system design determines how quickly the system can eliminate water level deviations. This represents the overall system error normalization factor or unit conversion coefficient, ensuring dimensional consistency in gain calculations. generally Set as to The magnitude (corresponding to an adjustment time constant of approximately 100 to 1000 seconds). Select an extremely small value. The value is to ensure that the water level adjustment process is extremely smooth, and to avoid perceptible fluctuations in the feed rate due to excessively fast adjustment.

[0120] S306: Hardware reload counter calculation and residual compensation. The FPGA's internal interpolation timer is based on the system clock. A down-counter driven by [the system]. Assume the nominal interpolation period is [value]. (e.g., 1ms), then the nominal count value .

[0121] In order to achieve To adjust the required rate, the ARM processor first calculates the theoretical target count value. (Floating-point number): ; in, This indicates the precise timer count value (including the decimal part) that should theoretically be set for the current control cycle in order to match the clock rhythm of the host computer (100). This represents the system clock count constant corresponding to a single interpolation cycle under standard conditions without any frequency adjustments. This represents the composite regulation ratio synthesized from the aforementioned steps, which includes clock frequency difference compensation and water level regulation.

[0122] Since FPGA hardware counters only accept integer inputs, if directly... Rounding introduces quantization error. For example, when... At that time, the quantization error of one count is approximately (i.e., 20ppm), which may be greater than the amount of crystal oscillator drift that needs to be compensated (typically <10ppm). Therefore, this embodiment introduces a "Residual Accumulation" mechanism (also known as time-domain jitter technology) at the software layer: definition The integer part after rounding. This represents the decimal residual.

[0123] ; Update the cumulative residual value for the current period: ; The integer to be written to the hardware is determined by the accumulated value. : like ,but Simultaneously update ; like ,but ,Keep constant.

[0124] in, This represents the base integer count value obtained by rounding down the theoretical count value. This indicates the floor function; and These represent the tiny time residuals accumulated between the current cycle and the previous cycle that have not yet been executed by the hardware (i.e., the integral of the quantization error). This represents the actual integer value that is ultimately written into the FPGA timer reload register.

[0125] Through this dynamic adjustment over multiple interpolation cycles or By using a counting method, the system can overcome the resolution limitations of hardware clock frequency by using an average value, achieving high-precision synchronization at the sub-microsecond level.

[0126] In addition, the system implements safety limiting logic. A maximum permissible adjustment range is preset. (For example If the calculated adjustment exceeds this range, a forced clamp is applied, and a clock source anomaly alarm is reported to prevent drastic changes in the physical operating cycle due to errors in the observed data.

[0127] S307: Bus write and shadow register update. Calculation completed. Write to the FPGA's Period Reload Register via the AXI-Lite bus.

[0128] This represents the final hardware timer reload integer value calculated in the aforementioned step S306, which includes clock frequency difference compensation and residual jitter adjustment. This value directly determines the physical duration of the next interpolation cycle.

[0129] The timer logic on the FPGA side uses a shadow register mechanism to receive this value. That is, a write operation does not immediately change the current count value; the hardware only loads the new value from the shadow register into the main counter when the current interpolation cycle count decreases to 0 and a TerminalCount signal is generated. This mechanism ensures that the adjustment of the time base period is strictly aligned with the interpolation boundary, ensuring the integrity of the currently executing pulse sequence and preventing timing errors or pulse truncation caused by asynchronous timer modifications.

[0130] Through the above processing, this invention establishes a dynamic time base tracking mechanism. The lower-level machine 200 fine-tunes its own physical definition to maintain strict synchronization with the logical time of the upper-level machine 100 in a statistical sense. This mechanism effectively suppresses the unidirectional drift of the buffer level caused by crystal oscillator frequency differences between heterogeneous clock domains, ensuring that the circular buffer operates stably at a preset ideal equilibrium level for a long period. nearby.

[0131] Due to the ideal equilibrium water level during system configuration. Set to a water level threshold greater than the safe water level threshold in the aforementioned embodiments. (For example ,and Therefore, under normal clock synchronization adjustment conditions, the real-time water level... Always maintain The safe zone above. Based on the mapping logic of step S202, the time scaling factor at this point... The value is kept constant at 1.0. This means that the system maintains supply and demand balance only by fine-tuning the hardware clock frequency, effectively preventing the system from falling into a slump. The linear adjustment zone triggers time scaling protection, thus ensuring the stability and surface quality of the CNC machining process without interrupting data.

[0132] After adjusting the hardware timer period of the lower-level machine 200 using the clock drift compensation mechanism in the aforementioned embodiment, although the stability problem of the buffer water level is solved, it will have a coupling effect on the processing speed.

[0133] The compensation principle in this embodiment is based on the principle of velocity consistency. According to the kinematic formula... When the processing command speed When constant, displacement increment With time cycle Proportional. In the aforementioned steps, in order to synchronize the clock, the physical execution cycle of the lower-level machine 200... Dynamically adjusted (no longer constant equal to the nominal period) If the interpolation step size sent by the host computer 100 If it remains unchanged, then the actual processing speed Deviations will occur. Therefore, this embodiment introduces a step-size predistortion strategy in the host computer's 100 interpolation operation layer, adjusting the transmitted step size in reverse. Offset time period The speed error caused by the change. The specific implementation process includes the following steps: S308: Reverse feedback and low-frequency update of drift parameters. The ARM processor uses the clock compensation coefficients calculated and smoothed in step S304. The data is fed back to the host computer 100 via the PCIe bus.

[0134] To ensure data security, the ARM processor writes the floating-point coefficient to a dedicated shared mailbox register in the PCIeBAR space and triggers a Message Signal Interrupt (MSI). The host computer's driver reads the coefficient in its interrupt service routine (ISR).

[0135] Considering that crystal oscillator frequency drift is mainly caused by temperature changes, which is a slow process (the rate of change is usually less than 100°C), The host computer 100 does not need to read this hardware register in every interpolation cycle. In this embodiment, the update cycle is set to... (For example, 100ms to 500ms), meaning the host computer 100 only periodically obtains the latest information from the driver layer. The value is then updated to the global variable area of ​​the CNC kernel. This low-frequency update strategy effectively reduces the communication load on the PCIe bus and is sufficient to track the trend of thermal drift.

[0136] S309: Predistortion factor calculation under constant speed constraint. Before calculating the displacement increment of each axis, the host computer 100 interpolator reads the latest clock compensation coefficient and calculates the predistortion scaling factor n[k]. Based on the adjustment logic of the lower-level computer 200 hardware timer, its actual physical cycle... It is necessary to make reverse adjustments based on the clock frequency difference to match the rhythm of the host computer. The relationship is as follows: ; To ensure actual execution speed Equal to instruction speed The following conditions must be met: ; in: This indicates the actual physical interpolation cycle duration (in seconds) generated after the lower-level FPGA dynamically adjusts the hardware reload value according to the clock drift compensation requirements. This indicates the system's preset standard interpolation period duration (e.g., 1ms), which is the physical period under ideal conditions with no frequency difference. The clock frequency difference ratio (compensation coefficient) calculated in the preceding steps reflects the speed ratio of the host computer 100 clock relative to the slave computer 200 clock. This represents the physical composite speed of the machine tool's actual operation. This indicates the target speed command set in the CNC machining program (G-code); This indicates the theoretical position increment step size that the host computer 100 should send after pre-distortion processing in order to adapt to the physical time changes of the slave computer 200.

[0137] Will Substituting into the above formula, we can obtain the target transmission step size after predistortion. : ; Therefore, the predistortion scaling factor is defined.

[0138] ; in, This represents the predistortion scaling factor used in the current interpolation cycle, which is used to perform reverse compensation for the position increment at the data source generated by the host computer 100. This formula explicitly states that if the clock of the host computer 100 is observed to be too fast ( This causes the lower-level machine 200 to shorten the physical cycle (run faster) to maintain synchronization. Therefore, the upper-level machine 100 should proportionally reduce the step size of the transmission (run even shorter), that is, use a coefficient less than 1 for correction, so as to ensure that the ratio of "distance / time" (i.e. speed) remains constant and to offset the change in physical speed caused by the lower-level machine adjusting the interpolation period timer.

[0139] S310: Independent pre-distortion processing for interpolation step size. In the CNC interpolation calculation stage, the system first determines the pre-distortion based on the instruction speed. and nominal period Calculate the original theoretical step size for each linkage axis (X, Y, Z, etc.). ( (Axis index).

[0140] Subsequently, a predistortion factor is applied for correction: ; in, Indicates the first The interpolation period is adjusted to compensate for the speed change caused by the 200-second time base adjustment of the lower-level machine. The axis should execute a high-precision floating-point position increment after pre-distortion correction; Indicates the speed according to CNC commands and nominal interpolation period The calculated original theoretical position increment (i.e. = × ); This indicates that the predistortion scaling factor calculated in step S309 is used to compensate for the speed scaling effect caused by the clock frequency difference at the source.

[0141] In the case of floating-point type When converting to integer pulse equivalents sent to the FPGA, to prevent inter-axis trajectory deviation due to long-term truncation errors, the system maintains an independent double-precision floating-point remainder accumulator for each linkage axis. .

[0142] The specific quantification formula is as follows: ; ; ; in, This represents the total number of target pulses in the current period after incorporating historical accumulated errors (floating-point number). Indicates the first The axis in the previous cycle The fractional residuals retained after rounding operations; Indicates to Perform rounding ( The result (after rounding down) is the actual data packet encapsulated and sent to the lower-level machine 200. Integer position increment of axis; This represents the remainder after the current period update; this value will be stored in [the database / store]. The axis-specific accumulator participates in the calculation of the next cycle.

[0143] Through this mechanism of independent accumulation for each axis, the system ensures that the interpolation straightness or circular profile accuracy between axes is not affected by quantization noise when scaling all axes to a uniform time / step.

[0144] Through the above processing, this invention constructs a dual closed-loop architecture where the bottom layer adjusts the time base to ensure buffering, and the upper layer adjusts the step size to ensure speed. This architecture successfully decouples the requirements of communication synchronization and motion control, enabling the distributed CNC system to achieve non-destructive control of machining dimensions and surface quality while correcting heterogeneous clock domain drift.

Claims

1. A distributed numerical control system based on PC and SOC, characterized in that, It includes a host computer (100), a slave computer (200), and a PCIe communication link (300) connecting the two for data transmission. The host computer (100) is configured to generate motion command data containing position increment information and write the motion command data to the slave computer (200) through the PCIE communication link (300). The lower-level machine (200) adopts a system-on-a-chip (SoC) architecture and integrates an FPGA logic module (240), an ARM processor module (250), and a DDR memory module (220). The lower-level machine (200) is connected to the PCIE communication link (300) through an XDMA communication module (210), and the XDMA communication module (210) is connected to the DDR memory module (220) and the FPGA logic module (240) through an AXI interconnect bus (230). The DDR storage module (220) is equipped with a ring buffer for receiving and storing the motion instruction data written by the host computer (100); The FPGA logic module (240) integrates a CNC machining control unit (243). The CNC machining control unit (243) is configured to read the motion command data from the circular buffer and calculate the current effective data level of the circular buffer in real time. The CNC machining control unit (243) dynamically generates a time scaling factor based on the current effective data level and uses the time scaling factor to modulate the execution speed of the motion command data in real time.

2. The distributed CNC system based on PC and SOC according to claim 1, characterized in that, The host computer (100) includes a numerical control processing module (110), a machine tool control module (120), and a PCIE device driver library (130). The numerical control processing module (110) is configured to parse and interpolate the input G-code trajectory file to generate the motion command data; The machine tool control module (120) is configured to process weak real-time logic control commands; The PCIE device driver library (130) is configured to call the XDMA driver interface to perform data writing; The AXI interconnect bus (230) includes an AXI-MM memory-mapped channel and an AXI-Lite lightweight channel; The motion command data is directly written to the DDR memory module (220) via the AXI-MM memory mapping channel. The logic control commands sent by the machine tool control module (120) are transmitted via the AXI-Lite lightweight channel to the AXI to Local Bus conversion unit (242) in the FPGA logic module (240), and then access the functional subunits mounted on the LocalBus communication bus (241).

3. The distributed CNC system based on PC and SOC according to claim 1, characterized in that, The circular cache is built on the physical linear address space of the DDR memory module (220) and manages the data flow through write pointer variables and read pointer variables; The host computer (100) maintains the write pointer variable, calculates the target write physical address based on the write pointer variable, updates the write pointer variable after completing the data writing, and writes the updated value into the write pointer register of the FPGA logic module (240). The CNC machining control unit (243) maintains the read pointer variable, calculates the source read physical address based on the read pointer variable, and updates the read pointer variable after completing the data reading. The updates to both the write pointer variable and the read pointer variable follow the modulo operation rules to achieve address looping.

4. The distributed CNC system based on PC and SOC according to claim 3, characterized in that, The CNC machining control unit (243) reads the value of the write pointer register and the current value of the read pointer variable in each system clock cycle, and calculates the current valid data level through segmented logic: When the value of the write pointer register is greater than or equal to the current value of the read pointer variable, the current valid data level is the difference between the two. When the value of the write pointer register is less than the current value of the read pointer variable, it is determined that the write pointer has wrapped around. The current valid data level is the total capacity of the circular buffer minus the current value of the read pointer variable, plus the value of the write pointer register.

5. The distributed CNC system based on PC and SOC according to claim 1, characterized in that, The CNC machining control unit (243) is pre-set with a safe water level threshold, an alarm water level threshold, and a minimum speed scaling factor; the CNC machining control unit (243) calculates the target time scaling factor based on a piecewise mapping function: When the current valid data level is greater than the safe data level threshold, the target time scaling factor is 1; When the current effective data level is between the alarm level threshold and the safe level threshold, the target time scaling factor is linearly positively correlated with the current effective data level, and the value of the target time scaling factor varies between the minimum speed scaling factor and 1. When the current valid data level is less than or equal to the alarm level threshold, the target time scaling factor remains the minimum speed scaling factor.

6. The distributed CNC system based on PC and SOC according to claim 5, characterized in that, The CNC machining control unit (243) is also configured to perform a smoothing filter based on a rate-limited variable on the target time scaling factor to generate the final execution scaling factor. The smoothing filtering process includes: Calculate the original deviation between the target time scaling factor and the execution scaling factor output at the previous time step; Determine whether the absolute value of the original deviation exceeds the preset maximum step increment to determine the effective deviation of the current cycle; If the deviation exceeds the limit, the original deviation is limited using the maximum step increment to obtain the effective deviation. If the deviation is not exceeded, the original deviation is directly taken as the effective deviation. The effective deviation is accumulated to the execution scaling factor output at the previous time step to obtain the execution scaling factor at the current time step.

7. The distributed CNC system based on PC and SOC according to claim 6, characterized in that, The FPGA logic module (240) also integrates a spindle control unit (244) and a pulse generation unit (245) for each axis. The pulse generation unit (245) of each axis performs scaling calculation and remainder compensation accumulation on the position increment in the motion command data according to the execution scaling factor to generate a pulse signal to drive the servo motor; The spindle control unit (244) synchronously modulates the spindle speed command according to the execution scaling factor; The spindle control unit (244) and the axis pulse generation unit (245) latch the execution scaling factor at the same time through a global synchronization signal line to maintain the synchronous proportional change of the feed rate and the spindle speed.

8. The distributed CNC system based on PC and SOC according to claim 1, characterized in that, The ARM processor module (250) is configured to run a clock drift observation process that mainly includes the following steps: Physical time is obtained by reading the hardware system counter of the lower-level machine (200), and logical time is obtained by counting the cumulative number of data packets received by the XDMA communication module (210). Within the sliding sampling window, the change in physical time and the change in logical time are calculated to obtain the clock frequency difference ratio of the host computer (100) relative to the slave computer (200). The clock frequency difference ratio is subjected to low-pass filtering to obtain a smoothed clock compensation coefficient.

9. The distributed CNC system based on PC and SOC according to claim 8, characterized in that, The system also performs lower-level machine time base synchronization control; The ARM processor module (250) calculates the composite adjustment ratio by combining the clock compensation coefficient and the deviation of the current effective data level from the ideal equilibrium level; The ARM processor module (250) calculates the reload value of the lower-level hardware timer according to the composite adjustment ratio and writes the reload value into the FPGA logic module (240). The FPGA logic module (240) dynamically adjusts the counting period of the interpolation period timer according to the overload value, so that the physical clock elapse rate of the lower-level machine (200) follows the logic clock of the upper-level machine (100).

10. The distributed CNC system based on PC and SOC according to claim 9, characterized in that, The system also performs host computer speed consistency compensation; The host computer (100) reads the clock compensation coefficient through the PCIE communication link (300) and calculates the predistortion scaling factor, which is inversely proportional to the clock compensation coefficient. When the host computer (100) generates the motion command data by performing interpolation calculations, it uses the predistortion scaling factor to correct the theoretical position increment of each axis in order to offset the physical velocity change caused by the lower computer (200) adjusting the interpolation period timer.

Images