A multi-screen display synchronous display optimization method

Abstract

The application discloses a kind of multi-screen display synchronous display optimization methods.This method includes: obtaining the extended display identification data of each display and timing parameter;Based on the actual time stamp of the vertical synchronization signal of each display clock monitor, construct timing drift characteristic model;Select timing reference source or generate virtual reference clock;Delay compensation instruction is inserted in GPU rendering command stream, and the scanning start offset address of the frame buffer of secondary display is adjusted dynamically, and the physical clock phase difference between each display is compensated.In addition, for the mixed refresh rate scene, a proactive double buffering queue is established, and a complete frame is selectively output based on the tear risk index.The application can achieve microsecond-level accurate synchronization of multi-screen display at the software level without external Genlock hardware, effectively eliminating the tearing phenomenon caused by heterogeneous screen clock drift and the periodic stutter caused by mixed refresh rate.

Description

Technical Field

[0001] This invention relates to the field of graphics processing and display control technology, specifically to a method for optimizing synchronous display of multiple screens. Background Technology

[0002] With the development of financial transaction monitoring, professional graphics workstations, e-sports live streaming and extended reality applications, connecting a single computer host to multiple heterogeneous monitors (different brands, models, and refresh rates) has become a common hardware deployment.

[0003] However, existing multi-screen display technologies mainly face the following three significant drawbacks:

[0004] 1. Hardware Clock Physical Drift: The crystal oscillator frequencies within each display have an unavoidable physical deviation. Even if the operating system sets all displays to a 60Hz refresh rate, the actual frame scanning cycle still has accumulated errors in the microsecond to millisecond range. The graphics processing unit (GPU) typically sends image frames based only on the main display or a single system clock, causing secondary displays to experience periodic "frame missing" or "frame snatching" due to clock asynchrony. This manifests as noticeable audio-visual desynchronization during cross-screen video playback or visual tearing when dragging windows across screens.

[0005] 2. Uncontrollable Vertical Blanking Delay: Different display interfaces (such as HDMI, DisplayPort, and USB-C) have different link training and transmission encoding mechanisms, resulting in differences in the transmission delay of the vertical blanking period (VBlank) during the process of pixel data traveling from GPU memory to the physical pixels on the screen. Existing technologies mostly rely on expensive Genlock hardware devices to achieve forced phase locking, lacking a low-cost, software-based, and precise compensation method.

[0006] 3. Interference from Mixed Refresh Rates: When a high refresh rate primary screen (e.g., 144Hz) and a low refresh rate secondary screen (e.g., 60Hz) coexist, the Desktop Window Manager (DWM) typically performs frame synthesis based on the primary screen's vertical sync signal. This causes the timing of the image updates sent to the secondary screen to often miss its own scan start point, resulting in periodic stuttering, jittering, or screen tearing that is visible to the naked eye on the secondary screen, severely damaging the user experience.

[0007] Therefore, there is an urgent need for an optimization method that can accurately model the timing differences of display hardware, dynamically compensate for phase deviations through software algorithms, and effectively alleviate interference between mixed refresh rates. Summary of the Invention

[0008] In view of the problems existing in the prior art, the present invention discloses a method for optimizing the synchronous display of multiple screens, comprising the following steps:

[0009] Step 1: In response to the activation of the multi-screen extended display mode, obtain the extended display identification data and corresponding display timing parameters of each connected display. The display timing parameters include at least the nominal refresh rate, pixel clock frequency and vertical blanking period duration.

[0010] Step 2: Based on the graphics processor core clock, continuously monitor and record the actual arrival timestamp of the vertical synchronization signal leading edge of each display in the current operating cycle. Based on the offset between the actual arrival timestamp and the theoretical arrival timestamp, construct an independent timing drift characteristic model for each display.

[0011] Step 3: Select a specified display as the timing reference source, or generate a virtual global reference clock according to a preset algorithm;

[0012] Step 4: In the graphics processor rendering command buffer, for each display except the reference source, insert a delay compensation instruction block. The delay compensation instruction block is used to predict the phase difference of the next frame period according to the timing drift feature model, and dynamically adjust the scan start offset address or pixel clock fine-tuning coefficient of the frame buffer of the sub-display, so that the phase difference between the actual scan line start time of each sub-display and the timing reference source is stabilized within the preset synchronization threshold range.

[0013] As a preferred technical solution of the present invention, the specific process of constructing the time-series drift feature model in step two includes:

[0014] Obtain the actual arrival timestamp sequence of N consecutive vertical synchronization cycles; where N is a natural number greater than 100;

[0015] Calculate the actual cycle length between adjacent cycles and perform a difference fitting with the theoretical cycle length corresponding to the nominal refresh rate;

[0016] The Kalman filter algorithm is used to filter out instantaneous jitter noise in the system bus and extract the inherent frequency drift slope and temperature-related fluctuation residuals of the crystal oscillators of each display.

[0017] As a preferred technical solution of the present invention, the specific process of dynamically adjusting the scan start offset address of the sub-display frame buffer in step four includes: if it is predicted that the scan line start time of the sub-display lags behind the timing reference source, then in the frame buffer allocated for the sub-display in the graphics processor memory, the initial offset of the video memory read pointer is set to a non-zero value, so that the display controller skips the virtual blank line data at the beginning of the frame buffer and enters the reading of the effective video data area in advance to offset the display delay caused by the physical clock lag.

[0018] As a preferred technical solution of the present invention, when the nominal refresh rates of the displays are coprime or differ by an integer multiple, the method further includes hybrid refresh rate smoothing processing, specifically: identifying an active display with a first refresh rate and a passive display with a second refresh rate; establishing a proactive double buffer queue for the passive display; when the vertical synchronization signal of the active display is interrupted, intercepting the current frame image sent to the passive display, and determining the tearing risk index of the frame image in the scanning cycle of the passive display based on the timing drift feature model; if the tearing risk index exceeds a preset threshold, extracting the previous complete rendering frame from the proactive double buffer queue to replace the current frame for transmission, thereby avoiding screen tearing.

[0019] As a preferred embodiment of the present invention, the process of generating a virtual global reference clock in step three includes:

[0020] Step 3.1: Calculate the arithmetic mean of the current actual refresh cycles of all connected displays to generate a virtual Vsync pulse sequence that does not exist in any physical hardware;

[0021] Step 3.2: Drive each display controller to calculate the phase mapping relationship with the virtual Vsync pulse sequence according to its own independent timing drift characteristic model, so as to realize the balanced distribution control of the overall delay of the multi-screen system.

[0022] As a preferred embodiment of the present invention, the display timing parameters further include the transmission line delay constant for each display interface type. The transmission line delay constant is pre-calibrated and stored in the driver configuration file according to the different protocols of HDMI, DisplayPort or USB-C.

[0023] The beneficial effects of this invention are as follows: By constructing a high-precision timing drift characteristic model, this invention achieves software-level prediction and tracking of the independent clock source of each display; by dynamically adjusting the starting offset address of the video memory scan, it achieves microsecond-level phase synchronization without changing the physical hardware clock; and by using a proactive buffer queue and tearing risk assessment, it completely eliminates screen jitter in mixed refresh rate environments. Detailed Implementation

[0024] Example 1

[0025] This invention discloses a method for optimizing synchronized display of multiple screens, comprising the following steps:

[0026] Step 1: In response to the activation of the multi-screen extended display mode, obtain the extended display identification data and corresponding display timing parameters of each connected display. The display timing parameters include at least the nominal refresh rate, pixel clock frequency and vertical blanking period duration.

[0027] Step 2: Based on the graphics processor core clock, continuously monitor and record the actual arrival timestamp of the vertical synchronization signal leading edge of each display in the current operating cycle. Based on the offset between the actual arrival timestamp and the theoretical arrival timestamp, construct an independent timing drift characteristic model for each display.

[0028] Step 3: Select a specified display as the timing reference source, or generate a virtual global reference clock according to a preset algorithm;

[0029] Step 4: In the graphics processor rendering command buffer, for each display except the reference source, insert a delay compensation instruction block. The delay compensation instruction block is used to predict the phase difference of the next frame period according to the timing drift feature model, and dynamically adjust the scan start offset address or pixel clock fine-tuning coefficient of the frame buffer of the sub-display, so that the phase difference between the actual scan line start time of each sub-display and the timing reference source is stabilized within the preset synchronization threshold range.

[0030] Furthermore, when the nominal refresh rates of the various displays are coprime or differ by integer multiples, the method further includes a hybrid refresh rate smoothing step: identifying an active display with a first refresh rate and a passive display with a second refresh rate; establishing a proactive double buffer queue for the passive display; when the active display experiences a vertical synchronization signal interruption, intercepting the current frame image sent to the passive display, and determining the tearing risk index of the frame image in the passive display's scanning cycle based on the timing drift feature model; if the tearing risk index exceeds a preset threshold, extracting the previous complete rendered frame from the proactive double buffer queue to replace the current frame for transmission.

[0031] This method is applied to a computer system connected to two monitors, both with a nominal refresh rate of 60Hz but different brands and models, for phase synchronization of different monitors with the same refresh rate.

[0032] In step one, the operating system loads the display driver and reads the Extended Display Identifier (EDID) data of the two monitors through the DDC / CI channel. The resolution shows that the pixel clock of monitor A is 148.5MHz and the pixel clock of monitor B is 148.3MHz.

[0033] In step two, the driver layer registers the VBLank interrupt callback function. Using the GPU's high-precision performance counter as the time base, the actual timestamps T_A(n) and T_B(n) of each VBLank interrupt occurring for monitors A and B are continuously recorded. After 1000 sampling cycles, the difference sequence between the actual cycle length and the theoretical cycle length (16.667ms) is calculated. A Kalman filter algorithm is used to filter out measurement noise caused by PCIe bus burst delay, extracting the inherent crystal oscillator frequency drift slope of monitor A as +0.003ms / cycle and monitor B as -0.001ms / cycle. Based on this, the timing drift characteristic model is established.

[0034] In step three, display A is selected as the timing reference source.

[0035] In step four, when the driver predicts the arrival of the next frame (the N+1th frame), the VBLank interrupt of display B will lag behind display A by approximately 0.12ms. At this point, directly waiting for the scan lines of display B to return to zero would result in a visually noticeable lag. Therefore, the system modifies the initial offset of the video memory read pointer in the frame buffer descriptor corresponding to display B.

[0036] Example 2

[0037] This embodiment applies to a scenario where the main screen is 144Hz and the secondary screen is 60Hz, addressing anti-jitter processing in a mixed refresh rate environment. In traditional solutions, the secondary screen will exhibit periodic stuttering.

[0038] Based on the phase compensation performed in step four, this embodiment further performs a hybrid refresh rate smoothing process:

[0039] The system identifies monitor A as the main screen (144Hz) and monitor B as the secondary screen (60Hz).

[0040] A proactive double buffer queue is established for the secondary screen, which means that a copy of the image data that has been fully rendered in the previous frame is always retained.

[0041] When the GPU completes a frame of compositing rendering for the full-screen desktop and is ready to submit the image to the display front buffer of the secondary screen, the system calculates the time offset between the current moment and the leading edge of the most recent VBLank signal of the secondary screen.

[0042] If calculations indicate that the secondary screen is in the middle of a valid video data scan when the frame data is sent (i.e., the "tearing risk index" exceeds the threshold), the driver layer intercepts the submission command and forces the extraction of the previous complete frame data from the double buffer queue for repeated display. Since the repeated display is of the complete frame rather than a torn half-frame, and this action occurs within a single refresh cycle (approximately 16.6ms), which is imperceptible to the human eye, the visual stuttering on the 60Hz secondary screen is effectively eliminated, while ensuring that the smoothness of the 144Hz main screen is not affected.

[0043] Components not described in detail in this article are existing technologies.

[0044] While the specific embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention, and modifications or variations without creative effort are still within the protection scope of the present invention.

Claims

1. A method for optimizing synchronized display across multiple screens, characterized in that, The steps include the following: Step 1: In response to the activation of the multi-screen extended display mode, obtain the extended display identification data and corresponding display timing parameters of each connected display. The display timing parameters include at least the nominal refresh rate, pixel clock frequency and vertical blanking period duration. Step 2: Based on the graphics processor core clock, continuously monitor and record the actual arrival timestamp of the vertical synchronization signal leading edge of each display in the current operating cycle. Based on the offset between the actual arrival timestamp and the theoretical arrival timestamp, construct an independent timing drift characteristic model for each display. Step 3: Select a specified display as the timing reference source, or generate a virtual global reference clock according to a preset algorithm; Step 4: In the graphics processor rendering command buffer, for each display except the reference source, insert a delay compensation instruction block. The delay compensation instruction block is used to predict the phase difference of the next frame period according to the timing drift feature model, and dynamically adjust the scan start offset address or pixel clock fine-tuning coefficient of the frame buffer of the sub-display, so that the phase difference between the actual scan line start time of each sub-display and the timing reference source is stabilized within the preset synchronization threshold range.

2. The method for optimizing synchronous display of multiple screens according to claim 1, characterized in that: The specific process of constructing the time-series drift feature model in step two includes: Obtain the actual arrival timestamp sequence of N consecutive vertical synchronization cycles; where N is a natural number greater than 100; Calculate the actual cycle length between adjacent cycles and perform a difference fitting with the theoretical cycle length corresponding to the nominal refresh rate; The Kalman filter algorithm is used to filter out instantaneous jitter noise in the system bus and extract the inherent frequency drift slope and temperature-related fluctuation residuals of the crystal oscillators of each display.

3. The method for optimizing synchronous display of multiple screens according to claim 1, characterized in that: The specific process of dynamically adjusting the scan start offset address of the sub-display frame buffer in step four includes: if it is predicted that the scan line start time of the sub-display lags behind the timing reference source, then in the frame buffer allocated for the sub-display in the graphics processor memory, the initial offset of the video memory read pointer is set to a non-zero value, so that the display controller skips the virtual blank line data at the beginning of the frame buffer and enters the reading of the effective video data area in advance to offset the display delay caused by the physical clock lag.

4. The method for optimizing synchronous display of multiple screens according to claim 1, characterized in that: When the nominal refresh rates of the displays are coprime or differ by integer multiples, the process further includes hybrid refresh rate smoothing, specifically: identifying the active display with a first refresh rate and the passive display with a second refresh rate. A proactive dual buffer queue is established for the passive display; When the vertical synchronization signal of the active display is interrupted, the current frame image sent to the passive display is intercepted, and the tearing risk index of the frame image in the scanning cycle of the passive display is determined based on the time drift feature model. If the tearing risk index exceeds a preset threshold, the previous complete rendered frame is extracted from the proactive double buffer queue to replace the current frame for transmission, thereby avoiding screen tearing.

5. The method for optimizing synchronous display of multiple screens according to claim 1, characterized in that: The process of generating a virtual global reference clock in step three includes: Step 3.1: Calculate the arithmetic mean of the current actual refresh cycles of all connected displays to generate a virtual Vsync pulse sequence that does not exist in any physical hardware; Step 3.2: Drive each display controller to calculate the phase mapping relationship with the virtual Vsync pulse sequence according to its own independent timing drift characteristic model, so as to realize the balanced distribution control of the overall delay of the multi-screen system.

6. The method for optimizing synchronous display of multiple screens according to claim 1, characterized in that: The display timing parameters also include the transmission line delay constant for each display interface type. The transmission line delay constant is pre-calibrated and stored in the driver configuration file according to the different protocols of HDMI, DisplayPort or USB-C.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the multi-screen display synchronization optimization method as described in any one of claims 1 to 6.