A security monitoring method based on VPX architecture

Abstract

The application belongs to the technical field of embedded computers and relates to a safety monitoring method based on a VPX architecture, which is applied to a safety monitoring device, the device comprising a processor, a bridge, a microcontroller MCU, a first level conversion module, a second level conversion module, a management daughter card, a TCM trusted card, a solid state disk SSD, a front panel and a VPX connector; the method comprising the following steps: system power-on timing control; system state monitoring and alarming; hardware watchdog reset control; data security encryption transmission; FRU information management and reporting, the microcontroller MCU reading FRU information stored in EEPROM on the management daughter card through an I2C bus and reporting the FRU information through an IPMB interface in response to a reading request of a backplane management controller. The independent management channel is reliable, and the maintainability and reliability of the system are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of embedded computer technology, and more specifically, to a security monitoring method based on the VPX architecture. Background Technology

[0002] With increasingly stringent requirements for self-reliance and controllability in critical infrastructure and defense equipment, the localization of core electronic equipment has become an inevitable trend. In application scenarios such as radar signal processing, real-time data acquisition and analysis, and security monitoring systems, embedded computers not only need to possess powerful high-speed data processing capabilities, but also need to operate stably for extended periods in harsh environments (such as high and low temperatures, vibration, and strong electromagnetic interference).

[0003] Currently, traditional embedded computer systems face the following technical challenges in security monitoring methods: Reliance on imported core components: Many high-performance computing modules still use foreign processors, posing supply chain security risks and making it difficult to meet compliance requirements for independent control.

[0004] Distributed management functions: The system's status monitoring (such as voltage and temperature), reset control, and power-on / off timing management are usually directly handled by the main processor. Once the main processor software crashes, the entire machine will lose its management capabilities, resulting in low reliability.

[0005] Limited interface and poor scalability: Existing devices often lack standardized architecture design when facing the need for high-speed data interaction (such as multiple gigabit Ethernet ports) and multiple low-speed management interfaces (such as I²C and GPIO), resulting in low system integration and complex wiring.

[0006] Lack of hardware-level trusted security mechanisms: In the process of storing and transmitting critical data, there is a lack of hardware trusted cards based on domestic cryptographic algorithms, which poses a risk of data being tampered with or illegally read.

[0007] Imprecise timing control: Existing methods are not precise enough in controlling the power-on and power-off timing of multiple power supplies, which can easily lead to processor startup failure or device latch-up, affecting system stability. Summary of the Invention

[0008] To address the aforementioned deficiencies in existing technologies, this invention provides a security monitoring method based on a VPX architecture, applied to a security monitoring device. The device includes a processor, a bridge chip, a microcontroller (MCU), a first level conversion module, a second level conversion module, a management daughter card, a TCM trusted card, a solid-state drive (SSD), a front panel, and a VPX connector. The method includes the following steps: S1: System power-on timing control. The microcontroller MCU controls the enable terminal of the onboard power module through the first level conversion module (4) to enable the processor core voltage V sequentially according to the preset timing.core Interface voltage V io and auxiliary voltage V aux ; S2: System status monitoring and alarm. The microcontroller (MCU) periodically collects temperature data T from the temperature sensor on the management daughter card via the I²C bus. sensor The voltage sample value V is obtained by analog-to-digital converter (ADC) sampling. sample Calculate the actual voltage V actual When the alarm LED on the front panel exceeds the preset threshold, it will flash an alarm and send an emergency alarm event to the host computer via the IPMB interface. S3: Hardware watchdog reset control. The microcontroller (MCU) runs an independent watchdog timer. If the preset watchdog cycle is reached... No dog-feed signal received from the processor. feed Then, the first level conversion module (4) outputs a reset signal RST to the processor. CPU Perform a hardware reset; S4: Secure encrypted data transmission. The processor sends the data stream to be encrypted to the TCM trusted card through the bridge chip. The TCM trusted card calls the built-in national cryptographic algorithm to encrypt the data. The encrypted data is then forwarded to the data interaction module for output via the bridge chip. S5: FRU Information Management and Reporting. The microcontroller (MCU) reads the FRU information data stored in the EEPROM on the management daughter card via the I²C bus. FRU It responds to the read request from the backplane management controller via the IPMB interface and reports the FRU information.

[0009] Preferably, the power-on timing control in step S1 further includes the following steps: S11: The microcontroller MCU monitors the processor core voltage V core Good power signal PGOOD core When PGOOD core When =1, it indicates that the core voltage has stabilized; S12: After the first delay T delay1 The microcontroller (MCU) pulls the first enable signal EN high through the first level conversion module. io Enable interface voltage V io ; S13: Voltage V of the microcontroller (MCU) monitoring interface io Good power signal PGOOD io When PGOOD io When =1, it indicates that the interface voltage has stabilized; S14: After the second delay T delay2 The microcontroller (MCU) pulls the second enable signal EN high through the first level conversion module. aux Enable auxiliary voltage V aux Wherein, the first delay T delay1 ≥10ms, the second delay T delay2 ≥5ms is used to ensure that the preceding voltage is fully established without glitches, avoid latch-up effects caused by power supply rising edge contention, and meet the processor's power timing requirements.

[0010] Preferably, the actual voltage V mentioned in step S2 actual Calculate using the following formula: V actual =(V sample ×R divider ) / (ADC ref ), where V sample These are ADC sample values, in volts (V); R divider The voltage divider coefficient of the voltage divider resistor network is dimensionless; ADC ref The reference voltage for the internal ADC of the microcontroller MCU is expressed in volts (V); the voltage divider factor R... divider Determined by the voltage divider resistor network, specifically R divider =(R1+R2) / R2, where R1 is the series voltage divider resistor and R2 is the grounding resistor.

[0011] Preferably, the hardware watchdog reset control in step S3 further includes the following steps: S31: The microcontroller (MCU) starts its internal watchdog timer, setting the watchdog period to T. WDG ; S32: During normal operation, the processor periodically sends a watchdog signal S to the microcontroller MCU. feed The microcontroller (MCU) resets the watchdog timer every time it receives a dog-feeding signal. S33: If the microcontroller MCU is in the watchdog cycle T WDG No dog feeding signal received. feed If so, the system is considered deadlocked; S34: The microcontroller (MCU) outputs a low-level active reset signal RST to the processor (1) through the first level conversion module. CPU Duration T reset Wherein, the watchdog period T WDG The value is set according to system requirements, ranging from 1 second to 60 seconds; the duration T of the reset signal reset ≥200ms ensures a complete reset of the processor and related peripherals.

[0012] Preferably, the secure encrypted data transmission in step S4 further includes the following steps: S41: The processor sends the data stream to be encrypted to the TCM trusted card via the bridge chip; S42: The random number generator inside the TCM trusted card generates the encryption key K. enc The encryption key K enc Stored and used only within the security domain of the TCM trusted card; S43: The TCM trusted card invokes the built-in SM4 algorithm engine, utilizing the encryption key K. enc The data is encrypted to generate ciphertext data; S44: The TCM trusted card forwards the encrypted ciphertext data to the data interaction module via the bridge chip; S45: The data interaction module converts the encrypted data into Ethernet frames and outputs them through the RJ45 interface; wherein, the encryption key K enc It does not transmit data in plaintext through an external bus to prevent physical probe attacks.

[0013] Preferably, the method further includes the step of: S6: System soft reset control. The microcontroller (MCU) receives a soft reset command from the backplane management controller via the IPMB interface. The MCU outputs a reset signal RST through the first level conversion module. CPU The system will be reset, and this reset process will not affect the power supply status.

[0014] Preferably, the voltage monitoring in step S2 includes monitoring the processor core voltage V. core Interface voltage V io Auxiliary voltage V aux and input voltage V in Multi-channel monitoring; when any actual voltage V actual Exceeding the preset voltage threshold range [V] min V max When an abnormal event occurs, the microcontroller (MCU) records the abnormal event and generates an alarm log.

[0015] Preferably, the FRU information Data mentioned in step S5 FRU This includes the board model, serial number, hardware version number, and rated power consumption; the microcontroller (MCU) responds to the backplane management controller's read request via the IPMB interface and reads the data from the EEPROM. FRU Reporting is performed via the IPMB bus.

[0016] Preferably, the method further includes the step of: S7: Front panel status indicator. The microcontroller (MCU) controls the on / off state and flashing frequency of the corresponding power LED, status LED, hard disk LED, alarm LED, network LED, TCM status LED, and TCM alarm LED on the front panel according to the system's power-on state, reset state, SSD read / write state, network connection state, and TCM trusted card health status.

[0017] Preferably, the method further includes: Step S8: Debug information output. The microcontroller (MCU) sends the debug information and system status log to the test serial port on the management sub-card via the UART interface. The test serial port outputs through an RS232 level conversion circuit and is used to obtain underlying operating data during system development and on-site troubleshooting.

[0018] The security monitoring method based on the VPX architecture of the present invention has the following beneficial effects: (1) Fully domestically produced and controllable: The core processor, bridge chip, MCU and Ethernet controller all use domestically produced chips, which eliminates the supply chain security risks from the source and meets the requirements of independent control of national key infrastructure.

[0019] (2) Highly reliable independent management channel: An independent GD32 MCU is used as the BMC to realize out-of-band management. Even if the main processor crashes or the operating system crashes, the BMC can still independently complete voltage and temperature monitoring, remote reset and power-on / off timing control, which greatly improves the maintainability and reliability of the system.

[0020] (3) It has refined timing and reset control: through formulaic timing control logic V core ->V io ->V aux and precise delay parameters (T) delay1 ≥10ms, T delay2 ≥5ms) ensures stable processor startup under complex power conditions, avoiding startup failures caused by timing irregularities; an independent hardware watchdog mechanism (T WDG T reset (≥200ms), effectively preventing system deadlock.

[0021] (4) It has comprehensive status monitoring and alarm: it samples the voltage through ADC and uses the formula V actual =(V sample ×R divider ) / (ADC ref By accurately calculating the actual voltage and combining it with temperature sensor data, real-time monitoring of key system parameters is achieved, and an alarm is immediately triggered when limits are exceeded, effectively preventing device damage.

[0022] (5) Hardware-level data security features: It integrates a TCM trusted card and uses its internal random number generator to generate the encryption key K. enc It uses the SM4 algorithm for data encryption, and the key is only used within the security domain and is not exposed to the external bus, thus realizing end-to-end hardware encryption from data storage to data transmission, effectively resisting software-level virus attacks and physical-level bus eavesdropping.

[0023] (6) Standardized FRU information management: FRU information (Data) stored in EEPROM can be reported via the IPMB interface. FRU It enables automatic identification and management of board assets, facilitating system integration and maintenance.

[0024] (7) It has rich interfaces and powerful expansion capabilities: Based on the 6U VPX standard architecture and combined with the powerful expansion capabilities of the Phytium X100 bridge chip, it provides SATA 3.0, USB 3.0, VGA, serial port and 4 gigabit network ports to meet the needs of high-speed data exchange and diverse peripheral access. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort. The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings: Figure 1 This is a schematic diagram of the security monitoring device structure used in the security monitoring method based on the VPX architecture of this invention; Figure 2 This is a flowchart of the security monitoring method based on the VPX architecture of the present invention.

[0026] In the diagram, 1-processor, 2-bridge chip, 3-microcontroller (MCU), 4-first level conversion module, 5-second level conversion module, 6-management daughter card, 7-TCM trusted card, 8-solid-state drive (SSD), 9-front panel, 10-VPX connector. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0029] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0030] Example 1 This invention provides a security monitoring method based on VPX architecture, which is applied to a security monitoring device. Please refer to [link / reference]. Figure 1 This is a schematic diagram of the security monitoring device structure used in the security monitoring method based on the VPX architecture of this invention. Figure 1 As shown, the device adopts a standard 6U VPX cooling structure design, including a main computing module, a management and control module, a data interaction module, a security encryption module, and a signal conditioning module.

[0031] The device includes: processor 1, bridge chip 2, microcontroller MCU 3, first level conversion module 4, second level conversion module 5, management daughter card 6, TCM trusted card 7, solid-state drive SSD 8, front panel 9, and VPX connector 10.

[0032] Processor 1: Employs a Phytium D2000 8-core CPU. This processor is a high-performance general-purpose processor designed for desktop applications, integrating eight Phytium-developed FTC663 cores with a clock speed of up to 2.3GHz, supporting dual-channel DDR4 memory. It is connected to bridge chip 2 via a PCIe 3.0 x16 bus, serving as the control core for the entire system's high-speed data flow. Processor 1 integrates a memory controller for connecting onboard DDR4 memory chips, ensuring fast read and write of business data.

[0033] Bridge chip 2: Employs the Phytium X100. This bridge chip is a companion chip for Phytium series processors, responsible for converting the processor's high-speed PCIe bus into various low-speed peripheral interfaces. The electrical connection between bridge chip 2 and processor 1 includes the PCIe bus, LPC bus, and SPI bus. Bridge chip 2 connects to the solid-state drive SSD 8 via its built-in SATA controller for storing the operating system and business data; it also outputs USB 3.0 signals to VPX connector 10 and front panel 9 via a USB controller; and it outputs display signals to front panel 9 and VPX connector 10 via a VGA controller.

[0034] Microcontroller MCU 3: Utilizing a domestically produced GD32F103RBT6 as the baseboard management controller (BMC). This MCU is based on an ARM Cortex-M3 core with a 72MHz clock speed, integrating 64KB Flash and 20KB RAM on-chip, and possessing abundant I²C, SPI, UART, and GPIO resources. MCU 3 connects to the first level conversion module 4 and the management daughter card 6 via the I²C bus. The general purpose input / output (GPIO) pins of MCU 3 are connected to the LED indicators on the front panel 9.

[0035] First level conversion module 4: This module uses TI's TXS0108E or a domestically compatible level conversion chip to achieve bidirectional conversion between 3.3V and 1.8V / 5V levels. Its input terminals are connected to the GPIO and I²C interfaces of MCU 3, and its output terminals are connected to the management daughter card 6 and the onboard reset circuit and power timing control circuit.

[0036] Second level conversion module 5: This module has a similar structure to the first level conversion module and is used for level adaptation of the high-speed control signals between the processor 1 and the bridge chip 2. It is connected between some low-speed control pins of the processor 1 and the VPX connector 10.

[0037] Management Daughter Card 6: This daughter card is independent of the main CPU board and connects to the motherboard via a board-to-board connector. Management Daughter Card 6 integrates: Temperature sensor: The DS18B20 digital temperature sensor is used and is mounted near the processor 1 and bridge chip 2. It communicates with the MCU 3 through a single bus interface to collect the temperature of key components in real time with an accuracy of ±0.5℃.

[0038] EEPROM: Uses the 24C02 series, used to store Field Replaceable Unit (FRU) information and device hardware configuration information, via I... 2 The C bus is connected to MCU 3.

[0039] IPMB interface: Used to connect to the intelligent platform management bus of the VPX backplane. MCU 3 receives management commands from the backplane through this interface and reports the status information of this board to the backplane.

[0040] Test serial port: Provides RS232 level conversion circuit for outputting debugging information of MCU 3.

[0041] TCM Trusted Card 7: Employs a trusted cryptographic module compliant with the standards of the State Cryptography Administration. This card connects to bridge chip 2 via an LPC bus or USB bus and integrates a random number generator and an SM2 / SM3 / SM4 algorithm engine, achieving security levels of Level 2 or higher according to national cryptographic standards.

[0042] Data interaction module: The domestic WX1860AL4-B Ethernet controller is used. It is connected to bridge chip 2 through PCIe 2.0 x4 interface to convert the PCIe bus into 4 independent Gigabit Ethernet MAC layers. After passing through the physical layer transceiver (PHY), 4 Gigabit RJ45 network ports are brought out.

[0043] The SSD 8 is a 256GB SATA SSD. The front panel 9 features seven LED indicators. The VPX connector 10 uses a VITA 46.0 standard connector.

[0044] Please see Figure 2 This is a flowchart of the security monitoring method based on the VPX architecture of the present invention. Figure 2 As shown, the security monitoring method based on VPX architecture provided in the first embodiment of the present invention includes the following steps: Step S1: System power-on timing control.

[0045] The purpose of step S1 is to ensure that the processor and all peripherals can start up stably in a strict sequence, avoid latch-up effects caused by power-on edge contention, and meet the strict power timing requirements of the Phytium D2000 processor.

[0046] This step is implemented by the microcontroller MCU 3 controlling the enable pin of the onboard power module through the first level conversion module 4. The input voltage is defined as V. in Typically +12V or +5V, it generates the processor core voltage V through a DC-DC converter. core (Typically around 1.0V), Interface voltage V io (Typically 3.3V or 1.8V), auxiliary voltage V aux (Used for clocking, management, etc., typically 1.2V or 3.3V). The power-on sequence must meet the following conditions: V core ->V in ->V aux .

[0047] In specific implementation, step S1 further includes the following steps: S11: The microcontroller MCU 3 monitors the processor core voltage V. core Good power signal PGOOD core When PGOOD core When =1, it indicates that the core voltage has stabilized.

[0048] S12: After the first delay T delay1 The microcontroller MCU (3) pulls the first enable signal EN high through the first level conversion module (4). io Enable interface voltage V io ; S13: The voltage V of the monitoring interface of the microcontroller MCU (3) io Good power signal PGOOD io When PGOOD io When =1, it indicates that the interface voltage has stabilized; S14: After the second delay T delay2 The microcontroller MCU (3) pulls the second enable signal EN high through the first level conversion module (4). aux Enable auxiliary voltage V aux .

[0049] Among them, T delay1 and T delay2 Set by the MCU 3's internal timer, typically T delay1 ≥10ms, T delay2 ≥5ms. These delays ensure that the preceding voltage is fully established without glitches, avoiding the impact on the power supply caused by simultaneous startup of high-current loads.

[0050] Step S2: System status monitoring and alarms.

[0051] The purpose of step S2 is to monitor the key electrical and thermal parameters of the system in real time, issue timely alarms when abnormalities occur, prevent device damage, and provide data support for fault analysis.

[0052] This step is achieved by the microcontroller MCU 3 periodically acquiring temperature sensor data via the I²C bus and obtaining voltage data through ADC sampling.

[0053] In specific implementation, step S2 further includes the following steps: S21: The microcontroller MCU 3 communicates via I 2 The temperature data T from the temperature sensor on the management daughter card 6 is read via the C bus. sensorThe DS18B20 temperature sensor uses a single-bus protocol, and the MCU 3 communicates via GPIO analog timing, achieving an accuracy of ±0.5℃ in the acquired temperature data.

[0054] S22: The microcontroller MCU 3 samples multiple voltages, including the processor core voltage V, through its internal ADC module. core Interface voltage V io Auxiliary voltage V aux and input voltage V in The voltage sample value V is obtained by sampling. sample .

[0055] S23: The microcontroller MCU 3 calculates the actual voltage V according to the following formula. actual V actual =(V sample ×R divider ) / (ADC ref ), where V sample R represents the ADC sample value, measured in volts (V), which is the actual voltage value measured at the ADC pin. divider R is the voltage divider coefficient of the voltage divider network, dimensionless, determined by the external voltage divider resistor. divider =(R1+R2) / R2, where R1 is the series voltage divider resistor and R2 is the grounding resistor; ADC ref This is the reference voltage for the internal ADC of the microcontroller MCU3, typically 3.3V, measured in volts (V). The purpose of this formula is to restore the ADC sampled value to the actual voltage value at the measured point, compensating for the influence of the voltage divider network.

[0056] S24: The microcontroller MCU 3 will collect the actual voltage V actual With respect to the preset voltage threshold range [V min V max Compare the temperature data T. sensor With the preset temperature threshold T max Compare them.

[0057] S25: If V actual ∉ [V min V max ] or T sensor >T max The microcontroller MCU 3 emits a flashing alarm via the alarm LED on the front panel 9 and sends an emergency alarm event to the host computer via the IPMB interface. At the same time, it records the abnormal event in the log buffer inside the MCU.

[0058] Step S3: Reset control is performed via hardware watchdog.

[0059] The purpose of step S3 is to automatically perform a hardware reset when the main processor software crashes or the system freezes, thereby restoring the system to normal operation and improving the system's self-recovery capability and reliability.

[0060] This step is implemented by an independent watchdog timer inside the microcontroller MCU 3, in conjunction with a hardware reset circuit.

[0061] In practice, step S3 further includes the following steps: S31: The microcontroller MCU 3 starts its internal watchdog timer and sets the watchdog period to T. WDG Watchdog cycle T WDG The value is set according to system requirements, and the range is usually from 1 second to 60 seconds, representing the maximum allowable dog feeding interval.

[0062] S32: During normal operation, processor 1 periodically sends a watchdog signal S to the microcontroller MCU 3 via its GPIO pins or LPC bus. feed The microcontroller MCU 3 resets the watchdog timer every time it receives a feed signal, causing it to start counting again.

[0063] S33: If the microcontroller MCU 3 is in the watchdog cycle T WDG No dog feeding signal received. feed If so, the system is considered deadlocked.

[0064] S34: The microcontroller MCU 3 outputs a low-level active reset signal RST to the processor 1 through the first level conversion module 4. CPU Duration T reset Among them, T reset ≥200ms, ensure processor 1 and related peripherals are completely reset and the system is restarted.

[0065] Step S4: Securely encrypt and transmit the data.

[0066] The purpose of step S4 is to perform hardware-level encryption on sensitive business data to prevent the data from being stolen or tampered with during transmission, and to ensure the confidentiality and integrity of the data.

[0067] This step is implemented by the national cryptographic algorithm engine built into the TCM Trusted Card 7, in conjunction with processor 1 and bridge chip 2.

[0068] In practice, step S4 further includes the following steps: S41: Processor 1 sends the data stream to be encrypted to TCM trusted card 7 via bridge chip 2. Data transmission is performed via LPC bus or USB bus.

[0069] S42: The random number generator inside the TCM Trusted Card 7 generates the encryption key K. enc This random number generator, based on a physical noise source, generates keys with high entropy and unpredictability. The encryption key K... enc It is stored and used only within the security domain of the TCM Trusted Card 7, and is not transmitted in plaintext through an external bus, effectively preventing physical probe attacks.

[0070] S43: TCM Trusted Card 7 invokes the built-in SM4 algorithm engine, utilizing the encryption key K. enc The data is encrypted to generate ciphertext data. The SM4 algorithm is a block cipher algorithm defined by the State Cryptography Administration of China, with a key length and block length of 128 bits.

[0071] S44: TCM Trust Card 7 forwards the encrypted ciphertext data to the data interaction module (Netcom WX1860AL4-B Ethernet Controller) via Bridge 2.

[0072] S45: The data interaction module converts encrypted data into Ethernet frames and outputs them to the external network through the RJ45 interface.

[0073] Step S5: Manage and report FRU information.

[0074] The purpose of step S5 is to enable automatic identification and management of board assets, facilitating asset inventory, configuration management, and fault location by the system management software.

[0075] FRU information is an abbreviation for Field Replaceable Unit Information. It refers to a set of structured data used to uniquely identify and describe a replaceable hardware board, which in this embodiment is the safety monitoring device itself. This information is stored in the EEPROM chip on the management daughter card 6 and is read and managed by the baseboard management controller (MCU).

[0076] Specifically, in this embodiment, the FRU information includes the following: Board model: such as "TR-6U-D2000", used to distinguish boards of different specifications or functions.

[0077] Serial number: such as "202410001", is a unique identifier for each board, which facilitates the traceability of production batches, maintenance records, etc.

[0078] Hardware version number: such as "V1.0", is used to identify the hardware design version of the board, which facilitates version matching during repair or upgrade.

[0079] Rated power consumption: such as "80W", indicates the maximum power consumed by the board during normal operation, for reference in system power management and heat dissipation design.

[0080] The main functions of FRU information are reflected in the following aspects: Automatic asset identification: When the device is inserted into the VPX chassis backplane, the chassis management controller (such as via IPMB bus) can automatically read this information and identify which type of board is inserted without manual input, thus achieving plug-and-play and automatic configuration.

[0081] System Management and Maintenance: Operation and maintenance personnel can remotely view the model, serial number and hardware version of the cards in each slot through the management software, which facilitates firmware upgrades, fault location and inventory management.

[0082] Rapid fault replacement: When a board fails, on-site maintenance personnel can quickly find a matching spare part to replace it based on the FRU information (especially the model and version), shortening the system recovery time.

[0083] Step S5 is achieved by the microcontroller MCU 3 reading the FRU information in the EEPROM via the I²C bus and reporting it through the IPMB interface.

[0084] In practice, step S5 further includes the following steps: S51: During the production process, the FRU information of the board is written into the EEPROM on the management daughter card 6. The FRU information includes the board model, serial number, hardware version number, and rated power consumption, and follows the PICMG FRU information format.

[0085] S52: After the system is running, the microcontroller MCU 3 communicates via I... 2 The C bus periodically reads the FRU information (Data) stored in the EEPROM. FRU And cached in internal RAM.

[0086] S53: When the backplane management controller sends an FRU information read request via the IPMB bus, the microcontroller MCU3 receives the request through the IPMB interface and stores the cached Data. FRU Reporting is performed via the IPMB bus.

[0087] Step S6: System soft reset control.

[0088] The purpose of step S6 is to support remote operation and maintenance, allowing the management platform to reset the system without affecting the power status, thereby improving the maintainability of the system.

[0089] This step is achieved by the microcontroller MCU 3 receiving instructions and outputting a reset signal through the IPMB interface.

[0090] In specific implementation, step S6 further includes the following steps: S61: The microcontroller MCU 3 continuously listens for management commands from the backplane management controller via the IPMB interface.

[0091] S62: When a soft reset command is received, the microcontroller MCU 3 parses the command content.

[0092] S63: The microcontroller MCU 3 outputs a reset signal RST through the first level conversion module 4. CPU The system will be reset. This reset process does not affect the power supply state, i.e., V. core V io V aux The power supply remains stable, and only the processor and related peripherals are reset.

[0093] Step S7: Front panel status indication.

[0094] The purpose of step S7 is to visually reflect the equipment's operating status through LED indicator lights, making it easier for on-site maintenance personnel to quickly assess the equipment's health condition.

[0095] This step is achieved by the microcontroller MCU 3 controlling the multiple LEDs on the front panel 9 according to the system status.

[0096] In practice, step S7 further includes the following steps: S71: The microcontroller MCU 3 monitors the power-on status, reset status, read / write status of the solid-state drive SSD 8, network connection status, and health status of the TCM trusted card 7 in real time.

[0097] S72: Based on the monitored status, the microcontroller MCU 3 controls the corresponding LEDs on the front panel 9 via GPIO pins: Power LED: Always on when the system is powered on, and off when the system is powered off.

[0098] Status LED: Flashes when the system is running normally, and remains on or off when there is an abnormality.

[0099] Hard drive LED: Flashes when the SSD is performing read / write operations.

[0100] Alarm LED: Flashes when voltage or temperature exceeds limits.

[0101] Network LED: Stays on when a network link is established, and flashes when data is being transmitted or received.

[0102] TCM Status LED: Always on when TCM trusted card initialization is successful, off when it fails.

[0103] TCM Alarm LED: Flashes when the TCM trusted card malfunctions.

[0104] Step S8: Output and display the debugging information.

[0105] The purpose of step S8 is to provide underlying operational data for system development and on-site troubleshooting, facilitating problem location and diagnosis.

[0106] This step is achieved by the microcontroller MCU 3 sending debugging information to the test serial port via the UART interface.

[0107] In practice, step S8 further includes the following steps: S81: The microcontroller MCU 3 outputs debugging information such as system startup log, status monitoring data, watchdog action record, alarm event, and system status log through the UART interface.

[0108] S82: The TTL level signal output by the UART interface is converted to RS232 level by the RS232 level conversion circuit on the management daughter card 6.

[0109] S83: The converted RS232 signal is output through the test serial port connector. Maintenance personnel can connect to this interface using a serial port debugging tool to obtain the underlying operating data.

[0110] Example 2 Step S1: System power-on timing control.

[0111] The system is connected to a +12V input voltage V. in Then, MCU 3 first enables V through the first level conversion module 4. core DC-DC converter. When PGOOD core After the signal changes from low to high, the MCU delays by T. delay1 =10ms, pull EN high io Enable V io (3.3V). When PGOOD io =1, then delay for T delay2 =5ms, pull EN high aux Enable V aux (1.2V). The entire process strictly follows V. core →V io →V aux The order of operations ensures a stable startup for the Phytium D2000 processor.

[0112] Step S2: System status monitoring and alarms.

[0113] MCU 3 reads data from the DS18B20 temperature sensor every 100ms via a single bus to obtain T. sensorSimultaneously, the MCU3's ADC module samples four voltage channels to monitor the 3.3V interface voltage V. io For example, if the voltage divider resistor network uses R1=10kΩ and R2=10kΩ, then the voltage divider coefficient R divider =(R1+R2) / R2 =2. ADC reference voltage. ref =3.3V, if the ADC sample value V sample =1.65V, then the actual voltage V actual =(1.65×2) / 3.3=1.0V. When the measured voltage is 3.3V, the voltage at the ADC pin is 1.65V after voltage division. If the actual voltage is out of range, or the temperature exceeds 85℃, MCU 3 will cause the front panel alarm LED to flash and send an emergency alarm event via IPMB.

[0114] Step S3: Hardware watchdog reset control.

[0115] MCU 3 internal watchdog cycle T WDG Set to 10 seconds. The operating system running on processor 1 sends a dog-feed signal S via GPIO every 5 seconds. feed If the system crashes, the watchdog timer stops, and MCU 3 detects a timeout after 10 seconds and outputs a low-level reset signal RST. CPU Duration T reset =250ms, causing processor 1 to reset and restart.

[0116] Step S4: Securely encrypt and transmit data.

[0117] When sensitive data needs to be transmitted, processor 1 sends the data to TCM Trust Card 7 via the PCIe bus and bridge chip 2. The internal random number generator of TCM Trust Card 7 generates a 128-bit SM4 encryption key K. enc The SM4 engine is invoked to encrypt the data. The encrypted ciphertext data is then forwarded via bridge chip 2 to the WX1860AL4-B Ethernet controller, where it is converted into Ethernet frames for output. The key K is used throughout the entire process. enc It was not transmitted on the external bus.

[0118] Step S5: FRU Information Management and Reporting.

[0119] The EEPROM (24C02) pre-stores the board's FRU information, including model "TR-6U-D2000", serial number "202410001", hardware version "V1.0", and rated power consumption "80W". After power-on, MCU 3 reads and caches this information via I²C. When the backplane management controller queries the FRU information via IPMB, MCU 3 packages and reports the cached data.

[0120] The implementation of steps S6 to S8 is the same as in Example 1, and will not be repeated here.

[0121] The beneficial effects of the present invention, through the design of the above embodiments, are as follows: (1) Fully domestically produced and controllable: The core processor, bridge chip, MCU and Ethernet controller all use domestically produced chips, which eliminates the supply chain security risks from the source and meets the requirements of independent control of national key infrastructure.

[0122] (2) Highly reliable independent management channel: An independent GD32 MCU is used as the BMC to realize out-of-band management. Even if the main processor crashes or the operating system crashes, the BMC can still independently complete voltage and temperature monitoring, remote reset and power-on / off timing control, which greatly improves the maintainability and reliability of the system.

[0123] (3) It has refined timing and reset control: through formulaic timing control logic V core ->V io ->V aux and precise delay parameters (T) delay1 ≥10ms, T delay2 ≥5ms) ensures stable processor startup under complex power conditions, avoiding startup failures caused by timing irregularities; an independent hardware watchdog mechanism (T WDG T reset (≥200ms), effectively preventing system deadlock.

[0124] (4) It has comprehensive status monitoring and alarm: it samples the voltage through ADC and uses the formula V actual =(V sample ×R divider ) / (ADC ref By accurately calculating the actual voltage and combining it with temperature sensor data, real-time monitoring of key system parameters is achieved, and an alarm is immediately triggered when limits are exceeded, effectively preventing device damage.

[0125] (5) Hardware-level data security features: It integrates a TCM trusted card and uses its internal random number generator to generate the encryption key K. enc It uses the SM4 algorithm for data encryption, and the key is only used within the security domain and is not exposed to the external bus, thus realizing end-to-end hardware encryption from data storage to data transmission, effectively resisting software-level virus attacks and physical-level bus eavesdropping.

[0126] (6) Standardized FRU information management: FRU information (Data) stored in EEPROM can be reported via the IPMB interface. FRU It enables automatic identification and management of board assets, facilitating system integration and maintenance.

[0127] (7) It has rich interfaces and powerful expansion capabilities: Based on the 6U VPX standard architecture and combined with the powerful expansion capabilities of the Phytium X100 bridge chip, it provides SATA 3.0, USB 3.0, VGA, serial port and 4 gigabit network ports to meet the needs of high-speed data exchange and diverse peripheral access.

[0128] This invention has been described with reference to specific embodiments, but those skilled in the art will understand that various changes and equivalent substitutions can be made without departing from the scope of the invention. Furthermore, numerous modifications can be made to this invention to suit specific applications without departing from its protection scope. Therefore, this invention is not limited to the specific embodiments disclosed herein, but includes all embodiments falling within the scope of the claims.

Claims

1. A security monitoring method based on VPX architecture, characterized in that, The method is applied to a security monitoring device, which includes a processor (1), a bridge chip (2), a microcontroller (MCU) (3), a first level conversion module (4), a second level conversion module (5), a management daughter card (6), a TCM trusted card (7), a solid-state drive (SSD) (8), a front panel (9), and a VPX connector (10); the method includes the following steps: S1: System power-on timing control. The microcontroller MCU (3) controls the enable terminal of the onboard power module through the first level conversion module (4) to enable the processor core voltage V sequentially according to the preset timing. core Interface voltage V io and auxiliary voltage V aux ; S2: System status monitoring and alarm. The microcontroller MCU (3) periodically collects the temperature data T from the temperature sensor on the management sub-card (6) via the I²C bus. sensor The voltage sample value V is obtained by analog-to-digital converter (ADC) sampling. sample Calculate the actual voltage V actual When the threshold is exceeded, the alarm LED on the front panel (9) is controlled to flash alarm and an emergency alarm event is sent to the host computer through the IPMB interface. S3: Hardware watchdog reset control. The microcontroller MCU (3) runs an independent watchdog timer. If the preset watchdog period T is reached... WDG No dog feeding signal S was received from processor (1) feed Then, the first level conversion module (4) outputs a reset signal RST to the processor (1). CPU Perform a hardware reset; S4: Data secure encrypted transmission, the processor (1) sends the data stream to be encrypted to the TCM trusted card (7) through the bridge chip (2), the TCM trusted card (7) calls the built-in national cryptographic algorithm to encrypt the data, and the encrypted data is forwarded to the data interaction module for output through the bridge chip (2); S5: FRU Information Management and Reporting. The microcontroller MCU (3) reads the FRU information Data stored in the EEPROM on the management sub-card (6) via the I²C bus. FRU It responds to the read request from the backplane management controller via the IPMB interface and reports the FRU information.

2. The security monitoring method based on VPX architecture according to claim 1, characterized in that, The power-on timing control mentioned in step S1 further includes the following steps: S11: The microcontroller MCU (3) monitors the processor core voltage V core Good power signal PGOOD core When PGOOD core When =1, it indicates that the core voltage has stabilized; S12: After the first delay T delay1 The microcontroller MCU (3) pulls the first enable signal EN high through the first level conversion module (4). io Enable interface voltage V io ; S13: The voltage V of the monitoring interface of the microcontroller MCU (3) io Good power signal PGOOD io When PGOOD io When =1, it indicates that the interface voltage has stabilized; S14: After the second delay T delay2 The microcontroller MCU (3) pulls the second enable signal EN high through the first level conversion module (4). aux Enable auxiliary voltage V aux Wherein, the first delay T delay1 ≥10ms, the second delay T delay2 ≥5ms is used to ensure that the preceding voltage is fully established without glitches, avoid latch-up effects caused by power supply rising edge competition, and meet the power timing requirements of the processor (1).

3. The security monitoring method based on VPX architecture according to claim 1, characterized in that, The actual voltage V mentioned in step S2 actual Calculated using the following formula: V actual =(V sample ×R divider ) / (ADC ref ), where V sample These are ADC sample values, in volts (V); R divider The voltage divider coefficient of the voltage divider resistor network is dimensionless; ADC ref The reference voltage of the internal ADC of the microcontroller MCU (3) is in volts (V); the voltage divider coefficient R divider Determined by the voltage divider resistor network, specifically R divider =(R1+R2) / R2, where R1 is the series voltage divider resistor and R2 is the grounding resistor.

4. The security monitoring method based on VPX architecture according to claim 1, characterized in that, The hardware watchdog reset control described in step S3 further includes the following steps: S31: The microcontroller MCU (3) starts the internal watchdog timer and sets the watchdog period to T. WDG ; S32: During normal operation, the processor (1) periodically sends a dog feed signal S to the microcontroller MCU (3). feed The microcontroller MCU (3) resets the watchdog timer every time it receives a dog-feeding signal; S33: If the microcontroller MCU (3) is in the watchdog cycle T WDG No dog feeding signal received inside S feed If so, the system is considered deadlocked; S34: The microcontroller MCU (3) outputs a low-level active reset signal RST to the processor (1) through the first level conversion module (4). CPU Duration T reset Wherein, the watchdog period T WDG The value is set according to system requirements, ranging from 1 second to 60 seconds; the duration T of the reset signal reset ≥200ms ensures complete reset of the processor (1) and related peripherals.

5. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The secure encrypted data transmission described in step S4 further includes the following steps: S41: The processor (1) sends the data stream to be encrypted to the TCM trusted card (7) through the bridge chip (2). S42: The random number generator inside the TCM trusted card (7) generates the encryption key K. enc The encryption key K enc Stored and used only within the security domain of the TCM trusted card (7); S43: The TCM trusted card (7) calls the built-in SM4 algorithm engine and uses the encryption key K enc The data is encrypted to generate ciphertext data; S44: The TCM trusted card (7) forwards the encrypted ciphertext data to the data interaction module through the bridge chip (2); S45: The data interaction module converts the encrypted data into Ethernet frames and outputs them through the RJ45 interface; wherein, the encryption key K enc It does not transmit data in plaintext through an external bus to prevent physical probe attacks.

6. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The method further includes the following steps: S6: System soft reset control. The microcontroller MCU (3) receives a soft reset command from the backplane management controller through the IPMB interface. The microcontroller MCU (3) outputs a reset signal RST through the first level conversion module (4). CPU The system will be reset, and this reset process will not affect the power supply status.

7. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The voltage monitoring described in step S2 includes monitoring the processor core voltage V. core Interface voltage V io Auxiliary voltage V aux and input voltage V in Multi-channel monitoring; when any actual voltage V actual Exceeding the preset voltage threshold range [V] min V max When an abnormal event occurs, the microcontroller MCU (3) records the abnormal event and generates an alarm log.

8. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The FRU information Data mentioned in step S5 FRU This includes the board model, serial number, hardware version number, and rated power consumption; the microcontroller MCU (3) responds to the backplane management controller's read request through the IPMB interface and reads the Data from the EEPROM. FRU Reporting is performed via the IPMB bus.

9. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The method further includes the following steps: S7: Front panel status indication. The microcontroller MCU (3) controls the on / off and flashing frequency of the corresponding power LED, status LED, hard disk LED, alarm LED, network LED, TCM status LED and TCM alarm LED on the front panel (9) according to the power-on status, reset status, read / write status of solid-state hard disk SSD (8), network connection status and health status of TCM trusted card (7).

10. A security monitoring method based on VPX architecture according to claim 1, characterized in that, The method further includes: Step S8: Output debugging information. The microcontroller MCU (3) sends the debugging information and system status log to the test serial port on the management sub-card (6) through the UART interface. The test serial port outputs through the RS232 level conversion circuit and is used to obtain the underlying running data during the system development stage and on-site troubleshooting.

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