Distributed feedback laser chip and method of manufacturing the same

Abstract

This invention discloses a distributed feedback laser chip and its fabrication method, relating to the field of lasers. The fabrication method of the distributed feedback laser includes: forming an initial epitaxial layer on a substrate; etching to form ridges and steps; forming a buried layer on the steps, the buried layer enclosing the active layer and blocking carrier diffusion; forming a cladding layer and a contact layer; forming at least one trench; the trench is located on one side of the ridge and extends into the buried layer; forming a first electrode layer, the first electrode layer covering the contact layer and the trench above the ridge; and forming a second electrode layer. Implementing this invention can reduce the threshold current of the distributed feedback laser chip and improve its electro-optical conversion efficiency. Simultaneously, it reduces the leakage risk of the distributed feedback laser chip and improves its reliability.

Description

Technical Field

[0001] This invention relates to the field of lasers, and more particularly to a distributed feedback laser chip and its fabrication method. Background Technology

[0002] With the rapid development of high-speed optical communication scenarios such as 5G communication and data center interconnection, increasingly stringent requirements are being placed on the transmission rate, output power, modulation bandwidth, and integration of laser chips. As the core optical emitting device in optical communication systems, laser chips have become a key component in the field of high-speed optical communication due to the need to meet core requirements such as narrow linewidth, stable single-mode output, and excellent modulation performance. However, current laser chips still suffer from problems such as current diffusion and low recombination efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a distributed feedback laser chip and its fabrication method, which can reduce threshold current, improve electro-optic conversion efficiency, and optimize reliability.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a distributed feedback laser chip, comprising: A substrate is provided, and an initial epitaxial layer is formed on a first surface of the substrate; wherein the initial epitaxial layer comprises a lower confinement layer, an etch stop layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper confinement layer, and a grating layer sequentially stacked on the first surface; The initial epitaxial layer is etched to form ridges and steps that expose the etch stop layer; wherein the ridges extend along a first direction that intersects the thickness direction of the substrate; A buried layer is formed on the step to obtain an initial epitaxial structure; wherein the buried layer encloses the active layer and can block carrier diffusion; A cladding layer and a contact layer are formed in the initial epitaxial structure to obtain a first intermediate. At least one groove is formed on the first intermediate to obtain a second intermediate; wherein the groove is located on one side of the ridge and extends along a first direction; in the thickness direction, the groove extends into the burial layer; A first electrode layer is formed on the second intermediate; wherein the first electrode layer covers the contact layer above the ridge and the trench; A second electrode layer is formed on the second surface of the substrate.

[0005] As an improvement to the above technical solution, the refractive index of the buried layer is less than that of the active layer; The burial layer encloses the ridge and exposes the top surface of the ridge.

[0006] As an improvement to the above technical solution, the buried layer includes a P-type InP layer, an intrinsic InP layer, and an N-type InP layer stacked sequentially on the step; The thickness of the P-type InP layer is 2000 Å to 10000 Å, the thickness of the intrinsic InP layer is 4000 Å to 10000 Å, and the thickness of the N-type InP layer is 2000 Å to 10000 Å.

[0007] As an improvement to the above technical solution, the ridge includes a first part and a second part that are sequentially stacked on the etching stop layer; in the direction from the etching stop layer to the cladding, the width of the first part decreases and the width of the second part increases.

[0008] As an improvement to the above technical solution, the step of etching the initial epitaxial layer to form ridges and expose the etch stop layer includes: A mask layer is formed and patterned on the first epitaxial structure to expose the initial epitaxial layer of the first preset region; The initial epitaxial layer of the first preset region is etched to a first preset depth using an ICP etching process; wherein the first preset depth is 2000 Å to 6000 Å. The initial epitaxial layer of the first preset region is etched to a second preset depth using a wet etching process to form the ridges and steps; wherein the second preset depth is 8000Å~15000Å.

[0009] As an improvement to the above technical solution, the process parameters of the ICP etching process include: The etching gases are Cl2, N2, and Ar. The flow rate of Cl2 is 5 sccm to 25 sccm, the flow rate of Ar is 15 sccm to 30 sccm, and the flow rate of N2 is 10 sccm to 30 sccm. The chamber pressure is 0.5 mtorr to 3 mtorr, the ICP power is 800 W to 1000 W, the RF power is 100 W to 200 W, and the etching temperature is 150 °C to 200 °C.

[0010] As an improvement to the above technical solution, the process parameters for the wet etching include: The etching solution is a mixture of phosphoric acid and hydrochloric acid, with a volume ratio of phosphoric acid to hydrochloric acid of 2:1 to 5:1; the concentration of phosphoric acid is 90wt% to 98wt%, and the concentration of hydrochloric acid is 30wt% to 35wt%. The etching temperature is 20℃~40℃.

[0011] As an improvement to the above technical solution, in the step of forming at least one trench on the first intermediate to obtain the second intermediate, the trench is formed by a wet etching process. The process parameters for the wet etching process include: The etching solution is a mixture of phosphoric acid, hydrogen peroxide, and water, with a volume ratio of 1:2:5 to 1:4:10; the concentration of phosphoric acid is 80wt% to 90wt%, and the concentration of hydrogen peroxide is 20wt% to 40wt%. The etching temperature is 20℃~40℃.

[0012] As an improvement to the above technical solution, in the step of forming at least one groove on the first intermediate to obtain the second intermediate: A groove is formed on each side of the ridge, and the depth of the groove is 30,000 Å to 50,000 Å. The distance between the sidewall of the groove and the sidewall of the ridge is 15000Å~25000Å.

[0013] Accordingly, the present invention also discloses a distributed feedback laser chip, which is prepared by the above-described method for preparing a distributed feedback laser chip.

[0014] Implementing this invention has the following beneficial effects: In one embodiment of the distributed feedback laser chip fabrication method of the present invention, ridges and steps are etched on the initial epitaxial layer; and a buried layer encapsulating the active layer is formed on the steps. This buried layer can block carrier diffusion, thereby effectively confining the carriers inside the active layer, enabling efficient recombination of carriers within the active region, improving carrier utilization efficiency, reducing the threshold current of the distributed feedback laser chip, and improving its electro-optical conversion efficiency. Furthermore, after forming the cladding and contact layers, a trench extending along a first direction is formed on one side of the ridge, and this trench extends into the buried layer in the thickness direction; this precisely defines the carrier transport path, effectively reducing the reverse current of the entire chip, not only improving conversion efficiency but also significantly reducing leakage risk and improving reliability. Attached Figure Description

[0015] Figure 1 This is a flowchart of a method for fabricating a distributed feedback laser chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the substrate and initial epitaxial layer obtained in step S1 of an embodiment of the present invention; Figure 3 This is a cross-sectional view of the ridge and steps obtained in step S2 of an embodiment of the present invention; Figure 4 This is a top view of the ridge and steps obtained in step S2 of an embodiment of the present invention; Figure 5This is an SEM image of the ridge obtained in step S2 of one embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the first intermediate obtained in step S4 of an embodiment of the present invention; Figure 7 This is a cross-sectional view of the second intermediate obtained in step S5 of an embodiment of the present invention; Figure 8 This is a top view of the second intermediate obtained in step S5 of an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a distributed feedback laser chip product according to one embodiment of the present invention; Figure 10 This is a SEM image of a finished distributed feedback laser chip according to an embodiment of the present invention; In the figure: 100 is the substrate, 110 is the first surface, 120 is the second surface, 210 is the lower confinement layer, 220 is the etch stop layer, 230 is the lower waveguide layer, 240 is the active layer, 250 is the upper waveguide layer, 260 is the upper confinement layer, 270 is the grating layer, 310 is the ridge, 311 is the first part, 312 is the second part, 320 is the step, 400 is the buried layer, 410 is the P-type InP layer, 420 is the intrinsic InP layer, 430 is the N-type InP layer, 510 is the cladding, 520 is the contact layer, 600 is the trench, 700 is the passivation layer, 800 is the first electrode layer, and 900 is the second electrode layer. Detailed Implementation

[0016] To facilitate understanding of the present invention, it will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. Rather, these embodiments or examples are provided to make the disclosure of the present invention more thorough and complete.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments or examples only and is not intended to limit the invention. The optional range of the term "and / or" as used herein includes any one of two or more of the related listed items, as well as any and all combinations of the related listed items, including any two related listed items, any more related listed items, or a combination of all related listed items.

[0018] In this invention, terms such as "first aspect" and "second aspect" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly indicating the importance or quantity of the indicated technical features.

[0019] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.

[0020] Please see Figure 1 As a first aspect of the present invention, the present invention provides a method for fabricating a distributed feedback laser (DFB) chip, which includes the following steps: S1. Provide a substrate and form an initial epitaxial layer on the first surface of the substrate; The substrate 100 may be an InP substrate or a GaAs substrate, but is not limited thereto. Preferably, in some embodiments, the substrate 100 is an InP substrate, which is formed into a conductive substrate by doping. The substrate 100 has a first surface 110 and a second surface 120 disposed opposite to each other.

[0021] Please see Figure 2 The initial epitaxial layer includes a lower confinement layer 210, an etch stop layer 220, a lower waveguide layer 230, an active layer 240, an upper waveguide layer 250, an upper confinement layer 260, and a grating layer 270, which are sequentially stacked on the first surface 110.

[0022] Specifically, the lower confinement layer 210 is an N-type AlInAs layer, an N-type InGaAsP layer, an N-type InP layer, or an N-type InGaAlAs layer, but is not limited thereto. Preferably, in some embodiments, the lower confinement layer 210 is an N-type InP layer with a thickness of 100 nm to 500 nm.

[0023] Specifically, the etching stop layer 220 is an InAlAs layer, an InGaAsP layer, or an InAlP layer, but is not limited to these. Preferably, in some embodiments, the etching stop layer 220 is an InGaAsP layer with a thickness of 800 nm to 2500 nm.

[0024] Specifically, the lower waveguide layer 230 is an undoped AlGaInAs layer, an undoped AlInAs layer, or an undoped InGaAsP layer, but is not limited to these. Preferably, in some embodiments, the lower waveguide layer 230 is an undoped InGaAsP layer with a thickness of 50 nm to 300 nm. The refractive index and bandgap of the lower waveguide layer 230 increase progressively; specifically, from the active layer 240 to the lower confinement layer 210, the bandgap and refractive index of the lower waveguide layer 230 increase progressively. In this way, the optical waveguide and carrier confinement functions of the lower waveguide layer 230 can be optimized.

[0025] Specifically, the active layer 240 is composed of alternating layers of AlGaInAs well layers and AlGaInAs barrier layers, or alternating layers of InGaAsP well layers and InGaAsP barrier layers, but is not limited thereto. Preferably, in some embodiments, the active layer 240 includes alternating layers of InGaAsP well layers and InGaAsP barrier layers. The thickness of the InGaAsP well layers is 5 nm to 10 nm, the thickness of the InGaAsP barrier layers is 10 nm to 15 nm, and the number of periods of the active layer 240 is 5 to 15.

[0026] Specifically, the upper waveguide layer 250 is an undoped AlGaInAs layer, an undoped AlInAs layer, or an undoped InGaAsP layer, but is not limited to these. Preferably, in some embodiments, the upper waveguide layer 250 is an undoped InGaAsP layer with a thickness of 50 nm to 300 nm. From the active layer 240 to the upper confinement layer 260, the bandgap of the upper waveguide layer 250 decreases, and the refractive index decreases.

[0027] Specifically, the upper confinement layer 260 is a P-type AlInAs layer, a P-type InGaAsP layer, a P-type InP layer, or an InGaAlAs layer, but is not limited thereto. Preferably, in some embodiments, the upper confinement layer 260 is a P-type InP layer with a thickness of 100 nm to 500 nm.

[0028] Specifically, the grating layer 270 is an undoped InGaAsP layer or an undoped AlGaAs layer, but is not limited thereto. Preferably, in some embodiments, the grating layer 270 is an undoped InGaAsP layer with a thickness of 30 nm to 50 nm, and the grating structure is formed by photolithography etching.

[0029] Preferably, in some embodiments, the initial epitaxial layer may further include a buffer layer, a lower cladding layer, a spacer layer, and a grating buried layer, but is not limited thereto. Specifically, the buffer layer, lower cladding layer, and spacer layer are sequentially disposed between the substrate 100 and the lower confinement layer 210. The buffer layer is an N-type InP layer with a thickness of 0.5 μm to 2 μm, the lower cladding layer 510 is an N-type InP layer with a thickness of 0.3 μm to 1 μm, and the spacer layer is an undoped InP layer with a thickness of 0.3 μm to 1 μm. The grating buried layer is disposed above the grating layer 270 and is an InP layer or an InGaAsP layer, but is not limited thereto.

[0030] S2: Etch the initial epitaxial layer to form ridges and expose the etch stop layer steps; Specifically, the initial epitaxial layer can be etched using wet or dry etching processes to form steps 320 and ridges 310 that expose the etch stop layer 220. For details, please refer to... Figure 3 , Figure 4 The ridge 310 extends along a first direction, and steps 320 are disposed on both sides of the ridge 310. The first direction intersects the thickness direction of the substrate 100, or more specifically, the first direction is perpendicular to the thickness direction of the substrate 100. By subsequently forming a buried layer 400 on the steps 320, the active layer 240 can be effectively wrapped, thereby blocking carrier diffusion and enabling carriers to recombine efficiently within the active region. This improves carrier utilization efficiency, reduces the threshold current of the DFB chip, and enhances its electro-optical conversion efficiency.

[0031] Specifically, the cross-sectional shape of the ridge 310 in the thickness direction is rectangular or trapezoidal, but not limited to these. Preferably, please refer to... Figure 3 , Figure 5 In some embodiments, the ridge 310 includes a first portion 311 and a second portion 312 sequentially stacked on the etching stop layer 220. Furthermore, in the direction from the etching stop layer 220 to the cladding layer 510, the width of the first portion 311 decreases progressively, while the width of the second portion 312 increases progressively. More preferably, the sidewalls of both the first portion 311 and the second portion 312 are arc-shaped. Based on the aforementioned shape of the ridge 310, the electro-optical conversion efficiency can be further improved.

[0032] Preferably, in some embodiments, step S2 includes: S21: A mask layer is formed and patterned on the first epitaxial structure to expose the initial epitaxial layer of the first preset region; The mask layer can be a silicon nitride layer or a silicon oxide layer, but is not limited to these. Preferably, in some embodiments, the mask layer is a SiO2 layer, which is formed by a PECVD process. After the mask layer is formed, the mask layer on the first predetermined area is removed by a photolithography-wet etching process to expose the initial epitaxial layer.

[0033] S22: The initial epitaxial layer of the first preset region is etched to a first preset depth using the ICP etching process; The process parameters for the ICP etching process include: etching gases are Cl2, N2, and Ar; the flow rate of Cl2 is 5 sccm to 25 sccm; the flow rate of Ar is 15 sccm to 30 sccm; the flow rate of N2 is 10 sccm to 30 sccm; the chamber pressure is 0.5 mtorr to 3 mtorr; the ICP power is 800 W to 1000 W; the RF power is 100 W to 200 W; and the etching temperature is 150 °C to 200 °C.

[0034] The first preset depth is 2000Å~6000Å.

[0035] S23: The initial epitaxial layer of the first preset region is etched to a second preset depth using a wet etching process to form the ridge and step; The wet etching process parameters include: the etching solution is a mixture of phosphoric acid and hydrochloric acid, with a volume ratio of phosphoric acid to hydrochloric acid of 2:1 to 5:1; the concentration of phosphoric acid is 90wt% to 98wt%, and the concentration of hydrochloric acid is 30wt% to 35wt%; the etching temperature is 20℃ to 40℃. During the wet etching process, both longitudinal etching along the thickness direction and transverse etching perpendicular to the thickness direction occur. Through the combination of ICP etching and wet etching, ridges with a specific morphology 310 are formed.

[0036] The second preset depth is 8000Å~15000Å.

[0037] More preferably, after the wet etching process is completed, the mask layer is not removed. After the buried layer 400 is formed, the mask layer and the buried layer 400 above it are removed by etching with BOE etching solution.

[0038] S3: A buried layer is formed on the step to obtain the initial extensional structure; Specifically, the buried layer 400 encloses the active layer 240 and is a high-resistivity dielectric layer, which can restrict carrier diffusion. Preferably, in some embodiments, the buried layer 400 completely encloses the ridge 310 and exposes the top surface of the ridge 310, and the refractive index of the buried layer 400 is lower than that of the active layer 240. Based on this structure, light extraction efficiency can be improved while limiting carrier transport.

[0039] The buried layer 400 may include, but is not limited to, a P-type InP layer and an N-type InP layer sequentially stacked on the step 320. Preferably, in some embodiments, the buried layer 400 includes a P-type InP layer 410, an intrinsic InP layer 420, and an N-type InP layer 430 sequentially stacked on the step 320; the thickness of the P-type InP layer 410 is 2000 Å to 10000 Å, the thickness of the intrinsic InP layer 420 is 4000 Å to 10000 Å, and the thickness of the N-type InP layer 430 is 2000 Å to 10000 Å. Based on the above-described buried layer 400, leakage current can be further reduced, chip threshold current can be reduced, and the electro-optical conversion efficiency of the chip can be improved.

[0040] S4: A cladding and contact layer are formed in the initial epitaxial structure to obtain the first intermediate; Please see Figure 6 By forming the cladding layer 510 and the contact layer 520, a flat surface can be obtained, which facilitates the formation of structures such as the passivation layer 700 and the first electrode layer 800 in the later stages.

[0041] The cladding 510 is a P-type InP layer, but is not limited to this. The thickness of the cladding 510 is 1.5 μm to 3 μm.

[0042] The ohmic contact layer 520 is a P-type InGaAs layer or a P-type InGaAsP layer, but is not limited thereto. Preferably, in some embodiments, the ohmic contact layer 520 is a P-type InGaAs layer with a thickness of 100 nm to 500 nm.

[0043] Preferably, in some embodiments, a barrier gradient layer, which is a P-type InGaAsP layer, is further disposed between the cladding layer 510 and the contact layer 520. This layer can buffer current injection and reduce optical loss. The thickness of the barrier gradient layer is 30 nm to 80 nm.

[0044] S5: Form at least one groove on the first intermediate to obtain the second intermediate; Please refer to Figure 7 , Figure 8 The trench 600 is located on one side of the ridge 310, and both the trench 600 and the ridge 310 extend along a first direction. In the thickness direction, the trench 600 extends into the buried layer 400. More specifically, the trench 600 extends into the P-type InP layer 410 or the intrinsic InP layer 420. Preferably, the bottom of the trench 600 exposes the etch stop layer 220. Through the combination of the trench 600 and the buried layer 400, the transport path of charge carriers can be precisely defined, significantly reducing the reverse current of the entire chip. This not only reduces the threshold current and improves the conversion efficiency, but also significantly reduces the risk of leakage current and improves reliability.

[0045] Preferably, in some embodiments, a groove 600 is formed on each side of the ridge 310. The depth of the groove 600 is 30,000 Å to 50,000 Å, and the distance between the sidewall of the groove 600 and the sidewall of the ridge 310 is 15,000 Å to 25,000 Å. It should be noted that the distance between the sidewall of the groove 600 and the sidewall of the ridge 310 refers to the distance between the top of the sidewall of the ridge 310 and the sidewall of the groove 600 on the same horizontal plane. By controlling the distance between these two elements and the depth of the groove 600, the risk of chip leakage can be further reduced.

[0046] Specifically, the trench 600 can be formed by a dry etching process or a wet etching process, but is not limited thereto. Preferably, in some embodiments, the trench 600 is formed by a wet etching process; the process parameters of the wet etching process include: the etching solution is a mixture of phosphoric acid, hydrogen peroxide and water, and the volume ratio of phosphoric acid, hydrogen peroxide and water is 1:2:5 to 1:4:10; the concentration of phosphoric acid is 80wt% to 90wt%, and the concentration of hydrogen peroxide is 20wt% to 40wt%; the etching temperature is 20℃ to 40℃.

[0047] Preferably, in some embodiments, after forming the trench 600, a passivation layer 700 is formed on the surface of the trench 600 and the surface of the contact layer 520, and the contact layer 520 above the ridge 310 is etched to expose it. Specifically, the passivation layer 700 may be a SiO2 layer, a silicon nitride layer, an Al2O3 layer, or an HfO2 layer, but is not limited thereto. Preferably, it is a SiO2 layer. The thickness of the passivation layer 700 is 100 nm to 800 nm.

[0048] S6: Form a first electrode layer on the second intermediate; The first electrode layer 800 is a stacked structure formed of metals such as Ti, Pt, Au, Ag, Cr, and Ni, but is not limited to these. The first electrode layer 800 can be formed by electron beam evaporation or PVD, but is not limited to these methods.

[0049] Specifically, please refer to Figure 9 , Figure 10 The first electrode layer 800 covers the contact layer 520 above the ridge 310 and the trench 600. More specifically, the first electrode layer 800 covers the passivation layer 700 on the surface of the trench 600, but the first electrode layer 800 exposes part of the passivation layer 700, that is, it does not cover all the passivation layer 700 outside the trench 600.

[0050] S7: A second electrode layer is formed on the second surface of the substrate; The second electrode layer 900 may be made of one or more of Pt, Au, Ti, Cu, Ag, TiW, and AuGe, but is not limited thereto. The second electrode layer 900 may be formed by electron beam evaporation or PVD, but is not limited thereto.

[0051] Preferably, in some embodiments, the substrate 100 is thinned before the second electrode layer 900 is formed.

[0052] Preferably, the preparation method of the present invention further includes steps such as bar strip dissociation, cavity surface coating, cutting, testing and sorting, but is not limited thereto.

[0053] Accordingly, as a second aspect of the present invention, a distributed feedback laser chip is also disclosed, which is prepared by the above-described preparation method. In the distributed feedback laser chip of the present invention, after etching the exposed step 320, a buried layer 400 encapsulating the active layer 240 is formed on the step 320. This layer blocks carrier diffusion, allowing carriers to recombine efficiently within the active region, improving carrier utilization efficiency, reducing the threshold current of the DFB chip, and enhancing its electro-optical conversion efficiency. Furthermore, a trench 600 exposing the buried layer 400 is formed on one side of the ridge 310, and the first electrode layer 800 covers the trench 600. This precisely defines the carrier transport path, effectively reducing the reverse current of the entire chip, not only improving conversion efficiency but also significantly reducing leakage risk and enhancing reliability.

[0054] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a method for fabricating a distributed feedback laser chip, which includes the following steps: (1) Provide a substrate and form an initial epitaxial layer on a first surface of the substrate; The substrate is an InP substrate. The initial epitaxial layer comprises a lower confinement layer, an etch stop layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper confinement layer, and a grating layer, sequentially stacked on the first surface. The lower confinement layer is an N-type InP layer with a thickness of 450 nm. The etch stop layer is an InGaAsP layer with a thickness of 1200 nm. The lower waveguide layer is an undoped InGaAsP layer with a thickness of 200 nm. The active layer comprises alternating layers of InGaAsP well layers and InGaAsP barrier layers. The InGaAsP well layers have a thickness of 8 nm, the InGaAsP barrier layers have a thickness of 12 nm, and the active layer has 8 periods. The upper waveguide layer is an undoped InGaAsP layer with a thickness of 250 nm. The upper confinement layer is a P-type InP layer with a thickness of 450 nm. The grating layer is an undoped InGaAsP layer with a thickness of 50 nm.

[0055] (2) The initial epitaxial layer is etched to form ridges and steps that expose the etch stop layer; Specifically, the initial epitaxial layer is etched using an ICP etching process. Specific process parameters include: etching gases are Cl2 and Ar, with a Cl2 flow rate of 22 sccm and an Ar flow rate of 18 sccm; chamber pressure is 2.2 mtorr; ICP power is 850 W; RF power is 140 W; and etching temperature is 180 °C.

[0056] The etching depth is 11600 Å, and the cross-sectional shape of the etched ridge in the thickness direction is rectangular.

[0057] (3) A buried layer is formed on the step to obtain the initial extensional structure; The buried layer consists of a P-type InP layer, an intrinsic InP layer, and an N-type InP layer stacked sequentially on the steps; the thickness of the P-type InP layer is 2500 Å, the thickness of the intrinsic InP layer is 6500 Å, and the thickness of the N-type InP layer is 2600 Å.

[0058] (4) A cladding and contact layer are formed in the initial epitaxial structure to obtain the first intermediate; The cladding layer is a P-type InP layer with a thickness of 2.2 μm. The ohmic contact layer is a P-type InGaAs layer with a thickness of 460 nm.

[0059] (5) Form at least one groove on the first intermediate to obtain the second intermediate; The trench is located on one side of the ridge, and both the trench and the ridge extend along a first direction. In the thickness direction, the trench extends into the burial layer. The trench has a depth of 38200 Å, and the distance between the sidewall of the trench and the sidewall of the ridge is 22000 Å.

[0060] Specifically, the trenches are formed using a wet etching process. The process parameters for the wet etching process include: the etching solution is a mixture of phosphoric acid, hydrogen peroxide, and water, with a volume ratio of phosphoric acid, hydrogen peroxide, and water of 1:3:8; the concentration of phosphoric acid is 85wt%, and the concentration of hydrogen peroxide is 35wt%; the etching temperature is 25℃.

[0061] (6) A passivation layer is formed on the surface of the trench and the surface of the contact layer, and the contact layer above the ridge is etched to expose it.

[0062] The passivation layer can be a SiO2 layer with a thickness of 550 nm.

[0063] (7) Forming the first electrode layer; The first electrode layer covers the passivation layer on the surface of the trench, but the first electrode layer exposes part of the passivation layer, that is, it does not cover all the passivation layer outside the trench.

[0064] (8) A second electrode layer is formed on the second surface of the substrate; (9) Bar strip dissociation, cavity surface coating, cutting, testing and sorting are performed to obtain distributed feedback laser chip.

[0065] Example 2 This embodiment provides a method for fabricating a distributed feedback laser chip, which differs from Embodiment 1 in that: Step (2) includes: (2.1) A mask layer is formed and patterned on the first epitaxial structure to expose the initial epitaxial layer of the first predetermined region; The mask layer is a silicon oxide layer.

[0066] (2.2) The initial epitaxial layer of the first preset region is etched to a first preset depth using an ICP etching process; The process parameters for the ICP etching process include: etching gases of Cl2, N2, and Ar, with a Cl2 flow rate of 20 sccm, an Ar flow rate of 18 sccm, and an N2 flow rate of 22 sccm; chamber pressure of 1.8 mtorr; ICP power of 840 W; RF power of 180 W; and etching temperature of 175 °C. The first preset depth is 2200 Å.

[0067] (2.3) The initial epitaxial layer of the first preset region is etched to a second preset depth using a wet etching process to form the ridge and step; The wet etching process parameters include: the etching solution is a mixture of phosphoric acid and hydrochloric acid, with a volume ratio of phosphoric acid to hydrochloric acid of 3:1; the concentration of phosphoric acid is 95 wt%, and the concentration of hydrochloric acid is 34.5 wt%; the etching temperature is 30°C. The second preset depth is 9400 Å.

[0068] Based on the above preparation steps, the ridge includes a first part and a second part sequentially stacked on the etch stop layer. Furthermore, in the direction from the etch stop layer to the cladding, the width of the first part decreases, while the width of the second part increases. The sidewalls of both the first and second parts are arc-shaped.

[0069] Everything else is the same as in Example 1.

[0070] Comparative Example 1 This comparative example provides a method for fabricating a distributed feedback laser chip, which differs from Example 1 in that it does not include step (5), i.e., it does not form a trench.

[0071] Everything else is the same as in Example 1.

[0072] Comparative Example 2 This comparative example provides a method for fabricating a distributed feedback laser chip, which differs from Example 1 in that it does not include steps (2) and (3), i.e., it does not form ridges, steps, and buried layers.

[0073] Everything else is the same as in Example 1.

[0074] The distributed feedback laser chips obtained in Examples 1 and 2, and Comparative Examples 1 and 2 were tested, and the specific performance parameters are as follows:

[0075] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A method for fabricating a distributed feedback laser chip, characterized in that, include: A substrate is provided, and an initial epitaxial layer is formed on a first surface of the substrate; wherein the initial epitaxial layer comprises a lower confinement layer, an etch stop layer, a lower waveguide layer, an active layer, an upper waveguide layer, an upper confinement layer, and a grating layer sequentially stacked on the first surface; The initial epitaxial layer is etched to form ridges and steps that expose the etch stop layer; wherein the ridges extend along a first direction that intersects the thickness direction of the substrate; A buried layer is formed on the step to obtain an initial epitaxial structure; wherein the buried layer encloses the active layer and can block carrier diffusion; A cladding layer and a contact layer are formed in the initial epitaxial structure to obtain a first intermediate. At least one groove is formed on the first intermediate to obtain a second intermediate; wherein the groove is located on one side of the ridge and extends along a first direction; in the thickness direction, the groove extends into the burial layer; A first electrode layer is formed on the second intermediate; wherein the first electrode layer covers the contact layer above the ridge and the trench; A second electrode layer is formed on the second surface of the substrate.

2. The method for fabricating a distributed feedback laser chip as described in claim 1, characterized in that, The refractive index of the buried layer is less than that of the active layer; The burial layer encloses the ridge and exposes the top surface of the ridge.

3. The method for fabricating a distributed feedback laser chip as described in claim 1, characterized in that, The buried layer includes a P-type InP layer, an intrinsic InP layer, and an N-type InP layer stacked sequentially on the step; The thickness of the P-type InP layer is 2000 Å to 10000 Å, the thickness of the intrinsic InP layer is 4000 Å to 10000 Å, and the thickness of the N-type InP layer is 2000 Å to 10000 Å.

4. The method for fabricating a distributed feedback laser chip as described in claim 1, characterized in that, The ridge includes a first part and a second part that are sequentially stacked on the etching stop layer; in the direction from the etching stop layer to the cladding, the width of the first part decreases and the width of the second part increases.

5. The method for fabricating a distributed feedback laser chip as described in claim 4, characterized in that, The step of etching the initial epitaxial layer to form ridges and expose the etch stop layer includes: A mask layer is formed and patterned on the first epitaxial structure to expose the initial epitaxial layer of the first preset region; The initial epitaxial layer of the first preset region is etched to a first preset depth using an ICP etching process; wherein the first preset depth is 2000 Å to 6000 Å. The initial epitaxial layer of the first preset region is etched to a second preset depth using a wet etching process to form the ridges and steps; wherein the second preset depth is 8000Å~15000Å.

6. The method for fabricating a distributed feedback laser chip as described in claim 5, characterized in that, The process parameters for the ICP etching process include: The etching gases are Cl2, N2, and Ar. The flow rate of Cl2 is 5 sccm to 25 sccm, the flow rate of Ar is 15 sccm to 30 sccm, and the flow rate of N2 is 10 sccm to 30 sccm. The chamber pressure is 0.5 mtorr to 3 mtorr, the ICP power is 800 W to 1000 W, the RF power is 100 W to 200 W, and the etching temperature is 150 °C to 200 °C.

7. The method for fabricating a distributed feedback laser chip as described in claim 5, characterized in that, The process parameters for the wet etching include: The etching solution is a mixture of phosphoric acid and hydrochloric acid, with a volume ratio of phosphoric acid to hydrochloric acid of 2:1 to 5:1; the concentration of phosphoric acid is 90wt% to 98wt%, and the concentration of hydrochloric acid is 30wt% to 35wt%. The etching temperature is 20℃~40℃.

8. The method for fabricating a distributed feedback laser chip as described in claim 1, characterized in that, In the step of forming at least one trench on the first intermediate to obtain the second intermediate, the trench is formed by a wet etching process. The process parameters for the wet etching process include: The etching solution is a mixture of phosphoric acid, hydrogen peroxide, and water, with a volume ratio of 1:2:5 to 1:4:10; the concentration of phosphoric acid is 80wt% to 90wt%, and the concentration of hydrogen peroxide is 20wt% to 40wt%. The etching temperature is 20℃~40℃.

9. The method for fabricating a distributed feedback laser chip as described in claim 1, characterized in that, In the step of forming at least one groove on the first intermediate to obtain the second intermediate: A groove is formed on each side of the ridge, and the depth of the groove is 30,000 Å to 50,000 Å. The distance between the sidewall of the groove and the sidewall of the ridge is 15000Å to 25000Å.

10. A distributed feedback laser chip, characterized in that, It is prepared by the method for preparing a distributed feedback laser chip as described in any one of claims 1 to 9.

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