Semiconductor wafer

Abstract

This invention provides a semiconductor wafer, comprising, for example: a base wafer having a first surface and a second surface opposite to the first surface, the base wafer being configured with a plurality of spaced-apart hole structures, each of the hole structures extending from the first surface toward the second surface, the base wafer being a non-gallium nitride (GaN) material; and a GaN layer formed at least within each of the hole structures. By configuring a plurality of spaced-apart hole structures on a non-GaN base wafer and then forming a GaN layer within each hole structure to obtain the semiconductor wafer, the fabrication cost of the non-GaN base wafer is lower than that of a traditional GaN single-crystal wafer, and it is easier to scale up. Therefore, applying this semiconductor wafer to fabricate GaN power devices or epitaxial structures can reduce device costs, thereby facilitating the mass production and commercialization of GaN power devices or epitaxial structures.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor wafer. Background Technology

[0002] Power devices, such as gallium nitride (GaN) power devices, can be categorized into lateral GaN power devices and vertical GaN power devices based on their structure. Lateral GaN power devices are suitable for high-frequency and medium-power applications, while vertical GaN power devices can be used in high-frequency modules, offering advantages such as high voltage withstand capability and small device area. However, vertical GaN power devices are typically fabricated using GaN monocrystalline wafers as substrates. The current mainstream size of GaN monocrystalline wafers is 2-4 inches, and they are expensive, making it difficult to fabricate 6-8 inch or larger sizes. This negatively impacts the mass production and commercialization of GaN power devices, especially vertical GaN power devices. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a semiconductor wafer that is beneficial to the mass production and commercialization of GaN power devices.

[0004] Specifically, an embodiment of the present invention provides a semiconductor wafer, for example comprising: a base wafer having a first surface and a second surface opposite to the first surface, wherein the base wafer is configured with a plurality of spaced-apart hole structures, and each of the hole structures extends from the first surface toward the second surface, the base wafer being a non-gallium nitride material; and a gallium nitride layer formed at least in each of the hole structures.

[0005] The above embodiments of the present invention can have the following beneficial effects: by configuring a plurality of mutually spaced hole structures on a base wafer of non-gallium nitride material, and then forming a gallium nitride layer in each hole structure to obtain the semiconductor wafer, since the manufacturing cost of the base wafer of non-gallium nitride material is lower than that of traditional gallium nitride single crystal wafers and is easy to scale up, the semiconductor wafer of this embodiment can be used to manufacture power devices such as GaN power devices or epitaxial structures required for power devices, thereby reducing device costs and facilitating the mass production and commercialization of GaN power devices or epitaxial structures. Attached Figure Description

[0006] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0007] Figure 1A This is a three-dimensional structural diagram of a semiconductor wafer provided in an embodiment of the present invention.

[0008] Figure 1B for Figure 1A A schematic diagram of the three-dimensional structure of the semiconductor wafer from another perspective.

[0009] Figure 2 for Figure 1A The diagram shows a cross-sectional structure of a semiconductor wafer along section line II-II.

[0010] Figure 3A This is a schematic cross-sectional view of another semiconductor wafer provided in an embodiment of the present invention.

[0011] Figure 3B This is a schematic diagram of a cross-sectional structure of another semiconductor wafer provided in an embodiment of the present invention.

[0012] Figure 4 This is a schematic diagram of a three-dimensional structure of a semiconductor wafer provided in an embodiment of the present invention.

[0013] Figure 5 for Figure 4 The diagram shows a cross-sectional structure of a semiconductor wafer along section line VV.

[0014] Figure 6A This is a schematic diagram of another cross-sectional structure of a semiconductor wafer provided in an embodiment of the present invention.

[0015] Figure 6B This is a schematic diagram of a cross-sectional structure of a semiconductor wafer provided in an embodiment of the present invention.

[0016] Figure 7 This is a three-dimensional structural diagram of another semiconductor wafer provided in an embodiment of the present invention.

[0017] Figure 8 for Figure 7 The diagram shows a cross-sectional structure of a semiconductor wafer along section line VIII-VIII.

[0018] Figure 9A This is a schematic diagram of another cross-sectional structure of a semiconductor wafer provided in an embodiment of the present invention.

[0019] Figure 9B This is a schematic diagram of another cross-sectional structure of a semiconductor wafer provided in an embodiment of the present invention.

[0020] Figure 10 This is a three-dimensional structural diagram of another semiconductor wafer provided in an embodiment of the present invention.

[0021] Figure 11 for Figure 10 The diagram shows a cross-sectional structure of a semiconductor wafer along section line XI-XI.

[0022] [Explanation of Key Figure Markings]

[0023] 11. Base wafer; 11g. Hole structure; 11B. First surface; 11T. Second surface; 13. Gallium nitride layer; 131. Third surface; 132. Fourth surface; B1. First orientation; 15. Transition layer; d. Spacing. Detailed Implementation

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0025] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0028] See Figure 1A , Figure 1B and Figure 2 The present invention provides a semiconductor wafer, which includes, for example, a base wafer 11 and a gallium nitride layer 13.

[0029] The base wafer 11 has a first surface 11B and a second surface 11T opposite to the first surface 11B. The base wafer 11 is configured with a plurality of spaced-apart hole structures 11g, for example, arranged in an array, with each hole structure 11g extending from the first surface 11B toward the second surface 11T. The base wafer 11 is made of a non-gallium nitride material, such as a silicon carbide (SiC) single-crystal wafer, a sapphire single-crystal wafer, or a silicon (Si) single-crystal wafer, etc., but this embodiment of the invention is not limited thereto. SiC single-crystal wafers and sapphire single-crystal wafers can reach 6-8 inches. SiC single-crystal wafers have better thermal and electrical conductivity than sapphire single-crystal wafers and can withstand higher temperatures; silicon single-crystal wafers can reach 12 inches or even larger. Furthermore, the silicon single-crystal wafer can be a Si(111), Si(100), or Si(110) wafer.

[0030] As described above, the gallium nitride layer 13 is formed at least within each of the said pore structures 11g. The gallium nitride layer 13 can be formed using epitaxial growth methods such as hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or metal-organic chemical vapor deposition (MOCVD), but the embodiments of the present invention are not limited thereto.

[0031] In this embodiment of the invention, a semiconductor wafer is obtained by configuring a plurality of spaced-apart hole structures 11g on a base wafer 11 made of non-gallium nitride material and then forming a gallium nitride layer 13 in each hole structure 11g. Since the manufacturing cost of the base wafer 11 made of non-gallium nitride material is lower than that of traditional gallium nitride single crystal wafers and is easy to scale up, the semiconductor wafer of this embodiment of the invention can be used to manufacture power devices such as GaN power devices (especially vertical GaN power devices) or epitaxial structures required for power devices, thereby reducing device costs and facilitating the mass production and commercialization of GaN power devices or epitaxial structures. It is worth mentioning that for vertical GaN power devices fabricated using traditional gallium nitride single-crystal wafers, there are some unused gallium nitride single-crystal wafer regions. These include gallium nitride single-crystal wafer regions between multiple vertical GaN power devices fabricated on the same gallium nitride single-crystal wafer, gallium nitride single-crystal wafer regions directly below the current blocking layer of a single vertical GaN power device, and edge regions of the gallium nitride single-crystal wafer, etc. Therefore, it is possible to use the base wafer 11 to replace these unused regions, thereby making it feasible to apply the semiconductor wafer of the present invention to the fabrication of GaN power devices, especially vertical GaN power devices.

[0032] In some embodiments, such as Figure 2 As shown, the spacing d between two adjacent hole structures 11g ranges from 5 micrometers (μm) to 200 micrometers. During device fabrication, a device array is first fabricated on the semiconductor wafer, and then the device array is cut into independent individual devices. The cutting method can be sawing, laser cutting, or plasma dicing, etc. Consequently, a portion of the semiconductor wafer needs to be used as a dicing line (or saw line). However, if the dicing line width is too small, the precision requirements during the cutting process may be too high, making it difficult to accurately control the cutting path, especially in high-density circuit areas, where even a small deviation can cause a single device to fail. Conversely, if the dicing line width is too large, the loss during the cutting process is greater, leading to more material waste and reducing the number of individual devices on each semiconductor wafer, thereby reducing the utilization rate of the semiconductor wafer. Therefore, in this embodiment, the spacing d between two adjacent hole structures 11g is designed to be in the range of 5μm-200μm to form the dicing channel, thereby achieving a higher utilization rate of the semiconductor wafer.

[0033] In some embodiments, such as Figure 1A , Figure 1B and Figure 2As shown, the projected area of ​​each of the hole structures 11g along the first direction B1 on the base wafer 11 is within the range of 0.016 mm. 2 -160mm 2 The first direction B1 is the direction from the first surface 11B to the second surface 11T. The projected area here is equal to the opening area of ​​the larger opening at both ends of the hole structure 11g. Figure 2 For example, the projected area is equal to the opening area of ​​the hole structure 11g on the first surface 11B. It is worth noting that for a single device, such as a vertical GaN device, its side length is typically between 0.1 mm and 10 mm. To ensure that the gallium nitride layer 13 within a single hole structure 11g can be used to fabricate a vertical GaN device to improve device performance, the projected area of ​​each hole structure 11g along the first direction B1 on the base wafer 11 is designed to be within the range of 0.016 mm. 2 -160mm 2 This allows a single device to be fabricated using the gallium nitride layer within the single-hole structure 11g, eliminating the need for dicing between adjacent devices to occupy the area of ​​the gallium nitride layer 13, thus improving the utilization rate of the semiconductor wafer. It should be noted that the semiconductor wafer used in this embodiment is not limited to the fabrication of vertical GaN devices; other devices traditionally fabricated using GaN single-crystal wafers can also be employed.

[0034] In some embodiments, such as Figure 1A , Figure 1B and Figure 2 As shown, in the semiconductor wafer, each of the via structures 11g is a through-hole extending from the first surface 11B to the second surface 11T; the gallium nitride layer 13 has a third surface 131 and a fourth surface 132 opposite to the third surface 131; the third surface 131 is flush with the first surface 11B, and the fourth surface 132 is flush with the second surface 11T. Furthermore, the opening size of the via structure 11g gradually decreases in a first direction B1 from the first surface 11B to the second surface 11T, for example, gradually decreasing, that is, the via structure 11g is a tapered through-hole; in this way, when the first surface 11B serves as the electrode contact surface of the device, a larger contact area between the electrode and the gallium nitride layer 13 can be achieved to reduce the contact resistance; or, when the first surface 11B serves as the epitaxial growth surface of the device, it is beneficial to provide a larger GaN area for epitaxial growth to improve the quality of the epitaxially grown crystal. Furthermore, the thickness of the gallium nitride layer 13 in the first direction B1 is equal to the depth of the hole structure 11g in the first direction B1, thus having the advantage of less stress accumulation.

[0035] See Figure 3A In some embodiments, Figure 2 The semiconductor wafer shown may also include a transition layer 15, which is formed on the sidewalls of each hole structure 11g and located between the base wafer 11 and the gallium nitride layer 13. For example, the transition layer 15 may be a nucleation layer such as an AlN layer, or a stress-relieving layer such as an AlN layer, an AlGaN layer, or an AlN / AlGaN stack, or a stack of both the stress-relieving layer and the nucleation layer. In this embodiment, when the transition layer 15 is a nucleation layer, it can reduce lattice defects in the gallium nitride layer 13 and improve the crystal quality of the gallium nitride layer 13; or when the transition layer 15 is a stress-relieving layer, it can alleviate stress concentration within the semiconductor wafer and improve its electrical and mechanical properties.

[0036] See Figure 3B In some embodiments, the opening size of each of the hole structures 11g remains constant along a first direction B1 from the first surface 11B to the second surface 11T. This allows for a balance between the electrode contact surface size and the epitaxial growth surface size when using the semiconductor wafer to fabricate vertical devices, thereby balancing contact resistance and epitaxial crystal quality. Furthermore, the thickness of the gallium nitride layer 13 along the first direction B1 is equal to the depth of the hole structure 11g along the first direction B1, resulting in less stress accumulation.

[0037] See Figure 4 and Figure 5 In some embodiments, the semiconductor wafer includes, for example, a base wafer 11 and a gallium nitride layer 13. The base wafer 11 has a first surface 11B and a second surface 11T opposite to the first surface 11B. The base wafer 11 is configured with a plurality of spaced-apart hole structures 11g, for example, arranged in an array, and each hole structure 11g extends from the first surface 11B toward the second surface 11T. The base wafer 11 is made of a non-gallium nitride material. The gallium nitride layer 13 is formed within each hole structure 11g and extends to the first surface 11B of the base wafer 11. More specifically, as... Figure 5As shown, each of the hole structures 11g is a through-hole extending from the first surface 11B to the second surface 11T; the gallium nitride layer 13 has a third surface 131 and a fourth surface 132 opposite to the third surface 131; the third surface 131 at least partially, for example, completely covers the first surface 11B in a first direction B1 from the first surface 11B to the second surface 11T, and the fourth surface 132 is flush with the second surface 11T. Furthermore, the opening size of the hole structure 11g gradually decreases in the first direction B1, for example, gradually shrinking. In addition, the thickness of the gallium nitride layer 13 in the first direction B1 is greater than the depth of the hole structure 11g in the first direction B1, and its fabrication process is relatively simple, for example, it does not require CMP (Chemical Mechanical Polishing) to grind the gallium nitride layer 13 to be flush with the base wafer 11.

[0038] See Figure 6A In some embodiments, Figure 5 The semiconductor wafer shown may also include, for example, a transition layer 15 formed on the sidewalls of each via structure 11g and extending to the first surface 11B, located between the base wafer 11 and the gallium nitride layer 13. For example, the transition layer 15 may be a nucleation layer such as an AlN layer, or a stress-relieving layer such as an AlN layer, an AlGaN layer, or an AlN / AlGaN stack, or a stack of both the stress-relieving layer and the nucleation layer.

[0039] See Figure 6B In some embodiments, each of the hole structures 11g is a through-hole extending from the first surface 11B to the second surface 11T, and the opening size of the hole structure 11g gradually increases in the first direction B1. The gallium nitride layer 13 is formed within each hole structure 11g and extends to cover the first surface 11B of the base wafer 11.

[0040] See Figure 7 and Figure 8In some embodiments, the semiconductor wafer includes, for example, a base wafer 11 and a gallium nitride layer 13. The base wafer 11 has a first surface 11B and a second surface 11T opposite to the first surface 11B. The base wafer 11 is configured with a plurality of spaced-apart hole structures 11g, for example, arranged in an array, with each hole structure 11g extending from the first surface 11B toward the second surface 11T. The base wafer 11 is made of a non-gallium nitride material. The gallium nitride layer 13 is formed within each hole structure 11g. More specifically, each of the hole structures 11g extends from the first surface 11B toward the second surface 11T but does not penetrate the second surface 11T; the gallium nitride layer 13 has a third surface 131 and a fourth surface 132 opposite to the third surface 131; the third surface 131 is flush with the first surface 11B, and the fourth surface 132 is located between the first surface 11B and the second surface 11T in a first direction B1 from the first surface 11B to the second surface 11T. Furthermore, the opening size of the hole structure 11g gradually decreases in the first direction B1, for example, gradually shrinking, that is, the hole structure 11g is a conical groove. Furthermore, the thickness of the gallium nitride layer 13 in the first direction B1 is equal to the depth of the hole structure 11g in the first direction B1, thus having the advantage of low stress accumulation. It is worth mentioning here that when... Figure 7 and Figure 8 When the semiconductor wafer shown is used to fabricate power devices such as GaN power devices, the second surface 11T of the base wafer 11 can be ground to thin and remove contaminants until the fourth surface 132 of the gallium nitride layer 13 is exposed. This can further improve the utilization rate of the gallium nitride layer 13. This is because contaminants are unavoidable on the surface of the semiconductor wafer during transportation, so thinning and decontamination treatment is required before subsequent device epitaxial growth. The second surface 11T here can act as a protective layer to protect the fourth surface 132 of the gallium nitride layer 13 from contamination. In other words, the second surface 11T of the base wafer 11 is processed until the fourth surface 132 is exposed, and then used as the epitaxial growth surface for fabricating semiconductor devices.

[0041] See Figure 9A In some embodiments, Figure 8 The semiconductor wafer shown may also include, for example, a transition layer 15 formed on the sidewalls of each hole structure 11g and located between the base wafer 11 and the gallium nitride layer 13. For example, the transition layer 15 may be a nucleation layer such as an AlN layer, or a stress-relieving layer such as an AlN layer, an AlGaN layer, or an AlN / AlGaN stack, or a stack of both the stress-relieving layer and the nucleation layer.

[0042] See Figure 9B In some embodiments, each of the hole structures 11g extends from the first surface 11B toward the second surface 11T but does not penetrate the second surface 11T, and the opening size of the hole structure 11g gradually increases, for example, in a first direction B1 from the first surface 11B to the second surface 11T.

[0043] See Figure 10 and Figure 11 In some embodiments, the semiconductor wafer includes, for example, a base wafer 11 and a gallium nitride layer 13. The base wafer 11 has a first surface 11B and a second surface 11T opposite to the first surface 11B. The base wafer 11 is configured with a plurality of spaced-apart hole structures 11g, for example, arranged in an array, and each hole structure 11g extends from the first surface 11B toward the second surface 11T. The base wafer 11 is made of a non-gallium nitride material. The gallium nitride layer 13 is formed within each hole structure 11g and extends to the first surface 11B of the base wafer 11. More specifically, as... Figure 11 As shown, each of the hole structures 11g extends from the first surface 11B toward the second surface 11T but does not penetrate the second surface 11T; the gallium nitride layer 13 has a third surface 131 and a fourth surface 132 opposite to the third surface 131; the third surface 131 at least partially, for example, completely covers the first surface 11B in a first direction B1 from the first surface 11B to the second surface 11T, and the fourth surface 132 is located between the first surface 11B and the second surface 11T. Furthermore, the opening size of the hole structure 11g gradually decreases in the first direction B1, for example, gradually shrinking. In addition, the thickness of the gallium nitride layer 13 in the first direction B1 is greater than the depth of the hole structure 11g in the first direction B1, and its fabrication process is relatively simple, for example, it is not necessary to use CMP to grind the gallium nitride layer 13 to the same plane as the base wafer 11.

[0044] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A semiconductor wafer, characterized in that, include: A base wafer has a first surface and a second surface opposite to the first surface, wherein the base wafer is configured with a plurality of spaced-apart hole structures, and each of the hole structures extends from the first surface toward the second surface, and the base wafer is a non-gallium nitride material; as well as A gallium nitride layer is formed at least within each of the said pore structures.

2. The semiconductor wafer according to claim 1, characterized in that, The spacing between two adjacent hole structures is in the range of 5μm-200μm.

3. The semiconductor wafer according to claim 1, characterized in that, The projected area of ​​each of the aforementioned hole structures on the base wafer along the first direction is within the range of 0.016 mm. 2 -160mm 2 The first direction is the direction from the first surface to the second surface.

4. The semiconductor wafer according to claim 1, characterized in that, Each of the hole structures is a through hole extending from the first surface to the second surface.

5. The semiconductor wafer according to claim 4, characterized in that, The gallium nitride layer has a third surface and a fourth surface opposite to the third surface; The third surface is flush with the first surface, and the fourth surface is flush with the second surface; or, The third surface at least partially covers the first surface in a first direction from the first surface to the second surface, and the fourth surface is flush with the second surface.

6. The semiconductor wafer according to claim 1, characterized in that, Each of the hole structures extends from the first surface toward the second surface but does not penetrate the second surface.

7. The semiconductor wafer according to claim 6, characterized in that, The gallium nitride layer has a third surface and a fourth surface opposite to the third surface; The third surface is flush with the first surface, and the fourth surface is located between the first surface and the second surface in a first direction from the first surface to the second surface; or The third surface at least partially covers the first surface in a first direction from the first surface to the second surface, and the fourth surface is located between the first surface and the second surface.

8. The semiconductor wafer according to claim 7, characterized in that, The second surface of the base wafer is processed until the fourth surface is exposed, which serves as the epitaxial growth surface for fabricating semiconductor devices.

9. The semiconductor wafer according to claim 1, characterized in that, Also includes: A transition layer is formed at least on the sidewall of each of the said hole structures and located between the base wafer and the gallium nitride layer; wherein the transition layer is a nucleation layer, a stress relief layer, or a stack of both.

10. The semiconductor wafer according to claim 1, characterized in that, The opening size of each of the hole structures either varies gradually or remains constant in a first direction from the first surface to the second surface.

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