Wafer level CSP light source package deviation tracing positioning system

Abstract

The present application relates to the technical field of wafer level detection and process tracing of semiconductor light source devices, and particularly relates to a wafer level CSP light source package deviation tracing positioning system, which acquires wafer identification and chip coordinates, collects package deviation and pulse forward voltage of a unit, calculates deviation multi-domain complexity, node temperature transient and drift, fuses into a risk index and controls encrypted sampling and current / duty cycle scanning with double thresholds, generates a hierarchical wafer map with deviation code levels and outputs positioning results combined with process tracing, binds coordinates and voltage deviation data, unifies complexity + thermal drift into a risk index, adaptively encrypts and scans according to double thresholds, and accurately positions by combining a hierarchical wafer map with process tracing.

Description

Technical Field

[0001] This invention relates to the field of wafer-level inspection and process traceability technology for semiconductor light source devices, and more specifically, to a wafer-level CSP light source packaging deviation traceability and positioning system. Background Technology

[0002] Wafer-level chip-scale packaged light sources complete the packaging, interconnection, and partial forming processes at the wafer level, featuring high batch processing efficiency, good device consistency, and simplified back-end assembly. However, due to factors such as curing shrinkage of the packaging layer material, pattern transfer errors, alignment misalignment, differences in metal interconnect forming, uneven stress release, and localized temperature rise, spatially uneven packaging deviations may occur between different chip units on the same wafer. These deviations may manifest as geometric shape shifts or further affect the electrical operating point and thermal path, thus causing forward voltage fluctuations and differences in the dynamic response of the junction temperature under pulsed operating conditions.

[0003] Existing solutions typically acquire deviation information through optical measurement, morphology inspection, or electrical sampling, and mark the locations using a wafer map. For process traceability, abnormal locations are often associated with batch numbers, equipment identifiers, formula versions, and key process curves to help pinpoint potential process steps. While these solutions meet basic screening and empirical analysis needs, in scenarios with a large number of wafer locations, complex packaging deviation morphologies, and thermoelectric coupling effects, engineering often requires a trade-off between measurement overhead and positioning accuracy. On the one hand, using fixed-resolution, full-wafer high-density sampling significantly increases the burden of acquisition and analysis; on the other hand, only unit-level sparse sampling or sampling may struggle to capture fine-grained deviation textures in high-risk local areas, and may also fail to cover sensitive ranges where deviations amplify with varying driving current and duty cycle. In addition, in existing processes, packaging deviation and thermal response information are often presented as parallel indicators, lacking a unified and comparable risk characterization to guide the hierarchical sampling strategy. There is also a lack of a way to hierarchically organize unit packaging deviation data, sub-unit packaging deviation data and scan packaging deviation data and map them to a layered wafer map. As a result, there is still room for improvement in the interpretability of traceability conclusions in terms of spatial details, operating condition evidence and process correlation.

[0004] Therefore, a demand has gradually formed in the industry: to combine the spatial complexity quantification results of packaging deviation with the dynamic response offset of node temperature to form a risk classification basis, and then adaptively decide whether to establish sub-cell coordinate encryption sampling and whether to perform drive current and drive duty cycle scanning, and finally integrate with the process traceability data associated with wafer identification to output more targeted traceability and positioning results. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a wafer-level CSP light source packaging deviation traceability and positioning system.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A wafer-level CSP light source packaging deviation traceability and positioning system includes: The data acquisition module is used to obtain the wafer identifier of the wafer under test; obtain the chip cell coordinates of each chip cell on the wafer under test; collect the cell packaging deviation data for each chip cell coordinate; and collect the forward voltage data under preset pulse excitation. The forward voltage data includes the forward voltage sampling sequence, and a data record is generated for each chip cell coordinate. The index calculation module is used to construct a deviation feature map based on the unit packaging deviation data and calculate the deviation multi-domain complexity value based on the deviation feature map; it is also used to obtain the node temperature transient sequence based on the forward voltage sampling sequence, the preset pulse excitation and the thermoelectric coupling calibration model, and to obtain the node temperature dynamic response drift value based on the difference between the node temperature transient sequence and the preset reference node temperature transient sequence. The preset reference node temperature transient sequence is the node temperature transient sequence corresponding to the reference chip unit under the same excitation conditions as the preset pulse excitation. The dynamic control module is used to calculate the deviation thermal coupling risk index based on the deviation multi-domain complexity value and the node temperature dynamic response drift value, and compare the deviation thermal coupling risk index with the preset first-level threshold and the preset second-level threshold. The dynamic control module is used to control the data acquisition module to establish sub-unit coordinates in the chip unit coordinates according to the comparison results and to collect packaging deviation data at the sub-unit coordinates as sub-unit packaging deviation data, and / or to perform drive current and drive duty cycle scanning based on the sub-unit coordinates and collect packaging deviation data during the scanning process as scan packaging deviation data. The traceability and positioning module is used to generate a wafer map, mark the packaging deviation code and packaging deviation level on the wafer map, and output the traceability and positioning results of the packaging deviation by combining the process traceability data associated with the wafer identifier.

[0007] Furthermore, the data record corresponds to the wafer identifier and the corresponding chip cell coordinates, and the data record includes at least the wafer identifier, chip cell coordinates, cell packaging deviation data, and forward voltage data.

[0008] Furthermore, the data acquisition module includes a probe station, an imaging detection unit, and an electrical measurement unit; the probe station positions the chip unit point by point according to the chip unit coordinates; the imaging detection unit acquires the packaged image and calculates the deviation through sub-pixel matching or edge fitting to generate unit packaged deviation data; the electrical measurement unit acquires a positive voltage sampling sequence as positive voltage data under preset pulse excitation and writes it into the corresponding data record.

[0009] Furthermore, the deviation feature map is used to characterize the spatial distribution of deviations within the coordinates of the chip unit; the index calculation module extracts the deviation distribution entropy component, directional consistency component, and periodic clustering component from the deviation feature map, normalizes the deviation distribution entropy component, directional consistency component, and periodic clustering component, and fuses them according to preset weights to obtain the deviation multi-domain complexity value.

[0010] Furthermore, the method for obtaining the transient sequence of node temperature includes: determining the pulse on-time and pulse off-time according to the preset pulse excitation; extracting the sampling points corresponding to the pulse on-time and / or pulse off-time from the forward voltage sampling sequence to form a transient forward voltage sequence; inputting the transient forward voltage sequence into the thermoelectric coupling calibration model for conversion to obtain the transient sequence of node temperature corresponding to the sampling time.

[0011] Furthermore, the thermoelectric coupling calibration model is a parameterized conversion function or lookup table established from the calibration data; the preset reference node temperature transient sequence is obtained by inputting the reference forward voltage sampling sequence into the thermoelectric coupling calibration model for conversion, and the reference forward voltage sampling sequence is the forward voltage sampling sequence collected by the reference chip unit under the same excitation conditions as the preset pulse excitation.

[0012] Furthermore, the method for obtaining the node temperature dynamic response drift value includes: aligning the node temperature transient sequence with a preset reference node temperature transient sequence at the trigger time of a preset pulse excitation; mapping the time-aligned node temperature transient sequence and the preset reference node temperature transient sequence to the same sampling time set within a preset evaluation time window; taking the absolute value of the temperature difference at each sampling time in the same sampling time set and summing or numerically integrating it to obtain the cumulative difference value; normalizing the cumulative difference value according to the temperature rise amplitude of the preset reference node temperature transient sequence within the preset evaluation time window to obtain the node temperature dynamic response drift value.

[0013] Furthermore, the method for obtaining the deviation thermal coupling risk index includes: normalizing the deviation multi-domain complexity value and the node temperature dynamic response drift value, and then performing fusion calculation according to the preset fusion weight to obtain the deviation thermal coupling risk index.

[0014] Furthermore, when the deviation thermal coupling risk index is less than the preset first-level threshold, only unit packaging deviation data is collected; when the deviation thermal coupling risk index is greater than or equal to the preset first-level threshold and less than the preset second-level threshold, sub-unit coordinates are established and sub-unit packaging deviation data is collected according to the sampling resolution enhancement coefficient dynamically set by the deviation thermal coupling risk index; when the deviation thermal coupling risk index is greater than or equal to the preset second-level threshold, based on the collected sub-unit packaging deviation data, the scanning range or scanning step size of the drive current and drive duty cycle is dynamically set according to the deviation thermal coupling risk index, and drive current and drive duty cycle scanning is performed to collect scanning packaging deviation data.

[0015] Furthermore, the wafer map is a layered wafer map, and the traceability and positioning module generates the layered wafer map based on unit packaging deviation data, sub-unit packaging deviation data, and scan packaging deviation data.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention uses wafer identifiers and chip unit coordinates as a unified index to bind unit packaging deviation data and forward voltage sampling sequence under preset pulse excitation in the same data record, so that packaging geometric deviation and electrical response are naturally aligned at the point level, reducing coordinate drift and inconsistency caused by cross-process and cross-equipment data splicing, and providing a consistent and verifiable data foundation for subsequent index calculation, hierarchical control and traceability analysis; By constructing a deviation feature map based on unit package deviation data and calculating the deviation multi-domain complexity value, and by using a forward voltage sampling sequence, a preset pulse excitation and a thermoelectric coupling calibration model to obtain a node temperature transient sequence, and then comparing it with a preset reference node temperature transient sequence to obtain the node temperature dynamic response drift value, the deviation thermal coupling risk index is formed. This achieves a joint quantitative characterization of the package deviation morphological complexity and thermal dynamic anomaly, improving risk judgment from a single dimension to a comparable, gradeable and interpretable unified scale, thereby more sensitively identifying coupling anomalies related to reliability and reducing the probability of missed detection. Guided by the risk index of deviation thermal coupling and the grading results of preset first-level and preset second-level thresholds, the system triggers the establishment of sub-unit coordinates within the chip unit coordinates and collects sub-unit packaging deviation data as needed, and / or performs drive current and drive duty cycle scanning and collects scan packaging deviation data. This allows measurement resources to adaptively focus on key areas and key operating conditions according to the risk level, obtaining higher resolution spatial evidence and more sufficient operating condition response evidence while controlling overall testing costs. Furthermore, based on unit packaging deviation data, sub-unit packaging deviation data, and scanned packaging deviation data, a layered wafer map is generated and package deviation codes and packaging deviation levels are marked. Combined with process traceability data associated with wafer identification, the traceability and positioning results are output, enabling anomaly points to be presented simultaneously at the spatial, severity, and process-related levels. This improves the directionality of the positioning conclusions for batch, equipment, and formulation factors and the efficiency of closed-loop improvement. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of a wafer-level CSP light source packaging deviation tracking and positioning system. Figure 2 This is a schematic diagram illustrating the composition and unit packaging of the data acquisition module of the present invention, as well as the acquisition, recording, and generation of deviation data and positive voltage data. Figure 3This is a schematic diagram illustrating the calculation of the deviation multi-domain complexity value, the node temperature dynamic response drift value, and the hierarchical dynamic control of the deviation thermal coupling risk index in this invention. Figure 4 This is a schematic diagram illustrating the generation of a layered wafer map based on unit / subunit / scan packaging deviation data and the output of traceability and positioning results in conjunction with process traceability data according to the present invention. Detailed Implementation

[0018] Reference Figures 1 to 4 A wafer-level CSP light source packaging deviation traceability and positioning system, comprising: The data acquisition module is used to obtain the wafer identifier of the wafer under test. By obtaining the wafer identifier of the wafer under test, a unique correspondence is established between all subsequent measurement data and the specific wafer under test, providing a basic index for the association, comparison and positioning of subsequent "process traceability data", ensuring that the starting point of the traceability chain is clear and traceable.

[0019] Obtain the chip cell coordinates of each chip cell on the wafer under test; by obtaining the chip cell coordinates of each chip cell on the wafer under test, the spatial position on the wafer under test is expressed in a structured way, so that the cell packaging deviation data and spatial distribution have a coordinate basis, thereby supporting the subsequent generation of wafer maps and the localization of abnormal distributions.

[0020] For each chip unit coordinate, unit packaging deviation data is collected. The chip unit coordinate is used as the smallest positioning unit to collect unit packaging deviation data, so that the packaging deviation has a "position-value" correspondence, providing the original data source for subsequent construction of deviation feature map, calculation of deviation multi-domain complexity value and generation of wafer map.

[0021] The system acquires forward voltage data under preset pulse excitation. The forward voltage data includes a forward voltage sampling sequence. Under the preset pulse excitation constraint, a forward voltage sampling sequence with time series characteristics is obtained, so that the electrical response can correspond to the transient process. This creates input conditions for obtaining the junction temperature transient sequence through the thermoelectric coupling calibration model. At the same time, it ensures that the measurement conditions between different chip units are consistent, which facilitates the comparison with the preset reference junction temperature transient sequence.

[0022] A data record is generated for each chip unit coordinate; wafer identification, chip unit coordinates, unit packaging deviation data, forward voltage data, etc. are organized in the same data record, so that the "deviation-electrical-identification" information of each chip unit coordinate forms the smallest traceable, calculable, and associative data unit, which facilitates the unified use of subsequent indicator calculation modules and traceability positioning modules.

[0023] In one specific implementation, a probe station, an imaging detection unit, and an electrical measurement unit are used to perform point-by-point packaging deviation and electrical data acquisition on the wafer under test. The wafer identifier of the wafer is read, and after the wafer is loaded onto the probe station, a wafer coordinate reference is established. The chip unit coordinates of each chip cell on the wafer are acquired according to a preset traversal order. The probe station positions the chip cells point-by-point based on their coordinates, and after stable positioning, triggers the imaging detection unit to acquire the corresponding packaging image. The imaging detection unit uses a reference image or reference structure boundary as an alignment basis, performs sub-pixel matching or edge fitting on key boundaries or key features in the packaging image to calculate the deviation, thereby outputting unit packaging deviation data that corresponds one-to-one with the chip cell coordinates. For example, when the chip cell coordinates are (12, 34), the unit packaging deviation data at that position is obtained and its association with the wafer identifier is maintained. After completing the acquisition of unit packaging deviation data, the electrical testing unit applies a preset pulse excitation to the same chip unit and acquires forward voltage data during the preset pulse excitation. The forward voltage data includes a forward voltage sampling sequence arranged in chronological order, and the forward voltage sampling sequence corresponds to the triggering sequence of the preset pulse excitation to ensure that the sampling of different chip units under the same excitation conditions is comparable. A data record is generated for each chip unit coordinate. The data record corresponds to the wafer identifier and the corresponding chip unit coordinate. The data record contains at least the wafer identifier, chip unit coordinate, unit packaging deviation data, and forward voltage data. The forward voltage sampling sequence is written as forward voltage data into the corresponding data record to form a searchable data entry. For example, the packaging deviation data of the unit with wafer identifier W20260323-01 and chip unit coordinate (12,34) and the forward voltage sampling sequence acquired by the chip unit under the preset pulse excitation are written into the same data record, thereby realizing the correspondence between unit packaging deviation data and forward voltage data by wafer identifier and precise positioning by chip unit coordinate.

[0024] In one optional implementation, the preset pulse excitation employs a two-stage current timing sequence: first, the driving current... Continuous conduction As a heating section, it then switches to measuring current at the moment of shutdown. (Preferably the rated drive current) ), and during the shutdown period Initial preset sampling delay Then, the forward voltage was collected. The influence of nonlinearity and self-heating superposition on nodal temperature conversion; among which The sampling duration covers the initial recovery phase of the shutdown.

[0025] The index calculation module is used to construct a deviation feature map based on the unit encapsulation deviation data and calculate the deviation multi-domain complexity value based on the deviation feature map. It organizes the unit encapsulation deviation data from discrete measurement values ​​into a deviation feature map that can reflect the spatial distribution characteristics, so that the "distribution pattern" of the deviation can be quantitatively described. On this basis, the deviation multi-domain complexity value is calculated to express the complexity, heterogeneity or clustering characteristics of the deviation distribution with a single index, thereby providing an important input for the subsequent deviation thermal coupling risk index to characterize the encapsulation deviation pattern.

[0026] The transient sequence of node temperature is obtained based on the forward voltage sampling sequence, preset pulse excitation and thermoelectric coupling calibration model. The dynamic change of the forward voltage sampling sequence under preset pulse excitation conditions is converted into the transient sequence of node temperature through the thermoelectric coupling calibration model, so that the coordinates of each chip unit can obtain a comparable "temperature change over time" characterization, thereby transforming the electrical sampling results into temperature domain data that can be used for thermal response evaluation.

[0027] The node temperature dynamic response drift value is obtained based on the difference between the node temperature transient sequence and the preset reference node temperature transient sequence. The preset reference node temperature transient sequence is the node temperature transient sequence of the reference chip unit under the same excitation conditions as the preset pulse excitation. Using the preset reference node temperature transient sequence as a benchmark, the degree of deviation of the node temperature transient sequence of the chip unit under test relative to the reference chip unit is measured, and this deviation is condensed into the node temperature dynamic response drift value. This drift value is used to reflect the difference level between the thermal dynamic response of the chip unit under test and the reference chip unit under the same preset pulse excitation conditions, thereby providing thermal response dimension input for the subsequent deviation thermal coupling risk index.

[0028] In one specific implementation, for the unit packaging deviation data already obtained within the same chip unit coordinate range, the following steps are performed sequentially to obtain the deviation multi-domain complexity value: Construct a deviation feature map, establish a two-dimensional coordinate grid corresponding one-to-one with the spatial position based on the chip unit coordinates, map the unit packaging deviation data at each chip unit coordinate to the deviation amount of the grid node, and use neighborhood interpolation to align missing points and threshold truncation to maintain dimensional consistency for outlier values; perform local convergence on the coordinate grid with a preset window so that the deviation feature map can continuously represent the spatial distribution of deviation within the same chip unit coordinate, while preserving the differences in deviation amount and the clustering pattern. For example, in the region of chip unit coordinates (12,34), if the deviation amount of adjacent coordinate points shows a banded distribution that increases from the upper left to the lower right, the deviation feature map can form a gradient texture with obvious directionality, thereby providing a stable input for the subsequent extraction of directional consistency components; The multi-domain complexity value of the deviation is calculated by extracting the deviation distribution entropy component, directional consistency component, and periodic clustering component from the deviation feature map. The deviation distribution entropy component is used to characterize the spatial dispersion of the deviation by statistically analyzing the histogram of the deviation amount distribution in the deviation feature map and calculating its information entropy. The directional consistency component is used to characterize the directional concentration of the deviation texture by calculating the local gradient direction of the deviation feature map and statistically analyzing the proportion of the main direction. The periodic clustering component is used to characterize whether the deviation exhibits repetitive periods and clustering in space by performing autocorrelation or frequency domain energy analysis on the deviation feature map. The deviation distribution entropy component, directional consistency component, and periodic clustering component are normalized to make them comparable. They are then fused according to preset weights to obtain the multi-domain complexity value of the deviation. For example, when the deviation feature map of a certain chip unit coordinate region shows multiple isolated high points and no obvious main direction, the normalized value of the deviation distribution entropy component is high, the normalized value of the directional consistency component is low, and the normalized value of the periodic clustering component is medium. After fusion with preset weights, a higher multi-domain complexity value of the deviation is obtained, which reflects that the spatial distribution of the deviation within the chip unit coordinate is more complex and the shape is more irregular.

[0029] In one specific implementation, for the forward voltage sampling sequence obtained under preset pulse excitation, in order to obtain a node temperature transient sequence corresponding one-to-one with the sampling time and form a comparable preset reference node temperature transient sequence, the following steps are performed sequentially: The pulse on-time and pulse off-time periods are determined based on the preset pulse excitation trigger timing parameters. The sampling time of the forward voltage sampling sequence is aligned with the preset pulse excitation trigger time to ensure that the subsequently extracted sampling points can accurately fall within the boundary range of the pulse on-time and pulse off-time periods. For example, when the preset pulse excitation is a periodic pulse and each cycle contains a fixed pulse on-time and a fixed pulse off-time, the start and end sampling times of each segment are marked cycle by cycle to form a time period index. A transient positive voltage sequence is formed by extracting sampling points corresponding to the pulse conduction period and the pulse turn-off period from the positive voltage sampling sequence. The transient positive voltage sequence is arranged in the order of sampling time, and complete conduction sampling points are retained during the pulse conduction period, and at least the recovery sampling points at the initial turn-off period are retained during the pulse turn-off period, so that the transient positive voltage sequence can simultaneously characterize the voltage change characteristics of the heating and cooling processes. Optionally, the transient positive voltage sequence can be uniformized to avoid the impact of dimensional or baseline differences on the conversion stability. The transient forward voltage sequence is input into the thermoelectric coupling calibration model for conversion. The thermoelectric coupling calibration model is a parameterized conversion function or lookup table established from the calibration data. The calibration data is used to characterize the correspondence between junction temperature and forward voltage under preset pulse excitation conditions, thereby outputting a junction temperature transient sequence that corresponds one-to-one with the sampling time. At the same time, in order to obtain a preset reference junction temperature transient sequence, a reference forward voltage sampling sequence collected by a reference chip unit under the same excitation conditions as the preset pulse excitation is selected. The reference forward voltage sampling sequence is subjected to the same time period determination, sampling point extraction and thermoelectric coupling calibration model conversion as in steps one to three above, to obtain the junction temperature transient sequence corresponding to the reference chip unit, which is used as the preset reference junction temperature transient sequence. For example, when the junction temperature transient sequence obtained by the reference chip unit reaches a certain peak at the end of the pulse conduction while the test object reaches a higher peak, subsequent difference calculations can be performed directly on the same sampling time set, thereby ensuring that the thermal response comparison of different objects under the same preset pulse excitation conditions has a consistent time reference and conversion reference.

[0030] Method for establishing a thermoelectric coupling calibration model: In one specific implementation, calibration data is obtained through a temperature-controlled platform. The chip unit to be calibrated is placed on a temperature-controlled hot plate or temperature-controlled fixture, placing it at a preset set of temperature points. (For example, multiple temperature points covering commonly used operating temperature ranges, and the number of temperature points is no less than...) (Number of units). At each temperature point, a reference measurement current or a reference pulse excitation is applied to the chip cell, wherein the reference measurement current is preferably a fraction of the rated drive current. To reduce the impact of self-heating; synchronously acquire the forward voltage and record the forward voltage value corresponding to the sampling time. The result will be The sample pairs are fitted with a parameterized transformation function, which can be a linear function, a piecewise linear function, or a low-order polynomial function; for example, a linear function can be used. ; where the coefficient Obtained by least squares fitting. If driving current or duty cycle is considered... The impact can also be established based on The calibration process uses multivariate functions or lookup tables with excitation parameters as independent variables, and performs conversions using linear interpolation / spline interpolation. After calibration, the fitting residuals or interpolation errors are recorded. When the error exceeds a preset threshold, recalibration or updating of the calibration model is triggered. The reference chip unit can be selected from the same wafer or batch of chip units that have been determined to be low-risk and have good electrical consistency, or a standard sample that has been validated over a long period of time.

[0031] In one specific implementation, to obtain the node temperature dynamic response drift value based on the difference between the node temperature transient sequence and a preset reference node temperature transient sequence, the following steps are performed sequentially: Using the trigger time of the preset pulse excitation as a unified time reference, the transient sequence of node temperature is time-aligned with the transient sequence of the preset reference node temperature so that the zero time of the two corresponds to the same trigger time, and a consistent relative time axis is established before and after the trigger time; when the two have sampling start and end times that are not completely consistent, the effective interval falling into the preset evaluation time window is retained first and the boundary is uniformly truncated to ensure that subsequent comparisons only occur within the same preset evaluation time window; Within a preset evaluation time window, the time-aligned nodal temperature transient sequence and the preset reference nodal temperature transient sequence are mapped to the same set of sampling times. This set can be the union or intersection of the two sampling times. During the mapping process, temperature values ​​not at the original sampling times are resampled using interpolation to obtain the corresponding temperature values ​​at those times. This ensures that each sampling time simultaneously contains both the temperature values ​​of the nodal temperature transient sequence and the preset reference nodal temperature transient sequence, thus avoiding distortion caused by differences in sampling frequency or sampling jitter. Example calculation definition and time window rules for the nodal temperature dynamic response drift value: Taking the preset pulse excitation trigger time as zero, the nodal temperature transient sequence... transient temperature sequence of the preset reference node Perform time alignment. The preset evaluation time window can be selected to cover the time intervals of the pulse turn-on phase and the initial recovery phase of the pulse turn-off phase. ,in Desirable , A method combining "pulse turn-on end time + preset turn-off duration" can be used to characterize the difference between temperature rise and initial cooling. Internal construction of the same sampling time set When using union, the temperature values ​​at missing time points are obtained using linear interpolation or spline interpolation. The cumulative difference can be approximated using a trapezoidal integral: ; The reference temperature rise can be defined as ;when When the temperature rise is less than the preset minimum temperature rise threshold, the drift value can be marked as invalid or set to zero to avoid normalization amplification. The node temperature dynamic response drift value is defined as: This ensures that the drift values ​​remain comparable under different temperature rise levels.

[0032] The absolute value of the temperature difference at each sampling time in the same sampling time set is taken and summed or numerically integrated to obtain the cumulative difference value. When the same sampling time set consists of discrete, equally spaced sampling times, point-by-point absolute value summation can be used; when the same sampling time set consists of unequal-interval sampling times, numerical integration can be used to account for time interval weights. The cumulative difference value is normalized according to the temperature rise amplitude of a preset reference node temperature transient sequence within a preset evaluation time window. The temperature rise amplitude can be determined by the difference between the highest and lowest temperatures within the preset evaluation time window, thus obtaining the node temperature dynamic response drift value, ensuring the drift value remains comparable under different temperature rise levels. For example, in the same preset pulse... Under impulse excitation, if the transient temperature sequence of a test object shows that the heating phase is earlier and the peak value is higher than that of the preset reference transient temperature sequence, the absolute value of the temperature difference at each sampling time within the preset evaluation time window will increase significantly near the heating phase and the peak value, forming a large cumulative difference value. When the temperature rise amplitude of the preset reference transient temperature sequence is used as a normalization benchmark, even if there are differences in the temperature rise amplitude of different wafers or different chip units, the obtained node temperature dynamic response drift value can still stably characterize the degree of deviation of the dynamic response of the test object relative to the reference object, thus providing a consistent quantitative basis for subsequent risk differentiation based on the degree of drift.

[0033] The dynamic control module is used to calculate the deviation thermal coupling risk index based on the deviation multi-domain complexity value and the node temperature dynamic response drift value. It integrates the deviation multi-domain complexity value (encapsulation deviation morphology dimension) and the node temperature dynamic response drift value (thermal dynamic response dimension) under the same evaluation framework to form the deviation thermal coupling risk index. This enables the system to express the risk level of "encapsulation deviation and abnormal thermal response coupling" with a unified index, providing a basis for subsequent graded control.

[0034] The deviation thermal coupling risk index is compared with preset primary threshold and preset secondary threshold. By comparing with the preset primary threshold and preset secondary threshold, the deviation thermal coupling risk index is mapped to an executable graded judgment result, enabling the system to select different collection strategies according to the risk level, and to realize the on-demand investment of collection resources while ensuring the effectiveness of traceability.

[0035] Based on the comparison results, the control data acquisition module establishes sub-unit coordinates within the chip unit coordinates and collects packaging deviation data at these sub-unit coordinates as sub-unit packaging deviation data. When the deviation thermal coupling risk index reaches a level requiring further refinement, sub-unit coordinates are established within the chip unit coordinates, forming a finer spatial resolution level than the chip unit coordinates. Packaging deviation data is then collected at these sub-unit coordinates as sub-unit packaging deviation data, thereby characterizing packaging deviations in suspected high-risk areas with finer granularity. This provides a data foundation for subsequent layered representation and improved positioning accuracy of the wafer map. And / or, based on the sub-unit coordinates, drive current and drive duty cycle scanning are performed, and packaging deviation data is collected during the scanning process as scanned packaging deviation data. In cases requiring further verification or enhanced risk characterization, the sub-unit coordinates are used as the object, and the scanning conditions of drive current and drive duty cycle are changed to obtain packaging deviation responses under different excitation conditions. Packaging deviation data is collected during the scanning process as scanned packaging deviation data. This allows the system to obtain supplementary information on "excitation condition changes—packaging deviation performance" at the same spatial subdivision level, thus providing data support for the traceability and positioning module to output more discriminative traceability and positioning results.

[0036] In one specific implementation, to calculate the deviation thermal coupling risk index based on the deviation multi-domain complexity value and the node temperature dynamic response drift value, the following steps are taken: The deviation multi-domain complexity value and the node temperature dynamic response drift value are normalized. First, normalization benchmark intervals are established for the two types of indicators. The benchmark intervals can be jointly determined by the historical batch statistical quantiles, design tolerance upper limit, and measurement uncertainty within the same process window. During the normalization process, boundary constraints are applied to the original indicators to suppress the amplification effect of extreme outliers on risk judgment. Then, linear scaling is used to map the indicators to a unified scale of zero to one. A smooth monotonic mapping can be superimposed to enhance the resolution of the medium and high risk range, so that the normalized deviation multi-domain complexity value and the normalized node temperature dynamic response drift value remain comparable across different wafers and different chip cell coordinates. The deviation thermal coupling risk index is obtained by fusing the two types of normalized results according to the preset fusion weights. The fusion weights can be preset according to the process focus, or can be robustly modified by combining quality factors such as sampling integrity, noise level and calibration residuals to ensure that the risk index is both sensitive and stable. The fusion calculation can use weighted summation combined with upper limit pruning and threshold grading output to make the risk index fall into a fixed range for easy direct judgment.

[0037] In one specific implementation, in order to improve the spatial resolution and operational coverage of high-risk areas while ensuring that the measurement cost is controllable, the following steps are performed in sequence: The deviation thermal coupling risk index is compared with the preset primary threshold and the preset secondary threshold to form a basis for graded control. The preset primary threshold is used to characterize the warning boundary of the transition from random fluctuations to suspected deviations. It can be taken as the high quantile or the mean plus two standard deviations of the risk index distribution of stable mass production batches, and the confidence margin obtained from the measurement repeatability and reproducibility assessment is superimposed to reduce false alarms. The preset secondary threshold is used to characterize the handling boundary of significant deviations that may trigger reliability risks. It can be taken as the higher quantile or the mean plus three standard deviations, and the failure sample backtracking labeling results can be introduced to calibrate the threshold, so that the sample set corresponding to the secondary threshold has a higher probability of adverse correlation in historical data. This ensures that the two thresholds not only conform to the statistical law of process fluctuations, but also establish an interpretable correspondence with yield and reliability performance. Based on the comparison results, the acquisition strategy is dynamically controlled and different levels of data sets are output. When the deviation thermal coupling risk index is less than the preset first-level threshold, only the packaging deviation data at the chip unit coordinates is collected as the unit packaging deviation data to obtain basic coverage and reduce cycle overhead. When the deviation thermal coupling risk index is greater than or equal to a preset first-level threshold and less than a preset second-level threshold, a sub-unit coordinate grid is established within the chip unit coordinate system, and sub-unit packaging deviation data is collected. The granularity of the sub-unit coordinate division is controlled by the sampling resolution enhancement factor. The sampling resolution enhancement factor can be monotonically increased according to the position of the risk index between the two threshold levels, smoothly increasing from one to multiple times, to achieve adaptive encryption where higher risk means denser sampling. The sub-unit coordinate system is established with the geometric center of the chip unit packaging image or a preset alignment mark as the origin, along the row and column directions of the packaging layout. A mapping relationship from pixel coordinates to physical coordinates is established through camera calibration parameters and probe station displacement parameters, and lens distortion is corrected, so that the sub-unit position of the same chip unit has reproducible consistency under different acquisition batches. The sub-unit coordinates can be increased according to the sampling resolution enhancement factor. The effective area of ​​the chip unit is divided into The grid is divided into equal parts, or an adaptive encryption method is used to increase the local sampling density in areas with large deviation gradients.

[0038] When the deviation thermal coupling risk index is greater than or equal to the preset secondary threshold, on the basis of completing the sub-unit packaging deviation data acquisition, the drive current and drive duty cycle are further scanned, and the packaging deviation data is collected during the scanning process as the scanning packaging deviation data. The scanning range or scanning step size is also set monotonically and dynamically according to the risk index. The higher the risk index, the wider the range or the smaller the step size, so as to capture the deviation amplification range caused by nonlinear thermal coupling.

[0039] Local window definition for the deviation feature map: For each chip cell coordinate, a preset neighborhood window is selected centered on that chip cell to form a local coordinate set. The window is preferably a rectangular or circular window with the center as the origin; for example, a rectangular window includes the central chip cell and its adjacent chip cells extending in the row and column directions, such that the number of chip cells within the window is [value missing]. ,in Desirable The unit packaging deviation data of each chip unit within the window is mapped to two-dimensional grid values ​​to form a local deviation feature map. When missing points exist, neighborhood interpolation is used to fill them in; when outliers exist, they are truncated according to preset upper / lower limits to suppress the outlier amplification effect.

[0040] Example definition of the entropy component of the deviation distribution: for local deviation feature map The deviation range is divided into bins, and the number of bins is... Preferred Record the first The number of samples in each bin is Then the probability The deviation distribution entropy component is defined as follows: ; in The range of values ​​after normalization is .

[0041] Example definition of directional consistency components: Calculate the spatial gradient over the local deviation feature map. To obtain the gradient direction ; Will Boxes are divided by directional interval (number of directional boxes) Preferred ), and record the main direction sub-box count as The total count is Then the directional consistency component is defined as ,in The range of values ​​is , The larger the value, the more concentrated the main direction of the deviation texture.

[0042] Example definition of periodic clustering components: Perform two-dimensional autocorrelation or frequency domain energy analysis on the local deviation feature map. Taking frequency domain energy analysis as an example, calculate the amplitude spectrum by calculating the two-dimensional discrete Fourier transform. After removing the DC component, take the first... The ratio of the sum of the energies of each main peak to the total energy is used as the periodic clustering component. ; in The frequency domain set after removing DC. For the highest energy A set of peak points Preferred , The range of values ​​is .

[0043] Fusion of biased multi-domain complexity values: combining the above The multi-domain complexity value of the deviation is obtained by fusing according to preset weights. ;in And satisfy For example, it is advisable to take The entropy component represents discreteness and heterogeneity, and is most sensitive to complex morphology, so its weight is slightly higher and set to 0.4. The directional consistency and periodic clustering reflect the main texture and repetitive cluster structure, respectively. They are complementary and have similar importance, so each is set to 0.3 to balance robustness and interpretation and make it easier to set the normalization threshold, while reducing the influence of noise and anomalies.

[0044] These are the deviation multi-domain complexity values. With drift value Set normalization upper and lower bounds and The upper and lower bounds can be determined jointly by the statistical quantiles, design tolerances, and measurement uncertainties of historical batches within the same process window. Normalization can be achieved using a truncated linear mapping. ; in This indicates that the value will be truncated to... scope.

[0045] Example definition of risk index fusion: Deviation thermal coupling risk indices can be expressed using weighted summation: ;in For example, it is preferable in scenarios that are more sensitive to thermal anomalies. .

[0046] Example setting rules for Level 1 / Level 2 thresholds: Statistics on stable mass production reference dataset Distribution, first-level threshold Desirable High quantiles (e.g.) (Quantities) and superimposed with the margin given by measurement repeatability and reproducibility; secondary threshold Higher quantiles can be taken (e.g.) (Quantities) and can be combined with failure sample backtracking to calibrate the threshold, so that the sample set corresponding to the secondary threshold has a higher probability of adverse association. The threshold can be updated in batches or on a rolling basis according to a preset period.

[0047] Example mapping of sampling resolution enhancement factor: when When the sampling resolution improvement factor is satisfied within the range of the first-level threshold to the second-level threshold, Piecewise linear mapping can be used: ; in The first-level threshold, This is a secondary threshold. Preferred Sub-unit coordinate grid can be set according to... The internal structure of the chip unit is divided into a finer, equally divided grid or an adaptive grid.

[0048] Example mapping of drive current to drive duty cycle scan range / step: when At that time, the nominal driving current Compared with nominal duty cycle Set the scan range around the center: ; ; in and Follow Monotonically increasing; scan step size Follow Monotonically reduced to improve resolution in high-risk areas. Optionally, the current scan range can cover a portion of the rated drive current. The duty cycle scanning range can cover [number] times. The minimum step size can be taken as the current. Duty cycle .

[0049] The traceability and location module generates a wafer map, organizing packaging deviation data according to chip unit coordinates (and further refined to sub-unit coordinates after establishing sub-unit coordinates) into a visualized and structured wafer map representation. This allows for a clear visual representation of the distribution of packaging deviations on the wafer space and provides a platform for subsequent annotation, grading, and location output. The wafer map is marked with packaging deviation codes and levels. The packaging deviation codes encode the category or status of the deviation, while the deviation levels grade the severity or risk level of the deviation. This ensures the wafer map not only shows "where the deviation is," but also "what the deviation is and how severe," facilitating rapid screening and targeted identification during subsequent process traceability.

[0050] By combining process traceability data associated with wafer identifiers, the system outputs traceability and location results for packaging deviations. Using wafer identifiers as the association key, the distribution of packaging deviations reflected in the wafer map is correlated with process traceability data, thereby outputting traceability and location results for packaging deviations. This ensures that the results not only remain at the detection level but also point to the associated process chain information, thus achieving a closed loop of "deviation discovery - deviation location - process traceability".

[0051] In one specific implementation, the unit packaging deviation data, sub-unit packaging deviation data, and scan packaging deviation data corresponding to the wafer identifier are read, and coordinate conversion and hierarchical connection are completed under the same wafer coordinate reference. A first-layer wafer map is generated using chip unit coordinates as grids, and the unit packaging deviation amount, deviation multi-domain complexity value, and deviation thermal coupling risk index of each grid are written into the attribute field. A second-layer refined map is generated for grids with sub-unit coordinate grids, and a high-resolution texture is unfolded inside the corresponding grid according to the sub-unit coordinates, and the peak value, gradient, and aggregation pattern of the sub-unit packaging deviation amount are recorded. Simultaneously, a third-layer operating condition map is generated for the grid with drive current and drive duty cycle scan records. The scanned package deviation data is arranged according to the two-dimensional plane of the scanned operating condition, and the deviation amount and sensitive interval of the most unfavorable operating condition point are extracted, thereby forming a three-layer switchable and overlayable layered wafer map. Package deviation codes are generated according to a unified coding rule. The coding rule includes at least a deviation morphology category field, a spatial clustering category field, and a severity field. The package deviation level is divided into level one, level two, and level three according to the severity field and is presented in different marking methods in the wafer map. The wafer identifier is linked to process traceability data, which includes batch number, key equipment identifier, key process recipe version, key temperature profile parameters, and key pressure timing parameters. The traceability and positioning unit clusters high-level packaging deviation points and traces back their common process characteristics, outputting traceability and positioning results that include suspected root cause process steps, related equipment ranges, and suggested review points. For example, when the wafer identifier is W20260323A and the first-layer wafer map shows that the coordinates of multiple chip cells in the edge ring area reach the level three packaging deviation, the second-layer refined map shows a gradient texture along the same direction within the chip cell coordinates (12,34), and the third-layer operating condition unfolded map shows a sudden increase in deviation near the 70% drive duty cycle, the packaging deviation code can be encoded as morphology category as directional gradient, clustering category as ring cluster, and severity as level three. In the associated process traceability data, these points are found to correspond to the same curing oven equipment identifier and the same temperature profile offset parameter, thus pointing the traceability and positioning results to the curing oven process window and giving a suggestion to prioritize the review of the equipment temperature calibration and the retest of the ring area.

[0052] The encapsulation deviation code consists of three fields: a morphology category field, a spatial clustering category field, and a severity field. These fields can be represented by Chinese phrases or preset enumerated values, and can be connected by separators to form a readable code. The morphology category field characterizes the local deviation texture morphology and can include, but is not limited to: isolated point peaks, directional gradient textures, ring-shaped offset textures, multi-peak scattered textures, and edge-clustered textures. The spatial clustering category field characterizes the clustering morphology at the wafer scale and can include, but is not limited to: random distribution, clustered clusters, ring-shaped clusters, and edge clusters. The severity field characterizes the severity of the deviation. The severity field can be based on the deviation thermal coupling risk index. The relationship with the threshold is determined when: It is classified as Level 1; when It is judged as Level 2; when The deviation level is determined to be level three. This deviation level aligns with the dynamic control strategy, facilitating unified presentation in the wafer map and its use for traceability and location. For example, when the morphology category is directional gradient and the aggregation category is annular aggregation, and... At that time, the packaging deviation code can be represented as And mark the corresponding deviation level on the wafer map.

[0053] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A wafer-level CSP light source packaging deviation traceability and positioning system, characterized in that, include: The data acquisition module is used to obtain the wafer identifier of the wafer under test; obtain the chip cell coordinates of each chip cell on the wafer under test; collect the cell packaging deviation data for each chip cell coordinate; and collect the forward voltage data under preset pulse excitation. The forward voltage data includes the forward voltage sampling sequence, and a data record is generated for each chip cell coordinate. The indicator calculation module is used to construct a deviation feature map based on the unit encapsulated deviation data and calculate the deviation multi-domain complexity value based on the deviation feature map; It is used to obtain the node temperature transient sequence based on the forward voltage sampling sequence, preset pulse excitation and thermoelectric coupling calibration model, and to obtain the node temperature dynamic response drift value based on the difference between the node temperature transient sequence and the preset reference node temperature transient sequence. The dynamic control module is used to calculate the deviation thermal coupling risk index based on the deviation multi-domain complexity value and the node temperature dynamic response drift value, and compare the deviation thermal coupling risk index with the preset first-level threshold and the preset second-level threshold. The dynamic control module is used to control the data acquisition module to establish sub-unit coordinates in the chip unit coordinates according to the comparison results and to collect packaging deviation data at the sub-unit coordinates as sub-unit packaging deviation data, and / or to perform drive current and drive duty cycle scanning based on the sub-unit coordinates and collect packaging deviation data during the scanning process as scan packaging deviation data. The traceability and positioning module is used to generate a wafer map, mark the packaging deviation code and packaging deviation level on the wafer map, and output the traceability and positioning results of the packaging deviation by combining the process traceability data associated with the wafer identifier.

2. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The data record corresponds to the wafer identifier and the corresponding chip cell coordinates. The data record includes at least the wafer identifier, chip cell coordinates, cell packaging deviation data, and forward voltage data.

3. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The data acquisition module includes a probe station, an imaging detection unit, and an electrical measurement unit; the probe station positions the chip unit point by point according to the chip unit coordinates; the imaging detection unit acquires the packaged image and calculates the deviation through sub-pixel matching or edge fitting to generate unit packaged deviation data; The electrical measurement unit acquires a forward voltage sampling sequence as forward voltage data under preset pulse excitation and writes it into the corresponding data record.

4. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The deviation feature map is used to characterize the spatial distribution of deviations within the coordinates of the chip unit. The index calculation module extracts the deviation distribution entropy component, directional consistency component, and periodic clustering component from the deviation feature map, normalizes the deviation distribution entropy component, directional consistency component, and periodic clustering component, and fuses them according to preset weights to obtain the deviation multi-domain complexity value.

5. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The method for obtaining the transient sequence of node temperature includes: determining the pulse on-time and pulse off-time according to the preset pulse excitation; extracting the sampling points corresponding to the pulse on-time and / or pulse off-time from the forward voltage sampling sequence to form a transient forward voltage sequence; inputting the transient forward voltage sequence into the thermoelectric coupling calibration model for conversion to obtain the transient sequence of node temperature corresponding to the sampling time.

6. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 5, characterized in that, The thermoelectric coupling calibration model is a parameterized conversion function or lookup table established from the calibration data; The preset reference node temperature transient sequence is obtained by inputting the reference forward voltage sampling sequence into the thermoelectric coupling calibration model and converting it. The reference forward voltage sampling sequence is the forward voltage sampling sequence collected by the reference chip unit under the same excitation conditions as the preset pulse excitation.

7. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The method for obtaining the node temperature dynamic response drift value includes: aligning the node temperature transient sequence with a preset reference node temperature transient sequence at the trigger time of a preset pulse excitation; mapping the time-aligned node temperature transient sequence and the preset reference node temperature transient sequence to the same sampling time set within a preset evaluation time window; taking the absolute value of the temperature difference at each sampling time in the same sampling time set and summing or numerically integrating it to obtain the cumulative difference value; normalizing the cumulative difference value according to the temperature rise amplitude of the preset reference node temperature transient sequence within the preset evaluation time window to obtain the node temperature dynamic response drift value.

8. The wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The deviation thermal coupling risk index is obtained by normalizing the deviation multi-domain complexity value and the node temperature dynamic response drift value, and then performing a fusion calculation according to the preset fusion weight to obtain the deviation thermal coupling risk index.

9. A wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, When the deviation thermal coupling risk index is less than the preset first-level threshold, only the unit packaging deviation data is collected. When the deviation thermal coupling risk index is greater than or equal to the preset first-level threshold and less than the preset second-level threshold, the sub-unit coordinates are established and the sub-unit encapsulated deviation data is collected according to the sampling resolution enhancement coefficient dynamically set by the deviation thermal coupling risk index. When the deviation thermal coupling risk index is greater than or equal to the preset secondary threshold, the scanning range or scanning step size of the drive current and drive duty cycle is dynamically set according to the deviation thermal coupling risk index based on the collected sub-unit packaging deviation data, and the drive current and drive duty cycle are scanned to collect the scanning packaging deviation data.

10. A wafer-level CSP light source packaging deviation traceability and positioning system according to claim 1, characterized in that, The wafer map is a layered wafer map. The traceability and positioning module generates the layered wafer map based on unit packaging deviation data, sub-unit packaging deviation data and scan packaging deviation data.

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