Amplification circuit, storage circuit, and electronic device

Abstract

An amplifier circuit for writing to or reading from a memory cell with reduced power consumption is provided. The amplifier circuit includes a first to a sixth switch and a sense amplifier. The sense amplifier is latching type and includes a first input / output terminal and a second input / output terminal. The first terminal of the first switch is electrically connected to the first terminal of the second switch, and the second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input / output terminal of the sense amplifier. The first terminal of the fourth switch is electrically connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second input / output terminal of the sense amplifier. The control terminals of the first and fifth switches are respectively electrically connected to a first wiring, and the control terminals of the third and sixth switches are respectively electrically connected to a second wiring.

Description

Technical Field

[0001] One aspect of the present invention relates to an amplifier circuit, a storage circuit, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical fields of the invention disclosed in this specification relate to an object, a method of operation, or a method of manufacturing. Furthermore, one aspect of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, specifically, examples of the technical fields of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods of driving them, methods of manufacturing them, or methods of inspecting them. Background Technology

[0003] In recent years, with the increase in the amount of data used, there is a need for storage devices with larger storage capacities. To increase the storage capacity per unit area, a structure in which multiple storage cells are stacked above the drive circuit is effective (Patent Document 1). By stacking storage cells, the storage capacity per unit area can be increased accordingly with the number of stacked storage cells.

[0004] Alternatively, the storage capacity of a storage device can be increased by increasing the number of storage cells in the same layer. However, as the number of storage cells increases, there is a risk of reading erroneous data. For example, in gain-cell type storage cells, the more storage cells in the non-selected state there are, the greater the leakage current flowing from these storage cells to the read bit line, which can sometimes cause the potential of the read bit line to deviate from the correct potential. Patent Document 2 discloses a structure in which a circuit for eliminating leakage current is provided in the column circuit (referred to in this specification as an amplifier circuit, write circuit, read circuit, etc.) to correct the potential of the read bit line to the correct potential.

[0005] Another example of a storage device is the cache memory included in a CPU (Central Processing Unit). For example, Non-Patent Document 1 discloses an SRAM (Static Random Access Memory) used in the cache memory of a CPU, employing transistors of indium gallium zinc oxide, which is an oxide semiconductor.

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] International Patent Application Publication No. 2022 / 238798 [Patent Document 2] International Patent Application Publication No. 2018 / 73708 [Non-patent literature] [Non-Patent Literature 1] S. Yamazaki and M. Fujita, “Physics and Technology of Crystalline Oxide Semiconductor CAAC-IGZO: Application to LSI”, Wiley-SID Series in Display Technology, 2016, pp.181-192. Summary of the Invention

[0007] The technical problem that the invention aims to solve As described in Patent Document 2, the operation of writing data to and reading data from a gain-type memory cell requires a column circuit that includes an amplifier such as a readout amplifier. Furthermore, this column circuit is connected to wiring for supplying a pre-charge potential, wiring for supplying a comparison potential (sometimes called a reference potential), and wiring for supplying a power supply potential to the readout amplifier.

[0008] This circuit has multiple switches. By controlling the on or off state of each switch, the circuit can obtain the various potentials supplied by the aforementioned wiring. Furthermore, depending on the on or off state of each switch, a through current may sometimes be generated between the wiring, which could potentially increase the power consumption of the amplifier circuit.

[0009] For example, when the high power supply potential input terminal of the aforementioned sense amplifier is connected to the wiring supplying the high power supply potential and the low power supply potential input terminal is connected to the wiring supplying the low power supply potential, when the sense amplifier is in an active state, one of the two input / output terminals of the sense amplifier is connected to the wiring supplying the low power supply potential, and the other of the two input / output terminals of the sense amplifier is connected to the wiring supplying the high power supply potential. At this time, when one of the two input / output terminals of the sense amplifier is connected to the wiring supplying the pre-charge potential, etc., a through-current may sometimes occur between the wiring supplying the low power supply potential and the wiring supplying the pre-charge potential, etc. Due to the generation of this through-current, the power consumption of the amplifier circuit may sometimes increase.

[0010] Furthermore, since the sense amplifier amplifies the potentials of the two input / output terminals into high and low level potentials, it is preferable to make the parasitic capacitances of the two input / output terminals as consistent as possible for accurate sensing. Additionally, to improve the operating speed of the sense amplifier, it is preferable to reduce the value of this parasitic capacitance.

[0011] Referring to Patent Document 2, in the array circuit, a logic circuit acting as a switch is provided between one of the two input / output terminals of the sense amplifier and the memory cell. When the two input / output terminals of the sense amplifier are connected to different circuit elements, the parasitic capacitances of the two input / output terminals of the sense amplifier differ, thus sometimes failing to correctly sense the data read from the memory cell, resulting in erroneous data being read. Similarly, sometimes failing to correctly sense the data written to the memory cell results in erroneous data being written.

[0012] Furthermore, in gain-cell type memory cells, the potential of the nodes holding the data in the memory cell is refreshed with appropriate timing to prevent data degradation. More frequent refreshes can maintain the data in the memory cell for a longer period, but more refreshes also result in higher power consumption.

[0013] One objective of this invention is to provide an amplifier circuit with reduced power consumption. Another objective is to provide an amplifier circuit capable of writing data to or reading data from a memory cell. Another objective is to provide an amplifier circuit in which through-current is not easily generated between wiring supplying a high power supply potential and wiring supplying a low power supply potential, or the through-current can be minimized. Another objective is to provide an amplifier circuit that correctly senses data during reading or writing. Another objective is to provide a memory circuit having the above-described amplifier circuit. Another objective is to provide an electronic device including the above-described memory circuit. Finally, another objective is to provide a novel amplifier circuit, a novel memory circuit, or a novel electronic device.

[0014] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above and other objectives without necessarily achieving all of them.

[0015] means of solving technical problems One aspect of the present invention is an amplifier circuit addressing the aforementioned problems, comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a sense amplifier. In particular, the sense amplifier is a latching type, having the function of amplifying the potential of one of the first and second input / output terminals to a high level and the potential of the other of the first and second input / output terminals to a low level, corresponding to the potentials of the first and second input / output terminals.

[0016] In this amplifier circuit, the first input / output terminal of the readout amplifier is connected to the write bit line via a second switch, and the second input / output terminal of the readout amplifier is connected to the readout bit line via a fifth switch. Additionally, the gain-cell type memory cell used for writing or reading data via this amplifier circuit is connected to both the write bit line and the readout bit line.

[0017] Additionally, the write bit line is connected to the wiring supplying the first potential via a first switch. Conversely, the read bit line is connected to the wiring supplying the second potential via a fourth switch.

[0018] Furthermore, the first input / output terminal of the sense amplifier is connected to the first data line via a third switch, and the second input / output terminal of the sense amplifier is connected to the second data line via a sixth switch. Additionally, the first and second data lines are paired wirings, and they serve as complementary data input / outputs for data written to or read from the memory cell.

[0019] As described above, one aspect of the amplifier circuit of the present invention uses a latching readout amplifier to control the on and off states of each switch, amplifies the potential corresponding to the data written to the gain cell, amplifies the potential corresponding to the data read from the gain cell, or rewrites (sometimes referred to as write-back or refresh) the potential held in the gain cell.

[0020] The following describes an example of an amplifier circuit, storage circuit, and electronic device used to solve the above problems. (1) One aspect of the present invention is an amplifier circuit comprising a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, and a sense amplifier. The sense amplifier includes a first input / output terminal and a second input / output terminal.

[0022] The first terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the first terminal of the third switch and the first input / output terminal of the sense amplifier. Additionally, the first terminal of the fourth switch is electrically connected to the first terminal of the fifth switch, and the second terminal of the fifth switch is electrically connected to the first terminal of the sixth switch and the second input / output terminal of the sense amplifier. The control terminals of the first and fifth switches are respectively electrically connected to the first wiring, and the control terminals of the third and sixth switches are respectively electrically connected to the second wiring.

[0023] The readout amplifier is a latching type, which has the function of amplifying the potential of one of the first input / output terminal and the second input / output terminal to a high level potential and amplifying the potential of the other of the first input / output terminal and the second input / output terminal to a low level potential. (2) Furthermore, in the above (1), one embodiment of the present invention may have the following structure: the first switch, the second switch, and the fifth switch are analog switches, the third switch includes a first transistor, the fourth switch includes a second transistor, and the sixth switch includes a third transistor. Additionally, one of the source and drain of the first transistor corresponds to the first terminal of the third switch, and the gate of the first transistor corresponds to the control terminal of the third switch. Furthermore, one of the source and drain of the second transistor corresponds to the first terminal of the fourth switch, and the gate of the second transistor corresponds to the control terminal of the fourth switch. Furthermore, one of the source and drain of the third transistor corresponds to the first terminal of the sixth switch, and the gate of the third transistor corresponds to the control terminal of the sixth switch. (3) In addition, in (2) above, one aspect of the present invention may have a structure in which the first transistor and the third transistor are both n-channel transistors and the second transistor is a p-channel transistor.

[0026] In particular, it is preferred that the first to third transistors each contain silicon in the channel formation region. (4) In addition, one aspect of the present invention is a storage circuit comprising an amplifier circuit and a storage unit as shown in any of (1) to (3) above. The storage unit includes a fourth transistor, a fifth transistor, and a capacitor.

[0028] The first terminal of the first switch and the first terminal of the second switch are respectively electrically connected to the third wiring, and the first terminal of the fourth switch and the first terminal of the fifth switch are respectively electrically connected to the fourth wiring. In addition, one of the source and drain of the fourth transistor is electrically connected to the gate of the fifth transistor and the first terminal of the capacitor, the other of the source and drain of the fourth transistor is electrically connected to the third wiring, and one of the source and drain of the fifth transistor is electrically connected to the fourth wiring. (5) In addition, in the above (4), one aspect of the present invention may employ a structure in which the fourth transistor and the fifth transistor each contain an oxide semiconductor in the channel forming region.

[0030] The oxide semiconductor contains one or more elements selected from indium, zinc, and element M. Element M is selected from one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. (6) Furthermore, one aspect of the present invention is an electronic device comprising the storage circuit described above (5) and a housing.

[0032] Invention Effects An amplifier circuit according to one aspect of the present invention, having any one of the structures described in (1) to (3) above, can perform the following operation: when writing data to or reading data from a gain-cell type memory cell, it is difficult for through-current to be generated between wiring supplying a high power supply potential and wiring supplying a low power supply potential, or the through-current can be minimized. Therefore, the power consumption of the amplifier circuit can be reduced.

[0033] Furthermore, in the above-described operating method, data can be rewritten while reading data from the gain-cell type memory cell. In other words, since rewriting can be performed simultaneously with reading, the number of data refreshes in the memory cell can be reduced. By reducing the number of refreshes, the power consumption of the amplifier circuit can be reduced.

[0034] According to one aspect of the present invention, an amplifier circuit with reduced power consumption can be provided. Additionally, according to one aspect of the present invention, an amplifier circuit capable of writing data to or reading data from a memory cell can be provided. Furthermore, according to one aspect of the present invention, an amplifier circuit in which through-current is not easily generated between wiring supplying a high power supply potential and wiring supplying a low power supply potential, or the through-current can be minimized. Furthermore, according to one aspect of the present invention, an amplifier circuit that correctly senses data during reading or writing can be provided. Furthermore, according to one aspect of the present invention, a memory circuit having the above-described amplifier circuit can be provided. Furthermore, according to one aspect of the present invention, an electronic device including the above-described memory circuit can be provided. Furthermore, according to one aspect of the present invention, a novel amplifier circuit, a novel memory circuit, or a novel electronic device can be provided.

[0035] Note that the effects of one aspect of the present invention are not limited to those described above. The above-described effects do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes lack the effects listed above, depending on the circumstances.

[0036] Brief description of the attached figures Figure 1 This is a circuit diagram showing an example of an amplifier circuit.

[0037] Figure 2 This is a circuit diagram showing an example of an amplifier circuit.

[0038] Figure 3 This is a circuit diagram showing an example of an amplifier circuit.

[0039] Figure 4 This is a circuit diagram showing an example of a storage unit and an amplifier circuit.

[0040] Figure 5A and Figure 5B This is a circuit diagram showing an example of a storage unit and an amplifier circuit.

[0041] Figure 6 This is a timing diagram showing an example of a storage circuit and an amplifier circuit.

[0042] Figure 7 This is a timing diagram showing an example of a storage circuit and an amplifier circuit.

[0043] Figure 8 This is a timing diagram showing an example of a storage circuit and an amplifier circuit.

[0044] Figure 9 This is a timing diagram showing an example of a storage circuit and an amplifier circuit.

[0045] Figure 10A This is a 3D diagram illustrating an example of the structure of a storage circuit. Figure 10B This is a block diagram illustrating an example of the structure of a storage circuit.

[0046] Figure 11 This is a block diagram illustrating an example of the structure of a storage circuit.

[0047] Figure 12 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0048] Figure 13A and Figure 13B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0049] Figure 14A This is a planar schematic diagram showing an example of a transistor structure. Figures 14B to 14D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0050] Figures 15A to 15C This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0051] Figure 16A This is a planar schematic diagram showing an example of a transistor structure. Figures 16B to 16D This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0052] Figure 17A and Figure 17B This is a three-dimensional schematic diagram showing an example of a transistor structure.

[0053] Figure 18 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0054] Figure 19A This is a planar schematic diagram showing an example of a transistor structure. Figure 19B This is a cross-sectional schematic diagram showing an example of a transistor structure.

[0055] Figure 20 This is a cross-sectional schematic diagram showing an example of the structure of a storage circuit.

[0056] Figure 21 This is a three-dimensional schematic diagram showing an example of the structure of the processing device.

[0057] Figure 22A and Figure 22B It is a diagram showing the hierarchy of various storage devices.

[0058] Figures 23A to 23DThis is a diagram showing an example of an electronic component.

[0059] Figure 24A and Figure 24B This is a diagram illustrating an example of an electronic device. Figure 24C This is a diagram illustrating an example of a large computer.

[0060] Figure 25 This is a diagram illustrating an example of a space device.

[0061] Figure 26 This is a diagram illustrating an example of a secondary storage system that can be used in a data center.

[0062] Figures 27A1 to 27A7 and Figures 27B1 to 27B6 It is a circuit diagram illustrating electrical connections.

[0063] Methods of implementing the invention (Notes regarding this instruction manual) In this specification, etc., a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as a circuit that includes semiconductor elements (e.g., transistors, diodes, and photodiodes) and a device that includes such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. Furthermore, a chip incorporating an integrated circuit can also be cited as an example of a semiconductor device, as can an electronic component containing a chip in a package. Additionally, for example, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0064] In this specification, “connection” includes, for example, “electrical connection”.

[0065] When describing the connection relationship of circuit elements as an object under the term "electrical connection," "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that A and B are connected without any circuit elements (such as transistors or switches; note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through more than one circuit element.

[0066] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when assuming the circuit is operating, if there is a sequence of electrical signal exchange or potential interaction between A and B during circuit operation, the circuit can be defined as an object as "indirectly connected between A and B." Furthermore, even if there is no sequence of electrical signal exchange or potential interaction between A and B, if there is a sequence of electrical signal exchange or potential interaction between A and B during circuit operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating due to the lack of a power supply voltage, the circuit can still be defined as an object as "indirectly connected between A and B" (however, this is limited, for example, to cases where electrical signal exchange or potential interaction occurs between A and B during circuit operation when the circuit is operating due to a power supply voltage).

[0067] The following are specific examples of "indirect connection". First, as an example of "A and B being indirectly connected", there is... Figure 27A1 and Figure 27A2 This includes cases where A and B are connected via the source and drain of one or more transistors, as shown. Other examples of "indirect connection between A and B" include cases where A and B are connected via one or more switches. In the case of "indirect connection between A and B," the timing sequence ensures that, assuming the circuit is operating, at least one transistor between A and B is in an on-state, a conducting state, or a state where current can flow at least once. Additionally, the "indirect connection between A and B" includes timing sequences where one transistor between A and B is in an off-state or a non-conducting state. In the case of "indirect connection between A and B," if multiple transistors are connected between A and B, the timing sequence ensures that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow at least once. In other words, in the case of "indirect connection between A and B," multiple transistors do not necessarily need to be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, in the case of "A and B being indirectly connected," this includes situations where multiple transistors between A and B are simultaneously or at different times in a closed or non-conducting state. Other examples include... Figure 27A3As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0068] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 27A4 The case shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 27A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0069] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 27A6 and Figure 27A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 27A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 27A6 and Figure 27A7 Since they have the same connection relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0070] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0071] The following shows specific examples of the "direct connection" case. For example, in the case of "A and B are directly connected,"... Figure 27B1 , Figure 27B2 and Figure 27B3 As shown, there are cases where A and B are not connected by circuit components. Furthermore, as... Figure 27B4 and Figure 27B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 27B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V or B and V are connected through the source and drain of a transistor, it cannot be said that they are directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected".

[0072] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0073] In this specification, the description of "multiple circuit elements connected in series" includes the case where multiple circuit elements are connected continuously by connecting the terminals of two adjacent circuit elements to each other. In addition, this connection also includes "electrical connection".

[0074] Furthermore, even when independent components are connected to each other in a circuit diagram, sometimes one component can function as multiple components. For example, when a part of a "wiring" also functions as an "electrode," a conductive film can function as both a "wiring" and an "electrode." Therefore, the scope of "connection" in this specification also includes such cases where a conductive film functions as multiple components.

[0075] In this specification, etc., a "resistive element" can be, for example, a circuit element having a resistance value greater than 0Ω or a wiring having a resistance value greater than 0Ω. Therefore, in this specification, a "resistive element" includes wiring having a resistance value, a transistor, a diode, or a coil through which current flows between the source and drain. Therefore, "resistive element" can sometimes be referred to as "resistor," "load," or "area having a resistance value." In contrast, "resistor," "load," or "area having a resistance value" can sometimes be referred to as "resistive element." As for the resistance value, it is preferably 1mΩ or more and 10Ω or less, more preferably 5mΩ or more and 5Ω or less, and even more preferably 10mΩ or more and 1Ω or less. Furthermore, it can be, for example, 1Ω or more and 1×10⁻⁶. 9 Below Ω.

[0076] In this specification, etc., "capacitor" can refer to, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, parasitic capacitance, or the gate capacitance of a transistor. Additionally, "capacitor," "parasitic capacitance," or "gate capacitance" can sometimes be referred to simply as "capacitor." Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) comprises an insulator and a pair of conductors clamping the insulator. Thus, the "pair of conductors" of a "capacitor" can be referred to as a "pair of electrodes," a "pair of conductive regions," a "pair of regions," or a "pair of terminals." Additionally, "one of the pairs of terminals" and "the other of the pairs of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. Furthermore, the electrostatic capacitance value can be, for example, 0.05fF or more and 10pF or less. Furthermore, for example, it can be 1pF or more and 10μF or less.

[0077] In addition, in this specification, a switch refers to a component that controls whether current flows by changing to an on or off state. Alternatively, a switch refers to a component that selects and switches the current path.

[0078] In this specification, "conducting state" refers to a state in which current may flow between the two input / output terminals, and "non-conducting state" refers to a state in which the two input / output terminals are electrically disconnected. Furthermore, in this specification, the open state of a switch falls within the category of "conducting state," and the closed state falls within the category of "non-conducting state." Therefore, in this specification, the "conducting state" and "open state" of the switch can be interchanged, as can the "non-conducting state" and "closed state."

[0079] Furthermore, switches sometimes include two or more terminals besides the control terminals, allowing current to flow through. As an example, electrical switches or mechanical switches can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0080] Examples of electrical switches include transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM) diodes, MIS (Metal-insulator-semiconductor) diodes, or diode-connected transistors), or logic circuits that combine these components. When a transistor is used as a switch, the "on state" or "turn-on state" of a transistor refers, for example, to the state where current can flow between the source and drain electrodes of the transistor. Conversely, the "off state" or "turn-off state" of a transistor refers to the state where the source and drain electrodes of the transistor are electrically disconnected. When a transistor is used solely as a switch, there are no particular restrictions on the transistor's polarity (conduction type).

[0081] As an example of a mechanical switch, there is a switch that utilizes MEMS (microelectromechanical systems) technology. This switch has mechanically movable electrodes, and operates by controlling the on and off states through the movement of these electrodes.

[0082] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate serves as a control terminal for switching the transistor between its on and off states. The two terminals used as the source or drain are the transistor's input and output terminals. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the input / output terminals is used as the source, and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. In this specification, when describing the transistor's connection relationships, the terms "one of the source and drain" and "the other of the source and drain" are used. In this specification, one of the source and drain is sometimes referred to as the "first electrode of the transistor" or "first terminal of the transistor," and the other is sometimes referred to as the "second electrode of the transistor" or "second terminal of the transistor." Furthermore, depending on the transistor's structure, a back gate may sometimes be included in addition to the three terminals mentioned above. In this case, in this specification and the like, one of the transistor's gate and back gate is sometimes referred to as the first gate, and the other of the transistor's gate and back gate is sometimes referred to as the second gate. Furthermore, in the same transistor, the terms "gate" and "back gate" can sometimes be interchanged. Additionally, when a transistor includes three or more gates, in this specification and the like, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc.

[0083] For example, as described in this specification, a multi-gate transistor with two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure in which multiple transistors are connected in series. Therefore, by using a multi-gate structure, the off-state current can be reduced, and the transistor's voltage withstand capability (reliability) can be improved. Alternatively, by utilizing a multi-gate structure, when the transistor is operating in the saturation region, even if the voltage between the drain and source changes, the change in the drain and source current is not significant, thereby obtaining a voltage-current characteristic with a flat tilt angle. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with extremely high resistance can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0084] Furthermore, a circuit diagram illustrating a single circuit element sometimes includes cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram illustrating a resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram illustrating a capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram illustrating a transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram illustrating a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0085] In addition, in this specification, nodes may also be referred to as terminals, wiring, electrodes, conductive layers, conductors, impurity regions, etc., depending on the circuit structure and device structure. Furthermore, terminals and wiring may also be referred to as nodes.

[0086] Furthermore, in this specification, etc., a selector sometimes refers to, for example, a circuit that includes multiple input terminals and one output terminal, and selects one from the multiple input terminals and establishes a conduction state between the selected input terminal and the output terminal. In other words, a selector sometimes refers to a circuit that selects one from each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to, for example, a circuit that includes multiple output terminals and one input terminal, and selects one from the multiple output terminals and establishes a conduction state between the selected output terminal and the input terminal. In other words, a selector sometimes refers to a circuit that selects one from multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. That is to say, a selector sometimes refers to a multiplexer or a multiplexer. In particular, in the case of inputting or outputting analog potentials or analog currents, a selector sometimes refers to an analog multiplexer or an analog multiplexer.

[0087] Furthermore, in this instruction manual and other documents, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference between the reference potential and a reference potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0088] Furthermore, in this specification and other materials, "high-level potential" and "low-level potential" do not imply specific potentials. For example, when two wires are both labeled as "wires used to supply a high-level potential," the high-level potentials supplied to the two wires may sometimes be different. Similarly, when two wires are both labeled as "wires used to supply a low-level potential," the low-level potentials supplied to the two wires may sometimes be different.

[0089] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current is input to element A" can be replaced with the description "current is output from element A."

[0090] Furthermore, in this specification and other documents, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Additionally, these ordinal numbers do not limit the order of the constituent elements. For example, in this specification and other documents, a "first" constituent element in one embodiment may be referred to as a "second" constituent element in other embodiments or claims. Furthermore, for example, in this specification and other documents, a constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0091] In this specification and other materials, for convenience, terms such as "upper" and "lower" are sometimes used to indicate the arrangement of components in conjunction with the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation of each structure being described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately replaced as needed. For example, if the description is "an insulator located on the top surface of a conductor," it can be changed to "an insulator located on the bottom surface of a conductor" by rotating the orientation of the shown drawings by 180°.

[0092] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, the expression "electrode B below insulating layer A" does not necessarily mean that electrode B is formed directly in contact below insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B.

[0093] Furthermore, in this specification and other materials, terms such as "row" and "column" are sometimes used to describe the constituent elements arranged in a matrix and their positional relationships. Moreover, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each structure is described. Therefore, the terminology used is not limited to that described in the specification and other materials, and may be appropriately changed as needed. For example, by rotating the orientation of the accompanying drawings by 90°, the expression "row direction" may sometimes be replaced with "column direction."

[0094] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged depending on the context. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer." Depending on the situation, other terms may be used instead of "film" and "layer." For example, "conductive layer" or "conductive film" may sometimes be replaced with "conductor." Likewise, "insulating layer" or "insulating film" may sometimes be replaced with "insulator."

[0095] Note that in this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, terms such as "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Thus, for example, an "electrode" can be part of "wiring" or "terminal," and, for example, a "terminal" can be part of "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," or "terminal" are sometimes replaced with terms such as "area," depending on the situation.

[0096] In this instruction manual and other documents, the terms "wiring," "signal line," or "power line" may be interchanged depending on the situation or circumstances. For example, sometimes "wiring" may be replaced with "signal line." Similarly, sometimes "wiring" may be replaced with "power line," and vice versa. Furthermore, sometimes "signal line" or "power line" may be changed to "wiring." Sometimes "power line" may be changed to "signal line," and vice versa. Additionally, depending on the situation or circumstances, sometimes the "potential" applied to the wiring may be changed to "signal." Conversely, sometimes "signal" may be changed to "potential."

[0097] Furthermore, in this specification and other documents, timing diagrams are sometimes used to describe the operation of semiconductor devices. Moreover, the timing diagrams used in this specification and other documents show ideal operating examples, and unless otherwise specified, are not limited to the periods, signal (e.g., potential or current) magnitudes, and timing shown in the timing diagram. In the timing diagrams described in this specification and other documents, the magnitudes and timing of signals (e.g., potential or current) input to each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods are shown at equal intervals in the timing diagram, the lengths of the two periods may sometimes be different. Furthermore, for example, even if one period is shown to be longer than the other, the lengths of the two periods may sometimes be the same, or sometimes one period may be shorter than the other.

[0098] In this specification and other materials, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also abbreviated as OS). For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide can form the channel formation region of a transistor that has at least one of amplification, rectification, and switching functions, the metal oxide can be called a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0099] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides are sometimes referred to as metal oxynitrides.

[0100] Furthermore, in this specification and the like, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 at.% are considered impurities. When impurities are present, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor. When the semiconductor is an oxide semiconductor, impurities that alter the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, especially, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0101] In this specification, "parallel" refers to two straight lines arranged at an angle of -10° to 10°. Therefore, it also includes cases where the angle is -5° to 5°. "Approximately parallel" refers to two straight lines arranged at an angle of -30° to 30°. Furthermore, "perpendicular" refers to two straight lines arranged at an angle of 80° to 100°. Therefore, it also includes cases where the angle is 85° to 95°. Additionally, "nearly perpendicular" or "approximately perpendicular" refers to two straight lines arranged at an angle of 60° to 120°.

[0102] Furthermore, the structures shown in each embodiment in this specification and the like can be appropriately combined with structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0103] Furthermore, the content described in one embodiment can be applied / combined / replaced with other content described in that embodiment and at least one content described in other embodiments.

[0104] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0105] Furthermore, more figures can be formed by combining the figures shown in one embodiment with other parts of the figures and at least one figure shown in one or more other embodiments.

[0106] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same part or parts having the same function, and sometimes repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0107] In this specification and other materials, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in the accompanying drawings and other materials, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification or other materials, these symbols are sometimes omitted.

[0108] In the accompanying drawings of this specification, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. For example, non-uniformity in signals, voltages, or currents caused by noise or timing deviations may be included.

[0109] (Implementation Method 1) This embodiment describes an amplifier circuit according to one aspect of the present invention.

[0110] <Example of amplifier circuit structure> Figure 1The circuit structure shown is an example of an amplifier circuit that can be used in a storage circuit. The amplifier circuit WRC has the function of amplifying the potential corresponding to the data written to the storage cell and amplifying the potential corresponding to the data read from the storage cell. Therefore, the amplifier circuit WRC can be called a write circuit or a read circuit.

[0111] As an example, the WRC amplifier circuit is an amplifier circuit capable of writing and reading data from gain-cell type memory cells. Gain-cell type memory cells will be explained later. As an example, the WRC amplifier circuit can write and read data from gain-cell type memory cells such as 2T (transistor) 0C (capacitor) type, 2T1C type, and 3T1C type.

[0112] As an example, the amplifier circuit WRC includes switches WSW1, WSW2, RSW1, RSW2, DSW, DBSW, and a sense amplifier LTSA.

[0113] Additionally, as an example, Figure 1 The sense amplifier LTSA shown is a latching sense amplifier. The sense amplifier LTSA has two input / output terminals: terminal IT and terminal ITB. Additionally, the sense amplifier LTSA includes inverters INV1 and INV2, a switch HSW, and a switch LSW.

[0114] The first terminals of both switches WSW1 and WSW2 are connected to wiring WBL. Additionally, the second terminal of switch WSW1 is connected to wiring VRE. Furthermore, the second terminal of switch WSW2, the first terminal of switch DSW, and terminal IT of the sense amplifier LTSA are all connected to wiring BL. Additionally, the second terminal of switch DSW is connected to wiring DBL.

[0115] Additionally, the first terminals of both switches RSW1 and RSW2 are connected to wiring RBL. Furthermore, the second terminal of switch RSW1 is connected to wiring VPE. Additionally, the second terminal of switch RSW2, the first terminal of switch DBSW, and the ITB terminal of the sense amplifier LTSA are all connected to wiring BLB.

[0116] Additionally, the control terminals of switches WSW1 and RSW2 are connected to wiring RE. Furthermore, the control terminal of switch RSW1 is connected to wiring PREB. Additionally, the control terminal of switch WSW2 is connected to wiring WE. Furthermore, the control terminals of switches DSW and DBSW are connected to wiring CSEL.

[0117] In the sense amplifier LTSA, the input terminal of inverter INV1 and the output terminal of inverter INV2 are both connected to terminal IT. Additionally, the input terminal of inverter INV2 and the output terminal of inverter INV1 are both connected to terminal ITB. Furthermore, the first terminal of switch HSW is connected to the high-supply-potential input terminals of inverters INV1 and INV2, and the first terminal of switch LSW is connected to the low-supply-potential input terminals of inverters INV1 and INV2. Furthermore, the second terminal of switch HSW is connected to wiring VDE, and the control terminal of switch HSW is connected to wiring SWEB. Additionally, the second terminal of switch LSW is connected to wiring VSE, and the control terminal of switch LSW is connected to wiring SWE.

[0118] As an example, the wiring BL has the function of connecting the wiring WBL and the wiring DBL. Furthermore, as an example, the wiring BL has the function of transmitting data for writing to memory cells. Additionally, the wiring BL is sometimes referred to as a bit line. Note that although... Figure 1 The connection between the second terminal of switch WSW2, the first terminal of switch DSW, and the terminal IT of the sense amplifier LTSA is represented as wiring BL. However, sometimes wiring BL is not considered as wiring but as a connection area or node.

[0119] As an example, a routing BLB has the function of routing to connect routing RBL and routing DBLB. Furthermore, as an example, a routing BLB has the function of routing to send data written to or read from a memory cell. Additionally, a routing BLB is sometimes referred to as the inverted bit line of a bit line routing BL. Note that in... Figure 1 In this context, the connection between the second terminal of switch RSW2, the first terminal of switch DBSW, and the terminal ITB of the sense amplifier LTSA is represented as wiring BLB. However, sometimes wiring BLB is not considered as wiring but as a connection area or node.

[0120] As an example, the WBL wiring function serves as a write bit line connected to the memory cell. Similarly, as an example, the RBL wiring function serves as a read bit line connected to the memory cell.

[0121] As an example, the wiring VRE has the function of supplying a fixed potential to the wiring WBL. This fixed potential is preferably, for example, a potential lower than the fixed potential supplied by the wiring VPE described later.

[0122] As an example, the wiring VPE has the function of supplying a fixed potential to the wiring RBL. This fixed potential is preferably, for example, a high-level potential.

[0123] As an example, the wiring VDE functions as a wiring that supplies a high-level potential to the high-power input terminals of inverters INV1 and INV2 at a fixed potential. The high-level potential supplied by the wiring VDE can be equal to the high-level potential supplied by the wiring VPE.

[0124] As an example, wiring VSE has the function of supplying a fixed potential to the low power supply potential input terminals of inverters INV1 and INV2. This fixed potential is preferably, for example, a low-level potential lower than the high-level potential supplied by wiring VPE and wiring VDE, a ground potential, a negative potential, etc.

[0125] Similarly, as an example, the wiring PREB has the function of sending control signals to switch the on and off states of switch RSW1.

[0126] As an example, the wiring RE has the function of sending control signals to switch the on and off states of switches WSW1 and RSW2, respectively. Note that the wiring RE is sometimes referred to as the read-enable wiring, and the control signal is sometimes referred to as the read-enable signal.

[0127] Similarly, as an example, the wiring WE has the function of sending a control signal to switch the on and off states of switch WSW2. Note that wiring WE is sometimes referred to as write enable wiring, and the control signal is sometimes referred to as write enable signal.

[0128] As an example, a CSEL (Column Select Line) has the function of transmitting control signals used to switch the on and off states of switches DSW and DBSW, respectively. Note that CSELs are sometimes referred to as column select lines.

[0129] Similarly, as an example, the wiring SWE has the function of sending a control signal to switch the on and off states of the switch LSW. Note that the wiring SWE is sometimes referred to as the sense amplifier enable wiring, and the control signal is sometimes referred to as the sense amplifier enable signal.

[0130] Similarly, as an example, the wiring SWEB has the function of sending a control signal to switch the on and off states of the switch HSW. Note that the logic of this control signal is the inverted logic of the control signal sent by the wiring SWEB. Therefore, the wiring SWEB is sometimes referred to as the inverting sense amplifier enable wiring, and the control signal is sometimes referred to as the inverting sense amplifier enable signal.

[0131] Both the DBL and DBLB wiring lines function as complementary data inputs to the WRC amplifier circuit for writing data into the memory cell. Furthermore, both DBL and DBLB wiring lines function as complementary data outputs from the WRC amplifier circuit to the outside. Therefore, the DBL wiring line is sometimes referred to as the data bit line, and the DBLB wiring line is sometimes referred to as the inverted data bit line. Additionally, to output data from the WRC amplifier circuit, both the DBL and DBLB wiring lines can be pre-charged to the same potential.

[0132] Switches WSW1, WSW2, RSW1, RSW2, DSW, DBSW, HSW, and LSW can be electrical switches (e.g., analog switches or transistors). In addition to electrical switches, mechanical switches can also be used.

[0133] For example, in Figure 1 In this circuit, switches WSW1, WSW2, and RSW2 can be used as analog switches, while switches RSW1, DSW, DBSW, HSW, and LSW can be used as transistors. Figure 2 As mentioned above, in the amplifier circuit WRC, the circuit structure of the amplifier circuit WRCA is shown as an example of using analog switches and transistors for each switch.

[0134] Especially in Figure 2 In the amplifier circuit WRCA, switch RSW1 includes p-channel transistor MP1, switch HSW includes p-channel transistor MP2, switch LSW includes n-channel transistor MN1, switch DSW1 includes n-channel transistor MN2, and switch DBSW includes n-channel transistor MN3.

[0135] Figure 2 The first terminal of each transistor corresponds to the first terminal of the switch having that transistor, the second terminal of each transistor corresponds to the second terminal of the switch having that transistor, and the gate of each transistor corresponds to the control terminal of the switch having that transistor.

[0136] Furthermore, transistors MP1, MP2, MN1, MN2, and MN3 are preferably transistors containing silicon in the channel formation region (hereinafter referred to as Si transistors). Alternatively, depending on the circumstances, transistors MP1, MP2, MN1, MN2, and MN3 may also be transistors other than Si transistors, such as OS transistors, transistors containing germanium in the channel formation region, transistors containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride, or silicon germanium in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region.

[0137] In addition, Figure 2 In the illustrated amplifier circuit WRCA, the wiring SWEB preferably functions as a pair with the wiring SWE. Specifically, the wiring SWEB functions to transmit the logically inverted signal sent to the wiring SWE. For example, when the wiring SWE is supplied with a high-level potential, the wiring SWEB is supplied with a low-level potential, and when the wiring SWE is supplied with a low-level potential, the wiring SWEB is supplied with a high-level potential.

[0138] In addition, Figure 2 In the WRCA amplifier circuit, the analog switch has two control terminals, so Figure 2 The diagram shows the wiring for two control signals used to switch the analog switch between its on and off states. The two control terminals of the analog switch will be referred to below as the first control terminal and the second control terminal.

[0139] Furthermore, in the analog switch described in this specification, when the first control terminal is supplied with a high-level potential and the second control terminal is supplied with a low-level potential, the analog switch becomes open. Conversely, when the first control terminal is supplied with a low-level potential and the second control terminal is supplied with a high-level potential, the analog switch becomes closed.

[0140] For example, in Figure 2 In the amplifier circuit WRCA, the first control terminal of switch WSW1 is connected to wiring RE, and the second control terminal of switch WSW1 is connected to wiring REB. Additionally, the first control terminal of switch RSW2 is connected to wiring RE, and the second control terminal of switch RSW2 is connected to wiring REB. Furthermore, the first control terminal of switch WSW2 is connected to wiring WE, and the second control terminal of switch WSW2 is connected to wiring WEB.

[0141] A routing REB is a routing pair that is paired with a routing RE and has the function of transmitting a signal whose logic has been inverted from the signal sent to the routing RE. For example, when the routing RE is supplied with a high level potential, the routing REB is supplied with a low level potential, and when the routing RE is supplied with a low level potential, the routing REB is supplied with a high level potential.

[0142] Similarly, a WEB is a pair of wires that are sent to a WE, and has the function of transmitting a signal whose logic has been inverted. For example, when a WE is supplied with a high level, a WEB is supplied with a low level, and when a WE is supplied with a low level, a WEB is supplied with a high level.

[0143] In addition, Figure 2 In the amplifier circuit WRCA, switches WSW1, WSW2, and RSW2, which act as analog switches, can include n-channel transistors and p-channel transistors. Similarly, inverters INV1 and INV2 can include n-channel transistors and p-channel transistors.

[0144] For example, Figure 3 The amplifier circuit WRCA shown has the following structure: Figure 2 In the amplifier circuit WRCA, switch WSW1 includes transistors MP4 and MN5, switch WSW2 includes transistors MP5 and MN6, switch RSW2 includes transistors MP6 and MN7, inverter INV1 includes transistors MP8 and MN9, and inverter INV2 includes transistors MP7 and MN8. Furthermore, transistors MP4 to MP8 are p-channel transistors, and transistors MN5 to MP9 are n-channel transistors.

[0145] In switch WSW1, the first terminals of transistor MP4 and transistor MN5 correspond to the first terminals of switch WSW1, respectively, and the second terminals of transistor MP4 and transistor MN5 correspond to the second terminals of switch WSW1, respectively. Furthermore, the gate of transistor MN5 corresponds to the first control terminal of switch WSW1, and the gate of transistor MP4 corresponds to the second control terminal of switch WSW1.

[0146] In switch WSW2, the first terminals of transistor MP5 and transistor MN6 correspond to the first terminals of switch WSW2, respectively, and the second terminals of transistor MP5 and transistor MN6 correspond to the second terminals of switch WSW2, respectively. Furthermore, the gate of transistor MN6 corresponds to the first control terminal of switch WSW2, and the gate of transistor MP5 corresponds to the second control terminal of switch WSW2.

[0147] In switch RSW2, the first terminals of transistor MP6 and transistor MN7 correspond to the first terminals of switch RSW2, and the second terminals of transistor MP6 and transistor MN7 correspond to the second terminals of switch RSW2. Furthermore, the gate of transistor MN7 corresponds to the first control terminal of switch RSW2, and the gate of transistor MP6 corresponds to the second control terminal of switch RSW2.

[0148] In the sense amplifier LTSA, the first terminal of transistor MP2 is connected to the first terminals of transistors MP7 and MP8, respectively. Additionally, the first terminal of transistor MN1 is connected to the first terminals of transistors MN8 and MN9. Furthermore, terminal IT of the sense amplifier LTSA is connected to the second terminals of transistors MP7 and MN8, the gate of transistor MP8, and the gate of transistor MN9. Finally, terminal ITB of the sense amplifier LTSA is connected to the gates of transistors MP7 and MN8, the second terminal of transistor MP8, and the second terminal of transistor MN9, respectively.

[0149] The first terminal of transistor MP8 corresponds to the high power supply potential input terminal of inverter INV1, and the first terminal of transistor MN9 corresponds to the low power supply potential input terminal of inverter INV1. Additionally, the first terminal of transistor MP7 corresponds to the high power supply potential input terminal of inverter INV2, and the first terminal of transistor MN8 corresponds to the low power supply potential input terminal of inverter INV2.

[0150] Furthermore, transistors MP4 to MP8, MN5, and MN9 are preferably Si transistors. In particular, when transistors MP1 to MP3, MN1, and MN4, as well as transistors MP4 to MP8, MN5, and MN9, are all Si transistors, these transistors can be formed on a semiconductor substrate containing silicon, thereby enabling the fabrication of an amplifier circuit WRCA on the semiconductor substrate.

[0151] In addition to Si transistors, transistors MP4 to MP8, MN5 and MN9 can also use the same OS transistors as transistors MP1 to MP3, MN1 and MN4, transistors containing germanium in the channel formation region, transistors containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride or silicon germanium in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region.

[0152] exist Figure 1 The amplifier circuit shown is WRC or Figure 2 and Figure 3In the illustrated amplifier circuit WRCA, terminal IT of the sense amplifier LTSA is connected to the second terminal of switch WSW2 and the first terminal of switch DSW, while terminal ITB of the sense amplifier LTSA is connected to the second terminal of switch RSW2 and the first terminal of switch DBSW. Thus, the types or numbers of circuit components connected to terminals IT and ITB of the sense amplifier LTSA are identical, allowing the parasitic capacitances of terminals IT and ITB of the sense amplifier LTSA to be as equal as possible. This improves the data sensing accuracy when using amplifier circuits WRC or WRCA for write or read operations, thereby preventing erroneous data writing or reading.

[0153] In addition, Figure 2 and Figure 3 In the amplifier circuit WRCA shown, switches WSW1, WSW2, RSW1, RSW2, DSW, and DBSW do not use logic circuits, thereby reducing the number of transistors included in the amplifier circuit WRCA. This reduces the circuit area of ​​the amplifier circuit WRCA. Furthermore, since no logic circuits are used, the power consumption of the amplifier circuit WRCA can be reduced.

[0154] <Example of storage device structure> Next, an example of the structure of a memory cell that can be configured in a cell array of a memory circuit having an amplifier circuit WRC will be described.

[0155] Figure 4 This is a circuit diagram illustrating an example of the circuit structure of a memory cell (MC). Additionally, Figure 4 In addition to the storage cell MC, a storage cell array MCA including the storage cell MC is also shown. Figure 2 The amplifier circuit shown is WRCA.

[0156] Figure 4 The memory cell MC shown is a 2T1C type memory cell, which, as an example, includes transistor MN11, transistor MN12 and capacitor C1.

[0157] Transistor MN11 is used as the write transistor in the memory cell MC. Therefore, transistor MN11 is preferably used as a switching transistor.

[0158] Transistor MN12 is used as the read transistor in the memory cell MC. Therefore, transistor MN12 is preferably used as an amplification transistor.

[0159] As an example, transistors MN11 and MN12 are preferably OS transistors. In particular, the metal oxide serving as the channel formation region of the OS transistor can be, for example, indium oxide, gallium oxide, and zinc oxide. Furthermore, the metal oxide preferably comprises one or more selected from indium, element M, and zinc. Element M is selected from one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, element M is preferably selected from one or more selected from aluminum, gallium, yttrium, and tin.

[0160] In particular, as the metal oxide used for the semiconductor layer, an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) is preferred. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) is preferred. Alternatively, an oxide containing indium, gallium, tin, and zinc is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) is preferred. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) is preferred. The OS transistor will be described in detail in Embodiment 2.

[0161] Furthermore, the metal oxide contained in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer having a two-layer structure with a first layer and a second layer directly above the first layer. The atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to the main component metal element, in the metal oxide used in the second layer. Furthermore, the atomic ratio of element M, relative to In, in the metal oxide used in the first layer is preferably greater than the atomic ratio of element M, relative to In, in the metal oxide used in the second layer. By employing this structure, the diffusion of impurities and oxygen from the structure formed beneath the first layer to the second layer can be suppressed.

[0162] Furthermore, the ratio of In atoms relative to element M in the metal oxide used in the second layer is preferably greater than the ratio of In atoms relative to element M in the metal oxide used in the first layer. By employing this structure, the OS transistor can achieve large on-state current and high-frequency characteristics.

[0163] Specifically, for example, as the metal oxide used for the first layer, metal oxides with an In:M:Zn ratio of 1:3:2 or similar, an In:M:Zn ratio of 1:3:4 or similar, or an In:M:Zn ratio of 1:1:0.5 or similar can be used. Furthermore, as the metal oxide used for the second layer, metal oxides with an In:M:Zn ratio of 1:1:1 or similar, an In:M:Zn ratio of 1:1:1.2 or similar, an In:M:Zn ratio of 1:1:2 or similar, or an In:M:Zn ratio of 4:2:3 or similar can be used. Moreover, the "simultaneous" composition includes a range of ±30% of the desired atomic ratio.

[0164] To reduce the off-state current of transistors, oxides containing indium (In), gallium (Ga), and zinc (Zn) are preferably used as the metal oxide for the semiconductor layer. For example, when the semiconductor layer of the transistor contains an oxide containing indium (In), gallium (Ga), and zinc (Zn), the current flowing through each channel width of 1 μm between the source and drain when the gate-source voltage of the transistor is 0V is 1 × 10⁻¹⁰ at room temperature (e.g., 25°C). -20 Below A, at 85℃, it is 1×10 -18 A and below or at 125℃ is 1×10 -16 Below A. Furthermore, as described above, in this specification, the condition where the current flowing through the source-drain junction is extremely small when the gate-source voltage of the transistor is 0V is referred to as normally off.

[0165] The first terminal of transistor MN11 is connected to the gate of transistor MN12 and the first terminal of capacitor C1. The second terminal of transistor MN11 is connected to wiring WBL. Furthermore, the gate of transistor MN11 is connected to wiring WWL. Additionally, the first terminal of transistor MN12 is connected to wiring RWL. Furthermore, the second terminal of transistor MN12 is connected to wiring RBL. The second terminal of capacitor C1 is connected to wiring VGE.

[0166] As an example, wiring VGE has the function of supplying a fixed potential to the second terminal of capacitor C1. Note that this fixed potential is preferably, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential.

[0167] As an example, the WWL (Write-On Line) has the function of sending control signals to switch the on and off states of transistor MN11. Because transistor MN11 is used as the write transistor in memory cell MC, the WWL can also be referred to as the write word line to memory cell MC.

[0168] As an example, the wiring RWL functions as a wiring to supply a specified potential to the first terminal of transistor MN12. Because transistor MN11 is used as the read transistor in memory cell MC, the wiring RWL can also be referred to as the read word line of memory cell MC.

[0169] For example, when data is read from the memory cell MC, the wiring RWL supplies a potential corresponding to the selection signal, thereby allowing source-drain current to flow between the first and second terminals of transistor MN12. Conversely, when data is not read from the memory cell MC, the wiring RWL supplies a potential corresponding to the non-selection signal, turning transistor MN12 off or preventing current from flowing between its first and second terminals.

[0170] Note that the storage unit according to one aspect of the present invention is not limited to... Figure 4 The storage unit MC shown is shown. Figure 4 The storage cell shown is a 2T1C type storage cell, but the amplifier circuit of one embodiment of the present invention can also write to or read from a 2T0C type or 3T1C type storage cell.

[0171] Figure 5A This is an example of a 2T0C type memory cell MC, and also Figure 4 The illustration shows a variation of the memory cell MC. Specifically, Figure 5A storage unit MC and Figure 4 The difference between the storage cell MC and the former is that the former does not have a capacitor C1, thus generating a parasitic capacitance PCP.

[0172] Figure 5A One end of the parasitic capacitance PCP can be node ND, and the other end of the parasitic capacitance PCP can be the first terminal of transistor MN12, the gate of transistor MN11, etc. In particular, the other end of the parasitic capacitance PCP is preferably the gate of transistor MN11.

[0173] Furthermore, in the case where the other end of the parasitic capacitance PCP is the gate of transistor MN11, Figure 5AThe memory cell MC preferably performs data writing operations when the routing line (RWL) is supplied with a high-level potential. That is, during data writing operations, it is preferable to supply a high-level potential to both the routing line (WWL) and the routing line (RWL). This is because when the potential of the routing line (RWL) changes, the potential of the node (ND) also changes due to the capacitive coupling of the parasitic capacitance (PCP). Therefore, in order to read the correct data from the memory cell MC, it is necessary to write a potential corresponding to the data to the node of the memory cell MC during the period when a high-level potential is supplied to the routing line (RWL).

[0174] Figure 5B This is an example of a 3T1C type memory cell MC, and also Figure 4 The illustration shows a variation of the memory cell MC. Specifically, Figure 5B storage unit MC and Figure 4 The difference between the memory cell MC and the former is that the former also has a transistor MN13.

[0175] exist Figure 5B In this configuration, the first terminal of transistor MN12 is connected to wiring VHE, and the second terminal of transistor MN12 is connected to the first terminal of transistor MN13. Additionally, the second terminal of transistor MN13 is connected to wiring RBL, and the gate of transistor MN13 is connected to wiring RWL.

[0176] Furthermore, transistor MN13 is used as a switching transistor. By turning on transistor MN13 when reading the memory cell MC, the potential of the second terminal of transistor MN12, which acts as the readout transistor, can be read from wiring RBL. Therefore, with Figure 4 Similarly, in the memory cell MC, the wiring RWL of transistor MN13 is used as the read word line.

[0177] As an example, wiring VHE is used to supply a fixed potential to the first terminal of transistor MN12. Note that this fixed potential is preferably, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential.

[0178] Figure 5B The memory cell MC includes a transistor MN13 that functions as a switching transistor. Therefore, when the memory cell MC is not being read, by turning off the transistor MN13, the read potential, which is the potential of the second terminal of the transistor MN12, can be prevented from being transmitted to the wiring RBL.

[0179] <Examples of how amplifier circuits work> Next, an example of the operation method of an amplifier circuit according to one aspect of the present invention will be described.

[0180] Figures 6 to 8 They are shown respectively Figure 2 and Figure 4 The timing diagram shows an example of how the WRCA amplifier circuit operates. Additionally, the timing diagram shows... Figure 4 The diagram illustrates the operation of the WRCA amplifier circuit during data writing and reading in the memory cell array (MC). Therefore, this timing diagram shows not only the wiring extending into the WRCA amplifier circuit, but also the WWL and RWL wiring extending into the memory cell array (MCA).

[0181] Figures 6 to 8 The timing diagrams show the potential changes for each of the following: PREB, RWL, WE, RE, SWE, WWL, CSEL, BL, BLB, WBL, RBL, ND, DBL, and DBLB. Specifically, in each timing diagram, the high-level potential is denoted as V. H Let the low-level potential be denoted as V. L .

[0182] <<Example 1 of a work method>> Figure 6 The timing diagram illustrates an example of the operation of the amplifier circuit WRCA and the memory cell MC during periods T01 to T07. Specifically, Figure 6 The timing diagram illustrates the following operational example: In the initial state, the first terminal of capacitor C1 in storage cell MC is held at a low level. In the amplifier circuit WRCA, this low level is read from storage cell MC, and the low level potential of the first terminal of capacitor C1 in storage cell MC is rewritten to a high level. Note that in Figure 6 In the timing diagram, a selection signal is sent not only to the memory cell MC during the write operation period T04, but also during periods T02 (activation period) and T05 (read operation). During periods T02 and T05, the data in the memory cell MC is rewritten (refreshed) by sending the selection signal to the memory cell MC.

[0183] [Period T01] During period T01, the wiring PREB is supplied to V in the idle state (idle state). L The wiring RWL is supplied by V H WE is supplied with wiring V H The wiring RE is supplied by V H SWE wiring is supplied by V L WWL wiring is supplied by V L The wiring CSEL is supplied by V L In addition, capacitor C1 will... L Maintain the node ND of the storage unit MC.

[0184] Because the potential of the wiring PREB is V L Therefore, the control terminal of switch RSW1 (the gate of transistor MP1) is supplied with V. L Therefore, transistor MP1 turns on, and wiring RBL is supplied with a potential from wiring VPE. Note that here, the potential supplied by wiring VPE is V. PRE V PRE equals V H Therefore, the potential of the wiring RBL is V. PRE (=V) H ).

[0185] Because the potential of wiring WE is V H Therefore, the potential supplied by the wiring WEB is the logic-inverted potential V of the potential supplied by the wiring WEB. L Therefore, the first control terminal of switch WSW2, which is an analog switch, is supplied with V. H The second control terminal is supplied with V L Switch WSW2 is switched to the ON position. Therefore, wiring WBL and wiring BL are now connected.

[0186] Since the potential of wiring RE is V H Therefore, the potential supplied by the wiring REB is the logic-inverted potential V of the potential supplied by the wiring RE. L Therefore, the first control terminal of switch WSW1, which is an analog switch, is supplied with V. H The second control terminal of switch WSW1 is supplied with V L Switch WSW1 is turned on. As a result, wiring WBL is supplied with potential from wiring VRE. Additionally, since switch WSW2 is on, wiring BL is also supplied with potential from wiring VRE through wiring WBL. Note that here, the potential supplied by wiring VRE is higher than V. L And below V H V REF Therefore, the potential of wiring WBL and wiring BL is V. REF .

[0187] Additionally, since the potential of wiring RE is V H And the potential of the wiring REB is V L Therefore, the first control terminal of switch RSW2, which acts as an analog switch, is supplied with V. H And the second control terminal of switch RSW2 is supplied with V L Switch RSW2 is switched on. This establishes a conductive connection between wiring RBL and wiring BLB. Furthermore, since switch RSW1 is on, wiring BLB is supplied with a potential V from wiring VPE via wiring RBL.PRE (=V) H Therefore, the potential of the wiring BLB is V. PRE (=V) H ).

[0188] Because the potential of the wiring WWL is V L Therefore, the gate of transistor MN11 in the memory cell MC is supplied with V. L Therefore, transistor MN11 becomes off, and the connection between wiring WBL and node ND becomes non-conductive.

[0189] Since the potential of the wiring RWL is V H Therefore, the second terminal of transistor MN12 in the memory cell MC is supplied with V. H Note that the gate potential of transistor MN12 is V. L The potential of the first terminal (wiring RBL) of transistor MN12 is V. PRE =V H Therefore, transistor MN12 becomes off, and wiring RWL and wiring RBL become non-conductive.

[0190] Because the potential of the wiring SWE is V L Therefore, the potential supplied by the routing SWEB is the logic-inverted potential V of the potential supplied by the routing SWWE. H Therefore, the control terminal of switch HSW (the gate of transistor MP2) is supplied with V. H Transistor MP2 is switched off. Additionally, the control terminal of switch LSW (the gate of transistor MN1) is supplied with V. L Transistor MN1 turns off. Consequently, the connection between wiring VDE and the high-power input terminals of inverters INV1 and INV2 becomes non-conductive, so the high-power input terminals of inverters INV1 and INV2 are not connected by the V supplied by wiring VDE. H Similarly, the connection between the wiring VSE and the low-power input terminals of inverters INV1 and INV2 becomes non-conductive, so the low-power input terminals of inverters INV1 and INV2 are not connected by the V supplied by the wiring VSE. L Therefore, V H and V L Since no power supply potential is input to inverters INV1 and INV2, the readout amplifier LTSA becomes inactive.

[0191] Because the potential of the wiring CSEL is V LTherefore, the control terminals of switch DSW (gate of transistor MN2) and switch DBSW (gate of transistor MN3) are supplied with V. L Therefore, transistors MN2 and MN3 are turned off, wiring BL and DBL become non-conductive, and wiring BLB and DBLB also become non-conductive.

[0192] Note that in Figure 6 During the timing diagram, the potentials of routing DBL and routing DBLB in period T01 are, for example, V. L However, since no read or write operations are performed during period T01, the potentials of wiring DBL and wiring DBLB are not limited to this. This also applies to periods T02 and T03, which will be discussed later.

[0193] [Periods T02 and T03] During periods T02 and T03, the amplifier circuit WRCA performs the readout operation of writing the low-level potential of the memory cell MC.

[0194] Period T02 is also known as the activation period, during which, for example, the potential corresponding to the data held in the memory cell is amplified using the sense amplifier LTSA. After activation in period T02, period T03 begins. Furthermore, period T03, also known as the active period, is the period during which the write or read operation can be initiated.

[0195] During period T02, V was first supplied to the wiring PREB. H Therefore, the control terminal of switch RSW1 (the gate of transistor MP1) is supplied with V. H Therefore, transistor MP1 becomes off, and wiring RBL and wiring BLB become floating.

[0196] Next, supply V to the wiring RWL. L Therefore, the second terminal of transistor MN12 in the memory cell MC is supplied with V. L At this time, the gate potential of transistor MN12 is V. L The potential of the first terminal (wiring RBL) of transistor MN12 is V. PRE =V H Therefore, transistor MN12 remains off from period T01.

[0197] Next, both the wiring WE and wiring RE were supplied by V. L .

[0198] By analyzing the wiring WE supply V L The potential of the web wiring becomes V. HTherefore, the first control terminal of switch WSW2, which acts as an analog switch, is supplied with V. L And the second control terminal of switch WSW2 is supplied with V H Therefore, switch WSW2 becomes closed. Consequently, wiring BL becomes floating.

[0199] Additionally, by supplying V to the wiring RE L The potential of the wiring REB becomes V. H Therefore, the first control terminal of switch WSW1, which functions as an analog switch, is supplied with V. L And the second control terminal of switch WSW1 is supplied with V H This causes switch WSW1 to become closed. Consequently, wiring WBL becomes floating. Additionally, the first control terminal of switch RSW2, which functions as an analog switch, is supplied with V. L And the second control terminal of switch RSW2 is supplied with V H Therefore, switch RSW2 is turned off.

[0200] Next, SWE supplied V for cabling. H By supplying V through cabling SWE H The potential of the wiring SWEB changes to V. L Therefore, the control terminal of switch HSW (the gate of transistor MP2) is supplied with V. L Transistor MP2 turns on. Additionally, the control terminal of switch LSW (the gate of transistor MN1) is supplied with V. H Transistor MN1 turns on. Consequently, the connection between wiring VDE and the high-power input terminals of inverters INV1 and INV2 becomes conductive, thus the V from wiring VDE... H The input is given to the high power supply potential input terminals of inverters INV1 and INV2 respectively. Similarly, the connection between wiring VSE and the low power supply potential input terminals of inverters INV1 and INV2 becomes active, so the V from wiring VSE... L The input is given to the low power supply potential input terminals of inverters INV1 and INV2 respectively. Therefore, V H and V L The power supply potential is input to inverters INV1 and INV2, thereby making the readout amplifier LTSA active.

[0201] By activating the sense amplifier LTSA, the potentials of terminals IT and ITB of the sense amplifier LTSA are amplified relative to each other. Specifically, when the sense amplifier LTSA is activated, the potential of wiring BL is V. REF The potential of the wiring BLB is V.PRE (=V) H Therefore, it can be known that the potential V of the wiring BL is... REF Down to V L The potential of the wiring BLB is maintained at V. PRE (=V) H The low-level potential read from the memory cell MC remains unchanged. Therefore, the low-level potential in the wiring BL becomes potential V. L In the wiring BLB, it becomes a potential V. H .

[0202] Next, apply V to the wiring PREB. L Apply V to the routing RWL, routing WE, and routing WWL respectively. H In particular, because the wiring WWL is supplied with a potential V H Therefore, during period T02, the data in the storage unit MC is rewritten (refreshed).

[0203] Because the potential of the wiring PREB is V L Therefore, the control terminal of switch RSW1 (the gate of transistor MP1) is supplied with V. L Therefore, transistor MP1 becomes active, and V... PRE (=V) H The potential of the wiring RBL is maintained at VPE via the wiring VPE. PRE (=V) H ).

[0204] By analyzing the wiring WE supply V H The potential of the web wiring becomes V. L Therefore, the first control terminal of switch WSW2, which acts as an analog switch, is supplied with V. H And the second control terminal of switch WSW2 is supplied with V L This causes switch WSW2 to turn on. Consequently, wiring WBL and wiring BL become conductive. Previously, before switch WSW2 turned on, wiring WBL was in a floating state, and wiring BL was supplied with the potential V of terminal IT of the active sense amplifier LTSA. L When switch WSW2 is turned on, the potential of wiring WBL changes from V REF Down to V L .

[0205] Because the potential of the wiring WWL is V H Therefore, the gate of transistor MN11 in the memory cell MC is supplied with V. H(Data is rewritten (refreshed) in memory cell MC). Therefore, transistor MN11 becomes on, and wiring WBL and node ND become conductive. Additionally, since switch WSW2 is on, node ND is supplied with the potential V of terminal IT of the active sense amplifier LTSA via wiring WBL and BL. L Therefore, the potential of node ND becomes the same as that of wiring BL and wiring WBL, V. L .

[0206] Note that when the wiring WBL and node ND become conductive, charge redistribution occurs between the wiring WBL and node ND. Figure 6 The timing diagram illustrates an example where the potential of node ND temporarily increases. This is because the potential of routing WBL is V before the connection between routing WBL and node ND becomes conductive. REF The positive charge of the wiring WBL temporarily flows into node ND.

[0207] Because the potential of the wiring RWL is V H Therefore, the second terminal of transistor MN12 in the memory cell MC is supplied with V. H At this time, the gate potential of transistor MN12 is V. L The potential of the first terminal (wiring RBL) of transistor MN12 is V. PRE (=V) H Therefore, transistor MN12 remains off.

[0208] As described above, period T03 can be the active period of the storage unit MC. During the active period of period T03, the operation of writing data to the storage unit MC (period T04) or reading data from the storage unit MC (period T05) can be initiated from period T03.

[0209] [Period T04] During period T04, data is written to the storage unit MC.

[0210] First, the wiring DBL is supplied with V as the potential corresponding to the data written to the memory cell MC. H Additionally, the logic of the potential supplied by the wiring DBLB to the wiring DBL is inverted to the potential V. L .

[0211] Subsequently, the wiring CSEL was supplied by V H Therefore, the control terminals of switch DSW (gate of transistor MN2) and switch DBSW (gate of transistor MN3) are supplied with V. HTherefore, transistor MN2 becomes active, and wiring BL and wiring DBL become conductive. Additionally, transistor MN3 becomes active, and wiring BLB and wiring DBLB become conductive.

[0212] In particular, the V supplied by the wiring DBL H and the V supplied by the wiring DBLB L The potential is preferably amplified by an amplifier (e.g., a sense amplifier) ​​located outside the WRCA amplifier circuit. In particular, this amplifier is preferably an amplifier capable of supplying charge to the level of the potential held by the active sense amplifier LTSA. When using this amplifier to rewrite the potential held by the sense amplifier LTSA, the power consumption may increase, but since it is not necessary to perform the work of making the sense amplifier LTSA inactive by wiring SWE and SWEB, the operating speed of the WRCA amplifier circuit can be improved.

[0213] On the other hand, to reduce power consumption, it is preferable to first deactivate the sense amplifier LTSA before switching DSW and DBSW are turned on, and then turn on the switches DSW and DBSW to supply the potential V from the wiring DBL to the wiring BL. H And supply the wiring BLB with a potential V from the wiring DBLB. L Then, the sense amplifier LTSA is brought into an active state. As described above, by appropriately switching the active and inactive states of the sense amplifier LTSA, the power consumption of the amplifier circuit WRCA can be reduced.

[0214] When transistors MN2 and MN3 are turned on, wiring BL is supplied with a potential V from wiring DBL. H The wiring BLB is supplied with a potential V from the wiring DBLB. L Thus, the terminal IT of the amplifier LTSA is read to hold V. H The ITB terminal of the readout amplifier LTSA holds V. L Additionally, since switch WSW2 is in the ON state, the potential of wiring BL and wiring WBL becomes V. H Additionally, the potential of the wiring BLB becomes V. L Note that since switch RSW2 is in the off state, the potential of wiring RBL remains at V. H constant.

[0215] Additionally, since the wiring WWL was supplied from period T02 onwards... H Therefore, transistor MN11 is in the ON state. Thus, node ND of memory cell MC is supplied with V from wiring DBL via wiring WBL and wiring BL. HTherefore, MC, as the write data storage unit, is written to V. H .

[0216] Then, supply V to the wiring CSEL. L Therefore, V is supplied to the control terminals of switch DSW (the gate of transistor MN2) and switch DBSW (the gate of transistor MN3). L Therefore, transistor MN2 becomes off, and wiring BL and wiring DBL become non-conductive. Similarly, transistor MN3 becomes off, and wiring BLB and wiring DBLB become non-conductive.

[0217] [Period T05] During period T05, the readout operation is performed at the potential held by the sense amplifier LTSA. Note that, as mentioned above, data can be read from the memory cell MC directly from the active period of period T03 to period T05.

[0218] First, wiring DBL and wiring DBLB are precharged to V. H .

[0219] Then, supply V to the wiring CSEL. H Therefore, V is supplied to the control terminals of switch DSW (the gate of transistor MN2) and switch DBSW (the gate of transistor MN3). H Therefore, transistor MN2 becomes on, and wiring BL and wiring DBL become conductive. Also, transistor MN3 becomes on, and wiring BLB and wiring DBLB become conductive.

[0220] When the wiring BLB and wiring DBLB become conductive, charge is redistributed between them. Therefore, Figure 6 The timing diagram illustrates an example where the potential of the routing BLB temporarily increases. After this, the potentials of both the routing BLB and the routing DBLB become V. L On the other hand, although the connection between wiring BL and wiring DBL becomes conductive, both wiring BL and wiring DBL are V. H Therefore, there is no potential change between wiring BL and wiring DBL.

[0221] Therefore, V is amplified by the readout amplifier LTSA. H The output is via terminal IT and wiring BL to wiring DBL. Additionally, V is amplified by the sense amplifier LTSA. L Output to the wiring DBLB via terminal ITB and wiring BLB.

[0222] Furthermore, based on the above work, it is preferable to read the potential held by the sense amplifier LTSA after the potentials of wiring BL and wiring BLB have been read to wiring DBL and wiring DBLB, respectively.

[0223] Then, supply V to the wiring CSEL. L Therefore, V is supplied to the control terminals of switch DSW (the gate of transistor MN2) and switch DBSW (the gate of transistor MN3). L Therefore, transistor MN2 becomes off, and wiring BL and wiring DBL become non-conductive. Similarly, transistor MN3 becomes off, and wiring BLB and wiring DBLB become non-conductive.

[0224] Note that during period T05, similar to period T02, the potential of the wiring WWL is V. H Therefore, transistor MN11 becomes turned on, and the data in memory cell MC is rewritten (refreshed) according to the potential changes of node ND and wiring WBL.

[0225] [Period T06] During period T06, the data in the storage cell MC is maintained, and the amplifier circuit WRC is put into sleep mode (quiet state). Note that in this specification, period T06 is sometimes referred to as the pre-charge period for entering sleep mode.

[0226] During period T06, the first step was to supply V to the cabling WWL. L Therefore, V is supplied to the gate of transistor MN11. L Therefore, transistor MN11 is switched off, serving as the write data holding potential V in node ND. H .

[0227] Next, SWE supplied V for cabling. L For cabling RE supply V H .

[0228] Because the potential of the wiring SWE is V L Therefore, the potential supplied by the routing SWEB is the logic-inverted potential V of the potential supplied by the routing SWWE. H Therefore, the control terminal of switch HSW (the gate of transistor MP2) is supplied with V. H Transistor MP2 is switched off. Additionally, the control terminal of switch LSW (the gate of transistor MN1) is supplied with V. LTransistor MN1 turns off. Consequently, the connection between wiring VDE and the high-power input terminals of inverters INV1 and INV2 becomes non-conductive, and the high-power input terminals of inverters INV1 and INV2 are no longer connected to the V-channel power supplied by wiring VDE. H Similarly, the connection between the wiring VSE and the low-power input terminals of inverters INV1 and INV2 becomes non-conductive, and the low-power input terminals of inverters INV1 and INV2 are not connected by the V supplied by the wiring VSE. L Therefore, V H and V L Since no power supply potential is input to inverters INV1 and INV2, the readout amplifier LTSA becomes inactive.

[0229] By supplying V to the wiring RE H The potential of the wiring REB becomes V. L Therefore, the first control terminal of switch WSW1, which functions as an analog switch, is supplied with V. H And the second control terminal of switch WSW1 is supplied with V L This causes switch WSW1 to become open. Consequently, wiring WBL is supplied with potential V from wiring VRE. REF Additionally, since switch WSW2 is in the ON state, wiring BL is also supplied with the potential V from wiring VRE through wiring WBL. REF .

[0230] Additionally, since the potential of wiring RE is V H And the potential of the wiring REB is V L Therefore, the first control terminal of switch RSW2, which acts as an analog switch, is supplied with V. H And the second control terminal of switch RSW2 is supplied with V L Therefore, switch RSW2 becomes open, and wiring RBL and wiring BLB become conductive. Additionally, since switch RSW1 is open, wiring BLB is supplied with a potential V from wiring VPE through wiring RBL. PRE (=V) H Therefore, the potential of the wiring BLB becomes V. PRE (=V) H ).

[0231] Through the operation of period T06, the amplifier circuit WRC can be in the same sleep state during period T07 as during period T01.

[0232] Note that in Figure 6 In the timing diagram, during period T06, the potentials of routing DBL and routing DBLB are, for example, V.L However, no read or write operations are performed during period T06, so the potentials of wiring DBL and wiring DBLB are not limited to this. Furthermore, this also applies to period T07.

[0233] exist Figure 6 During the timing diagram operation, data is rewritten (refreshed) in memory cell MC during period T02. Therefore, during the stage of reading data from memory cell MC to the sense amplifier LTSA, transistor MN11, acting as the write transistor, turns on. Note that at this time, the potential of node ND in memory cell MC is V. L The potential of wiring BL and wiring WBL is V. L Therefore, the potential (the data being held) of node ND in storage cell MC remains unchanged. Similarly, during this period, T15 also rewrites (refreshes) the data in storage cell MC, and the potential of node ND in storage cell MC becomes V. H The potential of wiring BL and wiring WBL is V. H Therefore, the potential (the data held) of node ND in the storage cell MC remains unchanged.

[0234] In addition, Figure 6 In the timing diagram, during period T02, the data in memory cell MC is rewritten (refreshed), so transistor MN11, which acts as the write transistor, can be turned on at an earlier stage. Therefore, when rewriting the data held in memory cell MC after period T03 (during period T04), the rewriting can be performed by changing the potentials of wiring BL and wiring WBL, thereby shortening the time required for the write operation.

[0235] In addition, Figure 6 In the operation of timing diagrams, since it is not easy to generate through current in the amplifier circuit WRC or the through current can be made extremely small (there is no timing of conduction between the wiring supplying high power potential and the wiring supplying low power potential), the power consumption of writing and reading data in the memory cell can be reduced by using the amplifier circuit WRC.

[0236] <<Example 2 of Work Methods>> Figure 7 The timing diagram is related to Figure 6 Different working examples of timing diagrams, Figure 7 This illustrates an example of the operation of the amplifier circuit WRCA and the memory cell MC during periods T11 to T17. Specifically, Figure 7The timing diagram shows an example of how the first terminal of capacitor C1 in the memory cell MC is initially held at a high level, how this high level is read from the memory cell MC in the WRCA amplifier circuit, and how the high level is changed to a low level at the first terminal of capacitor C1 in the memory cell MC. Note that in Figure 7 In the timing diagram, the selection signal for the memory cell MC to be written to is sent not only during the write operation period T14, but also during periods T12 (activation period) and T15 (read operation), which are described later. During periods T12 and T15, the data in the memory cell MC is rewritten (refreshed) by sending the selection signal to the memory cell MC.

[0237] [Date T11] During T11, with Figure 6 Similarly, during the timing diagram period T01, in the sleep state (quiet state), the routing PREB is supplied to V. L The wiring RWL is supplied by V H The wiring WE is supplied with V H The wiring RE is supplied by V H SWE wiring is supplied by V L The wiring WWL is supplied with V L The wiring CSEL is supplied by V L Therefore, the on / off state of each switch included in the amplifier circuit WRCA can be referenced. Figure 6 The timing diagram is for period T01. Therefore, the potential of wiring BL and wiring WBL becomes V. REF The potential of wiring BLB and wiring RBL becomes V. PRE Furthermore, there are no particular restrictions on the electrical potential. Figure 6 In the timing diagram, the potential of wiring DBL and wiring DBLB in period T01 is V. L .

[0238] Note that during period T11, capacitor C1 will V H The node ND is maintained in the storage cell MC. Therefore, during period T11, the potential of node ND is V. H .

[0239] [Periods T12 and T13] During periods T12 and T13, the high-level potential written to the storage cell MC is read out by the amplifier circuit WRCA.

[0240] and Figure 6 Similarly, in the timing diagram, period T02 is also referred to as the activation period, and period T12 is also called the activation period. Furthermore, with... Figure 6 Similarly, in the time series diagram, period T03 is also referred to as the activity period, and period T13 is also referred to as the activity period.

[0241] During period T12, V is first supplied to the wiring PREB. H Therefore, the control terminal of switch RSW1 (the gate of transistor MP1) is supplied with V. H Therefore, transistor MP1 becomes off, and wiring RBL and wiring BLB become floating.

[0242] Next, supply V to the wiring RWL. L Therefore, the second terminal of transistor MN12 in the memory cell MC is supplied with V. L At this time, since the gate potential of transistor MN12 is V... H Therefore, transistor MN12 becomes switched on, and the potential of the first terminal (wiring RBL) of transistor MN12 changes from V. PRE =V H The potential decreases. Note that, consequently, the potential of the wiring BLB, which is in the conductive state with wiring RWL, also decreases. Furthermore, the potentials of wiring RBL and wiring BLB are lower than the V supplied by wiring VRE. REF .

[0243] Next, both the wiring WE and wiring RE were supplied by V. L .

[0244] By analyzing the wiring WE supply V L The potential of the web wiring becomes V. H Therefore, the first control terminal of switch WSW2, which acts as an analog switch, is supplied with V. L And the second control terminal of switch WSW2 is supplied with V H Therefore, switch WSW2 is switched off. Consequently, wiring BL becomes floating.

[0245] Additionally, by supplying V to the wiring RE L The potential of the wiring REB becomes V. H Therefore, the first control terminal of switch WSW1, which functions as an analog switch, is supplied with V. L And the second control terminal of switch WSW1 is supplied with V H This causes switch WSW1 to become closed. Consequently, wiring WBL becomes floating. Additionally, the first control terminal of switch RSW2, which functions as an analog switch, is supplied with V. L And the second control terminal of switch RSW2 is supplied with V H Therefore, switch RSW2 is turned off.

[0246] When switch RSW2 is turned off, wiring BLB and wiring RBL become non-conductive, and wiring BLB becomes floating. Therefore, the potential of wiring BLB stops decreasing. On the other hand, wiring RBL remains conductive with wiring RWL, so the potential of wiring RBL continues to decrease.

[0247] Next, SWE supplied V for cabling. H By supplying V through cabling SWE H ,and Figure 6 Similarly, during the timing diagram period T02, the readout amplifier LTSA becomes active.

[0248] When the sense amplifier LTSA becomes active, the potentials of terminals IT and ITB of the sense amplifier LTSA are amplified according to their respective potentials. Specifically, the potential of wiring BL when the sense amplifier LTSA is active is V. REF The potential of the wiring BLB is lower than V. REF Therefore, the potential V of the wiring BL REF Rise to V H The potential of the wiring BLB drops to V. L Therefore, the high-level potential read from the memory cell MC is at potential V in the wiring BL. H In the wiring BLB, the potential is V L .

[0249] Furthermore, since switch WSW2 is in the closed state, wiring WBL and wiring BL are not conductive. Therefore, the potential of wiring WBL does not change due to the amplification of the sense amplifier LTSA.

[0250] Next, apply V to the wiring PREB. L Apply V to the routing RWL, routing WE, and routing WWL respectively. H In particular, because the wiring WWL is supplied with a potential V H Therefore, during period T12, the data in the storage unit MC is rewritten (refreshed).

[0251] Because the potential of the wiring PREB is V L Therefore, V L It is supplied to the control terminal of switch RSW1 (gate of transistor MP1). Therefore, transistor MP1 becomes turned on, and wiring RBL is supplied from wiring VPE. PRE (=V) H Therefore, the potential of the wiring RBL rises to V. PRE (=V) H ).

[0252] By analyzing the wiring WE supply V HThe potential of the web wiring becomes V. L Therefore, the first control terminal of switch WSW2, which acts as an analog switch, is supplied with V. H And the second control terminal of switch WSW2 is supplied with V L This causes switch WSW2 to turn on. Consequently, wiring WBL and wiring BL become conductive. Previously, before switch WSW2 turned on, wiring WBL was in a floating state, and a potential V was supplied to wiring BL from terminal IT of the active sense amplifier LTSA. H This causes switch WSW2 to turn on, and the potential of wiring WBL changes from V... REF Change to V H .

[0253] Because the potential of the wiring WWL is V H Therefore, V is applied to the gate of transistor MN11 in memory cell MC. H (Data is rewritten (refreshed) in memory cell MC). Therefore, transistor MN11 becomes on, and wiring WBL and node ND become conductive. Additionally, since switch WSW2 is on, node ND is supplied with the potential V from terminal IT of the active sense amplifier LTSA via wiring WBL and BL. H Therefore, the potential of node ND becomes the same as that of wiring BL and wiring WBL, V. H .

[0254] Note that by making the wiring WBL and node ND in a conductive state, charge is redistributed between the wiring WBL and node ND. Figure 7 The timing diagram illustrates an example where the potential of node ND temporarily drops. This is because the potential of routing WBL changes to V before it becomes conductive with node ND. REF The positive charge at node ND temporarily flows into wiring WBL.

[0255] Because the potential of the wiring RWL is V H Therefore, the second terminal of transistor MN12 in the memory cell MC is supplied with V. H At this time, the gate potential of transistor MN12 is V. H The potential of the first terminal (wiring RBL) of transistor MN12 is V. PRE (=V) H Therefore, transistor MN12 becomes off.

[0256] During period T13, with Figure 6Similarly, the period T03 in the timing diagram can be the activity period relative to the storage unit MC. Through the activity period T13, the work of writing data to the storage unit MC (period T14) or reading data from the storage unit MC (period T15) can be transferred from period T13.

[0257] [Date T14] During period T14, data is written to the storage unit MC.

[0258] First, V is supplied to the wiring DBL as the potential corresponding to the data written to the memory cell MC. L Additionally, the logic of the potential supplied by the wiring DBLB to the wiring DBL is inverted to the potential V. H .

[0259] Then, supply V to the wiring CSEL. H Therefore, V is supplied to the control terminals of switch DSW (the gate of transistor MN2) and switch DBSW (the gate of transistor MN3). H Therefore, transistor MN2 becomes on, and wiring BL and wiring DBL become conductive. Also, transistor MN3 becomes on, and wiring BLB and wiring DBLB become conductive.

[0260] Especially, with Figure 6 Similarly, the timing diagram for period T03, and the V supplied by the wiring DBL. L and the V supplied by the wiring DBLB H Preferably, the potential is amplified by an amplifier (e.g., a sense amplifier) ​​located outside the amplifier circuit WRCA. In particular, the amplifier is preferably an amplifier capable of supplying a charge to the extent that the sense amplifier LTSA, which is in a rewriting active state, holds.

[0261] When transistors MN2 and MN3 are switched on, wiring BL is supplied with a potential V from wiring DBL. L The wiring BLB is supplied with a potential V from the wiring DBLB. H Thus, the terminal IT of the amplifier LTSA is read to hold V. L The ITB terminal of the readout amplifier LTSA holds V. H Additionally, since switch WSW2 is in the ON state, the potentials of wiring BL and wiring WBL become V. L Additionally, the potential of the wiring BLB becomes V. H Note that because switch RSW2 is in the off state, the potential of wiring RBL remains at V. PRE =V H And it does not change.

[0262] Additionally, since the wiring WWL was supplied from period T12 onwards... H Therefore, transistor MN11 is in the ON state. Thus, V is supplied to node ND of memory cell MC via wiring WBL and wiring BL from wiring DBL. L Therefore, as the data V to be written... L It is written to the storage unit MC.

[0263] Then, supply V to the wiring CSEL. L Therefore, V is supplied to the control terminals of switch DSW (the gate of transistor MN2) and switch DBSW (the gate of transistor MN3). L Therefore, transistor MN2 becomes off, and wiring BL and wiring DBL become non-conductive. Similarly, transistor MN3 becomes off, and wiring BLB and wiring DBLB become non-conductive.

[0264] [Date T15] During T15, with Figure 6 Similarly, during period T05 of the timing diagram, the readout operation is performed at the potential held by the sense amplifier LTSA. Note that, as mentioned above, data can be read from the memory cell MC directly from the active period of period T13 to period T15.

[0265] First, wiring DBL and wiring DBLB are precharged to V. H .

[0266] Then, supply V to the wiring CSEL. H This turns transistors MN2 and MN3 on. At this time, the output of wiring DBL, amplified by the sense amplifier LTSA, is obtained through terminal IT and wiring BL. L Additionally, the V signal output from the wiring DBLB via the terminal ITB and wiring BLB is amplified by the sense amplifier LTSA. H .

[0267] By making wiring BLB and wiring DBLB conductive, charge is redistributed between wiring BL and wiring DBL. Furthermore, since switch SWS2 and transistor MN11 are both on, the potentials of wiring WBL and node ND simultaneously become the same as the potential of wiring BL. Therefore, Figure 7 The timing diagram shows an example where the potentials of trace BL, trace WBL, and node ND temporarily increase. After this, the potentials of trace BL, trace DBL, and node ND become V. L On the other hand, although the wiring BLB and wiring DBLB become conductive, since both the wiring BLB and wiring DBLB are V... HTherefore, the potential of the wiring BLB and the wiring DBLB does not change.

[0268] Therefore, the V signal output from the DBL wiring via terminal IT and the BL wiring is amplified by the sense amplifier LTSA. L Additionally, the V signal output from the wiring DBLB via the terminal ITB and wiring BLB is amplified by the sense amplifier LTSA. H .

[0269] Furthermore, based on the above work, it is preferable to read the potential held by the readout amplifier LTSA after the potentials of wiring BL and wiring BLB have been read out by wiring DBL and wiring DBLB, respectively.

[0270] Then, supply V to the wiring CSEL. L This causes transistors MN2 and MN3 to become off, makes wiring BL and DBL non-conductive, and makes wiring BLB and DBLB non-conductive.

[0271] Note that during period T15, similar to period T12, the potential of the wiring WWL is V. H Therefore, transistor MN11 becomes turned on, and as with the potential changes of node ND and wiring WBL mentioned above, the data in memory cell MC is rewritten (refreshed).

[0272] [Date T16] During period T16, with Figure 6 Similarly, during period T06 of the timing diagram, the data in the memory cell MC is maintained, and the amplifier circuit WRC is put into a sleep state (quiet state). Note that in this specification, period T16 is sometimes referred to as the pre-charge period used to enter the sleep state.

[0273] During T16, the first step was to supply V to the cabling WWL. L Therefore, V is supplied to the gate of transistor MN11. L Therefore, transistor MN11 is switched off, serving as the write data holding potential V in node ND. L .

[0274] Next, SWE supplied V for cabling. L For cabling RE supply V H .

[0275] By analyzing the wiring SWE supply V L ,and Figure 6 Similarly, during the timing diagram period T06, the readout amplifier LTSA becomes inactive.

[0276] By supplying V to the wiring RE H ,and Figure 6 Similarly, during period T06 of the timing diagram, switch WSW1 turns on. Consequently, wiring WBL is supplied with potential V from wiring VRE. REF Additionally, since switch WSW2 is in the ON state, wiring BL is also supplied with the potential V from wiring VRE through wiring WBL. REF .

[0277] Additionally, since the potential of wiring RE is V H And the potential of the wiring REB is V L Therefore, with Figure 6 Similarly, during period T06 of the timing diagram, switch RSW2 turns on, and wiring RBL and wiring BLB become conductive. Additionally, since switch RSW1 is on, wiring BLB is supplied with a potential V from wiring VPE through wiring RBL. PRE (=V) H Therefore, the potential of the wiring BLB is V. PRE (=V) H ).

[0278] By operating during period T16, the amplifier circuit WRC can be put into the same sleep state as during period T17.

[0279] Note that in Figure 7 During the timing diagram, period T16, the potentials of routing DBL and routing DBLB are, for example, V. L However, during period T16, no read or write operations are performed, so the potentials of wiring DBL and wiring DBLB are not limited to this. The same applies during period T17.

[0280] Figure 7 The workings of timing diagrams and Figure 6 Similarly, in period T02 of the timing diagram, during period T12, the data in memory cell MC is rewritten (refreshed). Therefore, during the read operation phase, transistor MN11, which acts as the write transistor, becomes active. Note that at this time, the potential of node ND in memory cell MC is V. L The potential of wiring BL and wiring WBL is V. L Therefore, the potential (the data held) of node ND in the storage cell MC does not change.

[0281] In addition, Figure 7 In the timing diagram, during the T12 phase, data is rewritten (refreshed) in memory cell MC, so transistor MN11, acting as the write transistor, can be turned on at an earlier stage. Therefore, with Figure 6Similarly, in the timing diagram, the data held by the memory cell MC is rewritten after period T12 (during period T14). This can be done by rewriting the potentials of the wiring BL and wiring WBL, thereby shortening the time required for the write operation.

[0282] In addition, Figure 7 In the work of timing diagrams, with Figure 6 Similarly, in the timing diagram, no through current is generated in the amplifier circuit WRC (there is no timing sequence between the wiring supplying the high power supply potential and the wiring supplying the low power supply potential to become in a conducting state). Therefore, by using the amplifier circuit WRC, the power consumption for writing and reading data in the memory cell can be reduced.

[0283] <<Example 3 of Work Methods>> Figure 8 The timing diagram is Figure 7 A variation of the timing diagram is shown, illustrating the operation of the amplifier circuit WRCA and the memory cell MC during periods T21 to T27. Note that in... Figure 8 In the timing diagram, with Figure 7 The timing diagrams differ; the rewriting (refreshing) of data in storage unit MC does not occur during the activation period T22, but rather during period T25, as described later. Specifically, in Figure 8 In the timing diagram, a selection signal is sent to the memory cell MC to be written during the data transmission period of the routing DBL and routing DBLB.

[0284] Figure 8 The work of timing diagrams is Figure 7 This is a variation of the timing diagram method, so this example only illustrates the differences; others can be found by referring to [the example provided]. Figure 7 This section provides an example illustrating how timing diagrams work.

[0285] and Figure 7 Similarly, in the timing diagram, period T12 is called the activation period, and period T22 is called the activation period. Note that, as mentioned above, in Figure 7 During the timing diagram, data in the memory cell MC is rewritten (refreshed) during period T12, but in Figure 8 The data is not rewritten during period T22 of the timing diagram. In other words, during period T22, the wiring WWL is input to the potential V. L Without being input potential V H Therefore, during period T22, transistor MN11 is in the off state, and the wiring WBL and node ND are in a non-conductive state. Thus, the potential of node ND does not change with the potential of wiring WBL.

[0286] During the period T23 and Figure 7 The period T13 in the timeline is also referred to as the activity period.

[0287] During period T24, with Figure 7 During the timing diagram, period T14 also involves writing data to the memory cell MC. Additionally, in... Figure 8 In the timing diagram operation, during period T24, the WWL input V is used for routing. H Transistor MN11 is in the ON state. Therefore, at this timing node ND, there is a conduction state between wiring WBL and wiring BL.

[0288] Additionally, during period T24, V is supplied to the cabling CSEL. H Transistors MN2 and MN3 are both turned on, and wiring BL and DBL, as well as wiring BLB and DBLB, are connected. Furthermore, here, wiring DBL is supplied with a potential V corresponding to the data written to the memory cell MC. L Therefore, V is supplied to node ND through wiring WBL and wiring BL. L Additionally, because the logic of the potential supplied to the wiring DBLB by the wiring DBL is inverted, the wiring BL is supplied with V from the wiring DBLB. H .

[0289] and Figure 7 Similarly, during period T15 of the timing diagram, data reading from the memory cell MC is performed during period T25. Note that the reading operation during period T25 can be referenced from the reading operation during period T15.

[0290] and Figure 7 Similarly, in the timing diagram, period T16 is also referred to as the pre-charge period, and period T26 is called the pre-charge period. The operation of this period can be found in [reference needed]. Figure 7 Explanation of period T16 in the timing diagram.

[0291] As mentioned above, Figure 8 The timing diagram and Figure 7 The operation of the timing diagram during period T12 is different. During the activation period of period T22, the data in the storage unit MC is not rewritten (refreshed).

[0292] <<Example 4 of Work Methods>> Figure 9 The timing diagram is Figure 8 A variation of the timing diagram is shown, illustrating the operation of the amplifier circuit WRCA and the memory cell MC during periods T31 to T36. Note that... Figure 8 The timing diagrams are different. Figure 9 The timing diagram is a working example of reading data without rewriting the data in the memory cell (MC). Specifically, Figure 9 The timing diagram and Figure 8 The timing diagrams differ in that the former does not include routing for WWL supply V. H During the period, etc. Furthermore, therefore, in Figure 9 In the timing diagram work, the data in the memory cell MC is not rewritten (refreshed).

[0293] Figure 9 The work of timing diagrams is Figure 8 This is a variation of the timing diagram method, so this example only illustrates the differences; others can be found by referring to [the example provided]. Figure 8 This section provides an example illustrating how timing diagrams work.

[0294] During both T31 ​​and T32, communication with... Figure 8 The timing diagram works the same way for periods T21 and T22. In particular, period T32 is the same activation period as period T22.

[0295] During this period, T33 can conduct with Figure 8 The timing diagram shows the same activity during period T23. In other words, period T33 is the same activity period as period T23.

[0296] During the period T34 and Figure 8 The timing diagram also shows that period T25 is the period during which the readout operation is performed.

[0297] In addition, both T35 and T36 during this period can conduct [operations / activities]. Figure 8 The timing diagram operates in the same way for periods T26 and T27. In particular, period T35 is the same pre-charge period as period T26.

[0298] In the storage unit MC, without needing to modify the data, by performing... Figure 9 The timing diagram operation does not require data rewriting of the memory cell MC (input of write data to the amplifier circuit WRCA), thus shortening the operation time.

[0299] By using the amplifier circuit described in this embodiment, the operating time can be shortened. Furthermore, in this operating method, no through current is generated between the wiring supplying the high power supply potential and the wiring supplying the low power supply potential, thus reducing power consumption. Additionally, by omitting the active period in the above operating method, standby power consumption can be reduced, thereby further reducing the power consumption of the amplifier circuit.

[0300] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0301] (Implementation Method 2) In this embodiment, an example of the structure of a storage circuit including the storage cell MC and the amplifier circuit WRC described in the above embodiment will be explained.

[0302] Figure 10A This is a three-dimensional schematic diagram showing an example of the structure of a storage circuit MDV. Figure 10B This is a block diagram illustrating an example structure of a memory storage device (MDV). The MDV includes layers SS1 and SS2, where layer SS1 includes a substrate 311 and a driving circuit region 50 formed on the substrate 311, and layer SS2 includes memory cells 10. Additionally, as... Figure 10A As shown, layer SS2 can be placed above layer SS1.

[0303] As substrate 311, for example, a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium) can be used. Other substrates besides semiconductor substrates include, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, and paper or substrate films containing fibrous materials. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Furthermore, examples of flexible substrates, laminated films, or substrate films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Other examples include synthetic resins such as acrylic resins. Other examples include polypropylene, polyester, ethylene fluoride, or polyvinyl chloride. Other examples include polyamides, polyimides, aromatic polyamides, epoxy resins, inorganic vapor-deposited films, or paper. Furthermore, when the manufacturing process of the memory circuit MDV includes heat treatment, a material with high heat resistance is preferably selected as the substrate.

[0304] In this embodiment, the substrate 311 is described as a semiconductor substrate containing silicon as a material.

[0305] Figure 10AThe storage cell 10 shown can use the storage cell MC described in Embodiment 1. Additionally, the storage circuit MDV includes a storage cell array MCA, which includes a plurality of storage cells 10. Figure 10A In the storage cell array MCA, multiple storage cells 10 are arranged in a matrix. Figure 10B An example is shown where the memory cell array MCA is configured with memory cells 10[1,1], memory cells 10[m,1] (where m is an integer greater than or equal to 1), memory cells 10[1,n] (where n is an integer greater than or equal to 1), memory cells 10[m,n], and memory cells 10[i,j] (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n).

[0306] <Example of a driver circuit structure> Figure 10A The drive circuit area 50 shown includes PSW22 (power switch), PSW23 and peripheral circuit 31. Peripheral circuit 31 includes peripheral circuit 41, control circuit 32 and voltage generation circuit 33.

[0307] In the MDV storage circuit, various circuits, signals, and voltages can be omitted as needed. Alternatively, other circuits or signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are externally input signals, while signal RDA is an output signal. Signal CLK is the clock signal.

[0308] In addition, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is for writing data, and signal RDA is for reading data. Signals PON1 and PON2 are power gating control signals. Furthermore, signals PON1 and PON2 can be generated in control circuit 32.

[0309] The control circuit 32 is a logic circuit that controls the overall operation of the storage circuit MDV. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage circuit MDV (e.g., write operation and read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 to execute the above-mentioned operating mode.

[0310] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input signal CLK to the voltage generation circuit 33. For example, when the signal WAKE supplies a potential level H, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0311] The peripheral circuit 41 is used to write and read data from the storage unit 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, and an output circuit 48.

[0312] Row decoder 42 and column decoder 44 are used to decode the signal ADDR. Row decoder 42 is used to specify the row to be accessed, and column decoder 44 is used to specify the column to be accessed. That is, row decoder 42 and column decoder 44 are sometimes referred to as selection circuits for selecting the memory cell 10 to be written to or read from.

[0313] The line driver 43 has the function of selecting the write and read word lines specified by the line decoder 42.

[0314] The column driver 45 has the following functions: writing data to the storage unit 10; reading data from the storage unit 10; and storing the read data. Specifically, for example, the column driver 45... Figure 10A The diagram shows multiple amplifier circuits 40 that have the function of reading out data and retaining the read out data. Alternatively, the amplifier circuit 40 can be the amplifier circuit WRC described in Embodiment 1.

[0315] Additionally, the column driver 45 has the function of selecting the write and read bit lines specified by the column decoder 44. Specifically, for example, the column decoder 44 can be connected to the wiring CSEL described in Embodiment 1, thereby allowing the column decoder 44 to select the column including the memory cell 10 as the object of writing or reading. Therefore, it is possible to... Figure 1 The switches DSW and DBSW shown are in the ON state, and the wiring WBL for the write bit line and the wiring RBL for the read bit line of this column can be selected.

[0316] Furthermore, as described above, the column driver 45 facilitates the writing operation to the memory cell 10, and is therefore sometimes referred to as a write circuit that sends write data to the memory cell 10. Similarly, the column driver 45 also facilitates the reading operation to the memory cell 10, and is therefore sometimes referred to as a read circuit that reads read data from the memory cell 10.

[0317] Input circuit 47 has the function of holding signal WDA. The data held in input circuit 47 is output to column driver 45. The output data of input circuit 47 is the data (Din) written to memory cell 10. The data (Dout) read from memory cell 10 is amplified by amplifier circuit 40 in column driver 45 and output to output circuit 48. Output circuit 48 has the function of holding Dout. In addition, output circuit 48 has the function of outputting Dout to the outside of memory circuit MDV. The data output from output circuit 48 is signal RDA.

[0318] PSW22 controls the supply of VDD to the peripheral circuit 31. PSW23 controls the supply of VHM to the row driver 43. Here, the high supply voltage of the memory circuit MDV is VDD, and the low supply voltage is GND (ground potential). Furthermore, VHM is a high supply voltage used to make the word line high, which is higher than VDD. The on and off states of PSW22 are switched according to signal PON1, and the on and off states of PSW23 are switched according to signal PON2. Figure 10B In the peripheral circuit 31, the number of power supply domains supplied with VDD is 1, but it can also be multiple. In this case, it is preferable to set a power switch for each power supply domain.

[0319] <Memory Cell Array and Peripheral Circuits> Next, the electrical connection between the memory cell array MCA and the peripheral circuit 41 will be explained.

[0320] Figure 11 This is a block diagram illustrating an example structure of the peripheral circuitry 41 and the memory cell array MCA. As described above, Figure 11 The storage circuit MDV shown illustrates an example of a structure in which a memory cell array (MCA) is positioned above the peripheral circuit 41. Figure 11 In the middle, the line decoder 42 and the line driver 43 are connected to the wiring WWL[1] to wiring WWL[m] and the wiring RWL[1] to wiring RWL[m].

[0321] Additionally, column decoder 44 is connected to amplifier circuit 40[j] and amplifier circuit 40[j+1] (where j is an integer greater than 1 and less than n-1) included in column driver 45. Furthermore, amplifier circuit 40[j] is connected to wiring WBL[j] and wiring RBL[j], and amplifier circuit 40[j+1] is connected to wiring WBL[j+1] and wiring RBL[j+1].

[0322] As described in Embodiment 1, wiring WWL[1] to WWL[m] are used as write word lines for memory cells 10[i,j]. Additionally, as described in Embodiment 1, wiring RWL[1] to RWL[m] are used as read word lines for memory cells 10[i,j]. Furthermore, as described in Embodiment 1, wiring WBL[j] and wiring WBL[j+1] are used as write bit lines for memory cells 10[i,j]. Additionally, as described in Embodiment 1, wiring RBL[j] and wiring RBL[j+1] are used as read bit lines for memory cells 10[i,j].

[0323] The storage cell 10[i,j] (not shown) configured in the i-th row and j-th column is electrically connected to the wiring WWL[i], wiring RWL[i], wiring WBL[j], and wiring RBL[j].

[0324] Regarding each storage unit 10, please refer to the description in Embodiment 1. Figure 4 storage unit MC, Figure 5A or Figure 5B The storage unit MC records.

[0325] In addition, Figure 11 In the column driver 45 shown, as an example, the amplifier circuit 40 is configured on the matrix in the 2nth row / 2nd column (where n is an even number). Furthermore, in the column driver 45, the amplifier circuit 40 in the first row serves as a write circuit or read circuit for the memory cells 10 in the odd-numbered rows of the memory cell array MCA, and the amplifier circuit 40 in the second row serves as a write circuit or read circuit for the memory cells 10 in the even-numbered rows of the memory cell array MCA.

[0326] As described above, by placing the amplifier circuit WRC and the like described in Embodiment 1 in the drive circuit region 50 of layer SS1 and placing the memory cell MC described in Embodiment 1 in layer SS2, the area of ​​the memory circuit can be reduced. Furthermore, the wiring connecting the memory cell MC and the amplifier circuit WRC can be shortened, thereby reducing parasitic resistance and thus reducing power consumption.

[0327] <Example of cross-sectional structure of storage circuit> Next, the explanation Figure 10A , Figure 10B and Figure 11 The diagram shows a specific structural example of the MDV storage circuit. Figure 12 yes Figure 10A , Figure 10B and Figure 11 The diagram shows a cross-sectional schematic of an example of a storage circuit MDV.

[0328] Figure 12 A cross-sectional schematic diagram of layer SS1 and storage layer SS2 is shown. Note that in... Figure 12 In the storage circuit MDV, layer SS1 is formed directly on layer SS1.

[0329] Figure 12 An example of a transistor 400 included in layer SS1 is shown. The transistor 400 is disposed on substrate 311 and includes a conductive layer 316 serving as a gate, insulating layers 315 and 317 serving as gate insulating films, a semiconductor region 313 comprising a portion of substrate 311, and low-resistance regions 314a and 314b comprising a portion of substrate and serving as source or drain regions. The transistor 400 can be a p-channel transistor or an n-channel transistor.

[0330] Here, in Figure 12 In the transistor 400 shown, the semiconductor region 313 (a portion of the substrate 311) forming the channel has a convex shape. Furthermore, a conductive layer 316 is provided such that it covers the sides and top surface of the semiconductor region 313 with an insulating layer 315 in between. Additionally, a material with an adjustable work function can be used as the conductive layer 316. Because of the convex portion of the semiconductor substrate, this transistor 400 is also referred to as a finned transistor. Furthermore, as a method for forming the convex portion, an insulating layer used as a mask for forming the convex portion can be formed on the semiconductor substrate. Although the case of forming the convex portion by processing a portion of the semiconductor substrate is shown here, a semiconductor film with a convex shape can also be formed by processing an SOI substrate.

[0331] Notice, Figure 12 The structure of transistor 400 shown is just an example and is not limited to the above structure. Appropriate transistors can be used depending on the circuit structure or driving method.

[0332] The structure of transistor 400 can be used, for example, for any one or more of transistors MN1 to MN9 and transistors MP1 to MP8 as described in embodiment 1.

[0333] Additionally, one or both of layers SS1 and SS2 may include a wiring layer with an interlayer film, wiring, and a connector. Furthermore, multiple wiring layers may be provided depending on the design. In this specification, the wiring and the connector connected to the wiring may be integrated. That is, sometimes a portion of the conductive layer is used as wiring, and sometimes a portion of the conductive layer is used as a connector.

[0334] For example, in transistor 400, insulating layers 320, 324, and 326 are sequentially stacked as interlayer films. Furthermore, conductive layers 328 and the like are embedded in insulating layer 320. Furthermore, conductive layers 330 and the like are embedded in insulating layers 324 and 326. Furthermore, conductive layers 328 and 330 serve as contact plugs or wiring.

[0335] Furthermore, the insulating layer used as an interlayer film can also be used as a planarization film covering the uneven shape underneath. For example, in order to improve the flatness of the top surface of the insulating layer 320, its top surface can also be planarized by a planarization process using chemical mechanical polishing (CMP).

[0336] Wiring layers can be disposed on the insulating layer 326 and the conductive layer 330. For example, in Figure 12 In the embodiment, insulating layers 350, 357, 352, and 354 are sequentially stacked on insulating layer 326 and conductive layer 330. Conductive layer 356 is formed in insulating layers 350, 357, and 352. Conductive layer 356 is used as a contact plug or wiring.

[0337] An insulating layer 354 is provided on the insulating layer 352 and the conductive layer 356. A contact plug or wiring for connecting to the circuit above (e.g., the circuit in layer SS2) can be embedded in the insulating layer 354.

[0338] in addition, Figure 12 The storage unit 10 included in layer SS2 is shown. Specifically, Figure 12 The diagram shows transistors MN11 and MN12, and capacitor C1 included in the memory cell MC. Note that the memory cell 10 can be any of the components described in the above embodiment. Figure 4 The storage unit MC shown is shown.

[0339] exist Figure 12 In the storage circuit MDV, layer SS2, transistor MN12 is formed on insulating layer STJ1. Additionally, transistor MN11 and capacitor C1 are formed on insulating layer STJ2. Insulating layer STJ2 is located above insulating layer STJ1. Therefore, transistor MN11 and capacitor C1 are located above transistor MN12.

[0340] exist Figure 12 In layer SS2, transistor MN12 is configured to include a fin semiconductor layer SC1. Specifically, the gate insulating film and gate electrode of transistor M2 are formed to overlap with one of the two regions of a fin semiconductor layer SC1.

[0341] Furthermore, one of the source and drain electrodes of transistor MN12 is connected to a conductive layer used as wiring RWL. The other of the source and drain electrodes of transistor MN12 is connected to a conductive layer used as wiring RBL. Additionally, as an example, wiring RWL and wiring RBL extend in the channel width direction of transistor M2. Note that the conductive layer used as wiring RWL is formed in a manner overlapping with the fin semiconductor layer SC1, and the conductive layer used as wiring RBL is disposed in a manner overlapping with the fin semiconductor layer SC1.

[0342] In addition, transistor MN12 is provided with a conductive layer MEG that serves as a gate electrode. In particular, the conductive layer MEG is disposed in a manner that overlaps with the fin semiconductor layer SC1.

[0343] An insulating layer serving as an interlayer film is formed between transistors MN12 and MN11. Furthermore, this insulating layer has an opening in the region overlapping with the conductive layer MEG of transistor MN12, and the conductive layer is embedded in this opening. This conductive layer is connected to one of the source or drain electrodes of transistor MN11. Note that this conductive layer MEG can be a part of node ND shown in FIG5 as described in Embodiment 1.

[0344] Additionally, as described above, transistor MN11 is located above transistor MN12. Furthermore, transistor MN11 includes a region of a portion of the finned semiconductor layer SC2. Additionally, in a region of transistor MN11 that serves as a conductive layer for one of the source and drain electrodes, an insulating layer for serving as the dielectric of capacitor C1 is formed, and in this insulating layer region, a conductive layer for serving as the second terminal of capacitor C1 is formed. This conductive layer serves as wiring VGE.

[0345] The gate insulating film and gate electrode of transistor MN11 are formed in a manner that overlaps with a portion of the fin-shaped semiconductor layer SC2 of transistor MN11. In particular, the conductive layer for the gate electrode of transistor MN11 extends in the channel width direction. Furthermore, this conductive layer serves as the wiring WWL.

[0346] Note that, although in Figure 12 Although not illustrated, a conductive layer serving as a back gate can be provided below the insulating layer STJ2 in transistor MN11. Similarly, a conductive layer serving as a back gate can be provided below the insulating layer STJ1 in transistor MN12. By providing a back gate in each transistor and varying the potential of the back gate, the threshold voltage of the transistor can be varied.

[0347] For example, by using a transistor including a back gate as transistor MN11, the influence of external electric fields can be mitigated, and the off state can be stably maintained. Therefore, data written to the first terminal of capacitor C1 can be stably maintained. By setting the back gate, the operation of memory cell 10 is stable, and the reliability of layer SS2, including memory cell MC, can be improved.

[0348] The semiconductor layers forming channels in transistors MN11 and MN12 can be combinations of one or more of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, and amorphous semiconductors. As semiconductor materials, silicon or germanium can be used, for example. Other examples include compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, or nitride semiconductors.

[0349] Transistors MN11 and MN12 are preferably oxide semiconductor transistors (OS transistors) in which one of the metal oxides is used in the semiconductor layer forming the channel. Since the bandgap of oxide semiconductors is 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the memory cell MC can be reduced. Therefore, the power consumption of the memory circuit MDV including the memory cell 10 can be reduced.

[0350] Furthermore, a memory cell that includes an OS transistor can be referred to as an "OS memory". Additionally, the memory circuitry MDV that includes this memory cell can also be referred to as an "OS memory".

[0351] Furthermore, OS transistors operate stably even at high temperatures with minimal characteristic variation. For example, even at high temperatures, their off-state current barely increases. Specifically, even in environments above room temperature but below 200°C, the off-state current shows almost no increase. Moreover, even at high temperatures, the on-state current does not easily decrease. Therefore, OS memory can operate stably at high temperatures, exhibiting high reliability.

[0352] Here, as an example of transistor MN12, Figure 13A and Figure 13B A three-dimensional diagram of them is shown. Note that in... Figure 13A and Figure 13B In the three-dimensional schematic diagram, some insulating layers and some conductive layers are omitted. In particular, Figure 13B The 3D diagram omits Figure 13A The 3D schematic diagram shows the wiring RWL and wiring WBL.

[0353] Figure 13A and Figure 13BThe diagram shows a fin-shaped semiconductor layer SC1 with two regions having rectangular openings. Therefore, it can be said that semiconductor layer SC3 has a circumferential and fin-like structure. Furthermore, the openings can also be rectangular or closed-curve shapes.

[0354] like Figure 13A and Figure 13B As shown, the wiring RWL, conductive layer MEG, and wiring WBL are formed in a manner that overlaps with a portion of the sidewalls of the two fin semiconductor layers SC1. Thus, by using the conductive layer MEG to surround the semiconductor layer SC3 forming the channel through the gate insulating film, transistor MN12 can be formed. This prevents electric fields generated outside transistor MN12 from affecting the semiconductor forming the channel. In other words, transistor MN12 can have electrostatic shielding functionality. Therefore, changes in the electrical characteristics of the transistor due to external electric fields such as static electricity can be prevented.

[0355] <<Examples of Transistor Structures>> Next, the explanation Figure 12 The cross-sectional schematic diagram shows the structure of transistors MN11 and MN12 used in the diagram.

[0356] Similar to transistors MN11 and MN12 mentioned above, Figures 14A to 14D A planar schematic and a cross-sectional schematic are shown for a transistor 500mf comprising two semiconductor layers with fin-like and circumferential shapes.

[0357] Figure 14A It can be used Figure 12 A planar schematic diagram of transistors MN11 and MN12 of the MDV memory circuit, showing a transistor with a capacitance of 500mF. Figures 14B to 14D This is a cross-sectional schematic diagram of a 500mF transistor. In particular, Figure 14B It is along Figure 14A The cross-sectional diagram of the section marked with dotted lines A1-A2 is also a cross-sectional diagram of the 500mF transistor along the channel width direction. Additionally, Figure 14C It is along Figure 14A The cross-sectional diagram of the section marked with dotted lines A3-A4 is also a cross-sectional diagram of the 500mF transistor along the channel width direction. Additionally, Figure 14D It is along Figure 14A The cross-sectional view of the section marked with dotted lines A5-A6 is also a cross-sectional view along the channel length of the 500mF transistor. Here, dotted lines A5-A6 are orthogonal to dotted lines A1-A2 and A3-A4, respectively, and dotted lines A1-A2 and A3-A4 are parallel to each other. Note that in Figure 14A In the plan view, for clarity, some constituent elements are omitted and shown transparently. Furthermore, Figure 15A Show Figure 14D A magnified view of the conductive layer near 560. Additionally, Figure 15B Show Figure 14B A magnified view of the area near semiconductor layer 530. Additionally, Figure 15C Show Figure 14C A magnified view of the area near semiconductor layer 530.

[0358] Transistor 500mf includes an insulating layer 516 on insulating layer 514, an insulating layer 521 on insulating layer 516, an insulating layer 522 on insulating layer 521, a semiconductor layer 530 on insulating layer 522, conductive layers 542a and 542b on semiconductor layer 530 and insulating layer 522, an insulating layer 550 on semiconductor layer 530, and conductive layers 560 (conductive layers 560a and 560b) on insulating layer 550. Hereinafter, conductive layers 542a and 542b are sometimes collectively referred to as conductive layer 542.

[0359] An insulating layer 575 is disposed on the conductive layer 542, and an insulating layer 580 is disposed on the insulating layer 575. The insulating layer 550 and the conductive layer 560 are disposed within an opening disposed in the insulating layer 580 and the insulating layer 575. This opening reaches the semiconductor layer 530, and the insulating layer 550 contacts the semiconductor layer 530 within this opening. Additionally, an insulating layer 582 is disposed on the insulating layer 580 and the conductive layer 560. Furthermore, an insulating layer 583 is disposed on the insulating layer 582.

[0360] An insulating layer 541a is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540a is provided in contact with the side surface of the insulating layer 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulating layer 541b is provided in contact with the inner wall of an opening in an insulating layer 580, etc., and a conductive layer 540b is provided in contact with the side surface of the insulating layer 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that, hereinafter, conductive layers 540a and 540b are sometimes collectively referred to as conductive layer 540. Additionally, insulating layers 541a and 541b are sometimes collectively referred to as insulating layer 541.

[0361] The insulating layers 541a and 541b are preferably made of insulating films that inhibit oxygen permeation to prevent a decrease in conductivity caused by oxidation of the conductive layers 542a and 542b. For example, silicon nitride is preferably deposited by PEALD (Plasma Enhanced Atomic Layer Deposition).

[0362] Insulating layer 516, for example, serves as a planarization film, similar to insulating layer 320, to flatten steps caused by plugs, etc. Therefore, like insulating layer 320, insulating layer 516 can use materials that serve as planarization films. Furthermore, by using a material with a low relative permittivity in insulating layer 516, parasitic capacitance between wirings can be reduced. Thus, insulating layer 516 can, for example, use materials that can be used in insulating layer IS1, as described later.

[0363] Similar to insulating layers 324 and 350, insulating layers 521 and 522 preferably use insulating layers that are barrier to one or more of hydrogen, oxygen, and water. Therefore, similar to insulating layers 324 and 350, insulating layers 521 and 522 can use insulating layers that are barrier to one or more of hydrogen, oxygen, and water.

[0364] Semiconductor layer 530 has a region serving as the channel formation region for transistor 500mf. Additionally, conductive layer 560 has a region serving as the first gate electrode (upper gate electrode) for transistor 500mf. Insulating layer 550 has a region serving as the first gate insulating film for transistor 500mf.

[0365] In particular, semiconductor layer 530 can use a metal oxide as an oxide semiconductor. In this case, transistor 500mf is an OS transistor. Semiconductor layer 530 corresponds to semiconductor layer SC1 or semiconductor layer SC2 as described above.

[0366] Furthermore, an oxide semiconductor with an AG CAAC (Axial Growth CAAC) structure can be used as the semiconductor layer 530. AG CAAC refers to an oxide semiconductor with a CAAC structure, formed by solid-phase growth of a metal oxide contained in the first layer using the second layer as a nucleus or seed in an oxide semiconductor layer comprising a first layer and a second layer with a higher crystallinity than the first layer.

[0367] For example, atomic layer deposition (ALD) or chemical vapor deposition (CVD) are preferred methods for depositing the first layer. Other CVD methods include plasma-enhanced CVD (PECVD), thermal CVD, photochemical CVD, and metal-organic CVD (MOCVD). Wet deposition methods can also be used as the first layer. Furthermore, molecular beam epitaxy (MBE) can be used, a deposition method that grows thin films reflecting the crystal structure of the substrate. Compared to sputtering, these deposition methods reduce damage to the surface being formed.

[0368] Next, sputtering or pulsed laser deposition (PLD) is preferably used as the deposition method for the second layer. In particular, by forming the second layer after the first layer, the formation of a mixed layer at the interface between the first and second layers can be suppressed. Furthermore, the incorporation of impurities contained in the formed surface into the second layer can be suppressed. This further improves the crystallinity of the second layer.

[0369] Furthermore, methods for solid-state growth of the metal oxide contained in the first layer using the second layer as a core or seed include, for example, heat treatment, plasma treatment, microwave treatment (typically 2.45 GHz), microwave plasma treatment, and light (e.g., ultraviolet light) irradiation. Note that multiple of these treatments can be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0370] Furthermore, in this specification and the like, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to a process using a device that includes a power source for generating high-density plasma using microwaves. Microwave plasma treatment can also be referred to as microwave-excited high-density plasma treatment.

[0371] Furthermore, it is preferable to perform multiple treatments to improve the crystallinity of the oxide semiconductor layer during the deposition of the oxide semiconductor layer. For example, when forming the oxide semiconductor layer using the ALD method, it is preferable to perform microwave plasma treatment after each atomic layer is formed. Alternatively, by performing crystallinity-improving treatments after each oxide semiconductor layer with a predetermined thickness is formed, productivity can be increased, and this is therefore preferred. Specifically, it is preferable to form a first oxide semiconductor layer of 1 nm or more and 10 nm or less, perform a first microwave plasma treatment, and then form a second oxide semiconductor layer of 1 nm or more and 10 nm or less, and perform a second microwave plasma treatment. There are no particular limitations on the deposition methods of the first and second oxide semiconductor layers; the ALD method or sputtering method can be used. In particular, by depositing the first oxide semiconductor layer using the ALD method, it is preferable to prevent elements constituting the layer of the formed surface from being mixed into (also called mixed with) the first and second oxide semiconductor layers. In particular, this is applicable when the element contained in the layer constituting the formed surface hinders the crystallization of the oxide semiconductor (e.g., the presence of silicon, carbon, etc.). In addition, the compositions of the first and second oxide semiconductor layers can be different from each other. Furthermore, although a stacked structure of a first oxide semiconductor layer and a second oxide semiconductor layer is shown herein, it is not a limitation. The same treatment can be applied even if the oxide semiconductor layer has a single-layer structure or a stacked structure of three or more layers.

[0372] Alternatively, a process to improve the crystallinity of the oxide semiconductor layer can be performed after deposition. Specifically, this process can be performed directly on the deposited oxide semiconductor layer or through an insulating film or other film deposited on the oxide semiconductor layer. For example, microwave plasma treatment can be performed after deposition of the oxide semiconductor layer, or an insulating film (e.g., silicon nitride film, silicon oxide film, aluminum oxide film, etc.) can be deposited after deposition of the oxide semiconductor layer, and then the oxide semiconductor layer can be subjected to heat treatment or microwave plasma treatment through the insulating film.

[0373] The aforementioned treatment to improve the crystallinity of the oxide semiconductor layer can also serve as a treatment to remove impurities contained in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, etc., contained in the oxide semiconductor layer can be appropriately removed. Alternatively, by performing the treatment to improve the crystallinity of the oxide semiconductor layer under an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0374] When performing a process to improve the crystallinity of the oxide semiconductor layer, it is preferable to set the substrate temperature to above room temperature, above 100°C and below 600°C, or above 300°C and below 450°C. Furthermore, the heat treatment temperature is preferably above 100°C and below 700°C, or above 300°C and below 450°C.

[0375] By further improving the crystallinity of the oxide semiconductor layer in addition to the manufacturing method described above, a transistor with high reliability can be achieved.

[0376] For example, such as Figure 15B As shown, the semiconductor layer 530 may include a semiconductor layer 530a, a semiconductor layer 530b in contact with the semiconductor layer 530a, and a semiconductor layer 530c in contact with the semiconductor layer 530b. In addition, the side surfaces of the semiconductor layers 530 (semiconductor layers 530a to semiconductor layers 530c) are preferably perpendicular to or substantially perpendicular to the substrate surface.

[0377] As described above, in the cross-section of semiconductor layer 530 (semiconductor layers 530a to 530c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction parallel or substantially parallel to the surface to which they were formed. In other words, in the cross-section of semiconductor layer 530 (semiconductor layers 530a to 530c) observed using TEM images, it was confirmed that the metal atoms were arranged in layers in a direction perpendicular or substantially perpendicular to the substrate surface. Furthermore, it can be stated that the c-axis of AGCAAC is substantially parallel to the normal direction of the side surface of semiconductor layer 530.

[0378] Thus, by using the semiconductor layer 530, which serves as the AG CAAC, in the channel formation region of the transistor 500mf, a transistor with high on-state current, high field-effect mobility, good S-value, high frequency characteristics, and high reliability can be provided. Note that the S-value refers to the subthreshold swing value, which represents the amount of gate voltage change in the subthreshold region required to change the drain current by one digit with a fixed drain voltage. The smaller the S-value, the steeper the slope of the drain current relative to the gate voltage, thereby improving the switching characteristics.

[0379] For example, a pillar serving as a sacrificial layer is provided on the insulating layer 522, and a first semiconductor film that will become semiconductor layer 530a, a second semiconductor film that will become semiconductor layer 530b, and a third semiconductor film that will become semiconductor layer 530c are sequentially deposited on the side of the pillar. The first to third semiconductor films located on the top surface of the insulating layer 522 and the top surface of the pillar are removed, and then the pillar is removed, thereby forming semiconductor layers 530a to 530c.

[0380] As described above, when the semiconductor layer 530 has a three-layer structure consisting of semiconductor layers 530a to 530c, semiconductor layers 530a, 530b, and 530c are sequentially formed around the region where the pillars are formed. That is, as... Figure 14A As shown, the semiconductor layer 530 has a structure surrounding the region where the pillars are formed when viewed from above.

[0381] The semiconductor layer 530 has a channel forming region for a transistor 500mF, as well as a source region and a drain region disposed in a manner that clamps the channel forming region. At least a portion of the channel forming region overlaps with the conductive layer 560. The source region overlaps with the conductive layer 542a, and the drain region overlaps with the conductive layer 542b. Note that the source region and the drain region can be interchanged.

[0382] Because it has fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions, the channel formation region is a high-resistivity region with low carrier concentration. Therefore, the channel formation region can be considered a type I (intrinsic) or essentially type I region.

[0383] Furthermore, due to the abundance of oxygen vacancies or the high concentration of impurities such as hydrogen, nitrogen, and metal elements, the source and drain regions are low-resistance regions with high carrier concentration. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentration compared to the channel formation region.

[0384] Furthermore, the carrier concentration in the channel formation region is preferably 1×10⁻⁶. 18 cm -3 The following are less than 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Or less than 1×10 10 cm -3 Note that there is no specific limit to the lower limit of carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0385] When the aim is to reduce the carrier concentration in the semiconductor layer 530, the impurity concentration in the semiconductor layer 530 is reduced to reduce the defect state density. In this specification and the like, a state with low impurity concentration and low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. Furthermore, oxide semiconductors (or metal oxides) with low carrier concentration are sometimes referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0386] To stabilize the electrical characteristics of the transistor 500mF, reducing the impurity concentration in the channel formation region of the semiconductor layer 530 is effective. To further reduce the impurity concentration in the semiconductor layer 530, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Furthermore, impurities in the semiconductor layer 530 refer, for example, to elements other than the main components constituting the semiconductor layer 530. For example, elements with a concentration less than 0.1 atomic% can be considered impurities.

[0387] Furthermore, in the semiconductor layer 530, it is sometimes difficult to clearly detect the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to vary in stages according to each region; they can vary continuously within each region. That is, the closer to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen can be.

[0388] In transistors using oxide semiconductors in semiconductor layer 530, the electrical characteristics can easily change and sometimes reduce reliability if impurities and oxygen vacancies are present in the region where the oxide semiconductor forms the channel. Furthermore, hydrogen near the oxygen vacancy forms a defect where hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V). O H) may generate electrons that become charge carriers. Therefore, when oxygen vacancies are included in the channel formation region of an oxide semiconductor, the transistor tends to have always-on characteristics. Thus, in the channel formation region of an oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, preferably, the carrier concentration in the channel formation region of the oxide semiconductor is reduced and is i-typed (intrinsicized) or substantially i-typed.

[0389] In contrast, by performing heat treatment with an insulating layer containing oxygen that has been removed by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor, oxygen can be supplied to the oxide semiconductor from the insulating layer, thereby reducing oxygen vacancies and V. OH. Note that supplying excessive oxygen to the source or drain regions can cause a decrease in the transistor's 500mF on-state current or a decrease in field-effect mobility. Furthermore, when the amount of oxygen supplied to the source or drain regions is uneven within the substrate surface, the characteristics of the semiconductor device, including the transistor, become non-uniform. Additionally, when oxygen supplied from the insulating layer to the oxide semiconductor diffuses to the conductive layers such as the gate, source, and drain electrodes, these conductive layers may sometimes be oxidized, leading to a loss of conductivity and thus negatively impacting the transistor's electrical characteristics and reliability.

[0390] Therefore, preferably, in the oxide semiconductor, the channel formation region is a region with reduced carrier concentration and is i-type or substantially i-type, while the source and drain regions are regions with high carrier concentration and are n-type. In other words, it is preferable to reduce oxygen vacancies and V0 in the channel formation region of the oxide semiconductor. O H. Furthermore, it is preferable that the source and drain regions are not supplied with excessive oxygen and that the V in the source and drain regions... O The amount of hydrogen (H) is not excessively reduced. Furthermore, a structure that suppresses the decrease in conductivity of conductive layers 560, 542a, and 542b is preferred. For example, a structure that suppresses oxidation of conductive layers 560, 542a, and 542b is preferred. Note that hydrogen in oxide semiconductors may form V0. O H, therefore, in order to reduce V O The amount of H needs to be reduced, so the hydrogen concentration needs to be lowered.

[0391] like Figure 15B As shown, insulating layer 550 includes insulating layers 550a, 550b, 550c, and 550d. In addition, insulating layers 550a to 550d serve as part of the first gate insulating film. Insulating layers 550a to 550d are disposed in openings formed in insulating layer 580, similar to the conductive layer 560 described later. To achieve miniaturization of the transistor 500mf, the thickness of each of insulating layers 550a to 550d is preferably small. The thickness of each of insulating layers 550a to 550d is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5.0 nm or less, further preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and even more preferably 1.0 nm or more and 3.0 nm or less. Furthermore, it is preferable that at least a portion of each of insulating layers 550a to 550d includes a region having the thicknesses described above.

[0392] In addition, the thickness of the silicon oxide film used as the insulating layer 550 is preferably 0.7 nm or more and 3 nm or less.

[0393] To reduce the thickness of insulating layers 550a to 550d as described above, deposition using the ALD method is preferred. Furthermore, to deposit insulating layers 550a to 550d within openings in insulating layers 580, etc., deposition using the ALD method is preferred. As the ALD method, thermal ALD, which uses only thermal energy to react the precursor and reactants, and PEALD, which uses reactants excited by plasma, can be employed. In the PEALD method, deposition can be performed at lower temperatures by utilizing plasma, and therefore it is sometimes preferred.

[0394] The ALD method can deposit atoms layer by layer, thus enabling the deposition of very thin films, high aspect ratio structures, deposition with fewer defects such as pinholes, high coverage deposition, and deposition at low temperatures. Therefore, a thin insulating layer 550 can be deposited with high coverage on the sides of the opening formed in the insulating layer 580.

[0395] Note that the precursors used in the ALD method sometimes contain carbon and other impurities. Therefore, films prepared using the ALD method sometimes contain more carbon and other impurities compared to films prepared using other deposition methods. Furthermore, the quantification of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0396] Note that in the description on the top surface, the insulating layer 550 has a four-layer structure consisting of insulating layers 550a to 550d, but the present invention is not limited thereto. The insulating layer 550 may have a structure including at least one of the insulating layers 550a to 550d. By having the insulating layer 550 consist of one, two, or three of the insulating layers 550a to 550d, the manufacturing process of semiconductor devices can be simplified, thereby improving productivity.

[0397] For example, insulating layer 550 may have a three-layer structure. In this case, insulating layer 550 preferably has a stacked structure of insulating layer 550a, insulating layer 550b on insulating layer 550a, and insulating layer 550c on insulating layer 550b. That is, it may also have a structure consisting of insulating layer 550a, insulating layer 550b on insulating layer 550a, and insulating layer 550c on insulating layer 550b. Figure 15A The structure shown is the structure with the insulation layer removed by 550d.

[0398] When forming the insulating layer 550, it is preferable to perform the ALD process twice or more. For example, it is preferable that the insulating layer 550 has a laminated structure composed of multiple insulating films, and that two or more of the multiple insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, the coverage and thickness uniformity of the insulating layer 550 can be improved. In addition, by continuously forming two or more different films, such as two or more insulating films, using the ALD process, productivity can be improved.

[0399] As an example, insulating layer 550a is preferably made of alumina or the like, which has a high ability to trap or fix hydrogen. In addition, insulating layer 550b is preferably made of silicon oxide or the like, which has high dielectric strength. Furthermore, insulating layer 550c is preferably made of hafnium oxide or the like, which has a high ability to trap or fix hydrogen. Furthermore, insulating layer 550d is preferably made of silicon nitride or the like, which has high hydrogen barrier properties.

[0400] exist Figure 14D In this embodiment, the conductive layer 560 has a two-layer structure. Preferably, the conductive layer 560 includes a conductive layer 560a and a conductive layer 560b disposed on the conductive layer 560a. For example, it is preferable that the conductive layer 560a is disposed such that it surrounds the bottom and side surfaces of the conductive layer 560b. In this case, as the conductive layer 560a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of inhibiting oxygen diffusion.

[0401] The conductive layer 560a preferably uses a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0402] Furthermore, by enabling the conductive layer 560a to suppress oxygen diffusion, the decrease in conductivity caused by oxidation of the conductive layer 560b due to oxygen contained in the insulating layer 580, etc., can be prevented. As a conductive material with the function of suppressing oxygen diffusion, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc., are preferably used, for example.

[0403] Furthermore, the conductive layer 560b is preferably a conductive layer with high conductivity. For example, the conductive layer 560b can use a conductive material with tungsten, copper, or aluminum as the main component. In addition, the conductive layer 560b can have a stacked structure, for example, it can have a stacked structure of titanium or titanium nitride and the aforementioned conductive material.

[0404] Furthermore, in transistor 500mf, conductive layer 560 is formed in a self-aligned manner by embedding it into openings formed in insulating layer 580, etc. Here, the side surface of insulating layer 580 in the aforementioned opening is aligned or substantially aligned with the side surface of conductive layer 542a and conductive layer 542b. Therefore, conductive layer 560 can be configured to overlap with the region between conductive layer 542a and conductive layer 542b without positional alignment.

[0405] Conductive layer 542a has a region that serves as one of the source and drain electrodes of transistor 500mf. Conductive layer 540a serves as a connector to conductive layer 542a. Conductive layer 542b has a region that serves as the other of the source and drain electrodes of transistor 500mf. Conductive layer 540b serves as a connector to conductive layer 542b.

[0406] As conductive layers 542a and 542b, conductive materials that are not easily oxidized or conductive materials that have the function of inhibiting oxygen diffusion are preferably used. Examples of such conductive materials include nitrogen-containing conductive materials and oxygen-containing conductive materials. This suppresses the decrease in conductivity of conductive layers 542a and 542b. When conductive materials containing metal and nitrogen are used as conductive layers 542a and 542b, conductive layers 542a and 542b are conductive layers that contain at least metal and nitrogen. For example, as materials for conductive layers 542a and 542b, conductive materials that are not easily oxidized or conductive materials that have the function of inhibiting oxygen diffusion can be selected from the materials that can be used in conductive layer 560 described above.

[0407] Conductive layers 540a and 540b are preferably made of conductive materials with tungsten, copper, or aluminum as the main components. Alternatively, conductive layer 540 may be a laminated structure in which a first conductive layer is disposed in contact with the side of insulating layer 541 and a second conductive layer is disposed inside it. In this case, the aforementioned conductive material can be used as the second conductive layer. Furthermore, conductive layers 540a and 540b may also use the materials described above that can be used in conductive layer 560. Here, the aforementioned first conductive layer corresponds to... Figure 15A The conductive layer 540a1 shown corresponds to the second conductive layer mentioned above. Figure 15A The conductive layer 540a2 is shown.

[0408] Furthermore, when a multilayer structure is adopted as the conductive layer 540, the first conductive layer disposed near the insulating layers 583, 582, 580, and 575 is preferably made of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferred. Alternatively, a single layer or a multilayer of a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen can also be used. By adopting this structure, impurities such as water and hydrogen contained in the layer above the insulating layer 583 can be suppressed from mixing into the semiconductor layer 530 through the conductive layers 540a and 540b.

[0409] As an example, insulating layer 575 preferably uses an oxygen-barrier insulating film. Examples of oxygen-barrier insulating films include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride. Additionally, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0410] As an example, the relative permittivity of insulating layer 580 is preferably lower than that of insulating layer 522. By using a material with a low permittivity in the interlayer film, the parasitic capacitance between wirings can be reduced. Therefore, in insulating layer 580, one or more of the following are preferably used as materials with a low relative permittivity: silicon oxide, silicon oxynitride, fluorinated silicon oxide, carbon-containing silicon oxide, silicon oxide containing both carbon and nitrogen, and porous silicon oxide.

[0411] In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. They are also preferred because materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released during heating.

[0412] Furthermore, at this time, the top surface of the insulating layer 580 is preferably planarized. Therefore, the insulating layer 580 is preferably also used as a planarization film.

[0413] As described above, insulating layer 580 can use the same material as insulating layer 516.

[0414] One or both of insulating layers 582 and 583 are preferably used as barrier insulating layers to suppress diffusion from above insulating layers 582 and 583 to transistor 500mf, etc. Therefore, one or both of insulating layers 582 and 583 preferably contain an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. (making it difficult for the aforementioned impurities to permeate). Furthermore, it is preferable to contain an insulating material that has the function of suppressing the diffusion of oxygen (making it difficult for the aforementioned oxygen to permeate).

[0415] Both insulating layers 582 and 583 preferably include insulating layers that suppress the diffusion of impurities such as water, hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon oxynitride can be used. For example, insulating layer 583 is preferably made of silicon nitride, which has higher hydrogen barrier properties. Furthermore, insulating layer 582 is preferably made of aluminum oxide, which has a high ability to trap or fix hydrogen.

[0416] The semiconductor layer 530 is formed on the insulating layer 522 in contact with it. For example... Figure 15B and Figure 15C As shown, the semiconductor layer 530 has a high aspect ratio when viewed in cross-section along the channel width direction. Therefore, it can be said that the semiconductor layer 530 has a fin-like shape.

[0417] Here, the aspect ratio of the semiconductor layer 530 when viewed in cross-section along the channel width direction refers to the ratio of the length L of the semiconductor layer 530 in the direction of the dashed line A1-A2 (also referred to as the width L of the semiconductor layer 530) to the length H (also referred to as the height H of the semiconductor layer 530) in the direction perpendicular to the surface of the semiconductor layer 530 (e.g., the insulating layer 522). The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range that will not cause the semiconductor layer 530 to collapse during the manufacturing process of the transistor 500mf. In the semiconductor layer 530, the height H is at least greater than the width L. The height H of the semiconductor layer 530 can be greater than 1 times and less than 400 times the width L, for example, preferably more than 2 times and less than 100 times, more preferably more than 5 times and less than 40 times, and even more preferably more than 10 times and less than 20 times. Furthermore, for example, the height H is preferably more than twice and less than ten times the width L. For example, the width L is preferably set to 5 nm or more and less than 100 nm, more preferably 5 nm or more and less than 50 nm, and more preferably 10 nm or more and less than 30 nm. Additionally, for example, the height H is preferably 50 nm or more and less than 2000 nm, and more preferably 100 nm or more and less than 1000 nm. Alternatively, for example, the height H can be 50 nm or more and less than 100 nm.

[0418] In addition, such as Figure 15B As shown, when viewed in a cross-section along the channel width direction, the angle θ formed by the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably perpendicular or substantially perpendicular. For example, the angle θ is preferably 80° or more and 100° or less, more preferably 85° or more and 95° or less.

[0419] An insulating layer 550, a conductive layer 560, and a conductive layer 542 are disposed to cover the aforementioned high aspect ratio semiconductor layer 530. In transistor 500mf, as... Figure 15B As shown, an insulating layer 550 and a portion of a conductive layer 560 are disposed in a folded state, sandwiching a semiconductor layer 530. Thus, when viewed in cross-section along the channel width direction, the semiconductor layer 530 and the conductive layer 560 are disposed with the insulating layer 550 sandwiched between them and facing each other. In other words, the top, side of A1, and side of A2 of the semiconductor layer 530 are all used as channel formation regions. Therefore, compared to the case where the semiconductor layer 530 is formed as a flat plate, the channel width of the transistor 500mf is increased by the size of the side of A1 and side of the semiconductor layer 530.

[0420] By increasing the channel width as described above, the on-state current of transistor 500mf can be increased. Furthermore, the transconductance of transistor 500mf is improved. Additionally, the frequency characteristics of transistor 500mf are improved. By using transistor 500mf in one or both of the pixel circuit and driving circuit included in a display device, a display device with a high frame rate can be provided. Furthermore, in the above structure, by providing semiconductor layer 530, the channel width can be increased without increasing the occupied area of ​​transistor 500mf. Therefore, miniaturization or high integration of the pixel circuit and driving circuit can be achieved.

[0421] In addition, such as Figure 15B As shown, the upper portion of the semiconductor layer 530 preferably has a curved shape. This curved shape prevents defects such as voids from forming in the insulating layer 550 and the conductive layer 542 near the top of the semiconductor layer 530. Note that although in Figure 14B and Figure 15C The invention employs a curved, symmetrical structure on both sides of the top of semiconductor layer 530, namely the A1 side (A3 side) and the A2 side (A4 side), but the invention is not limited thereto. For example, sometimes one of the A1 side (A3 side) and the A2 side (A4 side) of the top of semiconductor layer 530 has a curved, asymmetrical structure.

[0422] Because the semiconductor layer 530 has a high aspect ratio shape, when forming the semiconductor layer 530, it is preferable to form the pillars in one step, and then form the semiconductor layer 530 as a sidewall on the side of the pillars. Therefore, the semiconductor layer 530 is preferably formed using the ALD method, which has good coverage. In addition, when the semiconductor layer 530 has a stacked structure, it is preferable to deposit at least one layer using the ALD method, and particularly preferably to deposit the layer in contact with the pillars using the ALD method.

[0423] The semiconductor layer 530 is formed into a sidewall shape by contacting the sides of multiple pillars, such as... Figure 14A As shown, multiple semiconductor layers 530 can be formed simultaneously. Thus, by forming multiple semiconductor layers 530, the distance between each semiconductor layer 530 can be set according to the size and shape of the pillar. This reduces the distance between the semiconductor layers 530 and decreases the area occupied by the transistors 500mf, thereby achieving high integration of the display device.

[0424] Because the semiconductor layer 530 is formed as a sidewall in a manner that contacts the pillar, thus... Figure 14A As shown, the top surface of semiconductor layer 530 has a circumferential shape (also referred to as a frame, ring, donut, or closed curve) with both ends aligned. Alternatively, semiconductor layer 530 can be described as having a shape including an opening in the central portion. Note that in... Figure 14A In this invention, the top surface shape of semiconductor layer 530 is a line-symmetrical shape centered on the dotted line A1-A2, but the invention is not limited to this. For example, the top surface shape of semiconductor layer 530 can also be an asymmetrical shape.

[0425] exist Figure 14A In the structure shown, two pillars are arranged along the dotted line A1-A2, and a circumferential semiconductor layer 530 is formed in contact with the side of each pillar. For example... Figure 14A As shown, the semiconductor layer 530 preferably overlaps with the conductive layer 560 in more than two portions when viewed from above. That is, the structure has more than two regions where the semiconductor layer 530 and the conductive layer 560 overlap. By adopting this structure, as... Figure 14B As shown, multiple fin-shaped semiconductor layers 530 are formed when viewed in cross-section along the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 serves as a channel formation region. In other words, the transistor 500mf is used as a multi-channel transistor. Therefore, the channel width can be further increased in the transistor 500mf. Because it includes multiple fin-shaped semiconductor layers 530, the transistor 500mf is sometimes referred to as a multi-fin structure transistor.

[0426] Although the structure with two circumferential semiconductor layers 530 has been described above, the present invention is not limited thereto. For example, one or more circumferential semiconductor layers 530 may be provided. Furthermore, the circumferential semiconductor layers 530 may be combined to form a semiconductor layer 530 having a shape with multiple openings.

[0427] Although the circumferential semiconductor layer 530 has been described above, the present invention is not limited thereto. For example, the semiconductor layer 530 may not be circumferential. Figures 14A to 14D The transistor shown is 500mF, for example, it can also be as follows Figures 16A to 16DAs shown in transistor 500sf, the number of finned semiconductor layers 530 intersecting with conductive layer 540a, insulating layer 550, conductive layer 560, and conductive layer 540b is one. Furthermore, the three-dimensional schematic diagram of this transistor is as follows: Figure 17A and Figure 17B As shown. Thus, by reducing the number of finned semiconductor layers 530 intersecting with conductive layer 540a, insulating layer 550, conductive layer 560, and conductive layer 540b, the transistor's formation area can be reduced, thereby shrinking the area occupied by the circuit including the transistor. Note that... Figures 16A to 16D The accompanying drawings and their reference numerals are consistent with Figures 14A to 14D Correspondingly, the detailed structure can be found in the above content.

[0428] <Example 2 of cross-sectional structure> Figure 18 Is with Figure 12 Different Figure 10A , Figure 10B and Figure 11 The diagram shows a cross-sectional schematic of an example of a storage circuit MDV.

[0429] Figure 18 MDV storage circuit and Figure 12 The difference between the storage circuit MDV and the SS2 layer is that the transistors in the SS2 layer are vertical channel transistors.

[0430] Figure 18 Transistors MN11 and MN12 shown have a structure where the source and drain electrodes are located at different heights and the current flowing through the semiconductor layer flows in the height direction. In other words, because the channel length direction has a component in the height direction (vertical direction), they are called vertical channel transistors. Besides being called vertical channel transistors, transistors MN11 and MN12 can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, etc.

[0431] in addition, Figure 19A A plan view of an example of a memory storage device (MDV) circuit is shown. Figure 19B A cross-sectional schematic diagram of the computing device is shown. Figure 18 It is along Figure 19A The diagram shows a cross-section of the dotted line A1-A2. Additionally, Figure 19B It is along Figure 19A The diagram shows a cross-section along the dotted line A3-A4. Note that... Figure 19B The transistors and capacitors in layer SS2 are shown.

[0432] Reference Figure 19BExplain the structure of the longitudinal channel transistors and capacitors included in the MDV storage circuit.

[0433] Figure 19B Includes: a transistor MN12 that is a vertical channel transistor; a capacitor C1 located above the transistor MN12; and a transistor MN11 located above the capacitor C1.

[0434] As an example, layer SS2 includes: a conductive layer serving as wiring RBL, an insulating layer IS1 serving as an interlayer film, a conductive layer serving as wiring RWL, a semiconductor layer SC1 containing the channel formation region of transistor MN12, an insulating layer GI1 serving as the gate insulating film of transistor MN12, a conductive layer ME3, a conductive layer ME4, an insulating layer DI serving as a dielectric, a conductive layer serving as wiring VGE, an insulating layer IS2 serving as an interlayer film, a conductive layer serving as wiring WBL, a semiconductor layer SC1 containing the channel formation region of transistor MN11, an insulating layer GI2 serving as the gate insulating film of transistor MN11, a conductive layer ME6, and a conductive layer serving as wiring WWL.

[0435] An insulating layer IS1 and a conductive layer RWL are sequentially stacked above the conductive layer that forms the wiring RBL. Furthermore, a shared opening is formed in the conductive layer forming the wiring RBL, the insulating layer IS1, and the conductive layer forming the wiring RWL. A semiconductor layer SC1 is formed on the side and bottom of this opening. The semiconductor layer SC1 is also formed on the top surface of the conductive layer forming the wiring RWL. Additionally, an insulating layer GI1 is formed on the top surface of the semiconductor layer SC1, on the side surface of the conductive layer forming the wiring RWL, and above the insulating layer IS1. Furthermore, a conductive layer ME3 is formed on the top surface of the insulating layer GI1 by embedding the opening. Finally, a conductive layer ME4 is formed on the top surface of the conductive layer ME3.

[0436] The conductive layer that forms part of wiring RBL serves as one of the source and drain terminals of transistor MN12. Similarly, the conductive layer that forms part of wiring RWL serves as the other of the source and drain terminals of transistor MN12. Additionally, a portion of conductive layer ME3 serves as the gate terminal of transistor MN12.

[0437] As described above, by forming an insulating layer, a conductive layer, and a semiconductor layer, a vertical channel transistor with a height component (vertical direction) along its channel length can be formed. Furthermore, the channel length of the vertical channel transistor depends on the thickness of the insulating layer IS1; the thinner the insulating layer IS1, the shorter the channel length, and the larger the on-state current of the transistor MN12. Conversely, the thicker the insulating layer IS1, the longer the channel length, and the smaller the off-state current of the transistor MN12.

[0438] In addition, such as Figure 19AAs shown, the conductive layer that forms the conductive layer of the wiring RBL is arranged along the direction of the dotted line A1-A2. Additionally, as... Figure 19A As shown, the conductive layer that forms the wiring RWL is set along the direction of the dotted line A3-A4.

[0439] The wiring connecting the vertical channel transistor is not formed in the same process, but in different processes. Therefore, the wirings connecting the vertical channel transistor have overlapping areas when viewed from a planar perspective. In other words, because the wirings connecting the vertical channel transistor are positioned at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows for an increase in the driving frequency of transistor MN12, thereby increasing the driving speed of the memory circuit MDV.

[0440] Additionally, a conductive layer ME4 is formed above the conductive layer ME3, and an insulating layer DI and a conductive layer forming the wiring VGE are sequentially stacked above the conductive layer ME4. Specifically, for example, in Figure 18 and Figure 19B In the conductive layer ME4, an insulating layer DI is formed on the side and top surfaces, and a conductive layer that serves as wiring VGE is formed in such a way that it includes the area that overlaps with the side surface of the conductive layer ME4.

[0441] Here, a capacitor C1 is formed in the region where the conductive layer ME4 and the conductive layer that forms the wiring VGE overlap, separated by the insulating layer DI. For example, a portion of the conductive layer ME4 serves as one of the two electrodes of the capacitor C1, and a portion of the conductive layer that forms the wiring VGE serves as the other of the two electrodes of the capacitor C1. Furthermore, as... Figure 19A As shown, the conductive layer that forms the wiring VGE is set along the direction of the dotted line A1-A2.

[0442] Above the conductive layer ME4, an insulating layer DI, an insulating layer IS2, and a conductive layer forming the wiring WBL are stacked sequentially. Furthermore, a shared opening is formed in the conductive layer ME4, the insulating layer DI, the insulating layer IS2, and the conductive layer forming the wiring WBL. A semiconductor layer SC2 is formed on the side and bottom of this opening. The semiconductor layer SC2 is also formed on the top surface of the conductive layer forming the wiring WBL. Additionally, an insulating layer GI2 is formed on the top surface of the semiconductor layer SC2, on the side of the conductive layer forming the wiring WBL, and above the insulating layer IS2. Furthermore, a conductive layer ME6 is formed on the top surface of the insulating layer GI2 by embedding the opening. Finally, a conductive layer forming the wiring WWL is formed on the top surface of the conductive layer ME6.

[0443] A portion of conductive layer ME4 serves as one of the source and drain terminals of transistor MN11. Additionally, a portion of the conductive layer forming wiring WBL serves as the other of the source and drain terminals of transistor MN11. Furthermore, a portion of conductive layer ME6 serves as the gate terminal of transistor MN11.

[0444] Furthermore, similar to transistor MN12, the channel length of transistor MN11 depends on the thickness of the insulating layer IS2. Therefore, the thinner the insulating layer IS2, the larger the on-state current of transistor MN11. On the other hand, the thicker the insulating layer IS2, the smaller the off-state current of transistor MN11.

[0445] In addition, such as Figure 19A As shown, the conductive layer that forms the conductive layer of the wiring WBL is arranged along the direction of the dotted line A1-A2. Additionally, as... Figure 19A As shown, the conductive layer that forms the wiring WWL is set along the direction of the dotted line A3-A4.

[0446] As described above, by using vertical channel transistors as transistors MN11 and MN12 respectively, transistors MN11 and MN12 can be overlapped. This reduces the circuit area of ​​the memory circuit MDV.

[0447] <Example 3 of cross-sectional structure> Figure 20 Is with Figure 12 Different Figure 10A , Figure 10B and Figure 11 The diagram shows a cross-sectional schematic of an example of a storage circuit MDV.

[0448] Figure 20 MDV's storage circuit includes multiple Figure 10A and Figure 11 The layer SS2 shown here is similar to this point. Figure 12 The storage circuit shown is different from MDV. Additionally, in Figure 20 In the storage circuit MDV, layer SS2[1] and layer SS2[2] are shown as multiple layers SS2.

[0449] about Figure 20 The storage circuit MDV layer SS1 can be referenced. Figure 12 The description of layer SS1 of the MDV storage circuit. Additionally, regarding... Figure 20 The storage circuit MDV layer SS2[1] can be referred to Figure 12 The description of layer SS2 of the MDV storage circuit. That is to say, Figure 20 MDV storage circuits can have in Figure 12 The storage circuit MDV has a structure with layer SS2[2] above it.

[0450] Figure 20 The storage circuit MDV's layer SS2[2] includes a substrate BS. Additionally, transistors MN11 and MN12, and capacitor C1 are formed on the substrate BS. Note that although the structure of the storage cell 10 formed on the substrate BS is similar to... Figure 12 The storage cells 10 included in layer SS2 of the MDV storage circuit are the same, but can be changed as needed. Figure 20 The structure of the storage unit 10.

[0451] Note that the substrate BS can be any substrate that can be used in layer SS1 (e.g., substrate 311). For example, by using a semiconductor substrate made of silicon as the substrate BS, the transistors included in layer SS2[2] can be Si transistors. In addition, by using through-electrode technology (e.g., TSV: Through Silicon Via), layer SS2[1] and layer SS2[2] can be connected to each other through the substrate BS.

[0452] Alternatively, flip-chip bonding or wire bonding can be used as methods for mounting the substrate BS on the substrate 311. Alternatively, a bonding layer can be provided between the bonded substrates using one or both of surface-activated bonding and hydrophilic bonding methods. Alternatively, Cu-Cu (copper-copper) direct bonding can be used.

[0453] Note that the semiconductor device of one embodiment of the present invention is not limited to... Figure 10A , Figure 10B , Figure 11 , Figure 12 , Figure 18 and Figure 20 The structure shown. The semiconductor device of one aspect of the present invention can also be suitably modified. Figure 10A , Figure 10B , Figure 11 , Figure 12 , Figure 18 and Figure 20 The structure.

[0454] For example, in Figure 20 In the storage circuit MDV, the two layers SS2[1] and SS2[2] are shown as the layers including the storage unit 10, but the layers including the storage unit 10 can also be three or more.

[0455] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0456] (Implementation Method 3) In this embodiment, a processing apparatus according to one aspect of the present invention will be described.

[0457] Figure 21 A three-dimensional schematic diagram of the processing device 960 is shown. Figure 21 The processing device 960 shown can be used, for example, as a CPU. Alternatively, the processing device 960 can also be used with processors such as GPUs, TPUs (Tensor Processing Units), and NPUs (Neural Processing Units) that have multiple (tens to hundreds) processor cores capable of parallel processing compared to a CPU.

[0458] Figure 21 The processing device 960 shown includes, on a substrate 990: an ALU 991 (ALU: Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, etc. The processing device 960 may also include a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may be located on different chips.

[0459] Cache 999 is connected to the main memory located on different chips via cache interface 989. Cache interface 989 has the function of supplying a portion of the data stored in the main memory to cache 999. In addition, cache interface 989 has the function of outputting a portion of the data held in cache 999 to ALU 991 or register 996 via bus interface 998.

[0460] Note that the cache 999 may, for example, include the storage circuit MDV described in Embodiment 2. In this case, the processing device 960 includes the storage cell 10 and the drive circuit region 50 described in Embodiment 2. Therefore, it is sometimes possible to miniaturize the processing device 960 and increase the drive frequency of the processing device 960.

[0461] Figure 21 The processing device 960 shown is merely an example with a simplified structure; therefore, the actual processing device 960 has a wide variety of structures depending on its application. For example, it is preferable to include... Figure 21 The processing device 960 shown has a single core structure, employing a so-called multi-core architecture that includes multiple cores and allows them to operate simultaneously. The more cores, the better the computing performance. More cores are preferred; for example, two cores are preferred, four cores are more preferred, eight cores are even more preferred, twelve cores are still more preferred, and sixteen cores or more are even more preferred. Furthermore, when used in servers or other applications requiring very high computing performance, a multi-core architecture with 16 or more cores is preferred, more preferably 32 or more cores, and more preferably 64 or more cores. Additionally, the number of bits that the processing device 960 can process in its internal processing circuitry, data bus, etc., can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or more.

[0462] Instructions input to the processing unit 960 via the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997 and timing controller 995.

[0463] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when the processing device 960 executes a program, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc., based on their priority and mask status. The register controller 997 generates the address of register 996 and reads or writes register 996 according to the state of the processing device 960.

[0464] In addition, the timing controller 995 generates signals to control the operating timing of the ALU 991, ALU controller 992, instruction decoder 993, interrupt controller 994, and register controller 997. For example, the timing controller 995 has an internal clock generator that generates an internal clock signal based on a reference clock signal and supplies the internal clock signal to the aforementioned circuits.

[0465] exist Figure 21 In the processing apparatus 960 shown, the register controller 997 selects the holding operation in register 996 according to instructions from ALU 991. For example, the register controller 997 can select whether to write data to register 996 or read data from register 996 according to instructions from ALU 991.

[0466] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc., shown in this embodiment can be appropriately combined with those shown in other embodiments.

[0467] (Implementation Method 4) This embodiment describes an application example of a storage device including a storage circuit according to one aspect of the present invention.

[0468] Generally speaking, various storage devices are used in semiconductor devices such as computers, depending on their purpose. Figure 22A The various memory devices used in semiconductor devices are shown in a hierarchical manner. Higher-level memory devices are required to operate at faster speeds, while lower-level memory devices are required to have larger storage capacities and higher recording densities. Figure 22A In this system, from the top layer onwards, there are memory stored as registers in the CPU and other arithmetic processing units (sometimes referred to as processing units), L1 cache, L2 cache, L3 cache, main memory, secondary storage, etc. Note that although an example including up to L3 cache is shown here, it may also include caches at lower levels.

[0469] Note that the storage circuit MDV described in Embodiment 2 above can be used as a memory included in an arithmetic processing device. For example, the storage circuit MDV can be used as a register, L1 cache to L3 cache, or other memory.

[0470] Because the memory installed along with registers in arithmetic processing devices such as CPUs is used for temporary storage of calculation results, it is accessed frequently by the processing device. Therefore, a faster operating speed is required compared to storage capacity. Furthermore, registers also have the function of holding settings information of the processing device.

[0471] A cache is a device that copies and maintains a portion of the data that is held in main memory. By copying frequently used data into the cache, the speed of data access can be improved. A cache requires less storage capacity than main memory, but it requires a higher operating speed. Furthermore, data that is overwritten in the cache is copied and fed back to main memory.

[0472] The main memory has the function of storing programs, data, etc. read from secondary storage.

[0473] Secondary storage serves to hold data that needs to be preserved long-term and various programs used by computing devices. Therefore, compared to faster operating speeds, secondary storage requires larger storage capacity and higher recording density. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0474] According to one aspect of the present invention, a storage device using oxide semiconductors (OS memory) operates at high speed and can retain data for a long time. For example, the OS memory has the features shown in the table below.

[0475] [Table 1] By utilizing the features of the OS memory shown in the table above, such as Figure 22A As shown, a storage device according to one aspect of the present invention can be used for both a cache level and a main memory level. Additionally, a storage device according to one aspect of the present invention can also be used for a level including secondary storage.

[0476] in addition, Figure 22B Examples are shown of cases where SRAM is used for one part of the cache and OS memory of one aspect of the present invention is used for another part.

[0477] The lowest level cache can be referred to as an LLC (Last Level cache). LLCs do not require faster operating speeds than their parent caches, but are required to have larger storage capacity. One embodiment of the OS memory of this invention has a fast operating speed and can retain data for long periods, making it suitable for use with LLCs. Note that one embodiment of the OS memory of this invention can also be used with FLCs (Final Level caches).

[0478] For example, such as Figure 22B As shown, SRAM can be used for higher-level caches (L1 cache, L2 cache, etc.), and the OS memory of one embodiment of the present invention can be used for LLC. Additionally, as... Figure 22B As shown, DRAM can also be used in main memory in addition to OS memory.

[0479] Furthermore, the high power consumption of L3 cache and DRAM, which serve as main memory, in supercomputers and servers using supercomputers is one of the contributing factors to global warming. Figure 22A In this system, both the L3 cache and main memory use OS memory. Additionally, in... Figure 22BIn this method, the OS memory is used for the LLC. Thus, by using oxide semiconductors according to one aspect of the invention for the storage device, the power consumption of the supercomputer can be reduced, thereby enabling the supercomputer to consume power at a level comparable to that of a personal computer.

[0480] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0481] (Implementation Method 5) In this embodiment, electronic components, electronic devices, mainframe computers, space devices, and data centers (also known as DCs) that can use the storage circuits or storage devices including storage circuits described in the above embodiments are explained. Electronic components, electronic devices, mainframe computers, space devices, and data centers using semiconductor devices according to one aspect of the present invention are highly effective in achieving high performance such as low power consumption.

[0482] [Electronic Components] Figure 23A A three-dimensional view of electronic component 700 is shown. Figure 23A The illustrated electronic component 700 includes a substrate 701, a semiconductor device 710 on the substrate 701, and a mold 711. Specifically, the semiconductor device 710 is sealed by the mold 711. Note that in... Figure 23A In the text, a portion of the description of electronic component 700 is omitted to indicate its internal structure.

[0483] As the substrate 701, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used.

[0484] The electronic component 700 is provided with a lead frame 712, for example. A portion of the lead frame 712 located on the substrate 701 is covered by a mold 711, and another portion of the lead frame 712 is exposed outside the mold 711. In particular, the lead frame 712 exposed outside the mold 711 is used, for example, as a terminal for mounting the electronic component 700 to a printed circuit board.

[0485] In mold 711, lead frame 712 has electrode pads 713, which are electrically connected to semiconductor device 710 via leads 714. Electronic component 700 is mounted on printed circuit board, for example, by making lead frame 712 contact with wiring on one side of printed circuit board. In this way, by combining multiple electronic components and electrically connecting them on printed circuit board, a circuit board is completed.

[0486] Next, the semiconductor device 710 will be described. For example, such as Figure 23B As shown, the semiconductor device 710 includes a driving circuit layer 715 and a memory layer 716. The memory layer 716 may have a structure in which multiple memory cell arrays are stacked. In addition, the semiconductor device 710 may include the memory circuit or memory device described in the above embodiments.

[0487] The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, the layers can be connected without the need for through-electrode techniques (e.g., TSV) and Cu-Cu (copper-copper) direct bonding. When the driver circuit layer 715 and the memory layer 716 are stacked monolithically, for example, a so-called on-chip memory structure, in which memory is directly formed on the processor, can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0488] Furthermore, by employing an on-chip memory structure, the size of interconnect wiring can be reduced compared to through-electrode techniques such as TSVs, thus allowing for an increase in the number of pins. Increasing the number of pins enables parallel operation, thereby improving the memory's bandwidth.

[0489] Furthermore, it is preferable to use OS transistors to form multiple memory cell arrays in memory layer 716, and to stack these multiple memory cell arrays monolithically. When multiple memory cell arrays are stacked monolithically, one or both of the memory's bandwidth and access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange. When using Si transistors in memory layer 716, it is more difficult to employ a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0490] Furthermore, the semiconductor device 710 is sometimes referred to as a bare die. In this specification and the like, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into small rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0491] then, Figure 23C A variation of electronic component 700 is shown. Unlike electronic component 700, Figure 23CIn the illustrated electronic component 700A, an electrode 733 is provided on the bottom of the substrate 701 instead of a lead frame 712. The electrode 733 serves as a connection terminal for mounting the electronic component 700A onto a printed circuit board.

[0492] Figure 23C An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix on the bottom of substrate 701. Therefore, substrate 701 is provided with vias (through-holes) through which conductive layers 732 for wiring are disposed. Electrode pads 713 are disposed on substrate 701 above the conductive layer 732 in contact with ground, and electrodes 733 are disposed below substrate 701, below the conductive layer 732 in contact with ground.

[0493] Furthermore, electrode 733 can also be formed using conductive pins instead of solder balls. By arranging conductive pins in a matrix on the bottom of substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0494] Furthermore, the 700A electronic component can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0495] Alternatively, the electronic component of one embodiment of the present invention can also be in the form of SiP (System in Package) or MCM (Multi-Chip Module). For example, in Figure 23D In the electronic component 700C shown, an interposer 731 is provided on the packaging substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0496] exist Figure 23DIn the electronic component 700C, an example is shown where the semiconductor device 710 is used as a high-bandwidth memory (HBM). Additionally, the semiconductor device 735 can be used, for example, as a computing circuit in an integrated circuit such as a CPU, GPU, or FPGA (Field Programmable Gate Array).

[0497] Similar to substrate 701, packaging substrate 734 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. Through-hole 731 can be, for example, a silicon through-hole or a resin through-hole.

[0498] The through-hole board 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal spacings. The multiple wirings are arranged in a single layer or multiple layers. Additionally, the through-hole board 731 functions to electrically connect integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 734. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Furthermore, sometimes a through electrode is provided in the through-hole board 731 to electrically connect the integrated circuit to the package substrate 734. Moreover, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0499] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0500] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally on the interposer.

[0501] On the other hand, when multiple integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when it is desired to reduce the size of the electronic component 700C, the width of the aforementioned terminal pitch becomes a problem, and it is sometimes difficult to set to achieve the required amount of wiring to achieve a wider memory bandwidth. Therefore, as mentioned above, a monolithic stacked structure using OS transistors is preferred. Alternatively, for example, a memory cell array utilizing TSV stacking and a memory cell array stacked monolithically can be combined. Furthermore, the structure combining a memory cell array utilizing TSV stacking and a memory cell array stacked monolithically is sometimes referred to as a composite structure.

[0502] Furthermore, when the temperature of the electronic component 700C rises due to current heat or other reasons, the characteristics of the circuit components (e.g., transistors) included in the electronic component 700C may degrade. Therefore, it is preferable to provide a heat sink (heat plate) overlapping the electronic component 700C. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the insert 731 consistent. For example, in the electronic component 700C shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0503] [Electronic Devices] then, Figure 24A A 3D view of electronic device 6500 is shown. Figure 24A The illustrated electronic device 6500 is a portable information terminal device that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more components selected from a CPU, a GPU, and a memory circuit. A semiconductor device according to one aspect of the present invention can be used in the display unit 6502, the control device 6509, etc.

[0504] Figure 24B The illustrated electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, one or more selected from CPU, GPU, and memory circuitry. A semiconductor device according to one aspect of the present invention can be used in the display unit 6615, the control device 6616, etc.

[0505] By using a semiconductor device according to one aspect of the present invention in the above-described control devices 6509 and 6616, power consumption can be reduced, and therefore it is preferred.

[0506] [Mainframe Computer] then, Figure 24C A perspective view shows multiple large-scale computers 5600 installed in server rooms, etc. Figure 24C In the mainframe computer 5600 shown, multiple rack-mounted computers 5620 are housed in rack 5610. Additionally, the mainframe computer 5600 is sometimes referred to as a supercomputer.

[0507] The computer 5620 includes a motherboard with multiple slots, multiple connection terminals, etc. For example, one or more PC cards can be inserted into the slots.

[0508] This PC card is an example of a processing board that includes computing devices such as CPU and GPU. For example, electronic component 700 can be used as this computing device.

[0509] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0510] [Space Equipment] The semiconductor device of one aspect of the present invention can be applied to space devices (e.g., devices with the function of processing and storing information).

[0511] One aspect of the semiconductor device of the present invention may include an OS transistor. The OS transistor exhibits minimal change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation and is therefore suitable for environments where radiation may be incident. For example, the OS transistor is suitable for use in space.

[0512] exist Figure 25 The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Additionally, Figure 25 An example of a planet 6804 in outer space is shown. Note that outer space, for example, refers to an altitude of 100 km or higher, but the outer space described in this specification includes the thermosphere, mesosphere, and stratosphere.

[0513] In addition, although Figure 25 Although not illustrated, a battery management system (also known as a "BMS") or battery control circuit can also be configured for the secondary battery 6805. When an OS transistor is used in the aforementioned battery management system or battery control circuit, low power consumption and high reliability can be achieved even in space, making it a preferred option.

[0514] Furthermore, outer space is an environment where the radiation dose is more than 100 times that on Earth. Other examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0515] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, a secondary battery 6805 can be installed in the satellite 6800. Furthermore, the solar panel is sometimes referred to as a solar cell module.

[0516] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0517] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 uses, for example, one or more components selected from CPU, GPU, and memory circuitry. Additionally, a semiconductor device according to one aspect of the present invention is preferably used as the control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to radiation exposure. That is, they possess high reliability and are suitable for use even in environments where radiation is likely to occur.

[0518] Furthermore, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0519] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, the semiconductor device of one aspect of the invention can also be applied to space devices such as spacecraft, space capsules, and space probes.

[0520] As explained above, OS transistors offer superior performance compared to Si transistors, such as enabling wider memory bandwidth and higher radiation resistance.

[0521] [Data Center] For example, a semiconductor device according to one aspect of the present invention can be applied to secondary storage systems used in data centers, etc. Data centers are required to manage data over long periods, ensuring data immutability, etc. Long-term data management necessitates large-scale facilities, such as setting up secondary storage and servers to store massive amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment is available for data retention.

[0522] By using the storage circuit of one embodiment of the present invention in a secondary storage system employed in a data center, the power consumption required to retain data can be reduced, and the storage circuit for retaining data can be miniaturized. Therefore, miniaturization of the secondary storage system, miniaturization of the power supply used to retain data, and reduction in the size of cooling equipment are possible. This results in space savings in the data center.

[0523] Furthermore, the storage circuit of one embodiment of the present invention has low power consumption, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Additionally, by using the storage circuit of one embodiment of the present invention, a data center can operate stably even in high-temperature environments. Therefore, the reliability of the data center can be improved.

[0524] Figure 26 This illustrates a secondary storage system that can be used in data centers. Figure 26 The secondary storage system 7000 shown includes multiple servers 7001sb as hosts 7001 (illustrated as the main computer). Additionally, secondary storage 7003 includes multiple storage devices 7003md. Figure 26 The diagram shows the configuration in which the host 7001 and secondary storage 7003 are connected via a secondary storage area network 7004 (illustrated as SAN) and a secondary storage control circuit 7002 (illustrated as secondary storage controller).

[0525] Host 7001 can be a computer that accesses data stored in secondary storage 7003. Hosts 7001 are sometimes connected to each other via a network.

[0526] In the secondary storage 7003, flash memory is used to shorten data access speed, i.e., to shorten the time required for data storage and output. However, this time is much longer than that required by DRAM (Dynamic Random Access Memory), which can be used as cache memory in secondary storage. In secondary storage systems, to address the issue of the long access speed of the secondary storage 7003, cache memory is generally incorporated into the secondary storage to shorten the time required for data storage and output.

[0527] The aforementioned cache memory is used in the secondary storage control circuit 7002 and the secondary storage 7003. Data exchanged between the host 7001 and the secondary storage 7003 is output to the host 7001 or the secondary storage 7003 after being stored in the cache memory in the secondary storage control circuit 7002 and the secondary storage 7003.

[0528] When OS transistors are used to maintain the potential corresponding to the data in the aforementioned cache memory, the refresh frequency of the data can be reduced to lower power consumption. Furthermore, miniaturization can be achieved through stacked memory cell arrays.

[0529] Note that by using the semiconductor device of one aspect of the present invention in any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, a reduction in power consumption can be expected. Therefore, it is currently believed that with the increasing energy demands of high-performance or highly integrated semiconductor devices, the use of the semiconductor device of one aspect of the present invention can also reduce emissions of greenhouse gases, such as carbon dioxide (CO2). Furthermore, the semiconductor device of one aspect of the present invention has low power consumption, and is therefore effective as a measure against global warming.

[0530] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0531] [Symbol Explanation] ADDR: Signal, BL: Wiring, BLB: Wiring, BS: Substrate, BW: Signal, CE: Signal, CLK: Signal, CSEL: Wiring, DBL: Wiring, DBLB: Wiring, DBSW: Switch, DI: Insulating Layer, DSW: Switch, GW: Signal, HSW: Switch, IT: Terminal, ITB: Terminal, LSW: Switch, LTSA: Sensing Amplifier, MC: Memory Cell, MCA: Memory Cell Array, MDV: Memory Circuit, MEG: Conductive Layer, MN11: Transistor, MN12: Transistor, MN13: Transistor, ND: Node, PCP: Parasitic Capacitance, PREB: Wiring, RBL: Wiring, RDA: Signal, RE: Wiring, REB: Wiring RWL: Routing, SWE: Routing, SWEB: Routing, T01: Period, T02: Period, T03: Period, T04: Period, T05: Period, T06: Period, T07: Period, T11: Period, T12: Period, T13: Period, T14: Period, T15: Period, T16: Period, T17: Period, T21: Period, T22: Period, T23: Period, T24: Period, T25: Period, T26: Period, T27: Period, T31: Period, T32: Period, T33: Period, T34: Period, T35: Period, T36: Period, TrP: Transistor, TrQ: Transistor, VDE: Routing, VGE: Routing, VHE: Routing, V PE: Wiring, VRE: Wiring, VSE: Wiring, WAKE: Signal, WBL: Wiring, WDA: Signal, WE: Wiring, WEB: Wiring, WRC: Amplifier Circuit, WRCA: Amplifier Circuit, WWL: Wiring, 10: Memory Cell, 22: PSW, 23: PSW, 31: Peripheral Circuit, 32: Control Circuit, 33: Voltage Generation Circuit, 40: Amplifier Circuit, 41: Peripheral Circuit, 42: Row Decoder, 43: Row Driver, 44: Column Decoder, 45: Column Driver, 47: Input Circuit, 48: Output Circuit, 50: Driver Circuit Area, 311: Substrate, 313: Semiconductor Area, 314a: Low Resistance Area, 314b: Low Resistance Area, 315: Insulation Layers: 316: Conductive layer, 317: Insulating layer, 320: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 352: Insulating layer, 354: Insulating layer, 356: Conductive layer, 357: Insulating layer, 400: Transistor, 500mf: Transistor, 500sf: Transistor, 514: Insulating layer, 516: Insulating layer, 521: Insulating layer, 522: Insulating layer, 530: Semiconductor layer, 530a: Semiconductor layer, 530b: Semiconductor layer, 530c: Semiconductor layer, 540: Conductive layer, 540a: Conductive layer, 540b: Conductive layer, 541: Insulating layer, 541a: Insulating layer, 541b: Insulating layer.542: Conductive layer, 542a: Conductive layer, 542b: Conductive layer, 550: Insulating layer, 550a: Insulating layer, 550b: Insulating layer, 550c: Insulating layer, 550d: Insulating layer, 560: Conductive layer, 560a: Conductive layer, 560b: Conductive layer, 575: Insulating layer, 580: Insulating layer, 582: Insulating layer, 583: Insulating layer, 700: Electronic component, 700A: Electronic component, 700C: Electronic component, 701: Substrate, 710: Semiconductor Device, 711: Mold, 712: Lead frame, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 731: Through-hole board, 732: Conductive layer, 733: Electrode, 734: Packaging substrate, 735: Semiconductor device, 960: Processing device, 989: Buffer interface, 990: Substrate, 991: ALU, 992: ALU controller, 993: Instruction decoder, 994: Interrupt controller, 995: Timing controller, 996: Register, 997: Register Controller, 998: Bus Interface, 999: Buffer, 5600: Mainframe Computer, 5610: Rack, 5620: Computer, 6500: Electronic Equipment, 6501: Enclosure, 6502: Display Unit, 6503: Power Button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light Source, 6509: Control Device, 6600: Electronic Equipment, 6611: Enclosure, 6612 6613: Keyboard; 6614: Pointing device; 6615: External connection port; 6616: Display unit; 6800: Control device; 6801: Satellite; 6802: Main body; 6803: Solar panel; 6804: Planet; 6805: Secondary battery; 6807: Control device; 7000: Secondary storage system; 7001: Main unit; 7001sb: Server; 7002: Secondary storage control circuit; 7003: Secondary storage; 7003md: Storage device.

Claims

1. An amplifier circuit, comprising: First switch, second switch, third switch, fourth switch, fifth switch, sixth switch, and readout amplifier. The sense amplifier includes a first input / output terminal and a second input / output terminal. The first terminal of the first switch is electrically connected to the first terminal of the second switch. The second terminal of the second switch is electrically connected to the first terminal and the first input / output terminal of the third switch. The first terminal of the fourth switch is electrically connected to the first terminal of the fifth switch. The second terminal of the fifth switch is electrically connected to the first terminal and the second input / output terminal of the sixth switch. The control terminals of the first switch and the fifth switch are respectively electrically connected to the first wiring. The control terminals of the third switch and the sixth switch are respectively electrically connected to the second wiring. Furthermore, the sense amplifier is a latching type, which has the function of amplifying the potential of one of the first input / output terminals and the second input / output terminals to a high level potential and amplifying the potential of the other of the first input / output terminals and the second input / output terminals to a low level potential, corresponding to the potential of the first input / output terminals and the second input / output terminals.

2. The amplifier circuit according to claim 1, The first switch, the second switch, and the fifth switch are all analog switches. The third switch includes a first transistor. The fourth switch includes a second transistor. The sixth switch includes a third transistor. One of the source and drain terminals of the first transistor corresponds to the first terminal of the third switch. The gate of the first transistor corresponds to the control terminal of the third switch. One of the source and drain terminals of the second transistor corresponds to the first terminal of the fourth switch. The gate of the second transistor corresponds to the control terminal of the fourth switch. One of the source and drain of the third transistor corresponds to the first terminal of the sixth switch. Furthermore, the gate of the third transistor corresponds to the control terminal of the sixth switch.

3. The amplifier circuit according to claim 2, Both the first transistor and the third transistor are n-channel transistors. The second transistor is a p-channel transistor. Furthermore, the first transistor to the third transistor each contain silicon in the channel formation region.

4. A storage circuit, comprising: The amplifier circuit and storage unit according to any one of claims 1 to 3, The memory cell includes a fourth transistor, a fifth transistor, and a capacitor. The first terminal of the first switch and the first terminal of the second switch are respectively electrically connected to the third wiring. The first terminal of the fourth switch and the first terminal of the fifth switch are respectively electrically connected to the fourth wiring. One of the source and drain terminals of the fourth transistor is electrically connected to the gate of the fifth transistor and the first terminal of the capacitor. The other of the source and drain of the fourth transistor is electrically connected to the third wiring. Furthermore, one of the source and drain of the fifth transistor is electrically connected to the fourth wiring.

5. The storage circuit according to claim 4, The fourth transistor and the fifth transistor each contain an oxide semiconductor in the channel formation region. The oxide semiconductor comprises one or more elements selected from indium, zinc, and element M. Furthermore, element M comprises one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony.

6. An electronic device comprising the storage circuit and housing as described in claim 5.

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