A peak inductance multiplexed cml divide-by-two circuit
By integrating the peaking inductance of the CML latch into a loop, the problem of large area in traditional CML dividers is solved, achieving the effects of frequency increase and cost reduction.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU DIANZI UNIV
- Filing Date
- 2026-04-13
- Publication Date
- 2026-07-14
AI Technical Summary
Traditional CML dividers with peaked inductors are effective in improving the pre-division speed, but the two differential inductors required occupy a large chip area, increasing the difficulty and cost of layout.
By employing peaked inductor multiplexing technology, the peaked inductors required by two CML latches are merged into a loop consisting of four small inductors. These loops are connected by phase relationships to offset the effects of parasitic capacitance, thereby increasing the operating frequency and reducing the layout area.
This achieves a significant reduction in chip area while increasing operating frequency, thereby reducing the complexity and cost of layout.
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Figure CN122394549A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microelectronics technology, and more specifically to a CML divider circuit that uses peaked inductors for multiplexing. Background Technology
[0002] With the rapid development of communication technology, various electronic applications are evolving towards higher frequency bands and miniaturization. However, the large area of the RF front-end circuit remains a bottleneck restricting system miniaturization. The frequency synthesizer is a key module in the RF front-end circuit, including a voltage-controlled oscillator, a multimode divider, a frequency and phase detector, a charge pump, and a loop filter. Among them, the divider and the voltage-controlled oscillator operate at the highest frequency of the phase-locked loop, therefore, a high-speed, small-area prescaler becomes crucial for the RF front-end circuit.
[0003] Current-mode logic (CML) dividers with peaked inductors are commonly used prescaler structures. They consist of two CML latches and a peaked inductor. Each CML latch includes a clock pair, a sampling pair, and a latch pair. The clock pair switches between sampling and latching states, the sampling pair senses and amplifies the signal, and the latch pair latches the signal. The peaked inductor resonates with the parasitic capacitance at the CML latch output, thereby increasing the operating frequency of the CML divider.
[0004] Traditional CML dividers with peaked inductors play a significant role in improving prescaler operating speed, especially in millimeter-wave prescalers which are more sensitive to parasitics. However, the two differential inductors required occupy a large chip area, which greatly increases the difficulty of layout and routing, as well as chip cost. Summary of the Invention
[0005] In view of this, this application proposes a CML divider circuit that uses peaked inductors for frequency division, which improves the frequency division speed while reducing the chip area.
[0006] Specifically, this application is implemented through the following technical solution: According to an embodiment of this specification, a CML divider circuit with peaked inductor multiplexing is provided, comprising: The first CML latch and the second CML latch are interconnected in a divide-by-two manner; The first peaked inductor, the second peaked inductor, the third peaked inductor and the fourth peaked inductor are connected end to end to form a loop circuit. The non-inverting output of the first CML latch is connected to the first common connection point of the first peaking inductor and the fourth peaking inductor. The inverting output of the first CML latch is connected to the second common connection point of the second peaking inductor and the third peaking inductor; The non-inverting output of the second CML latch is connected to the third common connection point of the first peaking inductor and the second peaking inductor; The inverting output of the second CML latch is connected to the fourth common connection point of the third and fourth peaking inductors.
[0007] Alternatively, the four peaking inductors may use the same inductor.
[0008] Optionally, the four peaking inductors are formed by a metal ring, with each quarter arc of the metal ring serving as one of the peaking inductors.
[0009] Optionally, the first CML latch has a differential clock input terminal for receiving a differential input signal; the second CML latch has a differential clock input terminal for receiving an inverted differential input signal; the non-inverting input terminal of the first CML latch is connected to the inverting output terminal of the second CML latch, and the inverting input terminal of the first CML latch is connected to the non-inverting output terminal of the second CML latch; the non-inverting output terminal of the first CML latch is connected to the non-inverting input terminal of the second CML latch, and the inverting output terminal of the first CML latch is connected to the inverting input terminal of the second CML latch; the non-inverting output terminal and the inverting output terminal of the second CML latch are respectively used as differential output terminals of the CML divide-by-two frequency divider circuit.
[0010] The embodiments of this application have at least the following technical effects: This embodiment utilizes the phase relationship between the four output signals of a divide-by-two frequency divider. By connecting the output of the CML latch to four peaking inductors according to their phase relationship, the equivalent parallel inductance formed by the first and fourth peaking inductors resonates with the parasitic capacitance of the non-inverting output terminal of the first CML latch. The equivalent parallel inductance formed by the second and third peaking inductors resonates with the parasitic capacitance of the inverting output terminal of the first CML latch. The equivalent parallel inductance formed by the first and second peaking inductors resonates with the parasitic capacitance of the non-inverting output terminal of the second CML latch. The equivalent parallel inductance formed by the third and fourth peaking inductors resonates with the parasitic capacitance of the inverting output terminal of the second CML latch.
[0011] In this embodiment, the peaking inductors of two CML latches are merged into a loop consisting of four small inductors, which can greatly reduce the layout area while increasing the operating frequency. Attached Figure Description
[0012] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Some specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings indicate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic diagram of a CML divider circuit with peaked inductor multiplexing, as shown in an exemplary embodiment of this application. Figure 2 This is a schematic diagram of a CML latch circuit shown in an exemplary embodiment of this application. Detailed Implementation
[0013] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0014] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0015] The operating speed of a CML divider is difficult to improve due to the parasitic capacitance at the output of the CML latch. The traditional approach is to use peaking inductors at each output to offset the effect of parasitic capacitance, but this method occupies a large layout area.
[0016] Based on this, this application proposes a peaking inductor multiplexing technology, which integrates the peaking inductors required by two CML latches into a ring circuit composed of four small inductors, which effectively improves the operating frequency and significantly reduces the layout area.
[0017] The embodiments described in this specification will now be described in detail.
[0018] This application provides a CML divider circuit that uses peaked inductors for frequency division by two. Figure 1 This is a schematic diagram of a CML divider circuit using peaked inductors multiplexed according to an exemplary embodiment of this application, as shown below. Figure 1As shown, the CML divider circuit includes: a first CML latch, a second CML latch, and a first peaking inductor, a second peaking inductor, a third peaking inductor, and a fourth peaking inductor. Wherein: Two CML latches are interconnected using a divide-by-two frequency divider method. Specifically, the first CML latch has a differential clock input terminal for receiving differential input signals; the second CML latch has a differential clock input terminal for receiving inverted differential input signals; the non-inverting input terminal of the first CML latch is connected to the inverting output terminal of the second CML latch, and the inverting input terminal of the first CML latch is connected to the non-inverting output terminal of the second CML latch; the non-inverting output terminal of the first CML latch is connected to the non-inverting input terminal of the second CML latch, and the inverting output terminal of the first CML latch is connected to the inverting input terminal of the second CML latch; the non-inverting and inverting output terminals of the second CML latch serve as the differential output terminals of the CML divide-by-two frequency divider circuit.
[0019] Four peaked inductors are connected end to end to form a loop; the non-inverting output of the first CML latch is connected to the first common connection point of the first and fourth peaked inductors; the inverting output of the first CML latch is connected to the second common connection point of the second and third peaked inductors; the non-inverting output of the second CML latch is connected to the third common connection point of the first and second peaked inductors; and the inverting output of the second CML latch is connected to the fourth common connection point of the third and fourth peaked inductors.
[0020] like Figure 1 As shown, the clock signal input terminals CLK and CLKB of the first CML latch D1 are connected to the differential input signals Fin and FinB respectively. The clock signal input terminals CLK and CLKB of the second CML latch D2 are connected to the differential input signals FinB and Fin respectively. The output terminals Q and QB of the second CML latch D2 are used as the differential output signal output terminals Fout and FoutB of the circuit respectively.
[0021] The input terminal D of the first CML latch D1 is connected to the output terminal QB of the second CML latch D2. The input terminal DB of the first CML latch D1 is connected to the output terminal Q of the second CML latch D2. The output terminal Q of the first CML latch D1 is connected to the input terminal D of the second CML latch D2. The output terminal QB of the first CML latch D1 is connected to the input terminal DB of the second CML latch D2.
[0022] The output terminal Q of the first CML latch D1 is connected to the first connection point of peaking inductors L1 and L4. The output terminal QB of the first CML latch D1 is connected to the second connection point of peaking inductors L2 and L3. The output terminal Q of the second CML latch D2 is connected to the third connection point of peaking inductors L1 and L2. The output terminal QB of the second CML latch D2 is connected to the fourth connection point of peaking inductors L3 and L4.
[0023] The two CML latches each output two differential signals, resulting in a total of four output signals: Q1, Q1B, Q2, and Q2B. The theoretical phase difference between Q1 and Q1B is 180°, between Q1 and Q2 is 90°, between Q2 and Q2B is 180°, and between Q1B and Q2B is 90°.
[0024] In some embodiments, the four peaking inductors are identical. The four identical peaking inductors are connected in a loop, with their phases uniformly distributed across 360°. The equivalent parallel inductance formed by peaking inductors L1 and L4 resonates with the parasitic capacitance of the output terminal Q1 of the first CML latch D1; the equivalent parallel inductance formed by peaking inductors L2 and L3 resonates with the parasitic capacitance of the output terminal Q1B of the first CML latch D1; the equivalent parallel inductance formed by peaking inductors L1 and L2 resonates with the parasitic capacitance of the output terminal Q2 of the second CML latch D2; and the equivalent parallel inductance formed by peaking inductors L3 and L4 resonates with the parasitic capacitance of the output terminal Q2B of the second CML latch D2.
[0025] In some embodiments, the four peaking inductors are formed by a metal ring, with each quarter arc of the metal ring serving as one of the peaking inductors.
[0026] In some embodiments, such as Figure 2 As shown, the CML latch consists of six NMOS transistors and two identical resistors R1 and R2.
[0027] The gate of the first NMOS transistor MN1 serves as the clock input terminal CLK, and the gate of the second NMOS transistor MN2 serves as the clock input terminal CLKB. The drain of the first NMOS transistor MN1, the source of the third NMOS transistor MN3, and the source of the fourth NMOS transistor MN4 are connected. The gate of the third NMOS transistor MN3 serves as the non-inverting input terminal D, and the gate of the fourth NMOS transistor MN4 serves as the inverting input terminal DB. The drain of the third NMOS transistor MN3, the drain of the fifth NMOS transistor MN5, and the gate of the sixth NMOS transistor MN6 are connected to one end of resistor R1. The drain of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5, and the drain of the sixth NMOS transistor MN6 are connected to one end of resistor R2. The drain of the fifth NMOS transistor MN5 serves as the inverting output terminal QB, and the drain of the sixth NMOS transistor MN6 serves as the non-inverting output terminal Q. The drain of the second NMOS transistor MN2, the source of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 are connected. The source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded. Resistors R1 and R2 are connected to the power supply VDD.
[0028] The first CML latch D1 samples the input signals D and DB when the clock input signal Fin is high and FinB is low, and outputs them to the output terminals QB and Q respectively. When the clock input signal Fin is low and FinB is high, the sampled signals are latched.
[0029] The second CML latch D2 samples the input signals D and DB when the clock input signal Fin is low and FinB is high, and outputs them to the output terminals QB and Q respectively. When the clock input signal Fin is high and FinB is low, the sampled signals are latched.
[0030] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0031] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A CML divider circuit using peaked inductors, characterized in that, include: The first CML latch and the second CML latch are interconnected in a divide-by-two manner; The first peaked inductor, the second peaked inductor, the third peaked inductor and the fourth peaked inductor are connected end to end to form a loop circuit. The non-inverting output of the first CML latch is connected to the first common connection point of the first peaking inductor and the fourth peaking inductor. The inverting output of the first CML latch is connected to the second common connection point of the second peaking inductor and the third peaking inductor; The non-inverting output of the second CML latch is connected to the third common connection point of the first peaking inductor and the second peaking inductor; The inverting output of the second CML latch is connected to the fourth common connection point of the third and fourth peaking inductors.
2. The CML divider circuit according to claim 1, characterized in that, The four peaking inductors use the same inductance.
3. The CML divider circuit according to claim 1, characterized in that, The four peaking inductors are formed by a metal ring, with each quarter arc of the metal ring serving as one of the peaking inductors.
4. The CML divider circuit according to claim 1, characterized in that, The first CML latch has a differential clock input terminal for receiving differential input signals; The second CML latch has a differential clock input terminal for receiving inverted differential input signals; The non-inverting input of the first CML latch is connected to the inverting output of the second CML latch, and the inverting input of the first CML latch is connected to the non-inverting output of the second CML latch. The non-inverting output of the first CML latch is connected to the non-inverting input of the second CML latch, and the inverting output of the first CML latch is connected to the inverting input of the second CML latch. The non-inverting and inverting outputs of the second CML latch serve as the differential outputs of the CML divider circuit.