A method and system for coordinated control of pulse width modulation rectifiers under three-phase unbalanced grid

Abstract

The application discloses a kind of three-phase unbalanced power grid under pulse width modulation rectifier coordination control method and system, and it is related to power electronics and electric energy conversion control technical field.The method comprises: collecting three-phase voltage and current and DC bus voltage;By positive and negative sequence separation, construct unbalance degree index κ;With outer loop active power reference generated by active disturbance rejection controller, after amplitude limiting and slope limiting processing, it is sent into inner loop limited control set model predictive controller;Introduce κ-saturation flag joint gain scheduling mechanism on-line adjustment observer bandwidth and feedback gain, and set saturation fallback state machine to freeze integral channel;Inner ring uses two-step prediction, DC bus state perception, reactive power weight soft scheduling and reactive power average value offset removal.This application converts power grid unbalance degree into control parameter on-line setting basis, realizes outer ring safety constraint and inner ring prediction scheduling coordination, significantly suppresses DC bus voltage fluctuation and reactive power pulsation, improves system robustness and embedded realizability.

Description

Technical Field

[0001] This invention relates to the field of power electronics and power conversion control technology, and in particular to a method and system for coordinated control of pulse width modulation (PWM) rectifiers under three-phase unbalanced power grids. Background Technology

[0002] In scenarios where power distribution networks, new energy grid integration, and power electronic loads are widely used, three-phase voltage imbalance is a common phenomenon. The negative sequence voltage component in the power grid introduces power fluctuations at twice the power frequency, directly causing significant second-harmonic ripple and transient overshoot in the DC bus voltage of the PWM rectifier. At the same time, sudden load changes, circuit parameter drift, and measurement noise further exacerbate the control difficulty.

[0003] Currently, the mainstream control schemes for three-phase PWM rectifiers mainly fall into three categories: First, dual closed-loop control (Proportional-Integral Control (PI) / Proportional-Resonant Control (PR)) in the dq coordinate system, consisting of an outer voltage loop and an inner current loop; second, direct current / power control using Finite Control Set Model Predictive Control (FCS-MPC); and third, composite control that uses Active Disturbance Rejection Control (ADRC) in the outer bus voltage loop and connects it in series with MPC. Related research has compared the current tracking performance of different control strategies, promoting the application of FCS-MPC in power electronic converters, but existing technologies still face significant bottlenecks in engineering implementation.

[0004] Existing research often separates "imbalance analysis—controller design—hardware implementation," with the degree of grid imbalance typically used only as a monitoring parameter or offline analysis basis, rather than being transformed into inputs for online control parameter scheduling. Fixed-parameter controllers struggle to simultaneously achieve steady-state accuracy and transient response speed. When the control output enters saturation, integral accumulation and observer state divergence can easily occur, leading to system oscillations or even instability. Furthermore, FCS-MPC is highly sensitive to model uncertainties and external disturbances, lacks a collaborative compensation mechanism with the outer-loop control, and lacks system-level safety design for practical engineering problems such as discrete sampling delay and execution limiting. This makes it difficult to obtain a unified control scheme that balances robustness, stability, and embedded feasibility in this field. Summary of the Invention

[0005] To address these issues, this invention provides a collaborative control method and system for pulse width modulation rectifiers under three-phase unbalanced power grids. This system solves the problems in existing technologies where fixed-parameter controllers struggle to balance steady-state accuracy and transient response in DC bus voltage control of PWM rectifiers under three-phase unbalanced power grids. Furthermore, it addresses the challenges of integrating and observing the system to achieve instability when the execution quantity is saturated, and the lack of collaborative compensation mechanisms between finite control set model predictive control and outer-loop control, as well as the absence of system-level safety design for practical engineering problems such as discrete sampling delay and execution limiting. These issues result in difficulties in achieving a balance between system robustness, stability, and embedded feasibility.

[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for coordinated control of pulse width modulation rectifiers under a three-phase unbalanced power grid, the method comprising the following steps: Step S1: Synchronously acquire three-phase grid voltage, three-phase rectifier input current, and DC bus voltage; Step S2: Perform Clarke transformation on the three-phase grid voltage and the three-phase rectifier input current to obtain... The voltage and current components in the coordinate system, for the The voltage components in the coordinate system are separated into positive and negative sequences to obtain positive-sequence voltage components and negative-sequence voltage components. Step S3: Calculate the unfiltered imbalance index based on the positive-sequence voltage component and the negative-sequence voltage component. ,right By sequentially performing amplitude limiting and first-order discrete low-pass filtering, the imbalance index after filtering is obtained. ; Step S4: Using the DC bus voltage as the outer loop controlled state, construct an equivalent discrete extended model of the DC bus voltage. Based on this model, update the observation state of the discrete extended state observer to obtain the estimated value of the DC bus voltage state. and equivalent total disturbance estimate ; Step S5: Based on the DC bus voltage reference value and the... Calculate the state error, and generate an unlimited active power reference value based on the state error feedback. ,right Power limiting and slope limiting are performed sequentially to obtain the reference value of the actual active power sent into the inner loop. and according to and The deviation generates a saturation flag ; Step S6: Using the aforementioned DC bus voltage error, error change and the aforementioned As input, through a pre-established Joint gain scheduling and saturation backoff mechanism for online adjustment of extended state observer bandwidth Proportional gain of state error feedback and integral gain and according to Execute the saturation rollback state machine logic; Step S7: Taking the inner loop current as the controlled object, perform a two-step prediction based on the pre-established AC side discrete prediction model, according to the... , Equivalent reactive power reference value generated from DC bus status Equivalent DC bus voltage with state sensing Enumerate the eight finite switching states of the three-phase two-level pulse width modulation rectifier and calculate the predicted active power and predicted reactive power corresponding to each candidate switching state. Step S8: Construct a cost function that includes active power tracking terms and reactive power tracking terms, select the candidate switching state with the minimum cost function as the optimal switching state, and output it to the pulse width modulation drive and protection circuit to drive the rectifier main circuit.

[0007] Preferably, in step S3, the unfiltered imbalance index is calculated. The method is as follows: ; in, This is the positive sequence voltage amplitude. The magnitude of the negative sequence voltage. To prevent division by zero constant; For unfiltered imbalance index Limiting the amplitude: ; in, For the first The imbalance index after amplitude limiting in each control cycle The sequence number of the discrete control cycle represents the number of the... One control cycle, For the first The original unfiltered imbalance index for each control cycle This is the lower limit threshold for the imbalance index. This represents the upper limit threshold for the imbalance indicator; Imbalance index after amplitude limiting Perform first-order discrete low-pass filtering: ; in, For the first The degree of imbalance in the output after filtering for each control cycle. For the first An index of the degree of imbalance after filtering in each control cycle. The filter coefficients of a first-order discrete low-pass filter are... .

[0008] Preferably, in step S4, the equivalent discrete extended model of the DC bus voltage is: ; ; ; in, , The first , DC bus voltage status for each control cycle , The first , The equivalent total disturbance for each control cycle. To control the cycle, The nominal control gain is the equivalent of the DC bus voltage. This represents the equivalent total disturbance rate of change or the unmodeled dynamics. This is the outer loop observation output, i.e., the DC bus voltage measurement value. ; The update equation for the discrete extended state observer is: ; ; in, , The first , DC bus voltage state estimate for each control cycle , The first , Estimated equivalent total disturbance in the dynamic bus voltage of each control cycle. For the first The actual active power reference value sent into the inner loop for each control cycle. This is the DC bus voltage observation error. and To extend the state observer gain, , , For the first The bandwidth of the extended state observer for each control cycle.

[0009] Preferably, in step S5, the... The method for power limiting is as follows: ; in, For the first The active power reference value after power limiting processing for each control cycle It is a saturation limiting function. and These are the lower and upper limits of the active power reference value, respectively; Reference value of active power after limiting Apply slope limiting measures: ; in, For the first The actual active power reference value sent into the inner loop for each control cycle. This represents the maximum allowable power change within a single control cycle. according to and The deviation generates a saturation flag : ; ; in, This is the saturation deviation. This is the threshold for determining saturation.

[0010] Preferably, in step S6, the pre-established The joint gain scheduling and saturation backoff mechanism normalizes the imbalance factor. and normalized error factor The target values ​​of the generated parameters are then processed by slope limiting to obtain the final control parameters; among which the target value of the extended state observer bandwidth is... for: ; in, and These are the upper and lower limits of the bandwidth of the extended state observer, respectively. This represents the bandwidth backoff coefficient under saturation conditions.

[0011] Preferably, in step S6, the saturation rollback state machine includes three states: normal scheduling, saturation hold, and soft recovery; when the saturation duration count value... When the threshold value is greater than or equal to the trigger threshold, the system enters a saturation hold state, reducing the bandwidth and control gain of the extended state observer and freezing or releasing the integral channel; when the acknowledgment count value is released... When the threshold is ≥ cleared, the system enters a soft recovery state, gradually restoring the control parameters and integral channels in a limited slope manner.

[0012] Preferably, in step S7, a two-step prediction is performed based on a pre-established AC-side discrete prediction model to compensate for the one-step delay of digital control. The first step uses the voltage vector actually applied in the previous cycle for prediction. The second step is to predict the state of each candidate switch based on the instantaneous current. Current at any moment; The method for calculating the predicted active power is as follows: ; The method for calculating the predicted reactive power is as follows: ; in, and They represent the first The candidate switch state, the first Predicted active power and predicted reactive power for each control cycle For the first During each control cycle, the grid-side voltage is... coordinate system Axial components, No. During each control cycle, the grid-side voltage is... coordinate system Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current axis.

[0013] Preferably, in step S7, the state-sensing equivalent DC bus voltage The calculation formula is: ; in, This is the reference value for the DC bus voltage. This is the actual bus voltage after low-pass filtering. State-aware mixing coefficients; The equivalent reactive power reference value The calculation formula is: ; in, The set reactive power reference value, This is an unbalanced reactive power compensation term constructed based on positive and negative sequence voltage components. This is the reactive power average debiasing compensation amount.

[0014] Preferably, in step S8, the cost function is calculated using the following formula: ; in, For the first The cost function value of each candidate switch state. As a result of merit, For soft scheduling reactive power weights, The penalty weight for switch transitions, For a norm, Indicates the first The candidate switch state, the first Predicted active power corresponding to each control cycle For the first A three-dimensional column vector of candidate switch states, The actual switching state output in the previous control cycle; the optimal switching state. .

[0015] This invention also provides a coordinated control system for pulse width modulation rectifiers under a three-phase unbalanced power grid. This system is used to implement the aforementioned coordinated control method for pulse width modulation rectifiers under a three-phase unbalanced power grid, specifically including: The main circuit of the three-phase PWM rectifier has its AC side connected to the three-phase power grid through a filter inductor, and its DC side connected to the DC bus capacitor and load. The AC side voltage and current sampling module is used to synchronously acquire the three-phase grid voltage and the three-phase rectifier input current and output the sampling signal; The DC bus voltage sampling module is used to acquire the DC bus voltage and output the outer loop voltage feedback signal; The control calculation unit has its input terminals connected to the output terminals of the AC side voltage and current sampling module and the DC bus voltage sampling module, respectively. The control calculation unit integrates a coordinate transformation and sequence component separation unit, an imbalance degree identification unit, an outer loop active disturbance rejection control unit, a joint gain scheduling and saturation backoff unit, and an inner loop finite control set model prediction control unit. The PWM drive and protection circuit has its input terminal connected to the output terminal of the control calculation unit and its output terminal connected to the control terminal of the three-phase PWM rectifier main circuit. It is used to generate power device drive pulses according to the optimal switching state and control the operation of the three-phase PWM rectifier main circuit in combination with overcurrent, overvoltage, undervoltage and drive fault protection logic.

[0016] As can be seen from the above technical solutions, this invention application has the following beneficial effects: First, by incorporating the grid imbalance index into the online scheduling of control parameters, the outer loop active disturbance rejection controller achieves self-adaptation to operating conditions, significantly improving the dynamic response and steady-state robustness of the DC bus voltage.

[0017] Second, by introducing saturation-triggered backoff, dual-rate update, and integral channel freezing / release mechanisms, the integral accumulation and observer divergence when the execution quantity is saturated are effectively suppressed, and the stability of the system under strong disturbances and amplitude limiting conditions is improved.

[0018] Third, by introducing DC bus state perception prediction, reactive power weight soft dispatch and reactive power average de-biasing mechanism into the inner-loop FCS-MPC, reactive power fluctuations under unbalanced power grids are significantly reduced while maintaining the dynamic tracking capability of the DC bus. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Referring to the drawings will make the features and advantages of the present invention clearer. The drawings are illustrative and should not be construed as limiting the present invention in any way. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the overall system structure of the present invention; Figure 2 This is a flowchart of the operation and optimization of the control method of the present invention; Figure 3 The outer ring ADRC of this invention and Schematic diagram of joint scheduling; Figure 4 This is a schematic diagram of the inner-loop FCS-MPC state perception prediction and reactive power suppression of the present invention; Figure 5 This is a comparison diagram of the DC bus voltage response between the original scheme and this embodiment of the invention; Figure 6 This is a comparison diagram of the reactive power response between the original scheme and this embodiment of the invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This invention discloses a collaborative control method and system for pulse width modulation (PWM) rectifiers under three-phase unbalanced power grids. It aims to solve the shortcomings of existing technologies, such as the inability of fixed parameter controllers to balance steady-state accuracy and transient response of DC bus voltage control of PWM rectifiers under three-phase unbalanced power grids, the tendency for integral accumulation and observer divergence to cause system instability when the execution quantity is saturated, the lack of collaborative compensation mechanism between finite control set model predictive control (FCS-MPC) and outer loop control, and the lack of system-level safety design for practical engineering problems such as discrete sampling delay and execution limit.

[0022] Example 1: like Figure 1 The diagram shown is a schematic of the overall system structure of this invention. The system includes a three-phase PWM rectifier main circuit, an AC-side voltage and current sampling module, a DC bus voltage sampling module, a control and calculation unit, and a PWM drive and protection circuit. The three-phase power grid is connected to the three-phase PWM rectifier main circuit via an AC-side filter inductor. The rectifier output is connected to the DC bus capacitor and the DC-side load. The AC-side voltage and current sampling module collects the three-phase power grid voltages respectively. and three-phase input current The DC bus voltage sampling module acquires the DC bus voltage. The sampled signal is then sent to the control calculation unit. The control calculation unit performs Clarke transform, positive / negative sequence separation, and imbalance index on the sampled signal. Calculation, outer-loop active disturbance rejection control, and inner-loop finite control set model predictive control are used to generate the optimal switching states of the three-phase bridge arms. The PWM drive and protection circuit generates corresponding power device drive pulses based on the switching state output by the control calculation unit, and controls the operation of the three-phase PWM rectifier main circuit in conjunction with overcurrent, overvoltage, undervoltage, and drive fault protection logic. The following section will combine... Figure 1 The system structure shown illustrates the control method of the present invention in detail.

[0023] like Figure 2 As shown in this embodiment, the PWM rectifier collaborative control method under a three-phase unbalanced power grid specifically includes the following steps: Step S1: Sample the three-phase grid voltage , , Three-phase input current , , and DC bus voltage .

[0024] Step S2: Perform Clarke transformation on the three-phase grid voltage and the three-phase rectifier input current to obtain... The voltage and current components in the coordinate system, for the The voltage components in the coordinate system are separated into positive and negative sequences to obtain positive-sequence voltage components and negative-sequence voltage components.

[0025] Specifically, an equal-power Clarke transformation is performed on the three-phase grid voltage and the three-phase rectifier input current to obtain a two-phase static voltage. Voltage components in coordinate system , and current components , The transformation formula is: , ; After the above transformation, the three-phase variables are mapped to... The coordinate system variables facilitate subsequent positive and negative sequence separation, unbalance index calculation, and FCS-MPC current prediction.

[0026] Furthermore, regarding The voltage components in the coordinate system are separated into positive and negative sequences to obtain the positive sequence voltage components. and negative sequence voltage components : , ; in, , Indicates positive sequence voltage at Components in coordinate system , Indicates negative sequence voltage at Components in the coordinate system. Separation of positive and negative order can be achieved using conventional methods in the field, such as second-order generalized integrator (SOGI), delay signal cancellation (DSC), or phase-locked loop (PLL) assisted extraction.

[0027] Step S3: Calculate the unfiltered imbalance index based on the positive-sequence voltage component and the negative-sequence voltage component. ,right By sequentially performing amplitude limiting and first-order discrete low-pass filtering, the imbalance index after filtering is obtained. .

[0028] Specifically, the positive-sequence voltage amplitude is calculated based on the positive-sequence voltage component and the negative-sequence voltage component. and negative sequence voltage amplitude : , ; To quantify the degree of grid voltage imbalance, this invention defines an unfiltered imbalance index. The ratio of the negative sequence voltage amplitude to the positive sequence voltage amplitude: ; in, To prevent division by zero, a division-by-zero constant is used to avoid division-by-zero problems when the positive sequence voltage amplitude is too small or when sampling is abnormal. A suitable value can be selected. Or set according to the controller's point-to-point accuracy.

[0029] To avoid frequent scheduler actions caused by transient noise or second harmonic ripple, the first step is to... Amplitude limiting is applied: ; in, For the first The imbalance index after amplitude limiting in each control cycle The sequence number of the discrete control cycle represents the number of the... One control cycle, For the first The original unfiltered imbalance index for each control cycle This is the lower limit threshold for the imbalance index. This is the upper threshold for the imbalance index. It can usually be set as follows: , The setting depends on the level of imbalance allowed by the system.

[0030] Then, a first-order discrete low-pass filter is applied to the imbalance index after the amplitude limiting: ; in, For the first The degree of imbalance in the output after filtering for each control cycle. For the first An index of the degree of imbalance after filtering in each control cycle. The filter coefficients of a first-order discrete low-pass filter are... .

[0031] Step S4: Using the DC bus voltage as the outer loop controlled state, construct an equivalent discrete extended model of the DC bus voltage. Based on this model, update the observed state of the Extended State Observer (ESO) to obtain the DC bus voltage state estimate. and equivalent total disturbance estimate ; Specifically, to facilitate interface matching between the outer-loop Active Disturbance Rejection Controller (ADRC) and the inner-loop Finite Control Set Model Predictive Controller (FCS-MPC), and to ensure that the outer-loop control model remains consistent with the actual sampled signal, this embodiment uses the DC bus voltage. As the outer-loop controlled state, factors such as load disturbances, power fluctuations caused by grid imbalances, parameter deviations, inner-loop prediction errors, and digital control delays are uniformly incorporated into the equivalent total disturbance term. The equivalent extended state variable of the DC bus voltage is defined as follows: , ; in, Indicates the first DC bus voltage status for each control cycle This represents the equivalent total disturbance in the dynamics of the bus voltage. Factors include DC-side load power variations, second-harmonic power fluctuations caused by grid imbalances, bus capacitor parameter deviations, rectifier loss variations, inner-loop prediction errors, and digital control delays. Therefore, the equivalent discrete extended model of the DC bus voltage is constructed as follows: ; ; ; in, For the first DC bus voltage status for each control cycle 、 for the first The equivalent total disturbance for each control cycle. To control the cycle, The nominal control gain is the equivalent of the DC bus voltage. This represents the equivalent total disturbance rate of change or the unmodeled dynamics. This is the outer loop observation output, i.e., the DC bus voltage measurement value. .

[0032] In engineering implementation, The parameters can be set based on the DC bus capacitance, rated bus voltage, power transfer efficiency, and actual control calibration results. If there are deviations in the system parameters, the extended state observer will incorporate these deviations into the equivalent total disturbance term. Estimation and compensation are performed during this process. Because... Load changes, grid imbalances, parameter errors, and inner loop tracking errors have been integrated into the extended state, so the outer loop controller does not need to model all disturbances individually.

[0033] Furthermore, based on the aforementioned equivalent discrete expansion model of the DC bus voltage, a discrete second-order extended state observer (ESO) is constructed to estimate the DC bus voltage state and its equivalent total disturbance online. The observed state of the ESO is defined as: , ; in, This is an estimate of the DC bus voltage state. This is the estimated equivalent total disturbance in the dynamics of the bus voltage. The ESO output comparison is constructed from the sampled DC bus voltage values. ; The observation error is defined as: ; Right now: ; The discrete ESO update equation is then: ; ; in, For the first DC bus voltage state estimate for each control cycle For the first Estimated equivalent total disturbance in the dynamic bus voltage of each control cycle. For the first The actual active power reference value sent to the inner loop FCS-MPC for each control cycle This represents the DC bus voltage observation error. To facilitate parameter tuning, the extended state observer gain is set to the extended state observer bandwidth. Parameterization can be performed. In one embodiment, it can be set as follows: , ; in, For the first The bandwidth of the extended state observer is determined for each control cycle. A larger observer bandwidth results in faster disturbance tracking but is more sensitive to measurement noise and second-harmonic ripple; a smaller observer bandwidth produces smoother observations but reduces the disturbance estimation response speed. Therefore, this invention does not use a fixed bandwidth, but rather a bandwidth determined by subsequent... The joint gain scheduling and saturation backoff mechanism are adjusted online. In other embodiments, and It can also be used with Other related parameterization forms are acceptable, as long as they can achieve stable estimations of the DC bus voltage state and the equivalent total disturbance. To ensure the stability of the discrete implementation, the observer bandwidth must satisfy:

[0034] in, and These are the lower and upper limits of the observer bandwidth, respectively.

[0035] Step S5: Based on the DC bus voltage reference value and the... Calculate the state error, and generate an unlimited active power reference value based on the state error feedback. ,right Power limiting and slope limiting are performed sequentially to obtain the reference value of the actual active power sent into the inner loop. and according to and The deviation generates a saturation flag .

[0036] Specifically, the DC bus voltage state estimate based on the discrete ESO output. and equivalent total disturbance estimate A state error feedback control law is constructed. In this embodiment... express The estimated value, therefore the outer loop error is defined as: ; in, This is the reference value for the DC bus voltage. The estimated value of the DC bus voltage output by the ESO. This represents the DC bus voltage tracking error.

[0037] To eliminate steady-state error, a discrete integration channel is set up: ; in, In the integration state, For integral gain, This is the gating factor for the integration channel. Under normal scheduling conditions, it can be set to... When the system enters a saturation hold or rollback state, it can be set to... Or take less than The value of is adjusted to suppress integral accumulation.

[0038] Limit the integral state: ; in, and These are the upper and lower limits of the points system, respectively. This represents the saturation limiting function.

[0039] The proportional and integral channels are combined to form the desired regulation of the bus voltage state: ; in, This represents the desired regulation of the DC bus voltage state. For proportional gain, This is the proportional channel gating coefficient.

[0040] Based on the equivalent extended model of DC bus voltage: ; in, By ESO estimate.

[0041] To compensate for the total disturbance, an unlimited active power reference value is generated: ; in, This is the reference value for unlimited active power generated by the outer ring ADRC. This is the disturbance compensation coefficient. When When it means that the ESO disturbance rejection estimation is used entirely for compensation; when This indicates that conservative compensation is used to reduce the impact of noise on the control quantity.

[0042] To ensure that the reference input of the inner loop FCS-MPC does not exceed the rectifier's allowable range, for Perform power limiting: ; in, For the first The active power reference value after power limiting processing for each control cycle. and These are the lower and upper limits of the active power reference value, respectively.

[0043] Furthermore, to avoid abrupt changes in the active power reference value between adjacent control cycles, a slope limiting process is applied: ; in, This is the final active power reference value sent to the inner loop FCS-MPC. For the first The actual active power reference value sent into the inner loop for each control cycle. This represents the maximum allowable power change within a single control cycle. Furthermore, to determine whether the outer loop control quantity is subject to amplitude or slope limiting constraints, a saturation deviation quantity is defined. : ; And define the saturation flag. : ; in, This is the saturation threshold. When... When this occurs, it indicates a significant deviation between the original reference value and the actual reference value of the outer loop, and the outer loop output is subject to amplitude or slope limiting constraints; when When this occurs, it indicates that the outer loop output is within the allowable range.

[0044] In summary, the output link of the outer loop ADRC in this embodiment is as follows: ; in, As a reference value for active power in the inner loop FCS-MPC, As a follow-up Input signals for joint gain scheduling and saturation backoff mechanism.

[0045] Step S6: Using the aforementioned DC bus voltage error, error change and the aforementioned As input, through a pre-established Joint gain scheduling and saturation backoff mechanism for online adjustment of extended state observer bandwidth Proportional gain of state error feedback and integral gain and according to Execute the saturation rollback state machine logic.

[0046] Specifically, to enable the outer-loop active disturbance rejection controller to simultaneously sense the degree of grid imbalance and the outer-loop execution constraint state, this invention constructs... Joint gain scheduling and saturation backoff mechanism. For example... Figure 3 As shown, this invention's outer ring ADRC and - A schematic diagram of joint dispatching. This mechanism does not rely solely on grid imbalance indicators or output saturation flags, but rather uses both as the basis for adjusting outer-loop control parameters, thereby achieving closed-loop safe coordination of "disturbance identification—parameter backoff—reference constraints—inner-loop execution." Among these, the grid imbalance degree indicator... Used to characterize the strength of disturbances caused by negative sequence components on the power grid side; saturation indicator This is used to characterize whether there is a significant deviation between the unlimited active power reference value generated by the outer loop and the actual active power reference value sent to the inner loop. Both together reflect whether the system is currently under strong disturbance or execution-constrained conditions. The scheduling input is defined as: ; in: ; ; ; ; In the formula, For DC bus voltage error, The amount of error change, This represents the deviation of the active power reference value before and after the limiting. The dispatch output is: ; in, To expand the bandwidth of the state observer, and These represent the proportional gain and integral gain in the state error feedback control law, respectively. To achieve a continuous mapping from the degree of imbalance to the degree of parameter backoff, a normalized imbalance factor is constructed: ; in, The threshold for mild imbalance. The threshold for severe imbalance. .when An increase indicates a greater degree of imbalance in the power grid.

[0047] Simultaneously construct the normalized error factor: ; in, This is the preset maximum permissible error for the bus voltage.

[0048] In one embodiment, the target value of the extended state observer bandwidth is... It can be generated using the following formula: ; in, and These are the upper and lower limits of the bandwidth of the extended state observer, respectively. This represents the bandwidth backoff coefficient under saturation conditions. The formula indicates that the stronger the grid imbalance, the more conservative the observer bandwidth becomes; when the outer loop output enters saturation or a slope-limited state, the observer bandwidth is further reduced to avoid ESO tracking of second harmonic ripple or amplification of measurement noise.

[0049] Target value of proportional gain It can be generated using the following formula: ; in, This is the reference value for the proportional gain. This is the error enhancement coefficient. This is the imbalance suppression coefficient. This is the saturation backoff coefficient. and These represent the lower and upper limits of the proportional gain, respectively. This formula indicates that when the bus error is large, the proportional gain should be appropriately increased; however, when there is unbalanced enhancement or the outer loop output is limited, the proportional gain should be reduced to avoid sudden changes in the control quantity.

[0050] Integral gain target value It can be generated using the following formula: ; in, The integral gain reference value, This is the imbalance suppression coefficient. This is the saturation backoff coefficient. and These are the lower and upper limits of the integral gain, respectively. Since the integral term is prone to accumulation when execution is constrained, therefore... At this time, the integral gain should be significantly reduced, or the integral channel should be frozen by the saturation backoff state machine. To prevent abrupt changes in parameters within adjacent control cycles, the target parameters are subject to slope limiting. ; ; ; in, , , These represent the maximum allowable variations in the bandwidth, proportional gain, and integral gain of the extended state observer within a single control cycle.

[0051] In summary, this joint scheduling mechanism can be expressed as: ; in, This represents a joint scheduling mapping consisting of an imbalance factor, an error factor, a saturation flag, a parameter limit, and a slope limit.

[0052] In an alternative implementation, the aforementioned continuous mapping can also be implemented using a piecewise rule base, a lookup table method, or a piecewise linear function, and hysteresis intervals can be set at each segment threshold to avoid... Fluctuations around the threshold cause frequent parameter switching.

[0053] Furthermore, to avoid integral accumulation, observer divergence, or abrupt changes in the inner loop reference when the outer loop output is limited, this invention further incorporates a saturation backoff state machine. This state machine uses a saturation flag... Saturation Continuous Count Value , Deactivation confirmation count value and bus voltage error As input, perform rollback or soft recovery on the outer loop parameters and integration channel. Saturation deviation and saturation flag are defined as above.

[0054] To avoid false triggering of backoff by single-cycle disturbances, a saturation continuous counter is introduced: ; To determine whether the system has escaped saturation, a deacknowledgment counter is introduced: ; in, and These are the upper limits of the counter, This is the allowable bus voltage error threshold when saturation is removed.

[0055] A state machine includes three states: ; In this context, NORMAL represents the normal scheduling state, SAT_HOLD represents the saturation hold / rollback state, and RECOVER represents the soft recovery state. The state transition rules are as follows: ; ; ; If it is satisfied again in the RECOVER state If the SAT_HOLD state is entered again, the control actions in each state are as follows. In the NORMAL state, the controller uses the scheduling parameters output by the above-mentioned joint scheduling mechanism: , , .

[0056] In NORMAL mode, the points channel is open normally: .

[0057] In the SAT_HOLD state, a rollback is performed on the extended state observer bandwidth and control gain: ; ; ; in, , , Let be the backoff coefficient, and satisfy: .

[0058] Simultaneously, the points channel can be frozen or released. The freezing method is as follows: ; The discharge method is as follows: ; in, This is the integral discharge coefficient.

[0059] In RECOVER mode, the control parameters do not immediately jump back to normal values, but instead gradually recover using a slope-limiting method: ; ; .

[0060] The integration channel is gradually restored according to the step size: .

[0061] Through the aforementioned state machine, the system maintains a relatively fast dynamic response under normal operating conditions; under conditions of limited outer loop output or strong disturbance, it automatically reduces bandwidth and gain, and freezes or releases the integral state; after desaturation, it gradually restores control parameters, thereby suppressing integral saturation, reference mutation, and ESO observation state divergence.

[0062] Furthermore, to facilitate implementation in a digital controller Joint gain scheduling can adjust the imbalance index The influence of external loop control parameters is designed as a discrete rule base. This rule base mainly performs three functions: first, based on... The system employs three main methods: first, determining the appropriate level of grid imbalance; second, using hysteresis to prevent frequent switching of the level near the threshold; and third, outputting basic parameter command values ​​using a slow update method for subsequent saturation sensing correction and slope limiting processing. The imbalance indicators have already been provided above. The calculation and filtering methods are as follows. This embodiment directly uses the filtered result. As input to the scheduling rule base. Let the threshold for segmentation of imbalance be: ; in, Indicates the first Each imbalance level is segmented by a threshold. This represents the number of segments. According to... The location within the specified interval determines the current imbalance in the scheduling level. : ; in, The larger the gear number, the stronger the power grid imbalance, and the more conservative the corresponding outer loop control parameters should be.

[0063] For each scheduling gear Set the corresponding basic parameter command values: , , ; in, , , They represent the first The observer bandwidth command value, proportional gain command value, and integral gain command value at each unbalanced setting.

[0064] To reflect the scheduling principle that "the greater the imbalance, the more conservative the outer loop parameters," the parameters for each gear should meet the following requirements: ; ; ; In this configuration, the slightly unbalanced tap uses a larger observer bandwidth and control gain to ensure dynamic response of the bus voltage; the heavily unbalanced tap uses a smaller observer bandwidth and control gain to avoid excessive ESO tracking of second harmonic ripple and to reduce the risk of integral accumulation and reference abrupt changes. To avoid... Fluctuations around the threshold cause frequent switching of scheduling gears. A hysteresis interval is set for each segment threshold.

[0065] For the There are several thresholds, defining the overpass threshold and the underpass threshold as follows: , ; in, This is the hysteresis width.

[0066] Current gear is At that time, the gear update rule can be expressed as: .

[0067] The above rules ensure that the system only enters a more conservative mode when the imbalance index significantly exceeds the threshold, and only returns to a more aggressive mode when the imbalance index significantly falls below the threshold, thus avoiding parameter jumps around the critical point. Considering that the grid imbalance index may still contain second-harmonic fluctuations or sampling noise, the rule base can adopt a slow update method.

[0068] Assume the rule base update / cycle is: ; in, For the rule base update cycle, It is a positive integer. To control the cycle. When the following conditions are met: At that time, execute a gear selection and basic parameter update command once: ; in, This represents the rule base mapping, which consists of segmented thresholds, hysteresis logic, and gear parameter tables.

[0069] When the rule base update conditions are not met, retain the basic parameter command values ​​from the previous control cycle: .

[0070] thus, The scheduling rule base, acting as the slow channel, is only responsible for outputting basic parameter commands based on the degree of grid imbalance; while the saturation backoff state machine, acting as the fast channel, is responsible for... The above basic parameter commands are modified based on the saturation duration state. That is: ; in, This represents the saturation-sensing correction function. This is the state of the saturated backoff state machine. The corrected target parameters are then output as the final control parameters according to the slope limiting rule described above. , , The rule base implementation described above can transform the continuous changes in the degree of power grid imbalance into real-time parameter level scheduling, and use hysteresis and slow updates to suppress parameter jitter. At the same time, the rule base is only responsible for outputting basic parameter commands, while the saturation backoff state machine is responsible for handling execution-restricted conditions. The two have a clear division of labor, avoiding redundant scheduling and inconsistencies in parameters.

[0071] Step S7: Taking the inner loop current as the controlled object, perform a two-step prediction based on the pre-established AC side discrete prediction model, according to the... , Equivalent reactive power reference value generated from DC bus status Equivalent DC bus voltage with state sensing Enumerate the eight finite switching states of the three-phase two-level pulse width modulation rectifier and calculate the predicted active power and predicted reactive power corresponding to each candidate switching state.

[0072] Specifically, such as Figure 4 The diagram illustrates the inner-loop FCS-MPC state-aware prediction and reactive power suppression mechanism of this invention. The inner-loop finite control set model predictive controller uses the AC input current in a two-phase stationary coordinate system as the controlled object. It performs two-step prediction based on the candidate voltage vectors corresponding to the finite switching states of the three-phase two-level PWM rectifier, and selects the optimal switching state for the current control cycle through a cost function. To improve the reactive power suppression capability under three-phase grid voltage imbalance conditions and avoid the reactive power suppression process affecting the DC bus voltage stability, this embodiment simultaneously introduces DC bus state-aware prediction, reactive power weighted soft scheduling, and reactive power average de-biasing mechanism into the basic FCS-MPC structure. In the coordinate system, the grid-side voltage vector, AC-side input current vector, and rectifier AC-side equivalent voltage vector are defined as follows: , , ; in, For the first The grid-side voltage vector obtained by sampling in each control cycle For the AC side input current vector, The AC-side equivalent voltage vector is determined by the rectifier switching state.

[0073] The AC side filter inductor model is: ; in, For AC side filter inductance, This is the equivalent resistance on the AC side.

[0074] Discretizing the above model using the forward Euler method yields a one-step prediction model: ; in, Indicates the first The control cycle for the first The predicted value of the current for each control cycle. The sampling period.

[0075] Considering the sampling, calculation, and drive update delays in digital controllers, this embodiment employs a two-step prediction structure for one-cycle delay compensation. First, it utilizes the voltage vector actually applied in the previous cycle... Predict the current in the next cycle: .

[0076] Then for each candidate switch state Corresponding candidate voltage vector Perform the second step of prediction: ; in, Indicates the use of the first When the candidate switch state is... The predicted value of the current for each control cycle. For a three-phase two-level PWM rectifier, the finite set of switching states is defined as: ; in: ; and: ; in, , , They represent the first The switching states of the three-phase bridge arms are considered under each candidate state. To ensure that the candidate voltage vector calculation simultaneously reflects the DC bus reference value, the actual bus voltage, and its filtering state, this embodiment constructs a state-aware equivalent DC bus voltage. Let the DC bus voltage reference value be... The actual measured value is The actual bus voltage after low-pass filtering is The equivalent DC bus voltage used for candidate voltage vector calculation is defined as: ; in, For state-aware mixing coefficients. To avoid introducing additional overshoot during the startup and reference step phases, Controlled by a steady-state gating signal, the gating increases gradually only after the bus voltage error is small, the reference value remains stable, and the system enters steady-state operation; it also increases during the startup phase, the reference step phase, or when the bus error is large. near This makes the candidate voltage vector mainly composed of The decision is made. This method enhances the ability of candidate voltage vectors to perceive the actual bus state during the steady-state phase, while avoiding the impact of directly introducing bus fluctuations on voltage tracking during the dynamic phase. The corresponding set of candidate voltage vectors is as follows: .

[0077] Each candidate voltage vector can be expressed in complex form as: ; ; ; ; ; ; ; .

[0078] The real part in the above complex form corresponds to Axial components, imaginary parts correspond Axis components. According to the first... For each candidate switch state, predict the two-step current, and calculate the predicted active power and predicted reactive power: ; ; in, and They represent the first The candidate switch state, the first Predicted active power and predicted reactive power for each control cycle For the first During each control cycle, the grid-side voltage is... coordinate system Axial components, No. During each control cycle, the grid-side voltage is... coordinate system Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current axis.

[0079] Under unbalanced three-phase power grid conditions, reactive power compensation terms can be constructed based on the positive and negative sequence voltage components: ; in, This is an unbalanced reactive power compensation term constructed based on positive and negative sequence voltage components. To prevent division by zero, a constant is used to avoid numerical anomalies caused by an excessively small denominator.

[0080] Furthermore, to suppress the average deviation of reactive power under unbalanced operating conditions, the actual reactive power... Low-pass averaging is performed to obtain the average reactive power. and according to Generate reactive power offset compensation amount In one embodiment, According to inhibition The direction of generation, that is, when When it is the right time, Take the negative compensation trend; when When it is negative, A positive compensation trend is adopted, and abrupt changes in the compensation amount are avoided by limiting the amplitude and slope. This yields the equivalent reactive power reference value: ; in, The set reactive power reference value, This is the reference value for equivalent reactive power after considering unbalance compensation and reactive power average debiasing. It is only gradually activated after the system enters steady state, and frozen or slowly restored when the reference step or bus error is large, in order to avoid additional fluctuations in bus voltage caused by reactive power de-biasing process.

[0081] To balance the establishment of bus voltage during startup and the suppression of reactive power during steady state, the reactive power weight in the inner-loop cost function does not use a fixed value, but rather a reactive power weight soft adjustment mechanism: ; in, For reactive power base weight, Increase the weight of reactive power. This is the reactive power weighted soft-start gating coefficient. A smaller value is taken during the initial startup phase and the reference step recovery period, and then gradually increased after the system enters steady state. This avoids the controller prematurely strengthening reactive power suppression during startup, which could affect the DC bus voltage establishment process, while simultaneously enhancing the ability to suppress reactive power fluctuations during the steady-state phase.

[0082] Step S8: Construct a cost function that includes active power tracking term and reactive power tracking term, select the candidate switching state with the minimum cost function as the optimal switching state, and output it to the pulse width modulation drive and protection circuit to drive the rectifier main circuit.

[0083] Construct the first Cost function corresponding to each candidate switch state: ; in, For the first The cost function value of each candidate switch state. For active power tracking weights, The reactive power weight after soft scheduling The penalty weight for switch transitions, This represents the actual switching state output in the previous control cycle. It represents the first norm.

[0084] In one embodiment, it can be set that: At this point, the cost function degenerates into: .

[0085] If we further disable reactive power weight enhancement and reactive power average debiasing, that is: The above form can then degenerate into the basic FCS-MPC cost function: .

[0086] This form is consistent with the FCS-MPC enumeration logic in the basic simulation implementation; however, in this implementation scheme, through... , and The introduction of this feature allows the candidate voltage vector calculation, reactive power weight, and equivalent reactive power reference value to be adjusted according to the system state, thereby improving bus stability and reactive power suppression capability under unbalanced operating conditions. The optimal switch state number is: .

[0087] The final output three-phase bridge arm switch states are: ; in, , , These are the optimal switching commands output to the three-phase bridge arms for the current control cycle. The controller sends this optimal switching state to the PWM drive and protection circuit, which, after interlocking, dead-time, and protection logic processing, drives the three-phase PWM rectifier power devices.

[0088] In the next control cycle, update the switch state from the previous cycle: ; And update the applied voltage vector of the previous cycle: .

[0089] Then, the closed-loop control process of "sampling-prediction-enumeration-evaluation-output" continues into the next sampling cycle.

[0090] In this way, the inner-loop FCS-MPC no longer selects the switching state based solely on the fixed DC bus voltage and fixed reactive power weight. Instead, it incorporates the DC bus state, reactive power offset, and operational phase gating into the prediction enumeration process, enabling the controller to simultaneously consider DC bus voltage stability, reactive power suppression capability, and switching state feasibility during the finite switch set enumeration process.

[0091] Furthermore, to verify the technical effectiveness of this implementation scheme compared to existing technologies, a three-phase PWM rectifier simulation model was built based on MATLAB / Simulink, and the original scheme and this implementation scheme were compared and verified under the same main circuit parameters, the same sampling period, and the same three-phase power grid imbalance conditions.

[0092] The original model included a three-phase AC voltage source, a three-phase series RL branch, a three-phase Insulated Gate Bipolar Transistor (IGBT) rectifier bridge, DC-side capacitors and loads, DC bus voltage sampling, Clarke transformation, positive and negative sequence separation, a power calculation module, an ADRC outer loop control module, and an FCS-MPC inner loop predictive control module. The model used discrete simulation with a sampling time of 50μs and a total simulation duration of 3s. In the original model, the three-phase AC source was set to an unbalanced operating condition with inconsistent amplitudes, and all frequencies were 50Hz. The FCS-MPC module in the model was implemented using S-Function, with 18 input ports and 3 output ports, outputting the three-phase bridge arm switching states Sa, Sb, and Sc. The original FCS-MPC algorithm generated candidate voltage vectors based on the DC bus voltage reference value, calculated the predicted active and reactive power values ​​under the candidate vectors based on two-step current prediction, and then selected the optimal switching state through a cost function.

[0093] This implementation plan introduces strategies such as DC bus state perception and prediction, reactive power weighted soft dispatch, reactive power average de-biasing, and reference step recovery gating based on the original plan. It aims to improve the dynamic performance of DC bus voltage and reactive power fluctuations under unbalanced grid conditions. The comparison operating condition is set as follows: the initial reference value of the DC bus voltage is 400V, which steps to 500V at 1.5s, and the total simulation time is 3s. Statistical indicators include start-up adjustment time, maximum start-up overshoot, start-up stage error integral, start-up voltage oscillation amplitude, steady-state DC bus voltage ripple, peak-to-peak reactive power, and reactive power RMS.

[0094] Considering that this implementation scheme includes Q-weighted soft start and reactive power average de-biasing soft start, the steady-state ripple index is selected for statistical analysis during the stable time period after the control scheduling is completed, that is, the steady-state segment for 400V is selected as 1.0 to 1.45s, and the steady-state segment for 500V is selected as 2.3 to 3.0s; the start-up performance is statistically analyzed within 0 to 0.5s, and the reference voltage step response is statistically analyzed after 1.5s.

[0095] like Figure 5 The figure shows a comparison of the DC bus voltage response between the original scheme and this implementation scheme. The comparison shows that this implementation scheme can shorten the DC bus start-up regulation time and reduce start-up oscillation, while maintaining a low bus voltage ripple in the steady-state phase. Figure 6 The figure shows a comparison of the reactive power response between the original scheme and this implementation scheme. The comparison shows that this implementation scheme can significantly reduce the peak-to-peak value and RMS value of reactive power, and has excellent reactive power fluctuation suppression capability under unbalanced power grid conditions. Table 1 lists the key simulation performance index comparison data.

[0096] Table 1. Comparison of simulation performance between the original scheme and this implementation scheme

[0097] As shown in Table 1, compared with the original scheme, this implementation scheme has better dynamic performance in the startup phase. The DC bus startup adjustment time is reduced from 0.2950s to 0.1661s, the startup phase error integral is reduced from 30.406V·s to 12.011V·s, and the peak-to-peak value of the detrending oscillation in the startup phase is reduced from 74.178V to 11.891V. This indicates that this implementation scheme can significantly reduce the bus voltage oscillation during startup and improve the stability of the DC bus voltage build-up process.

[0098] During steady-state operation, the DC bus voltage ripple of this implementation scheme at 400V and 500V conditions decreased from 3.252V and 5.928V to 3.175V and 5.871V, respectively. This indicates that the implementation scheme can further improve steady-state bus voltage fluctuations without sacrificing bus voltage regulation performance. Simultaneously, this implementation scheme has a significant suppression effect on reactive power fluctuations. The QRMS in the steady-state segment at 400V decreased from 980.408var to 77.008var, and the QRMS in the steady-state segment at 500V decreased from 1535.572var to 94.036var. This demonstrates that the proposed reactive power synergistic suppression strategy can effectively reduce reactive power fluctuations under unbalanced grid conditions.

[0099] Furthermore, during the reference voltage step transition from 400V to 500V, the step adjustment time of the original scheme was 0.1653s, while that of this implementation scheme was 0.1667s, which is basically the same. This indicates that while significantly improving the startup performance and reactive power suppression effect, this implementation scheme can still maintain good DC bus dynamic tracking capability.

[0100] In summary, simulation results show that this implementation scheme has at least the following advantages over the original scheme: First, it can shorten the DC bus start-up adjustment time and reduce start-up oscillation; second, it can reduce DC bus voltage ripple during the steady-state phase; third, it can significantly reduce the peak-to-peak value and RMS value of reactive power; and fourth, it basically maintains the original dynamic response speed during the reference voltage step process. Therefore, the above data can prove that this implementation scheme has better bus stability, reactive power suppression capability, and overall operating performance than the original scheme.

[0101] Example 2 like Figure 1 As shown, this invention provides a coordinated control system for pulse width modulation rectifiers under a three-phase unbalanced power grid. This system is used to implement the coordinated control method for pulse width modulation rectifiers under a three-phase unbalanced power grid described in Embodiment 1 above, specifically including: The main circuit of the three-phase PWM rectifier has its AC side connected to the three-phase power grid through a filter inductor, and its DC side connected to the DC bus capacitor and load. The AC side voltage and current sampling module is used to synchronously acquire the three-phase grid voltage and the three-phase rectifier input current and output the sampling signal; The DC bus voltage sampling module is used to acquire the DC bus voltage and output the outer loop voltage feedback signal; The control calculation unit has its input terminals connected to the output terminals of the AC side voltage and current sampling module and the DC bus voltage sampling module, respectively. The control calculation unit integrates a coordinate transformation and sequence component separation unit, an imbalance degree identification unit, an outer loop active disturbance rejection control unit, a joint gain scheduling and saturation backoff unit, and an inner loop finite control set model prediction control unit. The PWM drive and protection circuit has its input terminal connected to the output terminal of the control calculation unit and its output terminal connected to the control terminal of the three-phase PWM rectifier main circuit. It is used to generate power device drive pulses according to the optimal switching state and control the operation of the three-phase PWM rectifier main circuit in combination with overcurrent, overvoltage, undervoltage and drive fault protection logic.

[0102] The pulse width modulation rectifier collaborative control system under a three-phase unbalanced power grid described in this embodiment is used to implement the aforementioned method embodiment. Its implementation method is the same as that of the method embodiment, and will not be repeated here.

[0103] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0106] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for coordinated control of pulse width modulation rectifiers under a three-phase unbalanced power grid, characterized in that, Includes the following steps: Step S1: Synchronously acquire three-phase grid voltage, three-phase rectifier input current, and DC bus voltage; Step S2: Perform Clarke transformation on the three-phase grid voltage and the three-phase rectifier input current to obtain... The voltage and current components in the coordinate system, for the The voltage components in the coordinate system are separated into positive and negative sequences to obtain positive-sequence voltage components and negative-sequence voltage components. Step S3: Calculate the unfiltered imbalance index based on the positive-sequence voltage component and the negative-sequence voltage component. ,right By sequentially performing amplitude limiting and first-order discrete low-pass filtering, the imbalance index after filtering is obtained. ; Step S4: Using the DC bus voltage as the outer loop controlled state, construct an equivalent discrete extended model of the DC bus voltage. Based on this model, update the observation state of the discrete extended state observer to obtain the estimated value of the DC bus voltage state. and equivalent total disturbance estimate ; Step S5: Based on the DC bus voltage reference value and the... Calculate the state error, and generate an unlimited active power reference value based on the state error feedback. ,right Power limiting and slope limiting are performed sequentially to obtain the reference value of the actual active power sent into the inner loop. and according to and The deviation generates a saturation flag ; Step S6: Using the aforementioned DC bus voltage error, error change and the aforementioned As input, through a pre-established Joint gain scheduling and saturation backoff mechanism for online adjustment of extended state observer bandwidth Proportional gain of state error feedback and integral gain and according to Execute the saturation rollback state machine logic; Step S7: Taking the inner loop current as the controlled object, perform a two-step prediction based on the pre-established AC side discrete prediction model, according to the... , Equivalent reactive power reference value generated from DC bus status Equivalent DC bus voltage with state sensing Enumerate the eight finite switching states of the three-phase two-level pulse width modulation rectifier and calculate the predicted active power and predicted reactive power corresponding to each candidate switching state. Step S8: Construct a cost function that includes active power tracking terms and reactive power tracking terms, select the candidate switching state with the minimum cost function as the optimal switching state, and output it to the pulse width modulation drive and protection circuit to drive the rectifier main circuit.

2. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S3, the unfiltered imbalance index is calculated. The method is as follows: ； in, This is the positive sequence voltage amplitude. The magnitude of the negative sequence voltage. To prevent division by zero constant; For unfiltered imbalance index Limiting the amplitude: ； in, For the first The imbalance index after amplitude limiting in each control cycle The sequence number of the discrete control cycle represents the number of the... One control cycle, For the first The original unfiltered imbalance index for each control cycle This is the lower limit threshold for the imbalance index. This represents the upper limit threshold for the imbalance indicator; Imbalance index after amplitude limiting Perform first-order discrete low-pass filtering: ； in, For the first The degree of imbalance in the output after filtering for each control cycle. For the first An index of the degree of imbalance after filtering in each control cycle. The filter coefficients of a first-order discrete low-pass filter are... .

3. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S4, the equivalent discrete extended model of the DC bus voltage is as follows: ； ； ； in, , The first , DC bus voltage status for each control cycle , The first , The equivalent total disturbance for each control cycle. To control the cycle, The nominal control gain is the equivalent of the DC bus voltage. This represents the equivalent total disturbance rate of change or the unmodeled dynamics. This is the outer loop observation output, i.e., the DC bus voltage measurement value. ; The update equation for the discrete extended state observer is: ； ； in, , The first , DC bus voltage state estimate for each control cycle , The first , Estimated equivalent total disturbance in the dynamic bus voltage of each control cycle. For the first The actual active power reference value sent into the inner loop for each control cycle. This is the DC bus voltage observation error. and To extend the state observer gain, , , For the first The bandwidth of the extended state observer for each control cycle.

4. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S5, for The method for power limiting is as follows: ； in, For the first The active power reference value after power limiting processing for each control cycle. It is a saturation limiting function. and These are the lower and upper limits of the active power reference value, respectively; Reference value of active power after limiting Slope limiting processing: ； in, For the first The actual active power reference value sent into the inner loop for each control cycle. This represents the maximum allowable power change within a single control cycle. according to and The deviation generates a saturation flag : ； ； in, This is the saturation deviation. This is the threshold for determining saturation.

5. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S6, the pre-established The joint gain scheduling and saturation backoff mechanism normalizes the imbalance factor. and normalized error factor Target values ​​for the parameters are generated, and then the final control parameters are obtained through slope limiting processing. The target bandwidth value of the extended state observer for: ； in, and These are the upper and lower limits of the bandwidth of the extended state observer, respectively. This is the bandwidth backoff coefficient under saturation conditions.

6. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S6, the saturation rollback state machine includes three states: normal scheduling, saturation hold, and soft recovery; when the saturation duration count value... When the threshold value is greater than or equal to the trigger threshold, the system enters a saturation hold state, reducing the bandwidth and control gain of the extended state observer and freezing or releasing the integral channel; when the acknowledgment count value is released... When the threshold is ≥ cleared, the system enters a soft recovery state, gradually restoring the control parameters and integral channels in a limited slope manner.

7. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S7, a two-step prediction is performed based on a pre-established AC-side discrete prediction model to compensate for the one-step delay of digital control. The first step uses the voltage vector actually applied in the previous cycle for prediction. The second step is to predict the state of each candidate switch based on the instantaneous current. Current at any moment; The method for calculating the predicted active power is as follows: ； The method for calculating the predicted reactive power is as follows: ； in, and They represent the first The candidate switch state, the first Predicted active power and predicted reactive power for each control cycle For the first During each control cycle, the grid-side voltage is... coordinate system Axial components, No. During each control cycle, the grid-side voltage is... coordinate system Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current Axial components, For the first Periodic information, prediction adopts the first In the first switch state, the second... Periodic input current Axial components.

8. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S7, the state-sensing equivalent DC bus voltage is... The calculation formula is: ； in, This is the reference value for the DC bus voltage. This is the actual bus voltage after low-pass filtering. State-aware mixing coefficients; The equivalent reactive power reference value The calculation formula is: ； in, The set reactive power reference value, This is an unbalanced reactive power compensation term constructed based on positive and negative sequence voltage components. This is the reactive power average debiasing compensation amount.

9. The method for coordinated control of pulse width modulation rectifiers under three-phase unbalanced power grids according to claim 1, characterized in that, In step S8, the cost function is calculated using the following formula: ； in, For the first The cost function value of each candidate switch state. As a result of merit, For soft scheduling reactive power weights, The penalty weight for switch transitions, For a norm, Indicates the first The candidate switch state, the first Predicted active power corresponding to each control cycle For the first A three-dimensional column vector of candidate switch states, The actual switching state output in the previous control cycle; the optimal switching state. .

10. A coordinated control system for pulse width modulation rectifiers under a three-phase unbalanced power grid, characterized in that, The system is used to implement the coordinated control method for pulse width modulation rectifiers under a three-phase unbalanced power grid as described in any one of claims 1 to 9, specifically including: The main circuit of the three-phase PWM rectifier has its AC side connected to the three-phase power grid through a filter inductor, and its DC side connected to the DC bus capacitor and load. The AC side voltage and current sampling module is used to synchronously acquire the three-phase grid voltage and the three-phase rectifier input current and output the sampling signal; The DC bus voltage sampling module is used to acquire the DC bus voltage and output the outer loop voltage feedback signal; The control calculation unit has its input terminals connected to the output terminals of the AC side voltage and current sampling module and the DC bus voltage sampling module, respectively. The control calculation unit integrates a coordinate transformation and sequence component separation unit, an imbalance degree identification unit, an outer loop active disturbance rejection control unit, a joint gain scheduling and saturation backoff unit, and an inner loop finite control set model prediction control unit. The PWM drive and protection circuit has its input terminal connected to the output terminal of the control calculation unit and its output terminal connected to the control terminal of the three-phase PWM rectifier main circuit. It is used to generate power device drive pulses according to the optimal switching state and control the operation of the three-phase PWM rectifier main circuit in combination with overcurrent, overvoltage, undervoltage and drive fault protection logic.

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