Video transcoding method, device, equipment and computer program product

Abstract

The invention provides a video transcoding method, device and equipment and a computer program product, and relates to the technical field of video processing. The method comprises the following steps: receiving a target video; performing format analysis on the target video, and determining a source format of the target video and a to-be-transcoded target format; determining a video format supported by the VPU cluster; if it is judged that the source format is not within the video format range supported by the VPU cluster and the target format is within the video format range supported by the VPU cluster, determining that the target format is within the video format range supported by the VPU cluster; and controlling the CPU cluster to carry out software decoding on the target video, and controlling the VPU cluster to carry out hardware coding on decoded video data so as to complete video transcoding. According to the embodiment of the invention, the compatible range of the input video format can be expanded, and meanwhile, the efficient hardware acceleration advantage of the VPU is kept.

Description

Technical Field

[0001] This disclosure relates to the field of video processing technology, and in particular to a video transcoding method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this disclosure as set forth in the claims. The description herein is not intended to be a prior art simply because it is included in this section.

[0003] In the field of video processing, the VPU (Video Processing Unit) is a dedicated video processing unit whose core task is to perform efficient video encoding and decoding operations. Specifically, the VPU can perform hardware-accelerated compression of raw video data based on specified encoding standards, effectively reducing the size of video data and thus facilitating storage and network transmission; at the same time, the VPU also supports re-decoding compressed video data to restore it to a video frame that can be directly rendered and played.

[0004] However, because VPUs are typically implemented with fixed hardware circuitry or dedicated acceleration cores, they lack programmability and scalability in terms of encoding / decoding logic and format support, resulting in significantly less flexibility compared to general-purpose central processing units (CPUs). This limitation is particularly evident in support for older encoding formats (such as MPEG-2) and emerging encoding standards (such as AV1 and H.266 / VVC), which often cannot be adapted through software upgrades, thus restricting the widespread application of VPUs in video transcoding scenarios. Summary of the Invention

[0005] The purpose of this disclosure is to provide a video transcoding method, apparatus, electronic device, computer-readable storage medium, and computer program product that can significantly improve the processing efficiency and resource utilization of the transcoding system while ensuring video format compatibility.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] This disclosure provides a video transcoding method, including: receiving a target video; parsing the target video to determine the source format and the target format to be transcoded; determining the video formats supported by a VPU cluster; if it is determined that the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster; controlling a CPU cluster to perform software decoding on the target video, and controlling the VPU cluster to perform hardware encoding on the decoded video data to complete the video transcoding.

[0008] In some embodiments, the VPU cluster and the CPU cluster interact via shared memory; wherein controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding includes: the CPU cluster decoding the target video to obtain decoded video data; the CPU cluster caching the decoded video data in the shared memory; and the CPU cluster sending a notification to the VPU cluster to enable the VPU cluster to read the decoded video data from the shared memory and perform hardware encoding processing.

[0009] In some embodiments, the CPU cluster and the data processing module interact via the same shared memory. The process of controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding includes: the CPU cluster decoding the target video to obtain decoded video data; the CPU cluster writing the decoded video data into the shared memory and notifying the data processing module; the data processing module, in response to the notification, reading the decoded video data from the shared memory and performing video enhancement processing on the decoded video data, the video enhancement processing including at least one of super-resolution reconstruction, noise reduction, or watermark addition; the data processing module writing the processed video data into the shared memory and notifying the VPU cluster; and the VPU cluster, in response to the notification, reading the processed video data from the shared memory and performing hardware encoding processing on the processed video data.

[0010] In some embodiments, the method further includes: if it is determined that neither the source format nor the target format is within the range of video formats supported by the VPU cluster; controlling the CPU cluster to perform full-process software transcoding on the target video to convert the target video from the source format to the target format.

[0011] In some embodiments, the CPU cluster and the data processing module interact with each other through the same shared memory; wherein, the method further includes: if it is determined that the source format is within the range of video formats supported by the VPU cluster, and the target format is not within the range of video formats supported by the VPU cluster; then controlling the VPU cluster to perform hardware decoding on the target video to obtain decoded video data; the VPU cluster writes the decoded video data into the shared memory and notifies the CPU cluster; in response to the notification, the CPU cluster reads the decoded video data from the shared memory and performs software encoding to generate the video in the target format.

[0012] In some embodiments, controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data includes: if the current load rate of the CPU cluster is lower than a first preset threshold and the current load rate of the VPU cluster is higher than a second preset threshold, then controlling the CPU cluster to perform software decoding and software encoding; if the current load rate of the VPU cluster is not higher than the second preset threshold, then controlling the CPU cluster to perform software decoding and controlling the VPU cluster to perform hardware encoding.

[0013] This disclosure provides a video transcoding apparatus, including: a video receiving module, a transcoding format determining module, a supported format determining module, a first format judging module, and a first control module.

[0014] The video receiving module is used to receive the target video; the transcoding format determination module can be used to parse the target video to determine the source format and the target format to be transcoded; the supported format determination module can be used to determine the video formats supported by the VPU cluster; the first format judgment module can be used to determine if the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster; the first control module can be used to control the CPU cluster to perform software decoding of the target video and control the VPU cluster to perform hardware encoding of the decoded video data to complete the video transcoding.

[0015] This disclosure provides an electronic device comprising: a memory and a processor; the memory for storing computer program instructions; and the processor for calling the computer program instructions stored in the memory to implement the video transcoding method described above.

[0016] This disclosure provides a computer-readable storage medium storing computer program instructions to implement the video transcoding method as described in any of the preceding embodiments.

[0017] This disclosure provides a computer program product or computer program that includes computer program instructions stored in a computer-readable storage medium. The computer program instructions are read from the computer-readable storage medium, and a processor executes the computer program instructions to implement the aforementioned video transcoding method.

[0018] The video transcoding method, apparatus, electronic device, computer-readable storage medium, and computer program product provided in this disclosure, by real-time parsing of video formats and matching them with the support capabilities of a VPU cluster, can automatically call upon the CPU for flexible decoding when the source format is not supported by the VPU but the target format is supported. This is combined with efficient encoding by the VPU, thereby ensuring broad video format compatibility while fully leveraging the hardware acceleration advantages of the VPU, significantly improving the overall efficiency and resource utilization of the transcoding process. This method effectively solves the efficiency bottleneck problem caused by the limited format support of hardware codecs in traditional solutions, providing a scalable and efficient transcoding solution for large-scale, multi-format video processing scenarios.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 A schematic diagram of a scenario that can be applied to the video transcoding method or video transcoding apparatus of the present disclosure is shown.

[0022] Figure 2 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0023] Figure 3 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0024] Figure 4 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0025] Figure 5 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0026] Figure 6 This is a functional block diagram illustrating a video transcoding method according to an exemplary embodiment.

[0027] Figure 7 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0028] Figure 8 This is a block diagram illustrating a video transcoding apparatus according to an exemplary embodiment.

[0029] Figure 9 A schematic diagram of the structure of an electronic device suitable for implementing embodiments of the present disclosure is shown. Detailed Implementation

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0031] Those skilled in the art will recognize that embodiments of this disclosure can be a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0032] The features, structures, or characteristics described in this disclosure can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0033] In this disclosure, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0034] The accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus omitting repeated descriptions of them. Some block diagrams shown in the drawings do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0035] The flowchart shown in the accompanying drawings is merely illustrative and does not necessarily include all content and steps, nor does it require execution in the described order. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0036] In the description of this disclosure, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. "And / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences; the terms "contains," "includes," and "has" are used to indicate an open-ended meaning of inclusion and refer to the existence of additional elements / components / etc. besides those listed.

[0037] To better understand the above-mentioned objectives, features and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0038] The following section will first explain some of the terms used in the embodiments of this disclosure so that those skilled in the art can understand them.

[0039] Hardware acceleration for video encoding and decoding supports mainstream standards such as H.264, H.265, and AV1, achieving high throughput and low power consumption video compression and decompression through dedicated hardware modules.

[0040] Zero-copy memory: Zero-copy is a technique that optimizes data transfer efficiency by reducing the number of data copies involving the CPU, thereby lowering latency and resource consumption. Zero-copy memory refers to a technique that avoids copying data from one storage area to another during computer operations, without CPU involvement. Its goal is to reduce or even eliminate unnecessary data copies, significantly reducing CPU overhead, memory bandwidth usage, and improving application performance.

[0041] The preceding text introduced some terms and concepts involved in the embodiments of this disclosure. The following text introduces the technical features involved in the embodiments of this disclosure.

[0042] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0043] Figure 1 A schematic diagram of a scenario that can be applied to the video transcoding method or video transcoding apparatus of the present disclosure is shown.

[0044] Please refer to Figure 1 The diagram illustrates an implementation environment provided by an exemplary embodiment of this disclosure.

[0045] like Figure 1 As shown, system architecture 100 may include terminal devices 101, 102, and 103, a network 104, and a server 105. Network 104 serves as the medium for providing communication links between terminal devices 101, 102, and 103 and server 105. Network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0046] Users can use terminal devices 101, 102, and 103 to interact with server 105 via network 104 to receive or send messages, etc. Terminal devices 101, 102, and 103 can be various electronic devices with displays and web browsing capabilities, including but not limited to smartphones, tablets, laptops, desktop computers, wearable devices, virtual reality devices, smart home devices, etc.

[0047] Server 105 can be a server that provides various services, such as a backend management server that supports the devices operated by users using terminal devices 101, 102, and 103. The backend management server can analyze and process received requests and other data, and feed the processing results back to the terminal devices.

[0048] A server can be a standalone physical server, a server cluster or a distributed system consisting of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. This disclosure does not impose any restrictions on this.

[0049] Server 105 may, for example, receive a target video; server 105 may, for example, perform format parsing on the target video to determine the source format and the target format to be transcoded; server 105 may, for example, determine the video formats supported by the VPU cluster; server 105 may, for example, if it determines that the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster, server 105 may, for example, control the CPU cluster to perform software decoding on the target video, and control the VPU cluster to perform hardware encoding on the decoded video data to complete the video transcoding.

[0050] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Server 105 can be a single physical server or a combination of multiple servers. Depending on actual needs, it can have any number of terminal devices, networks, and servers.

[0051] Under the above system architecture, this disclosure provides a video transcoding method that can be executed by any electronic device with computing power.

[0052] Figure 2 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment. The method provided in this disclosure can be executed by any electronic device with computing power, for example, the method can be implemented by the above-described... Figure 1 The execution can be performed by a server or terminal device in the embodiments, or it can be performed by both a server and a terminal device. In the following embodiments, the server is used as the execution subject for illustration, but this disclosure is not limited to this.

[0053] Reference Figure 2 The video transcoding method provided in this disclosure may include the following steps.

[0054] Step S202: Receive the target video.

[0055] Step S204: Analyze the format of the target video to determine the source format and the target format to be transcoded.

[0056] In some embodiments, the target video file can be parsed by calling a video analysis module (e.g., demultiplexing and stream analysis functions based on the FFmpeg library) to extract metadata information such as its encapsulation format, encoding format, resolution, frame rate, bitrate, and encoding parameters. This accurately identifies the current encoding format of the video as the source format, and determines the target format to be converted based on user configuration or transcoding task requirements. This parsing process is executed in real time after the system receives the video stream, providing accurate format information for subsequent heterogeneous scheduling and encoding / decoding path decisions.

[0057] Step S206: Determine the video formats supported by the VPU cluster.

[0058] In some embodiments, a pre-configured VPU hardware capability configuration file can be accessed or the VPU driver interface can be queried to obtain a list of encoding and decoding formats supported by the VPU cluster. This list may include mainstream video encoding standards such as H.264 / AVC, H.265 / HEVC, and AV1, as well as their specific levels and support information. The system loads this support list during initialization or dynamic updates and establishes a format matching judgment criterion based on it, which is used to compare the source and target formats of the video in real time during transcoding scheduling to see if they are within the range that the VPU can accelerate.

[0059] Step S208: If it is determined that the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster.

[0060] Step S210: Control the CPU cluster to perform software decoding of the target video, and control the VPU cluster to perform hardware encoding of the decoded video data to complete the video transcoding.

[0061] In some embodiments, if the current load rate of the CPU cluster is lower than a first preset threshold and the current load rate of the VPU cluster is higher than a second preset threshold, the CPU cluster is controlled to perform software decoding and software encoding; if the current load rate of the VPU cluster is not higher than the second preset threshold, the CPU cluster is controlled to perform software decoding and the VPU cluster is controlled to perform hardware encoding.

[0062] To enhance the flexibility and adaptability of scheduling strategies, the first and second threshold values ​​can abandon the traditional fixed-value model and adopt an adaptive adjustment mechanism based on historical system load trends. By statistically analyzing and predicting trends from historical load data, the threshold parameters are dynamically optimized, enabling the thresholds to accurately match the fluctuation patterns of system resources and task processing requirements, thereby significantly enhancing the elasticity and real-time adaptability of scheduling decisions. In some embodiments, real-time load metrics of each computing unit can be periodically collected through a performance monitoring module. For CPU clusters, the load rate can be comprehensively evaluated based on overall CPU utilization, the length of each core queue, or the number of frames to be processed by the soft-coding threads; for VPU clusters, the load rate can be quantified based on the utilization rate of its hardware encoding engine, the size of the frame buffer to be encoded, or the interface call latency. These metrics are aggregated by a lightweight load aggregator and compared with the preset first threshold value (corresponding to the CPU load threshold) and second threshold value (corresponding to the VPU load threshold).

[0063] In some embodiments, when the current load rate of the CPU cluster is detected to be lower than a first preset threshold and the current load rate of the VPU cluster is higher than a second preset threshold, the scheduler determines that the VPU is under high load while the CPU is relatively idle. At this time, in order to alleviate the pressure on the VPU and utilize idle CPU resources, the system allocates the transcoding tasks entirely to the CPU cluster, which then executes software decoding and software encoding sequentially to achieve full software path transcoding and avoid tasks accumulating in the VPU queue.

[0064] Conversely, if the current load rate of the VPU cluster is not higher than the second set threshold, indicating that the VPU encoding capacity is sufficient, the system adopts a heterogeneous division of labor strategy: the CPU is responsible for software decoding, and the VPU is responsible for hardware encoding. This approach leverages the CPU's flexible decoding advantages while fully utilizing the VPU's high-energy-efficiency encoding capabilities, thereby achieving an optimal balance between throughput and energy efficiency when the overall system load is light or balanced.

[0065] In addition, the threshold can be dynamically and adaptively adjusted according to historical load trends, and weighted decisions can be made in combination with factors such as task priority and timeliness requirements, so that the system can still maintain efficient path selection and resource scheduling in diverse video streams and dynamic resource environments.

[0066] In some embodiments, if it is determined that neither the source format nor the target format is within the range of video formats supported by the VPU cluster, the CPU cluster is controlled to perform full-process software transcoding on the target video to convert the target video from the source format to the target format.

[0067] The video transcoding method provided in this disclosure achieves dynamic collaborative scheduling of heterogeneous computing power between the CPU and VPU by real-time parsing of the source and target video formats and matching them with the VPU hardware capabilities. In scenarios where the VPU does not support the source format but does support the target format, the system intelligently allocates the CPU to perform software decoding and the VPU to perform hardware encoding, fully leveraging the hardware acceleration advantages while ensuring format compatibility. This method further incorporates dynamic path selection based on real-time load status, enabling full-process CPU software transcoding to balance system pressure when the VPU load is too high. This significantly improves processing efficiency, resource utilization, and system robustness in multi-format, high-concurrency video transcoding scenarios.

[0068] In some embodiments, scheduling can be performed based on load by: estimating the transcoding computation cost of the target video using a prediction model based on the target video's metadata, and then scheduling based on the estimated cost.

[0069] In some embodiments, the computational cost of the target video transcoding task can be predicted based on the target video's metadata (such as resolution, frame rate, motion complexity) and historical transcoding data using a machine learning prediction model.

[0070] In some embodiments, time series models or neural networks can be used to dynamically allocate CPU / VPU resources based on the complexity of the video content. For example, high-complexity tasks (such as those with large computational overhead) are preferentially allocated to the VPU cluster, while low-complexity tasks (such as those with small computational overhead) are processed by the CPU.

[0071] In some embodiments, a multi-level scheduling architecture can be designed to integrate business strategies and resource status for intelligent task distribution. This architecture prioritizes tasks based on their real-time requirements. For example, tasks with low latency requirements, such as live stream transcoding, are given high priority, while batch processing tasks, such as film and television archive transcoding, are given normal priority. For high-priority tasks, the scheduling module can bypass conventional load balancing threshold checks and directly distribute them to the VPU cluster to ensure transcoding response speed and end-to-end latency. Simultaneously, the system associates a dynamic timeout threshold with each task. If a task execution time exceeds expectations, it triggers task interruption or downgraded rescheduling, thereby releasing computing resources that have been occupied for a long time and preventing low-priority tasks from experiencing "resource starvation" due to continuous waiting. This ensures the quality of critical business services while maintaining the overall throughput and fairness of the system.

[0072] In some embodiments, a CRC (Cyclic Redundancy Check) checksum and retransmission coordination mechanism can be added. Before and after the CPU and VPU transmit video data via shared memory, a data checksum is calculated to verify integrity. If the checksum results are inconsistent (i.e., a transmission error is determined), the system will automatically trigger a repair process where the CPU re-decodes or the VPU re-encodes. Simultaneously, detailed log data such as error type, data frame information, and processing nodes are recorded, providing accurate evidence for system self-healing and further ensuring the stability and reliability of the transcoding process. In some embodiments, dynamic voltage and frequency adjustment technology can also be integrated, which can adjust the chip frequency and voltage in real time according to the VPU / CPU load. For example, when the VPU cluster idle rate exceeds 50%, the frequency is automatically reduced to a low-power mode; at the same time, a power consumption threshold is set, and when the total system power consumption exceeds the limit, high-energy-efficiency tasks are prioritized for scheduling.

[0073] In some embodiments, the resources of the VPU cluster can be virtualized into a resource pool for dynamic sharing and time-division multiplexing of multiple transcoding tasks.

[0074] In some embodiments, VPU cluster resources can also be pooled to support dynamic sharing of multiple transcoding tasks. For example, a time-division multiplexing mechanism can be used to allow VPU resources to be oversold to improve utilization; and a resource reservation pool can be designed to guarantee high-priority tasks.

[0075] In some embodiments, resource instances can also be automatically scaled based on monitoring data such as queue length. For example, when the number of pending tasks suddenly increases, additional VPU nodes can be dynamically allocated from the resource pool.

[0076] Figure 3 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0077] In some embodiments, the VPU cluster and the CPU cluster interact with each other through shared memory.

[0078] In some embodiments, the VPU cluster and the CPU cluster exchange data through the same physical memory area, eliminating the need to directly copy data between the two, thereby reducing transmission latency and CPU overhead, and enabling efficient heterogeneous collaborative processing.

[0079] refer to Figure 3 The process of controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding may include the following steps.

[0080] In step S302, the CPU cluster decodes the target video to obtain the decoded video data.

[0081] In step S304, the CPU cluster caches the decoded video data in shared memory.

[0082] In step S306, the CPU cluster sends a notification to the VPU cluster so that the VPU cluster can read the decoded video data from the shared memory and perform hardware encoding processing.

[0083] In some embodiments, the CPU cluster can send a hardware interrupt to the VPU driver directly through inter-process communication mechanisms provided by the operating system (such as semaphores, message queues, or event notifications), along with the address information of the decoded data in the shared memory and a data ready flag, thereby triggering the VPU cluster to read the decoded video data from the shared memory area and start its hardware encoding engine to perform encoding processing, thus realizing efficient and low-latency collaborative pipelined operation between heterogeneous units.

[0084] This application embodiment establishes an efficient and low-overhead data transfer path between the CPU and VPU by introducing a shared memory mechanism and an asynchronous notification mechanism. After the CPU directly writes the decoded video data into the shared memory, it actively notifies the VPU through inter-process communication or hardware interrupt, triggering the VPU to read the data from the memory and start hardware encoding. This avoids multiple copies of data between heterogeneous processors, significantly reducing transmission latency and CPU usage. As a result, it achieves pipelined collaboration between CPU software decoding and VPU hardware encoding, effectively improving the overall processing efficiency of video transcoding and the utilization rate of system resources.

[0085] In some embodiments, data interaction via shared memory may include: employing a mechanism based on atomic operations or lock-free queues to manage the access status of data blocks in the shared memory in order to resolve race conditions when CPU clusters and VPU clusters access each other.

[0086] In some embodiments, atomic operations (such as CAS (Compare And Swap) instructions) or lock-free queues can be introduced into shared memory management. This leverages the uninterruptible nature of atomic instructions to ensure data consistency during concurrent multi-threaded access, preventing data tampering or corruption. Furthermore, by setting clear status flags such as "ready" and "busy" for each memory block, memory access permissions can be precisely controlled, effectively avoiding race conditions caused by the CPU and VPU simultaneously reading and writing to the same memory region. This further improves the stability and processing efficiency of data interaction in heterogeneous architectures. In some embodiments, an elastic memory pool can be designed to dynamically adjust the size of shared memory blocks based on the video stream size. For example, memory blocks of different sizes can be pre-allocated (e.g., 4KB for metadata, 1MB for video frames), and optimal matching algorithms can be used to reduce fragmentation. Simultaneously, cache preheating can be supported, preloading data in high-frequency formats.

[0087] In some embodiments, memory blocks of fixed sizes such as 4KB, 1MB, and 8MB can be pre-allocated according to commonly used data types in video transcoding (metadata, video frames, etc.) and corresponding free lists can be established. Then, based on real-time parameters such as video resolution and bitrate of the target video, the optimal matching algorithm can be used to dynamically allocate suitable memory blocks to reduce fragmentation. At the same time, expansion (when continuous allocation fails) and release (when the free rate is too high) rules are set to optimize memory utilization. It also supports preloading encoding and decoding configuration information for high-frequency transcoding formats such as AV1 and H.265 to reduce processing latency.

[0088] In some embodiments, cache preheating can refer to identifying frequently used transcoding formats such as AV1 and H.265 before the video transcoding task starts, and preloading their corresponding encoding / decoding configuration parameters, data templates, and commonly used algorithm modules into a designated cache area of ​​the elastic memory pool. This avoids the time-consuming process of temporarily allocating memory and loading data during transcoding. In practice, high-frequency formats can be determined by statistically analyzing the frequency of format usage in historical transcoding tasks. Preloading can be triggered during system initialization or idle periods. At the same time, the cache area can be bound to the processing flow of the corresponding format to ensure that data can be directly read from the cache during transcoding, thereby improving processing efficiency.

[0089] Figure 4 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0090] In some embodiments, the CPU cluster, VPU cluster, and data processing module interact with each other through the same shared memory.

[0091] refer to Figure 4 The process of controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding may include the following steps.

[0092] In step S402, the CPU cluster decodes the target video to obtain the decoded video data.

[0093] In step S404, the CPU cluster writes the decoded video data into the shared memory and notifies the data processing module.

[0094] In step S406, the data processing module responds to the notification by reading the decoded video data from the shared memory and performing video enhancement processing on the decoded video data. The video enhancement processing includes at least one of super-resolution reconstruction, noise reduction processing, or watermark addition.

[0095] After receiving a notification carrying memory address and processing type parameters, the data processing module reads the decoded video data from a specified location in shared memory via direct memory access. Then, according to the task configuration, it calls the corresponding enhancement processing algorithm—such as a neural network-based super-resolution reconstruction model, a spatiotemporal noise reduction filter, or a graphics overlay watermarking engine—to process the video frame sequence. After processing, the module writes the result data back to another pre-allocated area of ​​shared memory via memory mapping, updates the metadata, and triggers the next stage notification. This achieves high-quality, low-latency video enhancement and transcoding pipeline collaboration without introducing additional data copying.

[0096] In step S408, the data processing module writes the processed video data into the shared memory and notifies the VPU cluster.

[0097] In step S410, the VPU cluster responds to the notification by reading the processed video data from the shared memory and performing hardware encoding on the processed video data.

[0098] In some embodiments, lightweight AI models (such as super-resolution networks or denoising models based on TensorFlowLite) can be integrated into the data processing module to achieve adaptive image quality enhancement. For example, model parameters can be dynamically selected based on the video scene—using a high frame rate model for moving scenes and a high resolution model for static scenes.

[0099] In some embodiments, for emerging standards such as AV1 or H.266, the data layout in shared memory can be optimized. For example, data blocks can be aligned using the SIMD (Single Instruction, Multiple Data) instruction set of the VPU to improve coding parallelism; at the same time, perceptual quantization technology can be introduced for AI coding to balance quality and compression ratio.

[0100] In some embodiments, the QUIC (Quick UDP Internet Connections) protocol can be used to adjust the video bitrate in real time after transcoding to adapt to network bandwidth. For example, a bitrate control submodule can be added to the data processing module to dynamically switch the output bitrate based on network latency, reducing playback buffering.

[0101] This embodiment introduces a shared-memory-based video enhancement processing module between CPU decoding and VPU encoding, constructing a flexibly scalable "decoding-enhancement-encoding" pipeline. The system utilizes shared memory to achieve zero-copy data transfer between processing units, and combines this with an asynchronous notification mechanism to coordinate the processing flow. This enables real-time image quality enhancement operations such as super-resolution, noise reduction, and watermarking to be completed without data migration, with the VPU ultimately performing efficient hardware encoding. This design significantly reduces data interaction overhead and processing latency between heterogeneous systems while ensuring video processing quality and functional flexibility, achieving high-throughput, low-latency, and customizable intelligent video transcoding and enhancement integrated processing.

[0102] Figure 5 This is a flowchart illustrating a video transcoding method according to an exemplary embodiment.

[0103] In some embodiments, the CPU cluster and the data processing module interact with each other through the same shared memory.

[0104] refer to Figure 5 The above video transcoding method may include the following steps.

[0105] Step S502: If it is determined that the source format is within the range of video formats supported by the VPU cluster, and the target format is not within the range of video formats supported by the VPU cluster.

[0106] Step S504: Control the VPU cluster to perform hardware decoding on the target video to obtain the decoded video data.

[0107] In step S506, the VPU cluster writes the decoded video data to the shared memory and notifies the CPU cluster.

[0108] In step S508, the CPU cluster responds to the notification by reading the decoded video data from shared memory and performing software encoding to generate a video in the target format.

[0109] This embodiment addresses scenarios where the VPU supports the source format but not the target format. It constructs a reverse heterogeneous collaborative pipeline of "VPU hardware decoding → CPU software encoding" through shared memory and asynchronous notification mechanisms. This solution fully utilizes the VPU's efficient decoding capabilities to process the input video, then hands it over to the CPU for flexible software encoding of new or special formats. This ensures broad compatibility with video formats while avoiding the efficiency bottleneck of traditional pure CPU-based end-to-end transcoding, achieving optimized processing efficiency and efficient reuse of hardware resources in a hybrid encoding support environment.

[0110] While CPUs, as central processing units, are powerful, their efficiency in processing video encoding and decoding tasks is relatively low, failing to meet the demands of real-time processing. GPUs, though adept at parallel computing, still suffer from high power consumption and a lack of specialization in video encoding and decoding. To address these issues, the Video Processing Unit (VPU) was developed. The core task of the VPU is video encoding and decoding. It can compress raw video data according to specific encoding formats (such as H.264, H.265 / HEVC, VP8, etc.), thereby reducing the size of the video data for easier storage and transmission; simultaneously, it can also restore the compressed video data into playable video footage.

[0111] However, VPU is a hardware implementation, which makes it less flexible than CPU and less supportive of old or new video formats.

[0112] In traditional video transcoding solutions, CPUs and VPUs are often used in isolation, leading to efficiency bottlenecks or compatibility issues. Specifically, 1) when transcoding is done with a VPU, a single hardware accelerator cannot adapt to rapidly evolving video coding standards; 2) when encoding is done with a CPU, CPU software encoding struggles to meet real-time and efficiency requirements.

[0113] In light of the above background, this application proposes a dynamic load-aware hybrid acceleration architecture that can accelerate heterogeneous video processing using a CPU+VPU architecture. The core of this architecture is to analyze and schedule the video stream according to processing tasks. Tasks that can be executed by the VPU are prioritized for VPU processing, while tasks that the VPU cannot handle can be processed in conjunction with the CPU using zero-copy memory technology, thereby improving the overall video processing efficiency.

[0114] In some embodiments, the solution proposed in this embodiment can be applied to scenarios requiring high-efficiency video processing. This technical solution performs different processing flows based on the format of the input video stream. For decoding formats not supported by the VPU, a CPU->shared memory->VPU processing flow is implemented. The functional modules involved are as follows: Figure 6 As shown.

[0115] Figure 6 This is a functional block diagram illustrating a video transcoding method according to an exemplary embodiment.

[0116] refer to Figure 6 This application makes the following: Figure 7 The video transcoding method shown.

[0117] like Figure 7 As shown, the video transcoding method may include the following steps.

[0118] Phase 1: Format Recognition Phase.

[0119] The input video stream is analyzed and identified using FFmpeg.

[0120] Phase Two: Dynamic Orchestration of Heterogeneous Resources.

[0121] By combining resource load data obtained from the resource monitoring module with task scheduling, and combining video format characteristics with hardware status to achieve dual-dimensional scheduling, the video processing throughput can be significantly improved compared to the fixed allocation mode.

[0122] Phase 3: CPU+VPU hybrid video processing phase.

[0123] For video frame processing requirements that VPU cannot support, CPU capabilities can be combined to meet the relevant processing needs.

[0124] After the CPU decodes the data, it generates YUV data. This data uses memory mapping and a DMA engine (shared memory) to avoid physical copying of YUV data between the CPU and VPU, reducing latency to the microsecond level. At the same time, it maintains metadata such as timestamps and frame types. Cross-device information synchronization is achieved through the PCIe P2P protocol (a technology that bypasses the CPU and system main memory to directly transmit data between two PCIe devices at high speed).

[0125] Then the VPU performs video encoding, which realizes a hybrid pipeline of CPU software decoding -> shared memory -> VPU hardware encoding.

[0126] This solution can significantly improve the success rate and overall efficiency of video processing compared to traditional solutions.

[0127] The above solution has at least the following technical effects.

[0128] 1. Dynamic heterogeneous load balancing: It is the first to use a dual-dimensional scheduling algorithm based on video format and hardware status (computing power, power consumption), breaking through the traditional fixed task allocation mode.

[0129] 2. Hybrid encoding and decoding process optimization: The "software and hardware decoupling + zero data copy" technology is proposed. By reducing the data migration overhead between the CPU and VPU through a shared memory pool, the throughput is significantly improved compared with the traditional solution. At the same time, the shared memory space is dynamically adjusted based on the elastic memory allocation strategy.

[0130] 3. Enhanced compatibility and energy efficiency: Combining the CPU's format compatibility with the VPU's efficient encoding capabilities, it supports full-coverage transcoding from older formats to AV1 / H.266, resulting in a significant improvement in overall energy efficiency.

[0131] It should be particularly noted that the steps in the various embodiments of the above video transcoding method can be overlapped, substituted, added, or deleted from each other. Therefore, these reasonable permutations and combinations of video transcoding methods should also fall within the protection scope of this disclosure, and the protection scope of this disclosure should not be limited to the described embodiments.

[0132] Based on the same inventive concept, this disclosure also provides a video transcoding apparatus, as described in the following embodiments. Since the principle by which this apparatus solves the problem is similar to that of the method embodiments described above, the implementation of this apparatus embodiment can refer to the implementation of the method embodiments described above, and repeated details will not be repeated.

[0133] Figure 8 This is a block diagram illustrating a video transcoding apparatus according to an exemplary embodiment. (Refer to...) Figure 8 The video transcoding device 800 provided in this embodiment may include: a video receiving module 801, a transcoding format determining module 802, a supported format determining module 803, a first format judging module 804, and a first control module 805.

[0134] The video receiving module 801 can be used to receive the target video; the transcoding format determination module 802 can be used to parse the target video to determine the source format and the target format to be transcoded; the supported format determination module 803 can be used to determine the video formats supported by the VPU cluster; the first format judgment module 804 can be used to determine if the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster; the first control module 805 can be used to control the CPU cluster to perform software decoding of the target video and control the VPU cluster to perform hardware encoding of the decoded video data to complete the video transcoding.

[0135] It should be noted that the video receiving module 801, transcoding format determination module 802, supported format determination module 803, first format judgment module 804, and first control module 805 mentioned above correspond to S202 to S210 in the method embodiment. The examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the content disclosed in the above method embodiment. It should be noted that the above modules, as part of the apparatus, can be executed in a computer system such as a set of computer-executable instructions.

[0136] In some embodiments, the VPU cluster and the CPU cluster interact via shared memory; wherein controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding includes: the CPU cluster decoding the target video to obtain decoded video data; the CPU cluster caching the decoded video data in the shared memory; and the CPU cluster sending a notification to the VPU cluster to enable the VPU cluster to read the decoded video data from the shared memory and perform hardware encoding processing.

[0137] In some embodiments, the CPU cluster and the data processing module interact via the same shared memory. The process of controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding includes: the CPU cluster decoding the target video to obtain decoded video data; the CPU cluster writing the decoded video data into the shared memory and notifying the data processing module; the data processing module, in response to the notification, reading the decoded video data from the shared memory and performing video enhancement processing on the decoded video data, the video enhancement processing including at least one of super-resolution reconstruction, noise reduction, or watermark addition; the data processing module writing the processed video data into the shared memory and notifying the VPU cluster; and the VPU cluster, in response to the notification, reading the processed video data from the shared memory and performing hardware encoding processing on the processed video data.

[0138] In some embodiments, the video transcoding apparatus 800 may include a second format determination module and a second control module.

[0139] The second format determination module can be used to determine if the source format and the target format are not within the range of video formats supported by the VPU cluster; the second control module can be used to control the CPU cluster to perform full-process software transcoding on the target video to convert the target video from the source format to the target format.

[0140] In some embodiments, the CPU cluster and the data processing module interact with each other through the same shared memory; wherein, the video transcoding device 800 may further include: a third judgment module, a third control module, a first memory writing module and a software encoding module.

[0141] The third judgment module can be used to determine if the source format is within the range of video formats supported by the VPU cluster and the target format is not within the range of video formats supported by the VPU cluster; the third control module can be used to control the VPU cluster to perform hardware decoding on the target video to obtain decoded video data; the first memory writing module can be used for the VPU cluster to write the decoded video data into the shared memory and notify the CPU cluster; the software encoding module can be used for the CPU cluster to read the decoded video data from the shared memory in response to the notification and perform software encoding to generate the video in the target format.

[0142] In some embodiments, controlling the CPU cluster to perform software decoding of the target video and controlling the VPU cluster to perform hardware encoding of the decoded video data includes: if the current load rate of the CPU cluster is lower than a first preset threshold and the current load rate of the VPU cluster is higher than a second preset threshold, then controlling the CPU cluster to perform software decoding and software encoding; if the current load rate of the VPU cluster is not higher than the second preset threshold, then controlling the CPU cluster to perform software decoding and controlling the VPU cluster to perform hardware encoding.

[0143] Since the functions of the device 800 have been described in detail in their respective method embodiments, they will not be repeated here.

[0144] The modules (and / or sub-modules and / or) units described in the embodiments of this disclosure can be implemented in software or in hardware. The described modules (and / or sub-modules and / or) units can also be located in a processor. The names of these modules (and / or sub-modules and / or) units do not, in some cases, constitute a limitation on the module (and / or sub-module and / or) unit itself.

[0145] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a portion of a module or program segment containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer program instructions.

[0146] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of this disclosure and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0147] Figure 9 A schematic diagram of an electronic device suitable for implementing embodiments of the present disclosure is shown. It should be noted that... Figure 9 The electronic device 900 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0148] like Figure 9 As shown, the electronic device 900 includes a central processing unit (CPU) 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage section 908 into a random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the electronic device 900. The CPU 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0149] The following components are connected to I / O interface 905: an input section 906 including a keyboard, mouse, etc.; an output section 907 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 908 including a hard disk, etc.; and a communication section 909 including a network interface card such as a LAN card, modem, etc. The communication section 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to I / O interface 905 as needed. A removable medium 911, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 910 as needed so that computer programs read from it can be installed into storage section 908 as needed.

[0150] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing computer program instructions for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 909, and / or installed from removable medium 911. When the computer program is executed by central processing unit (CPU) 901, it performs the functions defined above in the system of this disclosure.

[0151] It should be noted that the computer-readable storage medium disclosed herein may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium may be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable computer program instructions. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable storage medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. Computer program instructions contained on a computer-readable storage medium can be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0152] In another aspect, this disclosure also provides a computer-readable storage medium, which may be included in the device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable storage medium carries one or more programs that, when executed by the device, enable the device to perform the following functions: receiving a target video; parsing the target video to determine the source format and the target format to be transcoded; determining the video formats supported by the VPU cluster; if it is determined that the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster; controlling the CPU cluster to perform software decoding of the target video, and controlling the VPU cluster to perform hardware encoding of the decoded video data to complete the video transcoding.

[0153] According to one aspect of this disclosure, a computer program product or computer program is provided, comprising computer program instructions stored in a computer-readable storage medium. The computer program instructions are read from the computer-readable storage medium, and a processor executes the computer program instructions to implement the methods provided in various optional implementations of the above embodiments.

[0154] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions of the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, or portable hard drive) and includes several computer program instructions to cause an electronic device (such as a server or terminal device) to execute the method according to the embodiments of this disclosure.

[0155] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0156] It should be understood that this disclosure is not limited to the detailed structures, drawing arrangements or implementation methods shown herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A video transcoding method, characterized in that, include: Receive target video; The target video is parsed to determine its source format and target format to be transcoded. Determine the video formats supported by the VPU cluster; If it is determined that the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster; The CPU cluster is controlled to perform software decoding of the target video, and the VPU cluster is controlled to perform hardware encoding of the decoded video data to complete the video transcoding.

2. The method according to claim 1, characterized in that, The VPU cluster and the CPU cluster interact via shared memory; wherein, the CPU cluster is controlled to perform software decoding of the target video, and the VPU cluster is controlled to perform hardware encoding of the decoded video data to complete video transcoding, including: The CPU cluster decodes the target video to obtain decoded video data; The CPU cluster caches the decoded video data in the shared memory; The CPU cluster sends a notification to the VPU cluster, so that the VPU cluster reads the decoded video data from the shared memory and performs hardware encoding processing.

3. The method according to claim 1, characterized in that, The CPU cluster, the VPU cluster, and the data processing module interact via the same shared memory; wherein, the CPU cluster is controlled to perform software decoding of the target video, and the VPU cluster is controlled to perform hardware encoding of the decoded video data to complete video transcoding, including: The CPU cluster decodes the target video to obtain decoded video data; The CPU cluster writes the decoded video data into the shared memory and notifies the data processing module. In response to the notification, the data processing module reads the decoded video data from the shared memory and performs video enhancement processing on the decoded video data. The video enhancement processing includes at least one of super-resolution reconstruction, noise reduction processing, or watermark addition. The data processing module writes the processed video data into the shared memory and notifies the VPU cluster. In response to the notification, the VPU cluster reads the processed video data from the shared memory and performs hardware encoding on the processed video data.

4. The method according to claim 1, characterized in that, The method further includes: If it is determined that neither the source format nor the target format is within the range of video formats supported by the VPU cluster; The CPU cluster is controlled to perform a full-process software transcoding of the target video to convert the target video from the source format to the target format.

5. The method according to claim 1, characterized in that, The CPU cluster and the VPU cluster interact with each other via the same shared memory; wherein, the method further includes: If it is determined that the source format is within the range of video formats supported by the VPU cluster, and the target format is not within the range of video formats supported by the VPU cluster; Then, the VPU cluster is controlled to perform hardware decoding on the target video to obtain the decoded video data; The VPU cluster writes the decoded video data into the shared memory and notifies the CPU cluster. In response to the notification, the CPU cluster reads the decoded video data from the shared memory and performs software encoding to generate a video in the target format.

6. The method according to claim 1, characterized in that, Controlling the CPU cluster to perform software decoding of the target video, and controlling the VPU cluster to perform hardware encoding of the decoded video data, including: If the current load rate of the CPU cluster is lower than a first preset threshold and the current load rate of the VPU cluster is higher than a second preset threshold, then the CPU cluster is controlled to perform software decoding and software encoding. If the current load rate of the VPU cluster is not higher than the second set threshold, then the CPU cluster is controlled to perform software decoding, and the VPU cluster is controlled to perform hardware encoding.

7. A video transcoding device, characterized in that, include: The video receiving module is used to receive the target video. The transcoding format determination module is used to parse the target video to determine the source format and the target format to be transcoded. A format determination module is included to determine the video formats supported by the VPU cluster. The first format determination module is used to determine if the source format is not within the range of video formats supported by the VPU cluster, and the target format is within the range of video formats supported by the VPU cluster. The first control module is used to control the CPU cluster to perform software decoding of the target video and to control the VPU cluster to perform hardware encoding of the decoded video data to complete video transcoding.

8. An electronic device, characterized in that, include: Memory and processor; The memory is used to store computer program instructions; the processor calls the computer program instructions stored in the memory to implement the video transcoding method as described in any one of claims 1-6.

9. A computer-readable storage medium storing computer program instructions thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the video transcoding method as described in any one of claims 1-6.

10. A computer program product comprising computer program instructions stored in a computer-readable storage medium, characterized in that, When the computer program instructions are executed by the processor, they implement the method according to any one of claims 1-6.

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