High concentration thick silicon layer doping method

Abstract

This invention provides a method for high-concentration thick silicon layer doping, belonging to the field of semiconductor silicon doping technology. The invention uses a fixed closed-loop processing unit consisting of shallow junction phosphorus ion implantation, high-temperature annealing, dry oxygen thermal oxidation, and CMP oxide layer removal, repeating this cycle 9 or 10 times to prepare the doped layer. Utilizing the Si / SiO₂ interface dragging effect, the junction depth is gradually increased round by round. Combined with a segmented gradient phosphorus implantation scheme of high dose in the first three rounds and low dose in subsequent rounds, this overcomes the limitation of phosphorus solid solubility in the silicon substrate. The final result is a doped layer with a thickness of 20.1~20.2 μm and a phosphorus doping concentration ≥1×10⁻⁶. 20 This invention produces heavily doped silicon with atoms / cm³ and concentration fluctuation ≤5%. It solves the industry problems of thin doped layers, low concentration, and poor uniformity in existing processes. The entire process is compatible with existing mass production lines, and the prepared silicon substrates are widely used in power semiconductors, RF substrates, and MEMS devices, showing excellent industrialization prospects.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor silicon wafer doping technology, specifically a method for high-concentration thick silicon layer doping. Background Technology

[0002] Heavily doped silicon materials are widely used in power semiconductor devices such as IGBTs, MOSFETs, and power diodes. They are also the core substrate for radio frequency conductive substrates and conductive layers in microelectromechanical systems (MEMS). High doping concentration and thick-layer uniformity directly determine the device's conductivity, heat dissipation performance, and operational stability. Phosphorus (P), as the mainstream N-type doping element, has advantages such as fast diffusion rate, high activation efficiency, and low cost, making it the preferred doping ion for silicon-based heavy doping processes.

[0003] Existing silicon-layer phosphorus doping processes have significant technical shortcomings: traditional single-stage high-energy ion implantation processes are prone to surface lattice collapse and impurity aggregation due to high-dose implantation, resulting in poor doping uniformity. Furthermore, the effective junction depth of a single implantation is typically no more than 5 μm, making it impossible to fabricate a 20 μm thick doped layer. Conventional high-temperature thermal diffusion doping processes are limited by the solubility of silicon, with an upper limit of phosphorus doping concentration of only 5 × 10⁻⁶ at room temperature. 19 atoms / cm³, difficult to reach 10 20 Ultra-high doping requirements of atoms / cm³; epitaxial growth doping process is expensive, thick epitaxy is prone to lattice mismatch defects, and has poor applicability to mass production.

[0004] Currently, relevant doping patents in the industry have not effectively solved the above-mentioned pain points. Specifically, the following is an example: Chinese patent "A method for preparing heavily doped silicon-based thin films and the thin films obtained therefrom and their applications", patent number CN111312859A. This patent first grows a lightly doped silicon-based thin film on a substrate, and then performs high-temperature activation in an atmosphere rich in doped elements to increase the surface doping concentration. It is mainly suitable for shallow, heavily doped applications such as thin-film transistors and photovoltaics. However, its shortcomings are that it is only suitable for shallow, heavily doped thin-film layers (≤2 μm) and cannot achieve 20 μm thick layers; it relies on atmospheric diffusion, and the upper limit of the concentration is about 6 × 10⁻⁶. 19 atoms / cm³, less than 10 20 atoms / cm³; large concentration gradient in the depth direction, poor uniformity.

[0005] Chinese patent CN117966252A, entitled "Doping Device and Doping Method for Heavily Doped Semiconductor Single Crystal Silicon," designs a multi-layer bell-jar type doping device to extend the residence time of the dopant in the silicon melt, thereby improving the doping efficiency and uniformity of Czochralski silicon single crystals. It is primarily used for bulk silicon heavy doping (such as heavily doped phosphorus / boron silicon single crystals). Its limitations include the inability to form a 20 μm local high-concentration doped layer on the silicon wafer surface due to the overall bulk silicon doping; and the upper limit of phosphorus concentration is approximately 7 × 10⁻⁶ due to limitations in silicon solid solubility and segregation coefficient. 19atoms / cm 3 Furthermore, it is difficult to achieve partitioned doping with "high concentration on the surface and low concentration in the bulk".

[0006] Chinese patent CN120797198A, entitled "A Method for Preparing Silicon Epitaxial Wafers from Heavy-Doped Silicon Single Crystal Substrates and the Formed Epitaxial Wafers," uses carbon-oxygen co-doped heavy-doped silicon single crystals as substrates. After high-temperature hydrogen pretreatment, an epitaxial layer is grown to suppress impurity diffusion during epitaxy and improve the voltage withstand capability and gettering ability of the epitaxial wafer. Its shortcomings are that it is an epitaxial process, focusing on solving the problem of "substrate impurity diffusion" rather than actively preparing a 20μm high-concentration doped layer; the epitaxial layer thickness is typically ≤10μm, and the doping concentration is limited by the thermodynamics of epitaxial growth, making it difficult to exceed 8×10⁻⁶. 19 atoms / cm 3 High cost and thick epitaxial growth is prone to mismatch.

[0007] Currently, the industry lacks silicon doping preparation solutions that simultaneously achieve large thickness, ultra-high concentration, and overall uniformity. A single doping process cannot simultaneously meet the requirements of 20μm doping thickness and phosphorus doping concentration ≥10². 0 The stringent requirement of atoms / cm³. Summary of the Invention

[0008] This invention aims to overcome the problems of small doping thickness, doping concentration constrained by solid solubility, uneven longitudinal distribution of impurities, and numerous lattice defects in existing phosphorus doping processes. It provides a high-concentration thick silicon layer doping method, which combines a four-step closed-loop process, an oxide interface drag-deepening method, and a segmented gradient ion implantation method. This method overcomes the dual limitations of phosphorus solid solubility in silicon substrate and single-stage doping depth, and prepares a highly uniform, ultra-high concentration thick doped layer on the surface of a silicon wafer. The entire process is compatible with existing semiconductor mass production equipment, has low production costs, and produces a finished product with excellent lattice integrity.

[0009] This application provides the following technical solution: A method for high-concentration thick silicon layer doping, using high-purity single-crystal silicon as a substrate, involves sequentially performing phosphorus ion implantation, high-temperature annealing, thermal oxidation, and CMP chemical mechanical polishing. The method is characterized by: The four processes of shallow junction phosphorus ion implantation, high-temperature annealing, dry oxygen thermal oxidation, and oxide layer CMP removal are integrated into a closed-loop processing unit. This closed-loop unit is repeatedly executed to complete localized surface doping. Low-energy shallow junction implantation is used in each round of closed-loop processing, with a single implantation junction depth of 2.0–2.5 μm and a single-round implantation dose controlled at 1 × 10⁻⁶. 15 ~1×10 16 ions / cm 2The ion implantation dose was controlled in a segmented gradient; after each round of thermal oxidation, the surface oxide layer was completely removed by CMP, while retaining the internal doped structure; after 9 or 10 consecutive cycles, a surface phosphorus doping concentration ≥1×10⁻⁶ was obtained. 20 toms / cm 3 Thick-layer phosphorus-doped silicon with an intralayer concentration fluctuation error ≤5%.

[0010] Based on the above technical solutions, the following further technical solutions are also possible: The substrate is selected from N-type high-purity single crystal silicon, with a substrate resistivity ≥1000Ω・cm, a thickness of 300μm~350μm, and an original surface roughness of ≤0.3nm, without a native oxide layer or surface scratches.

[0011] During phosphorus ion implantation, the ion source implantation parameters are: ion implantation energy 80 keV~100 keV, beam current density 4~6 μA / cm. 2 7° tilt angle injection, cavity vacuum ≤5×10 -4 Pa; the injection dose for the first 1-3 rounds is 8 × 10⁻⁶. 15 ~1×10 16 ions / cm 2 Except for the last round, the injection dose was reduced to 5×10⁻⁶ in the remaining rounds. 15 ~6×10 16 ions / cm 2 .

[0012] The high-temperature annealing is carried out at 1100℃ under nitrogen protection, and held for 40-50 min. The heating and cooling rates are 8℃ / min and 5℃ / min, respectively, and the phosphorus impurity activation rate is ≥95%.

[0013] The dry oxidation temperature is 1050-1080℃, and the holding time is 30-35 min to generate an 80-100nm silicon dioxide layer with an oxide layer thickness tolerance of ±5nm; the single-wheel dragging junction depth is 0.8-1.0μm.

[0014] The CMP uses silica polishing slurry, with a polishing pressure of 15-18 kPa and a rotation speed of 45-50 r / min. The surface roughness after polishing is ≤0.47 nm, and polishing only removes the silica oxide layer.

[0015] A method for high-concentration thick silicon layer doping, characterized by the following specific steps: S1. The silicon wafer substrate is ultrasonically cleaned stepwise with organic solvent and deionized water, dried at 120°C, and the natural oxide layer is removed by HF for a short time. S2-S5, sequentially complete ion implantation, annealing, thermal oxidation, and CMP; S6, cycle 9 or 10 times, each round SIMS detects junction depth and concentration and dynamically corrects injection and oxidation process parameters, single round junction depth deviation is controlled ≤0.15μm; S7. After processing, hold at 650℃ for 20 minutes for low-temperature annealing to eliminate internal stress in the silicon wafer.

[0016] In S2, the initial rounds use a high dose of phosphorus injection, while subsequent rounds use a lower injection dose for supplemental doping.

[0017] Advantages of the invention: This invention provides a high-concentration thick silicon layer doping method that employs a synergistic process combining a four-step closed-loop cycle, interface stress-driven depth expansion, and segmented gradient ion implantation. This avoids lattice collapse and phosphorus impurity agglomeration defects caused by single high-dose ion implantation, while overcoming the limitation of phosphorus solid solubility in silicon substrates at room temperature, enabling stable preparation of large-thickness, ultra-high-concentration phosphorus-doped silicon. The process parameter range is reasonably covered, with 9-cycle and 10-cycle modes adaptable to the mass production needs of high-end RF and MEMS products, as well as conventional power devices such as IGBTs and MOSFETs, making it suitable for a wide range of applications. The entire process uses commercially available mass production equipment, ensuring strong process controllability. Combined with sequential SIMS online detection and dynamic parameter correction, product consistency is high. The final product exhibits significantly better doping uniformity and lattice integrity than traditional processes. The finished product undergoes low-temperature annealing to eliminate internal stress, resulting in silicon wafers free from warping and cracking, and excellent subsequent processing performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the overall closed-loop process flow of the present invention; Figure 2 This is a schematic diagram showing the change of phosphorus impurity concentration with depth during single-wheel machining. Figure 3 This is a cross-sectional view of the longitudinal concentration distribution of the doped layer in the finished silicon wafer of this invention.

[0019] Brief description of the attached diagram: Figure 1 The process sequence of "ion implantation-annealing-thermal oxidation-CMP" is visually demonstrated in both single-cycle and multi-cycle repeating. Figure 2 This reflects the trend of gradual downward shift in the oxidation depth and uniform concentration change from injection to oxidation in a single-round process. Figure 3 The results show a stable concentration distribution across the entire 20μm doped layer. Detailed Implementation

[0020] This invention provides a high-concentration thick silicon layer doping method, all of which are carried out in a Class 10,000 clean semiconductor wafer workshop, and the production equipment and testing instruments are all commercially available mass-produced models in the industry.

[0021] Processing equipment list: horizontal ion implanter, high-purity nitrogen atmosphere tube annealing furnace, dry oxygen vertical oxidation furnace, wafer CMP polishing machine; Testing equipment: SIMS secondary ion mass spectrometer (for measuring doping depth and longitudinal phosphorus concentration distribution), AFM atomic force microscope (for surface roughness), TEM transmission electron microscope (for crystal defect observation), four-probe sheet resistance meter, high-precision film thickness meter. The silicon wafers used in the experiment were commercially available N-type single-sided polished high-purity single-crystal silicon with crystal orientation... <100> Cleaning reagents: industrial grade acetone, anhydrous ethanol, electronic grade deionized water (resistivity 18.2 MΩ·cm), 5 wt% electronic grade hydrofluoric acid; ion source raw material is ultra-high purity. PH 3. Phosphine gas (purity ≥99.9999%); CMP consumables are high-purity silica neutral polishing slurry. The entire process workshop maintains a constant temperature of 23±2℃ and relative humidity of 40%~55% to avoid interference from temperature and humidity fluctuations on process stability. Intermediate sampling inspections are set up for each process, with 5 silicon wafers of the same specification tested per batch, and the average value is taken as the final test data.

[0022] Two sets of embodiments are provided, corresponding to two cycle processes of 9 rounds and 10 rounds respectively. The comparative example adopts the existing traditional doping process. The technical advantages of the present invention are demonstrated through performance testing. SIMS is used to detect the doping depth and concentration, AFM is used to detect the surface roughness, and TEM is used to observe the lattice defects.

[0023] Example 1 (9-round closed-loop cycle, optimized median process, targeting high-end RF and MEMS products) S1. Substrate pretreatment: Select: Type N <100> Single-sided polished monocrystalline silicon wafer, 320μm thick, substrate resistivity 1200Ω・cm, original surface roughness 0.27nm, free from chipping, scratches, and natural oxide layer.

[0024] Cleaning Step-by-Step Control: 1. Use an acetone water bath for 10 minutes with an ultrasonic power of 300W to remove photolithography residue and organic oil stains; 2. Dissolve residual acetone by sonication in anhydrous ethanol for 10 minutes; 3. Use ultrapure water to sonicate for 15 minutes to remove solid particulate impurities; 4. Dry the surface of the product thoroughly at a constant temperature of 120℃ for 30 minutes in a forced-air drying oven to completely dry the adsorbed water. 5. Immerse in 5% HF at room temperature for 15 seconds to chemically remove the natural oxide layer, then rinse quickly with ultrapure water for 10 seconds for high purity. N 2 (5N) Oblique blowing drying, then transferred to a sealed clean wafer box for later use. After pretreatment, one wafer was randomly selected and a film thickness gauge was used to confirm that there was no oxide layer residue.

[0025] S2, Phosphate ion shallow junction implantation: The silicon wafer is fixed in place by a quartz fixture and fed into the ion implanter, with the cavity continuously evacuated to 4×10⁻⁶. -4 After holding the pressure at Pa for 30 minutes, confirm that the leakage rate of the cavity meets the standard. PH 3 Ion source, implantation energy 100keV, beam current density 6μA / cm², 7° tilt angle spin implantation, uniform wafer rotation to ensure uniform implantation across the entire surface, and measured dose uniformity error of 1.2% for a single batch.

[0026] Gradient dosing rule: Single injection dose of 1×10 in rounds 1-3 16 ions / cm 2 Phosphorus atoms are rapidly enriched in the near-surface layer; the concentration decreases to 6 × 10⁻⁶ in rounds 4–9. 15 ions / cm², low-rate doping suppresses phosphorus supersaturation precipitation; single-round shallow junction injection measured effective junction depth of 2.5μm.

[0027] After each injection cycle, one sample is taken for SIMS single-point detection, and the initial phosphorus concentration on the surface is recorded.

[0028] S3, 1100℃ nitrogen-protected high-temperature annealing: The wafer is placed into a quartz boat and pushed into a tube annealing furnace, with 5N high-purity oxygen flowing through it throughout the process. N 2. Gas flow rate 2L / min; programmed temperature rise: room temperature → 8℃ / min to 1100℃, hold at constant temperature for 50min; after holding, cool down at a uniform rate of 5℃ / min to room temperature.

[0029] Function: Repairs lattice vacancies and interstitial atomic defects caused by ion implantation, and activates phosphorus impurities embedded in the lattice. The measured phosphorus electrical activation rate is 96.2%. After annealing, random samples are taken, and the sheet resistance is roughly measured with four probes. Abnormal data are used to fine-tune the implantation parameters for the next round.

[0030] S4, Deep advancement of dry oxygen thermal oxidation junction: After annealing, the wafers are transferred to a vertical dry oxygen oxidation furnace with a dry oxygen inlet flow rate of 1.5 L / min and an oxidation temperature of 1080℃, held at this temperature for 30 min. The resulting SiO2 film has an average thickness of 100 nm, with a single oxide layer thickness fluctuation of ±3 nm, meeting a process tolerance of ±5 nm. Due to the interfacial drag stress generated by the volume expansion at the Si / SiO2 interface, phosphorus impurities are carried into the silicon substrate, resulting in a single junction depth reduction of 1.0 μm.

[0031] Dynamic control details: For each round of SIMS measured junction depth, if the single-round advance depth is less than 0.9μm, the oxidation and heat preservation time for the next round will be increased by 2min; if it is greater than 1.1μm, it will be shortened by 2min. The single-round junction depth advance error for the entire process is ≤0.12μm.

[0032] S5, CMP chemical mechanical polishing to remove oxide layer: The CMP equipment uses polyurethane polishing pads, a neutral silica polishing slurry, a polishing pressure of 18 kPa, and a rotary table speed of 50 r / min. The process objective is to remove only the entire SiO2 oxide layer, retaining the underlying doped silicon layer. After polishing, the wafer is rinsed with ultrapure water for 3 minutes on both sides and then dried with nitrogen. AFM sampling inspection shows a surface roughness of 0.35 nm, with no over-polishing loss of doped silicon.

[0033] S6, 9-wheel closed-loop control: Repeat steps S2 through S5 for a total of 9 cycles. A SIMS profile test must be performed after each cycle to fine-tune the implantation dose for the next cycle based on the longitudinal concentration distribution, preventing excessive local enrichment of phosphorus in multilayered stacks. After 9 cycles, the total doped thickness is 20.2 μm.

[0034] S7. Low-temperature stress-relieving annealing of finished products: After all cycles are completed, the wafer is annealed at 650°C in a nitrogen atmosphere for 20 minutes, and then slowly cooled to room temperature in the furnace to release the internal thermal stress of the silicon wafer caused by multiple high and low temperature cycles, thus preventing warping and cracking in subsequent processing and obtaining a high-concentration thick-layer phosphorus-doped single-crystal silicon substrate without voids, dislocations and impurity agglomeration defects.

[0035] Average of five tests on finished products 1. SIMS: Doped layer 20.2 μm, phosphorus concentration 1.05 × 10⁻⁶ 20 ~1.12×10 20 atoms / cm 3 The concentration fluctuated by 3.2%. 2. AFM: Surface roughness 0.42nm; 3. TEM: The doped region is free of voids, dislocations, and phosphorus agglomerates; 4. Four probes: The surface sheet resistance is uniform, and the substrate resistivity is 1195 Ω·cm; 5. Appearance: The wafer is free from warping and edge chipping.

[0036] Example 2 (10 closed-loop cycles, lower limit of parameters, mass production solution for conventional power devices IGBT / MOSFET) S1. Substrate pretreatment: N-type silicon wafer: 300 μm thickness, 1020 Ω·cm resistivity, and 0.29 nm original roughness; the entire process of cleaning, drying, and HF deoxidation, including operating conditions, time, and reagent specifications, is completely consistent with Example 1.

[0037] S2, Ion Implantation: Cavity vacuum 4.8 × 10 -4 Pa, PH 3 Ion source, implantation energy 80 keV, beam current density 4 μA / cm 2Inject at a 7° tilt angle; 1-3 injection cycles with a dose of 8×10⁻⁶. 15 ions / cm 2 4 to 10 rounds, 5 x 10 15 ions / cm 2 The depth of each injection was 2.0 μm. Samples were taken after each injection to monitor the initial phosphorus content of the surface layer.

[0038] S3, High-temperature annealing: N 2. Flow rate 2L / min, heat preservation at 1100℃ for 40min, heating and cooling rates 8℃ / min and 5℃ / min, phosphorus impurity activation rate 95.1%.

[0039] S4, Dry Oxygen Thermal Oxidation: Dry oxygen temperature 1050℃, holding time 35min, SiO2 thickness 80nm, single ring junction depth subsidence 0.8μm, oxide layer thickness error ≤4nm; oxidation time fine-tuned based on SIMS measured data, single ring junction depth deviation ≤0.13μm.

[0040] S5, CMP grinding Grinding pressure 15 kPa, rotation speed 45 r / min, silica polishing slurry, roughness after polishing 0.47 nm.

[0041] S6, S7, Cyclic and Stress-Relief Annealing: Ten consecutive closed-loop cycles were performed, with each cycle using SIMS detection to dynamically correct process parameters. Finally, a 20-minute low-temperature stress relief process at 650°C was completed to obtain a high-concentration, thick-layer phosphorus-doped single-crystal silicon substrate free of voids, dislocations, and impurity agglomeration defects.

[0042] Average values ​​of finished product inspections: The doping thickness is 20.1 μm, and the phosphorus concentration is 9.8 × 10⁻⁶. 19 ~1.06×10 20 atoms / cm³, average concentration ≥1×10 20 atoms / cm 3 The concentration fluctuated by 4.5%, with no lattice defects, meeting the standards for general power semiconductor substrates.

[0043] Comparative Example 1: Traditional single-stage high-energy ion implantation: Using a 320μm, 1200Ω·cm silicon wafer of the same specifications, with an implantation energy of 200keV, a single, one-time implantation, the total dose is 1×10⁻⁶. 16 ions / cm²; annealing at 1100℃ for 50 minutes only, without oxidation, CMP, or cyclic processes.

[0044] Detection: Effective doping thickness 4.2 μm; surface concentration 1.2 × 10⁻⁶ 20 atoms / cm3 Only 3.5 × 10 at a depth of 5 μm 19 atoms / cm 3 The concentration fluctuated by 70.8%; TEM showed a large number of lattice voids and phosphorus agglomerates.

[0045] Comparative Example 2: Gas-phase thermal diffusion from a conventional high-temperature phosphorus source: Using the same substrate silicon wafer, the temperature is maintained at 1150℃ for 120 minutes in a phosphorus source atmosphere, without ion implantation, oxidation, or CMP processes.

[0046] Testing revealed a maximum doping thickness of 12 μm and a maximum phosphorus concentration of 4.8 × 10⁻⁶. 19 atoms / cm 3 Impurities are severely agglomerated, failing to reach ≥1×10 20 atoms / cm 3 index.

[0047] Overall test summary: Comparative examples and comparative data show that the innovative four-step closed-loop cycle combined with interface dragging for depth expansion and two-stage gradient phosphorus injection synergistic process of this invention overcomes the dual limitations of silicon-phosphorus solid solubility and single injection depth, stably preparing 20.1–20.2 μm silicon with phosphorus ≥1×10⁻⁶. 20 atoms / cm 3 Highly uniform heavy doping of silicon with concentration fluctuation ≤5%; the entire process uses mature mass production equipment, and the product's lattice integrity and doping uniformity are significantly better than existing mainstream processes, making industrialization highly feasible.

Claims

1. A method for high-concentration thick silicon layer doping, using high-purity single-crystal silicon as a substrate, and sequentially performing phosphorus ion implantation, high-temperature annealing, thermal oxidation, and CMP chemical mechanical polishing, characterized in that: The four processes of shallow junction phosphorus ion implantation, high-temperature annealing, dry oxygen thermal oxidation, and oxide layer CMP removal are integrated into a closed-loop processing unit. This closed-loop unit is repeatedly executed to complete localized surface doping. Low-energy shallow junction implantation is used in each round of closed-loop processing, with a single implantation junction depth of 2.0–2.5 μm and a single-round implantation dose controlled at 1 × 10⁻⁶. 15 ~1×10 16 ions / cm 2 The ion implantation dose is controlled in segments with a gradient; after each round of thermal oxidation, the surface oxide layer is completely removed by CMP, while the internal doped structure is preserved. After 9 or 10 consecutive cycles, a surface phosphorus doping concentration ≥1×10⁻⁶ was obtained. 20 toms / cm 3 Thick-layer phosphorus-doped silicon with an intralayer concentration fluctuation error ≤5%.

2. The method for high-concentration thick silicon layer doping according to claim 1, characterized in that: The substrate is selected from N-type high-purity single crystal silicon, with a substrate resistivity ≥1000Ω・cm, a thickness of 300μm~350μm, and an original surface roughness of ≤0.3nm, without a native oxide layer or surface scratches.

3. The method for high-concentration thick silicon layer doping according to claim 1, characterized in that: During phosphorus ion implantation, the ion source implantation parameters are: ion implantation energy 80 keV~100 keV, beam current density 4~6 μA / cm. 2 7° tilt angle injection, cavity vacuum ≤5×10 -4 Pa; the injection dose for the first 1-3 rounds is 8 × 10⁻⁶. 15 ~1×10 16 ions / cm 2 Except for the last round, the injection dose was reduced to 5×10⁻⁶ in the remaining rounds. 15 ~6×10 16 ions / cm 2 .

4. The method for high-concentration thick silicon layer doping according to claim 1, characterized in that: The high-temperature annealing is carried out at 1100℃ under nitrogen protection, and held for 40-50 min. The heating and cooling rates are 8℃ / min and 5℃ / min, respectively, and the phosphorus impurity activation rate is ≥95%.

5. The high-concentration thick silicon layer doping method according to claim 1, characterized in that: The dry oxidation temperature is 1050-1080℃, and the holding time is 30-35 min to generate an 80-100nm silicon dioxide layer with an oxide layer thickness tolerance of ±5nm; the single-wheel dragging junction depth is 0.8-1.0μm.

6. The method for high-concentration thick silicon layer doping according to claim 1, characterized in that: The CMP uses silica polishing slurry, with a polishing pressure of 15-18 kPa and a rotation speed of 45-50 r / min. The surface roughness after polishing is ≤0.47 nm, and polishing only removes the silica oxide layer.

7. The method for high-concentration thick silicon layer doping according to claim 1, characterized in that: Specific steps: S1. The silicon wafer substrate is ultrasonically cleaned stepwise with organic solvent and deionized water, dried at 120°C, and the natural oxide layer is removed by HF for a short time. S2-S5, sequentially complete ion implantation, annealing, thermal oxidation, and CMP; S6, cycle 9 or 10 times, each round SIMS detects junction depth and concentration and dynamically corrects injection and oxidation process parameters, single round junction depth deviation is controlled ≤0.15μm; S7. After processing, hold at 650℃ for 20 minutes for low-temperature annealing to eliminate internal stress in the silicon wafer.

8. The method for high-concentration thick silicon layer doping according to claim 7, characterized in that: In S2, the initial rounds use a high dose of phosphorus injection, while subsequent rounds use a lower injection dose for supplemental doping.

Images