A method for packaging a silicon photonic chip with thermal-induced deformation regulation

Abstract

The application discloses a kind of thermally induced deformation regulation and control silicon optical chip packaging methods, belong to semiconductor packaging and optoelectronic communication technical field.It includes: obtaining the packaging substrate including flexible compensation area, rigid fixed area and thermal isolation groove;Heating electrode array and double material strain layer are set in flexible compensation area, and temperature sensor is set in rigid fixed area;Silicon optical chip is fixed to the surface of rigid fixed area, and preset bias voltage is input to heating electrode array, so that flexible compensation area generates initial bending deformation state;In the initial bending deformation state, optical fiber assembly is solidified and connected to the end of flexible compensation area, and initial optical coupling link is constructed.The application obtains real-time temperature by temperature sensor, dynamically adjusts driving voltage to change the curvature of flexible compensation area, and drives optical fiber assembly to generate alignment displacement.Active thermal deformation feedback adjustment means is used, which can effectively offset the coupling offset caused by temperature drift and improve the stability of optical coupling link.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor packaging and optoelectronic communication technology, and in particular to a method for packaging silicon photonic chips with thermal deformation regulation. Background Technology

[0002] Currently, with the rapid development of optical communication and high-performance computing, silicon photonics chips are widely used due to their high bandwidth and low power consumption advantages. However, during the high-speed, high-frequency operation of silicon photonics modules, their internal core components generate a large amount of heat, inevitably causing thermal expansion or contraction of the chip and its underlying packaging components. This microscopic deformation induced by thermal stress can easily disrupt the submicron-level optical coupling alignment between the silicon photonics chip and external fiber optic components, leading to severe attenuation and loss of optical power, reducing the stability of the entire communication link and data transmission efficiency. Traditional packaging solutions typically employ static high-precision alignment and passive physical fixing processes, overly relying on special packaging materials with low thermal expansion coefficients, or forcibly attaching large-volume heat sinks and thermoelectric coolers to the outside of the chip to maintain a constant temperature environment. This not only increases the packaging size, power consumption, and manufacturing cost, but also fails to fundamentally eliminate the problem of thermal mismatch between materials under extreme operating conditions.

[0003] In related technologies, Chinese invention patent CN120507844B discloses a packaging structure and packaging method for an optical module and an optical chip, including: an independently deployed receiver component, a stepped metal heat sink, and a silicon-based optical interconnect component mounted on the stepped metal heat sink; the silicon-based optical interconnect component includes a laser, a silicon optical beam splitter, a lens group, a light transmittance compensation pad, a silicon optical modulator, and an optical fiber array; wherein the light-emitting end face of the laser and the incident end face of the silicon optical beam splitter form a coplanar coupling in the direction perpendicular to the optical axis; the silicon optical beam splitter and at least some of the collimating lenses in the lens group are fixed on the light transmittance compensation pad; this scheme attempts to achieve displacement compensation through material synergistic deformation under temperature fluctuation conditions by matching the thermal expansion coefficients of the light transmittance compensation pad and the silicon optical beam splitter.

[0004] However, the aforementioned technologies are essentially limited to a passive material-coordinated anti-misalignment design, which has application limitations. On the one hand, relying solely on the pre-defined thermal expansion properties of materials for passive matching limits the deformation direction and amplitude to the materials themselves, making it impossible to overcome physical limitations and achieve flexible bidirectional active compensation. This makes it difficult to cope with the complex and dynamically changing non-uniform thermal fields generated by high-speed chip operation. On the other hand, after long-term thermal cycling of the optical module, the encapsulation colloid and component materials will undergo irreversible aging fatigue and minor stiffness loss. Once this statically solidified coupling point undergoes permanent misalignment, the system itself has no ability to actively sense and correct the misalignment. Due to the lack of closed-loop feedback and active actuation adjustment mechanisms for temperature sensing, this solution cannot maintain the optimal optical power coupling point throughout the device's entire lifespan, directly restricting the long-term reliability of silicon photonic chips under high-density integration and extreme thermal environments. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a silicon photonics chip packaging method for thermal deformation control. By employing a dual-material strain layer in a flexible compensation region and combining it with closed-loop feedback from a temperature sensor to adjust a preset bias voltage, real-time bidirectional automatic compensation of the coupling displacement between the optical fiber and the silicon photonics chip can be achieved.

[0006] The above objectives can be achieved through the following approach:

[0007] A method for packaging silicon photonics chips with thermally induced deformation control includes obtaining a packaging substrate, the packaging substrate including a flexible compensation region, a rigid fixing region, and a thermal isolation groove; setting a heating electrode array and a dual-material strain layer in the flexible compensation region, and setting a temperature sensor in the rigid fixing region; fixing the silicon photonics chip on the surface of the rigid fixing region, and inputting a preset bias voltage to the heating electrode array to generate an initial bending deformation state in the flexible compensation region; in the initial bending deformation state, curing and connecting an optical fiber assembly to the end of the flexible compensation region to construct an initial optical coupling link.

[0008] Optionally, obtaining the packaging substrate includes: forming a cantilever structure as the flexible compensation area in the edge region of the packaging substrate by deep silicon etching, and forming the rigid fixing area in the central region; etching a through hole between the flexible compensation area and the rigid fixing area, and filling the through hole with a heat-insulating medium material to form the thermal isolation groove.

[0009] Optionally, the step of setting the heating electrode array and the dual-material strain layer in the flexible compensation region includes: depositing the heating electrode array on the surface of the flexible compensation region; and sequentially depositing a first metal thin film and a second dielectric thin film above the heating electrode array to form a dual-material strain layer, wherein the thermal expansion coefficient of the first metal thin film is greater than that of the second dielectric thin film.

[0010] Optionally, the step of curing the optical fiber assembly to the end of the flexible compensation region to construct the initial optical coupling link includes: adjusting the spatial pose of the optical fiber assembly to a preset optical power coupling point while maintaining the preset bias voltage; at the preset optical power coupling point, using UV-curable adhesive to cure and connect the end face of the optical fiber assembly to the end of the flexible compensation region to form the initial optical coupling link.

[0011] Optionally, the method further includes: acquiring the real-time temperature of the packaging area through the temperature sensor; generating dynamic adjustment parameters for the preset bias voltage based on the preset deformation control mapping relationship and the real-time temperature; outputting a driving voltage to the heating electrode array according to the dynamic adjustment parameters; adjusting the curvature of the flexible compensation area; and driving the optical fiber assembly to generate an alignment displacement relative to the silicon photonic chip.

[0012] Optionally, the preset deformation control mapping relationship includes: driving the silicon photonic chip to heat up, obtaining the offset coordinates of the optical fiber component relative to the silicon photonic chip to generate a base distortion feature; applying a step voltage increment to the preset bias voltage, obtaining the displacement vector of the flexible compensation region to generate an actuation offset feature; and fitting and generating a deformation control mapping relationship between the preset bias voltage and the alignment displacement based on the base distortion feature and the actuation offset feature.

[0013] Optionally, obtaining the real-time temperature of the packaging area through the temperature sensor includes: obtaining the analog temperature electrical signal output by the temperature sensor; determining the thermal crosstalk noise threshold according to the preset thermal damping parameters of the thermal isolation groove; and filtering the analog temperature electrical signal using the thermal crosstalk noise threshold to obtain discrete temperature values, i.e., the real-time temperature.

[0014] Optionally, the step of outputting a driving voltage to the heating electrode array according to the dynamic adjustment parameter includes: when the dynamic adjustment parameter indicates positive compensation, outputting a driving voltage higher than the preset bias voltage to the heating electrode array; and when the dynamic adjustment parameter indicates negative compensation, outputting a driving voltage lower than the preset bias voltage to the heating electrode array.

[0015] Optionally, the method further includes: obtaining the cumulative number of heating cycles of the dual-material strain layer; calculating a fatigue compensation coefficient based on the cumulative number of heating cycles and a preset material stiffness loss parameter; and using the fatigue compensation coefficient to correct the deformation control mapping relationship.

[0016] Compared with the prior art, the present invention has the following advantages:

[0017] 1. By dividing the packaging substrate into a flexible compensation region and a rigid fixing region, and setting a heating electrode array and a dual-material strain layer in the flexible compensation region, an active thermal deformation control structure was constructed. This scheme can dynamically adjust the curvature of the flexible compensation region according to the real-time temperature, driving the optical fiber component to generate alignment displacement relative to the silicon photonic chip. This active feedback mechanism effectively counteracts the thermal expansion displacement caused by the high-speed operation of the chip, improving the transmission stability and coupling efficiency of the optical coupling link in complex thermal environments.

[0018] 2. Before curing the optical fiber assembly, a preset bias voltage is applied to induce an initial bending deformation in the flexible compensation region. This pre-bias design provides bidirectional flexibility for subsequent alignment adjustments, allowing for flexible positive or negative compensation based on dynamic adjustment parameters. This bidirectional adjustment capability breaks the physical limitation that traditional thermally strained materials can only expand or contract in one direction, expanding the deformation compensation range of the encapsulation module.

[0019] 3. Noise filtering and fatigue correction algorithms are introduced to ensure long-term reliability. On the one hand, the temperature signal is filtered by the preset thermal damping parameters of the thermal isolation groove, effectively blocking thermal crosstalk noise interference in the core area of ​​the chip. On the other hand, the cumulative heating cycle count of the dual-material strain layer can be obtained, and the deformation control mapping relationship can be dynamically corrected using the fatigue compensation coefficient. This enables the packaged component to maintain a very high degree of displacement compensation after long-term thermal cycling aging, extending the service life of the device.

[0020] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic flowchart of a silicon photonics chip packaging method for thermal deformation regulation according to an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the preset deformation control mapping relationship curve of a silicon photonic chip packaging method for thermal deformation regulation according to an embodiment of the present invention.

[0024] Figure 3 A schematic diagram of the thermal crosstalk noise dead zone filtering curve based on preset thermal damping parameters in a silicon photonic chip packaging method with thermal deformation control according to an embodiment of the present invention.

[0025] Figure 4 A schematic diagram of material aging and fatigue compensation curves based on cumulative heating cycles in a silicon photonics chip packaging method for thermal deformation regulation according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Reference Figure 1 One embodiment of the present invention proposes a silicon photonic chip packaging method for thermal deformation control. By setting a dual-material strain layer in the flexible compensation region and combining it with closed-loop feedback from a temperature sensor to adjust the preset bias voltage, real-time bidirectional automatic compensation of the coupling displacement between the optical fiber and the silicon photonic chip can be achieved.

[0028] The method described in this embodiment specifically includes:

[0029] A packaging substrate is obtained, the packaging substrate including a flexible compensation area, a rigid fixing area and a thermal isolation groove;

[0030] A heating electrode array and a dual-material strain layer are provided in the flexible compensation region, and a temperature sensor is provided in the rigid fixing region.

[0031] The silicon photonic chip is fixed to the surface of the rigid fixing area, and a preset bias voltage is input to the heating electrode array to generate an initial bending deformation state in the flexible compensation area.

[0032] In the initial bending deformation state, the optical fiber assembly is fixedly connected to the end of the flexible compensation area to construct the initial optical coupling link.

[0033] Specifically, a packaging substrate with a functional partition design is used. This substrate is spatially divided into a flexible compensation area, a rigid fixing area, and a thermal isolation groove for thermal blocking. Within the flexible compensation area, a deformation actuation structure is constructed by integrating a heating electrode array and a dual-material strain layer with different coefficients of thermal expansion. A temperature sensor is placed in the rigid fixing area for closed-loop monitoring. During the packaging process, a preset bias voltage is input to the heating electrodes to force controlled initial bending deformation in the flexible compensation area. Under this specific deformation state, the fiber optic component and the end of the flexible area are precisely bonded, thus establishing an initial optical coupling link with dynamic adjustment capabilities. By introducing an active thermally induced deformation compensation mechanism, the optical link mismatch problem caused by thermal stress in silicon photonics chips under complex thermal environments is effectively solved, improving the accuracy and stability of optical coupling. The initial bending state generated by the preset bias voltage provides bidirectional displacement adjustment margins, enabling flexible handling of alignment deviations in different directions. The thermal isolation groove design effectively suppresses thermal crosstalk during the actuation process, ensuring the temperature stability of the chip core area; combined with the compensation algorithm for material fatigue correction, it ensures the reliability and alignment accuracy of the package structure under long-term thermal cycling conditions.

[0034] Optionally, obtaining the packaging substrate includes:

[0035] A cantilever structure is formed at the edge region of the packaging substrate by deep silicon etching as the flexible compensation region, and a rigid fixing region is formed in the central region.

[0036] A through hole is etched between the flexible compensation area and the rigid fixing area, and the through hole is filled with a heat-insulating medium material to form the thermal isolation groove.

[0037] Specifically, high-purity single-crystal silicon is selected as the substrate material. The topological boundary between the flexible compensation region and the rigid fixing region is defined on the substrate surface using photolithography. Subsequently, deep silicon etching is used to anisotropically etch the edge region of the substrate. By precisely controlling the etching rate and time, the edge region is thinned to form a cantilever structure with specific mechanical elasticity, serving as the flexible compensation region. The unetched, thicker central region forms the rigid fixing region with higher mechanical strength. At the boundary between the flexible compensation region and the rigid fixing region, a mask is used to redefine the location of the thermal isolation trench. A second deep silicon etching process forms a micro-through-hole penetrating the entire thickness of the substrate. Finally, chemical vapor deposition or vacuum filling is used to fill the through-hole with a low thermal conductivity insulating medium, ultimately forming the thermal isolation trench. This isolation trench physically blocks the large-scale conduction of heat generated by the silicon photonics chip to the flexible compensation region. The quantitative evaluation of the thermal barrier capability is expressed by the following formula:

[0038]

[0039] in the formula d represents the thermal resistance of the thermal isolation trench, and d represents the thickness of the isolation trench in the direction of heat conduction, i.e., the etching depth. Let W be the equivalent thermal conductivity of the filling material, and let H be the width and cross-sectional height of the thermal isolation groove, respectively.

[0040] Deep silicon etching is an anisotropic fabrication process that uses high-density plasma to prepare high aspect ratio microstructures on semiconductor substrates. The cantilever structure is a beam-like geometry with one end fixed and the other suspended, utilizing material thickness reduction to achieve controlled elastic deformation. The flexible compensation region is an actuation function area within the packaging structure that possesses thermally induced deformation freedom and is used to support the fiber optic end. The rigid fixing region is a relatively thick and structurally stable area within the substrate, specifically designed for mounting silicon photonic chips. The thermal isolation trench is a heat flow impediment structure composed of through-holes and an insulating medium. The insulating medium material is a polymer or oxide-based material with a thermal conductivity far lower than that of single-crystal silicon.

[0041] For example, a single-crystal silicon substrate with a thickness of 400 μm is selected, and deep silicon etching is performed using the Bosch process. The number of etching cycles is set so that the remaining thickness of the cantilever structure is 50 μm, forming a flexible compensation region with a length of 2000 μm. A through-hole with a width of 100 μm, a height of 350 μm, and a lateral length of 500 μm is etched at the interface. The thermal resistance material used is polyimide with a thermal conductivity of 0.15 W / mK, chosen because polyimide possesses good high-temperature packaging stability while meeting thermal insulation requirements. The thermal resistance of this thermal isolation trench is derived using the thermal resistance calculation formula. Under extreme operating conditions where the chip generates 2W of heat, the temperature rise to the flexible compensation area is limited to a small range due to the presence of this high thermal resistance structure, ensuring that the actuation accuracy does not fluctuate with the chip's workload.

[0042] Optionally, the step of setting the heating electrode array and the dual-material strain layer in the flexible compensation region includes:

[0043] The heating electrode array is deposited on the surface of the flexible compensation region;

[0044] A first metal thin film and a second dielectric thin film are sequentially deposited above the heating electrode array to form a dual-material strain layer, wherein the thermal expansion coefficient of the first metal thin film is greater than that of the second dielectric thin film.

[0045] Specifically, the surface of the cantilever beam in the flexible compensation area is cleaned, and a 20-nanometer-thick titanium adhesion layer is deposited on the surface using magnetron sputtering. Subsequently, a 200-nanometer-thick platinum layer is deposited as the conductive substrate. A microscale heating electrode array with a serpentine distribution is then formed using photolithography and lift-off processes. Above the heating electrode array, a first metal thin film is deposited using electron beam evaporation, employing aluminum, a metal with a high coefficient of thermal expansion, with its deposition thickness precisely controlled at 1000 nanometers. After metal deposition, a second dielectric thin film is grown in situ on the surface of this metal layer using plasma-enhanced chemical vapor deposition, employing silicon nitride, a material with a low coefficient of thermal expansion and good mechanical properties, also with a growth thickness of 1000 nanometers. This creates a dual-material strain layer structure with a longitudinal thermal stress gradient in space. When a bias voltage is applied to the heating electrode array, the platinum electrodes generate heat through the Joule heating effect. This heat is conducted to the strain layer, where the first metal film and the second dielectric film undergo unequal linear expansion at the same temperature rise. This results in unbalanced compressive stress within the dual-material strain layer, which in turn drives the cantilever structure of the flexible compensation region to bend in a controlled manner. The degree of bending is determined by curvature calculation, the formula of which is as follows:

[0046]

[0047] in , where is the curvature of the cantilever beam, w is the equivalent Young's modulus of the material, and h is the film thickness. This represents the difference in the coefficients of thermal expansion of the two materials. The temperature rise caused by heating.

[0048] The heating electrode array is a combination of miniature heating units that utilize the high resistivity of platinum to convert electrical energy into Joule heat, providing controlled heat source excitation for the deformation layer. The dual-material strain layer is a composite thin-film structure composed of two materials with significantly different coefficients of thermal expansion bonded together, converting thermal energy into mechanical kinetic energy using the principle of thermal stress mismatch. The first metal thin film is an active layer with a higher coefficient of thermal expansion located below the strain layer; metals such as aluminum or copper are typically chosen to obtain a larger deformation driving force. The second dielectric thin film is a constraint layer with a lower coefficient of thermal expansion located above the strain layer; it acts as a rigid framework to restrict the free expansion of the metal layer, forcing the structure to bend. Deposition is a microfabrication process that grows thin films of specific functional materials on the substrate surface using physical or chemical means.

[0049] For example, the cantilever beam with a flexible compensation zone has a length of 500 micrometers. Aluminum is selected as the first metal film, and its Young's modulus is... The coefficient of thermal expansion is 70 gigapascals. The modulus is 23.1 times 10 to the power of negative 6 per Kelvin; silicon nitride is selected as the second dielectric film, and its Young's modulus is... The coefficient of thermal expansion is 160 gigapascals. It is 2.8 times 10 to the power of -6 per Kelvin. This sets the aluminum layer thickness. With silicon nitride layer thickness All are 1.0 micrometers. When the ambient temperature rises... Calculate curvature at 50 Kelvin. The derivation process is as follows: First, calculate the ratio of material parameters and the thickness ratio. Modulus ratio Based on the simplified parameter terms, the denominator is calculated as follows: Substituting the values ​​into the equation yields the curvature. per meter. According to the cantilever beam deflection formula, the alignment displacement generated at the end is... This translates to an offset compensation of approximately 50.8 micrometers. This displacement is sufficient to cover the spot offset of up to 30 micrometers caused by thermal mismatch in conventional silicon photonics packaging, ensuring that the optical power coupling efficiency remains locked at the preset threshold corresponding to the maximum value under temperature fluctuations of 50 Kelvin.

[0050] Optionally, the step of fixing the optical fiber assembly to the end of the flexible compensation region to construct the initial optical coupling link includes:

[0051] While maintaining the preset bias voltage, adjust the spatial pose of the optical fiber assembly to the preset optical power coupling point;

[0052] At the preset optical power coupling point, the end face of the optical fiber assembly is cured and connected to the end of the flexible compensation area using UV-curable adhesive to form an initial optical coupling link.

[0053] Specifically, before the fiber optic assembly is solidified and connected, a preset bias voltage is continuously input to the heating electrode array through an external high-precision constant voltage source, causing the flexible compensation area to generate and maintain a stable initial bending deformation state. Under this thermodynamic steady state, a multi-degree-of-freedom high-precision automatic alignment platform is activated to clamp the fiber optic assembly. Simultaneously, the light-emitting port of the silicon photonic chip is connected to a power monitoring system, driving the automatic alignment platform to perform micro-step scanning in three-dimensional space, and real-time acquisition of the light signal intensity received at the fiber end face. When the monitored optical power efficiency reaches its maximum value, the spatial coordinates of the current automatic alignment platform are locked; these coordinates correspond to the preset optical power coupling point. At this point, the coupling efficiency calculation and evaluation process is introduced, with the specific formula as follows:

[0054]

[0055] in the formula Represents the real-time monitored power efficiency of the coupled optical system. This represents the peak coupling efficiency under ideal, unbiased conditions. and These represent the relative displacement deviations of the fiber optic assembly relative to the silicon photonic chip in the horizontal and vertical directions, respectively. This represents the equivalent mode field radius of the light beam. Because it is located at the preset optical power coupling point, the displacement deviation approaches zero, achieving maximum real-time efficiency. After locking the coordinates, a suitable amount of UV-curable adhesive is applied using a high-precision dispensing machine to the tiny gap between the fiber optic assembly end face and the flexible compensation area end. Once the adhesive has uniformly filled the gap due to capillary action, the UV curing lamp is turned on to irradiate the adhesive at a fixed point. During irradiation, the bias voltage and alignment platform position are strictly maintained until the adhesive is completely cross-linked and cured.

[0056] The preset bias voltage is a reference electrical signal pre-set during the packaging stage and input to the electrode array to induce a specific initial deflection in the cantilever beam. The fiber optic assembly is the optical medium carrier and its protective housing responsible for guiding optical signals into or out of the chip. Spatial pose is a comprehensive representation of the object's absolute position coordinates and attitude angles in a three-dimensional Cartesian coordinate system. The preset optical power coupling point is a spatial relative position determined by an automatic optimization algorithm that maximizes the mode matching degree between the chip waveguide and the fiber endface while minimizing optical signal transmission loss. The UV-curable adhesive is a photosensitive adhesive that can rapidly undergo a polymerization and cross-linking reaction under specific wavelengths of light, thereby achieving high-strength adhesion at the material interface.

[0057] For example, the preset bias voltage input to the platinum heating electrode array is set to 2.5 volts. This voltage value is set based on the system design requirement that the flexible compensation area has a mechanical margin of half the total effective displacement stroke to uniformly cope with positive and negative temperature drift. Measurements using a white light interferometer show that the initial downward bending displacement of the cantilever beam in the flexible compensation area under a 2.5-volt bias voltage is 25 micrometers. Maintaining this constant voltage, the alignment algorithm is activated for optimization, with a displacement scan step set to 0.1 micrometers. The measured equivalent mode field radius of the silicon photonic chip waveguide is... The ideal peak coupling efficiency is calibrated to be 5.0 micrometers. The value is 0.80. During this optimization process, if the sensor measures a horizontal displacement deviation at a certain instant... The vertical deviation is 1.0 micrometer. The value is 0.5 micrometers. The real-time coupling efficiency is derived. The specific process is as follows The value was determined not to have reached its peak, and the coordinates were fine-tuned until the deviation approached zero and the measured efficiency stabilized at 0.80. At this point, the preset optical power coupling point was confirmed. Subsequently, 0.5 microliters of epoxy-based UV-curable adhesive were dropped into the assembly gap of 100 micrometers, and a point light source with a wavelength of 365 nanometers was used to irradiate the area with a light intensity of 500 milliwatts per square centimeter for 10 seconds. The light intensity and time parameters were set to ensure that the cumulative energy absorbed by the adhesive reached 5000 millijoules per square centimeter, thus fully meeting the energy threshold for complete cross-linking of this type of epoxy resin, ultimately forming a steady-state initial optical coupling link with extremely low mechanical loss.

[0058] Optionally, the method further includes:

[0059] The real-time temperature of the packaging area is obtained through the temperature sensor, and dynamic adjustment parameters for the preset bias voltage are generated according to the preset deformation control mapping relationship and the real-time temperature.

[0060] According to the dynamic adjustment parameters, a driving voltage is output to the heating electrode array to adjust the curvature of the flexible compensation region and drive the optical fiber assembly to generate an alignment displacement relative to the silicon photonic chip.

[0061] Specifically, the analog electrical signal transmitted from a high-sensitivity temperature sensor located in the rigid fixed area is read through a high-precision analog-to-digital converter interface and converted into a digital temperature value characterizing the current heating state of the silicon photonics chip. After acquiring this real-time temperature, the controller extracts the reference ambient temperature of the initial packaging state and compares the temperature difference based on this. Subsequently, it retrieves a preset deformation control mapping model pre-stored in the microprocessor's non-volatile memory. This model is a mathematical function fitted from multiple sets of experimental data of cantilever beam actuation displacement under different temperature gradients, responsible for converting the current temperature difference data into corresponding electrical control commands to generate dynamic adjustment parameters. Based on these dynamic adjustment parameters, the microprocessor sends commands to an external voltage-controlled constant current source through a digital-to-analog converter to change the amplitude of the original preset bias voltage, thereby outputting a real-time corrected driving voltage to the heating electrode array. As the driving voltage changes, the Joule heat generated by the platinum heating electrode array increases or decreases accordingly, causing a redistribution of internal stress within the two thin films of the dual-material strain layer due to the difference in thermal expansion coefficients. The dynamic equilibrium change of internal stress directly adjusts the physical curvature of the cantilever structure in the flexible compensation zone, causing it to drive the fiber optic assembly fixed at the end to generate high-precision alignment displacement in three-dimensional space, thus compensating for waveguide port misalignment caused by the thermal expansion and contraction of the chip. Based on the principles of energy conservation and thermo-elastic-plastic mechanics, the derivation formula of the driving voltage is expressed as follows:

[0062]

[0063] in the formula The final driving voltage output to the heating electrode array, The preset bias voltage applied during the initial optical coupling link construction in the packaging stage. The electrothermal compensation coefficient is used in the preset deformation control mapping relationship. The real-time temperature of the packaged area obtained by the temperature sensor. The reference ambient temperature for constructing the initial optical coupling link.

[0064] The real-time temperature is a discrete value of the current packaging environment temperature, continuously collected by thermistors distributed in the rigid fixed area and processed by analog-to-digital conversion. The preset deformation control mapping relationship is a mathematical equation or lookup table pre-calibrated and embedded in the memory chip, characterizing the matching rule between the thermal expansion displacement of the silicon photonic chip and the actuation bias voltage of the dual-material strain layer. The dynamic adjustment parameter is the voltage correction amount calculated by the control system based on the temperature difference and the mapping relationship, used to correct the original solidified bias state. The driving voltage is the final potential difference, after parameter modulation, actually applied across the heating electrodes to drive the dual materials to generate a new thermodynamic deformation steady state. The alignment displacement is the spatial relative position correction amount generated between the end fiber assembly and the light-emitting chip due to the curvature change of the flexible compensation area under thermal strain.

[0065] For example, the baseline ambient temperature for constructing the initial optical coupling link is set to 25°C, and the preset bias voltage is 2.5V. The preset electrothermal compensation coefficient is determined to be 0.05V² / °C based on the ratio of the bulk expansion rate of the silicon photonics chip to the electrothermal actuation efficiency of the dual-material strain layer. This is based on the fact that previous factory testing and calibration showed that the silicon photonics chip generates a thermally induced offset of 0.5μm for every degree Celsius increase in temperature, while the dual-material strain layer generates an actuated displacement of 10μm for every volt squared increase in bias voltage. The physical response ratio of these two is taken as 0.05 and solidified as the mapping relationship coefficient. When the temperature sensor detects that the real-time temperature of the packaging area rises to 65°C due to the high-frequency operation of the chip, the preset deformation control mapping relationship is invoked to generate dynamic adjustment parameters. The specific derivation process for calculating the driving voltage is as follows:

[0066] By outputting a driving voltage of 2.0615V to the heating electrode array, the internal Joule heat generation rate is reduced in a controlled manner. Due to the decrease in its internal temperature, the dual-material strain layer reduces the initial downward bending curvature of the original cantilever structure, thereby driving the end fiber component to generate a 20μm mechanical alignment displacement relative to the silicon photonic chip. This process precisely offsets the 20μm downward structural thermal expansion offset of the chip itself caused by the extreme temperature rise of 40℃, thus keeping the optical signal coupling efficiency continuously stable within the preset optimal conduction range.

[0067] Optionally, the preset deformation control mapping relationship includes:

[0068] The silicon photonic chip is driven to heat up, and the offset coordinates of the optical fiber component relative to the silicon photonic chip are obtained to generate the base distortion characteristics;

[0069] Apply a step voltage increment to the preset bias voltage to obtain the displacement vector generation actuation offset characteristics of the flexible compensation region;

[0070] Based on the background distortion characteristics and the actuation offset characteristics, a deformation control mapping relationship between the preset bias voltage and the alignment displacement is fitted and generated.

[0071] Specifically, a test electrical signal is injected into the silicon photonics chip through an external high-power test platform to drive it to heat up under full load. The absolute spatial coordinate change of the center point of the fiber optic component end face relative to the waveguide emission center of the silicon photonics chip is continuously tracked, and continuous temperature coordinates are recorded to generate the background distortion characteristics. The power supply to the silicon photonics chip is then cut off to allow it to cool naturally to room temperature. A stepped voltage increment is applied to the heating electrode array of the flexible compensation area in the initial bending deformation state through a high-precision programmable power supply. The displacement vector data of the flexible compensation area after each voltage change is recorded simultaneously to generate the actuated offset characteristics. The thermal offset in the background distortion characteristics and the electroinduced displacement in the actuated offset characteristics are extracted. The least squares polynomial fitting algorithm is used to solve for the inverse operation intersection set of the two response curves, generating a precise deformation control mapping relationship between the preset bias voltage and the alignment displacement. The core mapping relationship calculation formula used in this calibration and fitting process is as follows:

[0072]

[0073] in the formula Represents the target driving voltage. This represents the preset bias voltage. Represents the coefficient of the first term of voltage displacement. Represents the coefficient of the second term of voltage displacement. Represents the coefficient of the first-order term of temperature displacement. Represents the coefficient of the quadratic term of temperature displacement. This represents the absolute temperature difference between the real-time operating temperature of the silicon photonics chip and its package reference temperature. For example... Figure 2 The diagram shows a preset deformation control mapping relationship curve, illustrating the nonlinear operating mechanism of multi-physics coupling compensation in the form of statistical data charts. As the chip temperature rises along the horizontal axis, the blue dashed line, representing the background distortion displacement, exhibits an intensified downward misalignment trend. To achieve precise optical path calibration, the green solid line shows the actuation compensation displacement, equal in magnitude and opposite in direction, generated by the cantilever. The red dotted line visually reflects the trajectory of the target driving voltage value dynamically applied for this compensation. The coordinate points in the chart, such as under a 40℃ temperature rise condition, clearly map the logical closed loop between thermal disturbance, displacement compensation, and driving energy distribution.

[0074] Among them, the background distortion feature is a dataset of spatial relative position offsets between the fiber and waveguide interface caused by the purely passive thermal expansion due to the self-heating of the silicon photonic chip. The step voltage increment is a discrete DC signal gradient applied to the heating electrode array during calibration, increasing at a fixed difference. The actuation offset feature is a dataset of mechanical displacement responses, including direction and magnitude, generated by the thermal deformation of the dual-material strain layer in the flexible compensation region under different bias voltages. Fitting is a data processing procedure that uses numerical approximation algorithms such as the least squares method to derive a data description of the continuous nonlinear functional relationship between temperature, voltage, and displacement from discrete calibration data points.

[0075] For example, the reference room temperature is set to 25 degrees Celsius and the initial preset bias voltage is 2.5 volts. The temperature displacement first-order coefficient is extracted from the measured temperature displacement characteristics based on the chip's heating record background distortion features. The value is -0.5 micrometers per degree Celsius and the coefficient of the quadratic term of temperature displacement. A value of -0.005 micrometers per square degree Celsius, with a negative sign, indicates a downward offset due to thermal mismatch in material stacking. The chip heating was turned off, and incremental step voltages were applied to the electrodes. The actuated offset characteristics were recorded, and the first-order coefficient of the voltage displacement was extracted through actual measurement. The value is 20 micrometers per volt and the coefficient of the second term of voltage displacement. The value is 4 micrometers per square volt. The quadratic polynomial fitting algorithm is used because the lattice thermal expansion of semiconductor materials and the generation of Joule heating in the electrodes both exhibit nonlinear physical characteristics over a wide temperature range; therefore, quadratic compensation is used to ensure control accuracy across the entire range. When the environmental sensor measures the actual operating temperature to be 45 degrees Celsius, the temperature difference... That is, 20 degrees Celsius. The downward offset of the chip that needs to be offset at this point is derived as follows: Micrometers. To generate a 12-micrometer upward actuation compensation displacement, the system directly solves for the target driving voltage using the mapping formula. The verification and derivation process is as follows: the target voltage increment equals... Volts. This increment is added to the reference voltage to obtain the target driving voltage output by the system to the electrode array: 2.5 + 0.541 = 3.041 volts. This accurately drives the cantilever beam to rise precisely by 12 micrometers, completing the absolute zeroing of the optically coupled displacement. This verifies the calculation accuracy and compensation reliability of the nonlinear mapping model under extreme heat dissipation conditions.

[0076] Optionally, obtaining the real-time temperature of the packaging area through the temperature sensor includes:

[0077] Acquire the analog temperature electrical signal output by the temperature sensor;

[0078] The thermal crosstalk noise threshold is determined based on the preset thermal damping parameters of the thermal isolation groove;

[0079] The simulated temperature signal is filtered using the thermal crosstalk noise threshold to obtain discrete temperature values, i.e., real-time temperature.

[0080] Specifically, a high-sensitivity thermistor or thermocouple mounted on a rigid fixed area serves as a temperature sensor to sense the temperature state of the micro-region in real time and outputs an analog temperature signal that is physically proportional to its absolute surface temperature. The preset thermal damping parameters of the thermal isolation groove, solidified in the read-only memory during the manufacturing stage, are retrieved. Combined with the dynamic thermal power consumption characteristics of the silicon photonics chip itself, the maximum transient thermal fluctuation amplitude that can penetrate the thermal isolation groove and reach the sensor is calculated, thus establishing the thermal crosstalk noise threshold for signal judgment. The analog electrical signal output by the temperature sensor is converted into a digital sequence through high-frequency sampling, and the thermal crosstalk noise threshold is introduced as a core boundary condition for dead-zone filtering. Any abrupt signal with a fluctuation amplitude below the threshold is identified as transient thermal crosstalk noise generated during high-frequency communication of the chip and is directly filtered out, maintaining the temperature reading of the previous sampling period. Slow drift signals exceeding the threshold are identified as a real change in the thermal balance of the packaging environment and are allowed to pass through. Finally, a discrete temperature value that accurately reflects the background state of the environment, i.e., the real-time temperature, is obtained. The physical formula for calculating the thermal crosstalk noise threshold is as follows:

[0081]

[0082] in the formula This represents the thermal crosstalk noise threshold that needs to be established. This represents the peak value of dynamic thermal power fluctuations in silicon photonics chips caused by high-speed data throughput. The preset thermal damping parameters represent the thermal insulation groove. This represents the effective cross-sectional area of ​​the thermal insulation groove that blocks heat conduction. For example... Figure 3 The figure shows the thermal crosstalk noise dead-zone filtering curve based on preset thermal damping parameters. Presented as a time-domain waveform, it clearly and intuitively demonstrates how the dual mechanisms of physical damping and digital filtering are used to address extremely complex high-frequency thermal interference. The orange curve represents the original analog temperature signal collected by the temperature sensor mounted on the rigid fixed area. It is evident that, along with the slow temperature rise with the ambient background, a large number of transient high-frequency thermal crosstalk spikes caused by the high-speed throughput of the silicon photonics chip are superimposed. The red shaded area represents the noise judgment dead zone, rigorously calculated using preset thermal damping parameters. After dead-zone boundary comparison and interception processing by the central processing unit, glitch fluctuations are successfully removed, ultimately outputting the discrete real-time temperature represented by the dark blue stepped thick line. This purified temperature data is smooth and highly stable, providing a pure reference benchmark for subsequent high-precision closed-loop actuation compensation.

[0083] The analog temperature signal is a continuously changing voltage or current physical quantity representing the amount of heat output by the temperature probe based on the thermoelectric or thermal resistance effect. The preset thermal damping parameter is an intrinsic constant that quantifies the ability of the insulating medium inside the thermal isolation tank to physically attenuate and phase-lag high-frequency heat conduction waves. The thermal crosstalk noise threshold is a quantitative decision boundary that distinguishes between the gradual change in the overall ambient temperature of the packaging substrate and the spurious transient temperature rise caused by localized high-frequency heating of the chip. Filtering is a data purification process that uses digital control algorithms to remove high-frequency thermal noise interference mixed in the discrete sampling sequence to restore the true thermodynamic steady-state baseline. The discrete temperature values ​​are digital real-time temperature parameters that, after analog-to-digital conversion and dead-zone digital filtering purification, are directly used by the next-level microcontroller for closed-loop actuation compensation.

[0084] For example, the peak value of dynamic thermal power fluctuation of a silicon photonic chip within a known packaging system at the limiting modulation frequency is... The value is 2.0 watts, based on the device's factory-specified maximum transient communication loss rate. The effective cross-sectional area of ​​the thermal isolation trench was determined through micro / nano structure design. The area is 0.00005 square meters. The polyimide insulation material filling the isolation groove has a preset thermal damping parameter. The threshold was set at 80,000 watts per square meter Kelvin, a parameter derived from the phonon scattering impedance characteristics of the corresponding polymer materials at the micro-nano scale. The derivation process for verifying the thermal crosstalk noise threshold using the formula is as follows: Kelvin. The dead-zone filtering algorithm is based on the assumption that the residual temperature rise after the chip's transient heating is attenuated by the physical isolation trench will absolutely not exceed this calculated limit. At this time, the sensor collects and converts the digital steady-state temperature at the first sampling moment to 45.0 degrees Celsius. At the second sampling moment, due to the chip's instantaneous loading of a full-rate communication signal, the original sampling temperature jumps abruptly to 45.3 degrees Celsius. The system calculates and verifies that the absolute value of the temperature difference between the two samplings is |45.3-45.0|=0.3 degrees Celsius. Since 0.3 degrees Celsius is strictly less than the derived 0.5 Kelvin thermal crosstalk noise threshold, the filtering algorithm triggers the interception mechanism, determines that the temperature rise is high-frequency thermal crosstalk, directly filters it out, and forces the real-time temperature at the second sampling moment to be maintained at 45.0 degrees Celsius. At the third sampling moment, the external packaging environment experiences a real overall temperature rise, causing the original sampling data to smoothly rise to 45.6 degrees Celsius. The difference between this and the previous steady-state temperature is calculated again to be |45.6-45.0|=0.6 degrees Celsius. Since 0.6 degrees Celsius is greater than the noise threshold of 0.5 Kelvin, it is determined that temperature drift has occurred in the real environment. The purified discrete temperature value is then updated to 45.6 degrees Celsius, thus ensuring the purity of the closed-loop control input source under complex dynamic heat flow background.

[0085] Optionally, outputting a drive voltage to the heating electrode array according to the dynamic adjustment parameters includes:

[0086] When the dynamic adjustment parameter indicates positive compensation, a driving voltage higher than the preset bias voltage is output to the heating electrode array;

[0087] When the dynamic adjustment parameter indicates negative compensation, a driving voltage lower than the preset bias voltage is output to the heating electrode array.

[0088] Specifically, during dynamic alignment compensation, the logic unit of the central processing unit analyzes the polarity and amplitude of the dynamic adjustment parameters generated by the front-end module. When the logic unit determines that the value of the dynamic adjustment parameter is positive, indicating positive compensation, the controller sends a digital instruction to the high-precision digital-to-analog converter to increase the output bit width. This causes the peripheral voltage control circuit to output a driving voltage to the heating electrode array that is significantly higher than the original preset bias voltage. This increased voltage causes the heating electrodes to release more Joule heat, thereby increasing the curvature of the dual-material strain layer. Conversely, when the logic unit determines that the value of the dynamic adjustment parameter is negative, indicating negative compensation, the controller sends an instruction to decrease the output bit width. This causes the peripheral circuit to output a driving voltage to the heating electrode array that is significantly lower than the preset bias voltage. This decreased voltage reduces the heat input, thus slowing down the curvature of the strain layer. This reference voltage-based up-and-down floating control enables bidirectional mechanical addressing within a single physical structure. The synthesis formula for the core driving voltage of the above control logic is as follows:

[0089]

[0090] in the formula This represents the driving voltage of the final output. This represents the constant preset bias voltage established during the curing phase. This represents a dynamic adjustment parameter with positive and negative polarities.

[0091] Among them, the dynamic adjustment parameters are numerical variables with polarity signs used to characterize the electrical control quantities that the system needs to supplement or reduce in order to eliminate optical path deviation. Positive compensation is an electrothermal correction process in which the system actively increases thermally induced deformation to offset thermal displacement of the chip in a specific direction, causing the fiber optic assembly to follow the displacement to the same side. Negative compensation is an electrothermal correction process in which the system actively reduces thermally induced deformation to offset thermal displacement of the chip in the opposite direction, causing the fiber optic assembly to fall back to the other side. The preset bias voltage is a constant electrical signal set during the packaging stage and serves as the physical energy starting point for all subsequent dynamic adjustment actions. The driving voltage is the final control potential actually applied to both ends of the platinum heating electrode after superimposing the algebraic adjustment parameters.

[0092] For example, a preset bias voltage formed during the packaging stage is set. The voltage is 2.5V. Based on the law of thermal expansion of materials and extensive previous microscopic ranging experimental data, two fixed compensation constants were extracted: the temperature displacement coefficient of the silicon photonic chip. The voltage-displacement response coefficient of the dual-material strain layer is set to 0.5 μm / ℃. The constant value was set to 10.0 μm / V, based on the measured bulk expansion rate of single-crystal silicon and the electrothermal conversion efficiency of the aluminum-silicon composite thin film. In the first operating condition, the temperature sensor measured the ambient temperature... The temperature is raised to 10.0℃. At this point, the upward thermal offset of the silicon photonics chip is derived to be 0.5 * 10.0 = 5.0 μm. To make the fiber optic assembly move upward 5.0 μm along with the chip, the control system generates dynamic adjustment parameters indicating positive compensation. The calculated value is 5.0 / 10.0 = 0.5V. The output drive voltage at this point is derived to be 2.5 + 0.5 = 3.0V. This 3.0V is significantly higher than the preset bias voltage of 2.5V, successfully increasing the Joule heating of the heating electrode and driving the cantilever beam upwards to compensate for 5.0μm. In the second operating condition, the ambient temperature drops sharply, leading to a temperature difference... The temperature is -8.0℃. The downward thermal offset generated by the silicon photonics chip is derived to be 0.5 * -8.0 = -4.0 μm. Dynamic adjustment parameters indicating negative compensation are immediately generated, calculated to be -4.0 / 10.0 = -0.4V. The output drive voltage is then derived to be 2.5 + (-0.4) = 2.1V. This 2.1V is significantly lower than the preset bias voltage of 2.5V. By reducing Joule heat input, the system releases stress within the strain layer, causing the cantilever beam to smoothly drop back 4.0 μm. The bidirectional voltage adjustment eliminates the persistent optical misalignment caused by bidirectional temperature drift.

[0093] Optionally, the method further includes:

[0094] Obtain the cumulative number of heating cycles for the dual-material strain layer;

[0095] The fatigue compensation coefficient is calculated based on the cumulative number of heating cycles and the preset material stiffness loss parameters.

[0096] The deformation control mapping relationship is corrected using the fatigue compensation coefficient.

[0097] Specifically, when a preset non-volatile counter detects a complete pulse of the driving voltage applied to the heating electrode array, rising from a reference value and falling back, and the corresponding temperature sensor records a recurring heating and cooling process, the counter will accumulate one heating cycle. As the accumulated number increases, the actuation efficiency of the dual-material strain layer in converting thermal energy into mechanical bending displacement will nonlinearly decrease due to repeated thermal stress friction and lattice defect accumulation at the interface of the two materials. The preset material stiffness loss parameters in the memory are retrieved, and combined with the real-time accumulated heating cycle count, a fatigue compensation coefficient characterizing the current aging degree is calculated. This fatigue compensation coefficient is multiplied as a dynamic weighting factor into the original deformation control mapping model. By proportionally amplifying the amplitude of the target driving voltage, the increased actuation stiffness resistance due to thermal fatigue is overcome, thereby ensuring the output accuracy of the fiber alignment displacement throughout the entire lifespan of the device. The formula for calculating the fatigue compensation coefficient is as follows:

[0098]

[0099] in the formula Represents the fatigue compensation coefficient. This represents the preset material stiffness loss parameter. This represents the cumulative number of heating cycles for the bimaterial strain layer. The formula for correcting the deformation control mapping relationship is as follows:

[0100]

[0101] in the formula This represents the corrected actual drive voltage. This represents the theoretical driving voltage output by the original deformation control mapping relationship. For example... Figure 4 The diagram illustrates the material aging and fatigue compensation curves based on cumulative heating cycles, employing a dual Y-axis structure to demonstrate the adaptive electrical compensation logic under long-term thermomechanical fatigue conditions. The purple dashed line depicts the irreversible exponential decline in the intrinsic actuation efficiency of the dual-material strain layer as it undergoes multiple heating cycles. To completely overcome the mechanical displacement deviation caused by the loss of stiffness in the underlying material, an exponential compensation model is introduced. The green solid line represents the fatigue compensation coefficient calculated based on preset material stiffness loss parameters. The highlighted points in the verification example clearly show that when the device reaches 10,000 thermal cycles, the fatigue compensation coefficient is precisely amplified to 1.6487. This means that the target driving voltage is proportionally increased to forcibly inject more Joule thermal energy to combat stress fatigue, thereby maintaining the alignment accuracy of the fiber optic link throughout the device's demanding lifespan of 100,000 cycles.

[0102] The cumulative heating cycle count is the sum of the thermal cycles that the encapsulation system has undergone since its first power-on operation, causing significant stress alternation in the dual-material strain layer. The material stiffness loss parameter is an empirical rate constant, determined in advance through high and low temperature shock accelerated aging experiments, characterizing the exponential decay of the work capacity of the dual-material composite film with the number of cycles. The fatigue compensation coefficient is a dimensionless multiplier that dynamically increases with the degree of material aging and is used to compensate for actuation displacement loss. The algorithm processing flow is modified to use a digital compensation factor to multiply and weight the theoretical voltage control model to output higher driving energy to compensate for mechanical attenuation.

[0103] For example, the cumulative number of heating cycles recorded in the current non-volatile memory is read. For 10,000 cycles. The preset material stiffness loss parameters are retrieved. The parameter is set at 0.05%, based on calibration results from standard thermal shock aging tests conducted on the same batch of dual-material strain layers at temperatures ranging from -40°C to 85°C, which showed that approximately 65% ​​of the actuation efficiency would be lost per 100,000 cycles. The calculation and derivation process based on the fatigue compensation coefficient formula is as follows: At this point, the theoretical driving voltage that should have been output is derived by substituting the real-time temperature drift data obtained from the temperature sensor into the original deformation control equation. The value is 2.0 volts. The corrected formula is immediately used for secondary derivation to verify its calculation process. Volts. Finally, an absolute correction drive voltage of 3.2974 volts is output to the heated electrode array. This increased voltage provides the electrode array with additional Joule thermal energy, completely overcoming the stiffness attenuation and deformation resistance caused by 10,000 thermal stress cycles of the two materials. This allows the cantilever beam to still output the same amount of high-precision mechanical alignment displacement to the fiber optic assembly as it would in its brand-new condition, eliminating the long-term degradation and attenuation of coupled optical power caused by the aging of the underlying encapsulation material.

[0104] It should be noted that the electrical connections between the various units described above do not necessarily represent direct or indirect connections. Any indirect connection method can be applied to the embodiments of the present invention as long as it achieves the purpose of the present invention. The above descriptions are merely exemplary embodiments of the present invention and should not be construed as limiting the scope of the present invention.

[0105] All equivalent changes and modifications made in accordance with the teachings of this invention are still within the scope of this invention. Those skilled in the art will readily conceive of other embodiments of this invention upon considering the specification and the disclosure of practical truth. This application is intended to cover any variations, uses, or adaptations of this invention that follow the general principles of this invention and include common knowledge or conventional techniques in the art not described herein.

Claims

1. A method for packaging silicon photonic chips with thermally induced deformation modulation, characterized in that, include: A packaging substrate is obtained, the packaging substrate including a flexible compensation area, a rigid fixing area and a thermal isolation groove; A heating electrode array and a dual-material strain layer are provided in the flexible compensation region, and a temperature sensor is provided in the rigid fixing region. The silicon photonic chip is fixed to the surface of the rigid fixing area, and a preset bias voltage is input to the heating electrode array to generate an initial bending deformation state in the flexible compensation area. In the initial bending deformation state, the optical fiber assembly is fixedly connected to the end of the flexible compensation area to construct the initial optical coupling link.

2. The method for thermally deformable silicon photonic chip packaging according to claim 1, characterized in that, The acquisition of the packaging substrate includes: A cantilever structure is formed at the edge region of the packaging substrate by deep silicon etching as the flexible compensation region, and a rigid fixing region is formed in the central region. A through hole is etched between the flexible compensation area and the rigid fixing area, and the through hole is filled with a heat-insulating medium material to form the thermal isolation groove.

3. The method for packaging silicon photonics chips with thermally induced deformation control according to claim 1, characterized in that, The provision of a heating electrode array and a dual-material strain layer in the flexible compensation region includes: The heating electrode array is deposited on the surface of the flexible compensation region; A first metal thin film and a second dielectric thin film are sequentially deposited above the heating electrode array to form a dual-material strain layer, wherein the thermal expansion coefficient of the first metal thin film is greater than that of the second dielectric thin film.

4. The method for thermally deformable silicon photonic chip packaging according to claim 1, characterized in that, The step of fixing the optical fiber assembly to the end of the flexible compensation region to construct the initial optical coupling link includes: While maintaining the preset bias voltage, adjust the spatial pose of the optical fiber assembly to the preset optical power coupling point; At the preset optical power coupling point, the end face of the optical fiber assembly is cured and connected to the end of the flexible compensation area using UV-curable adhesive to form an initial optical coupling link.

5. The method for thermally deformable silicon photonic chip packaging according to claim 1, characterized in that, The method further includes: The real-time temperature of the packaging area is obtained through the temperature sensor, and dynamic adjustment parameters for the preset bias voltage are generated according to the preset deformation control mapping relationship and the real-time temperature. According to the dynamic adjustment parameters, a driving voltage is output to the heating electrode array to adjust the curvature of the flexible compensation region and drive the optical fiber assembly to generate an alignment displacement relative to the silicon photonic chip.

6. The method for thermally deformable silicon photonic chip packaging according to claim 5, characterized in that, The preset deformation control mapping relationship includes: The silicon photonic chip is driven to heat up, and the offset coordinates of the optical fiber component relative to the silicon photonic chip are obtained to generate the base distortion characteristics; Apply a step voltage increment to the preset bias voltage to obtain the displacement vector generation actuation offset characteristics of the flexible compensation region; Based on the background distortion characteristics and the actuation offset characteristics, a deformation control mapping relationship between the preset bias voltage and the alignment displacement is fitted and generated.

7. The method for thermally deformable silicon photonic chip packaging according to claim 5, characterized in that, The step of obtaining the real-time temperature of the packaging area through the temperature sensor includes: Acquire the analog temperature electrical signal output by the temperature sensor; The thermal crosstalk noise threshold is determined based on the preset thermal damping parameters of the thermal isolation groove; The simulated temperature signal is filtered using the thermal crosstalk noise threshold to obtain discrete temperature values, i.e., real-time temperature.

8. A method for packaging silicon photonics chips with thermally induced deformation control according to claim 5, characterized in that, The step of outputting a driving voltage to the heating electrode array according to the dynamic adjustment parameters includes: When the dynamic adjustment parameter indicates positive compensation, a driving voltage higher than the preset bias voltage is output to the heating electrode array; When the dynamic adjustment parameter indicates negative compensation, a driving voltage lower than the preset bias voltage is output to the heating electrode array.

9. A method for packaging silicon photonics chips with thermally induced deformation control according to claim 5, characterized in that, The method further includes: Obtain the cumulative number of heating cycles for the dual-material strain layer; The fatigue compensation coefficient is calculated based on the cumulative number of heating cycles and the preset material stiffness loss parameters. The deformation control mapping relationship is corrected using the fatigue compensation coefficient.

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